diff --git a/components/esp_driver_gpio/test_apps/.build-test-rules.yml b/components/esp_driver_gpio/test_apps/.build-test-rules.yml
index 68cfc3a41d..f0eb84e6e2 100644
--- a/components/esp_driver_gpio/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_gpio/test_apps/.build-test-rules.yml
@@ -1,10 +1,6 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
 components/esp_driver_gpio/test_apps:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not support yet # TODO: [ESP32C5] IDF-8717
   disable_test:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
diff --git a/components/esp_driver_gpio/test_apps/gpio/README.md b/components/esp_driver_gpio/test_apps/gpio/README.md
index bf47d80ec6..3a502b1f86 100644
--- a/components/esp_driver_gpio/test_apps/gpio/README.md
+++ b/components/esp_driver_gpio/test_apps/gpio/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
index 177c65862f..d1811d2a06 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
@@ -535,6 +535,8 @@ TEST_CASE("GPIO_set_output_level_get_input_level_test", "[gpio]")
     TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "get level error! the level should be high!");
 }
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
+// C5 on FPGA do not support GPIO pull down
 // This test routes constant-high/low signal to pins, another way is to directly connect TEST_GPIO_EXT_IN_IO to
 // 3.3v or GND pin
 TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
@@ -662,6 +664,8 @@ TEST_CASE("GPIO_mode_test", "[gpio]")
     TEST_ASSERT_EQUAL_INT_MESSAGE(!level, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT set error, it gives incorrect output");
 }
 
+#endif
+
 static void prompt_to_continue(const char *str)
 {
     printf("%s , please press \"Enter\" to go on!\n", str);
diff --git a/components/esp_pm/Kconfig b/components/esp_pm/Kconfig
index 3058381fbd..718379486d 100644
--- a/components/esp_pm/Kconfig
+++ b/components/esp_pm/Kconfig
@@ -2,7 +2,8 @@ menu "Power Management"
     config PM_ENABLE
         bool "Support for power management"
         # SMP FreeRTOS currently does not support power management IDF-4997
-        depends on !FREERTOS_SMP || __DOXYGEN__
+        # Power Management is not supported on ESP32C5 MP IDF-8643
+        depends on (!FREERTOS_SMP || __DOXYGEN__) && !IDF_TARGET_ESP32C5
         default n
         help
             If enabled, application is compiled with support for power management.
diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h
index 57df8172cd..75d809bc73 100644
--- a/components/hal/esp32c5/include/hal/gpio_ll.h
+++ b/components/hal/esp32c5/include/hal/gpio_ll.h
@@ -22,23 +22,17 @@
 #include "soc/gpio_struct.h"
 #include "soc/lp_aon_struct.h"
 #include "soc/pmu_struct.h"
+#include "soc/io_mux_struct.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "soc/usb_serial_jtag_struct.h"
+#include "hal/gpio_types.h"
+#include "hal/assert.h"
 #if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
 #include "soc/lp_io_struct.h"
-#include "soc/pcr_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/usb_serial_jtag_struct.h"
-#include "soc/io_mux_struct.h"
-#include "hal/gpio_types.h"
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 #include "soc/lp_gpio_struct.h"
-#include "soc/usb_serial_jtag_reg.h"
-#include "soc/pcr_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/io_mux_struct.h"
-#include "hal/gpio_types.h"
-#include "hal/misc.h"
 #endif
-#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -69,15 +63,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
                                          bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
                                          uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
 {
-    *pu = IOMUX.gpio[gpio_num].fun_wpu;
-    *pd = IOMUX.gpio[gpio_num].fun_wpd;
-    *ie = IOMUX.gpio[gpio_num].fun_ie;
+    *pu = IO_MUX.gpio[gpio_num].fun_wpu;
+    *pd = IO_MUX.gpio[gpio_num].fun_wpd;
+    *ie = IO_MUX.gpio[gpio_num].fun_ie;
     *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
     *od = hw->pin[gpio_num].pad_driver;
-    *drv = IOMUX.gpio[gpio_num].fun_drv;
-    *fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
+    *drv = IO_MUX.gpio[gpio_num].fun_drv;
+    *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
     *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
-    *slp_sel = IOMUX.gpio[gpio_num].slp_sel;
+    *slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
 }
 
 /**
@@ -88,12 +82,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
   */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpu = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpu = 1;
 }
 
 /**
@@ -105,12 +94,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpu = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpu = 0;
 }
 
 /**
@@ -121,12 +105,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpd = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpd = 1;
 }
 
 /**
@@ -143,20 +122,11 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
     // Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
     // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
     // TODO: read the specific efuse with efuse_ll.h
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
     if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
         USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
         USB_SERIAL_JTAG.conf0.dp_pullup = 0;
     }
-    IOMUX.gpio[gpio_num].fun_wpd = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
-    //     SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
-    // }
-    // REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpd = 0;
 }
 
 /**
@@ -182,11 +152,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
     (void)core_id;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
     *status = hw->pcpu_int.procpu_int;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    abort();
-#endif
 }
 
 /**
@@ -261,12 +227,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_ie = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_ie = 0;
 }
 
 /**
@@ -277,12 +238,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_ie = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_ie = 1;
 }
 
 /**
@@ -293,12 +249,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].filter_en = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].filter_en = 1;
 }
 
 /**
@@ -309,15 +260,9 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].filter_en = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].filter_en = 0;
 }
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
 /**
   * @brief Enable GPIO hysteresis
   *
@@ -330,8 +275,8 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
     // We are not going to use the hardware control in IDF for C5.
     // Therefore, we need to always switch to use software control first.
     // i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
-    IOMUX.gpio[gpio_num].hys_sel = 1;
-    IOMUX.gpio[gpio_num].hys_en = 1;
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 1;
 }
 
 /**
@@ -342,10 +287,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
   */
 static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].hys_sel = 1;
-    IOMUX.gpio[gpio_num].hys_en = 0;
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 0;
 }
-#endif
 
 /**
   * @brief Disable output mode on GPIO.
@@ -461,12 +405,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_drv = strength;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_drv = strength;
 }
 
 /**
@@ -478,12 +417,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
   */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    *strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
-    abort();
-#endif
+    *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
 }
 
 /**
@@ -527,7 +461,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
 }
 
 /**
-  * @brief Set pad input to a peripheral signal through the IOMUX.
+  * @brief Set pad input to a peripheral signal through the IO_MUX.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.
@@ -537,7 +471,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
     hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
-    IOMUX.gpio[gpio].fun_ie = 1;
+    IO_MUX.gpio[gpio].fun_ie = 1;
 }
 
 /**
@@ -554,11 +488,10 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
         USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
     }
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
-    // if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
-    // }
-    abort();
+    // Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
+    if (pin_name == IO_MUX_GPIO13_REG || pin_name == IO_MUX_GPIO14_REG) {
+        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+    }
 #endif
     PIN_FUNC_SELECT(pin_name, func);
 }
@@ -590,19 +523,18 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
     if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
         USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
     }
-    IOMUX.gpio[gpio_num].mcu_sel = func;
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
-    // if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
-    // }
-    // PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
-    abort();
+    // Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
+    if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
+        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+    }
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 #endif
 }
 
 /**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  * @brief Set peripheral output to an GPIO pad through the IO_MUX.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num gpio_num GPIO number of the pad.
@@ -625,7 +557,6 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
 static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
 {
     switch (src) {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
      case SOC_MOD_CLK_XTAL:
         PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
         break;
@@ -635,14 +566,6 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
     case SOC_MOD_CLK_PLL_F80M:
         PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
         break;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    case SOC_MOD_CLK_XTAL:
-        PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
-        break;
-    case SOC_MOD_CLK_PLL_F80M:
-        PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
-        break;
-#endif
     default:
         // Unsupported IO_MUX clock source
         HAL_ASSERT(false);
@@ -694,12 +617,7 @@ static inline void gpio_ll_force_unhold_all(void)
   */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].slp_sel = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].slp_sel = 1;
 }
 
 /**
@@ -711,12 +629,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].slp_sel = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].slp_sel = 0;
 }
 
 /**
@@ -727,12 +640,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpu = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpu = 0;
 }
 
 /**
@@ -743,12 +651,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpu = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpu = 1;
 }
 
 /**
@@ -759,12 +662,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpd = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpd = 1;
 }
 
 /**
@@ -775,12 +673,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpd = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpd = 0;
 }
 
 /**
@@ -791,12 +684,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_ie = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_ie = 0;
 }
 
 /**
@@ -807,12 +695,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
   */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_ie = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_ie = 1;
 }
 
 /**
@@ -823,12 +706,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_oe = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_oe = 0;
 }
 
 /**
@@ -839,12 +717,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
   */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_oe = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_oe = 1;
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h
index 94a4df3918..ff3e0ea90e 100644
--- a/components/hal/esp32p4/include/hal/gpio_ll.h
+++ b/components/hal/esp32p4/include/hal/gpio_ll.h
@@ -64,15 +64,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
 {
     uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32);
     uint32_t bit_mask = 1 << bit_shift;
-    *pu = IOMUX.gpio[gpio_num].fun_wpu;
-    *pd = IOMUX.gpio[gpio_num].fun_wpd;
-    *ie = IOMUX.gpio[gpio_num].fun_ie;
+    *pu = IO_MUX.gpio[gpio_num].fun_wpu;
+    *pd = IO_MUX.gpio[gpio_num].fun_wpd;
+    *ie = IO_MUX.gpio[gpio_num].fun_ie;
     *oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift;
     *od = hw->pin[gpio_num].pad_driver;
-    *drv = IOMUX.gpio[gpio_num].fun_drv;
-    *fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
+    *drv = IO_MUX.gpio[gpio_num].fun_drv;
+    *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
     *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
-    *slp_sel = IOMUX.gpio[gpio_num].slp_sel;
+    *slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
 }
 
 /**
@@ -83,7 +83,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
   */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpu = 1;
+    IO_MUX.gpio[gpio_num].fun_wpu = 1;
 }
 
 /**
@@ -95,7 +95,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpu = 0;
+    IO_MUX.gpio[gpio_num].fun_wpu = 0;
 }
 
 /**
@@ -106,7 +106,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpd = 1;
+    IO_MUX.gpio[gpio_num].fun_wpd = 1;
 }
 
 /**
@@ -133,7 +133,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
         USB_WRAP.otg_conf.pad_pull_override = 1;
         USB_WRAP.otg_conf.dp_pullup = 0;
     }
-    IOMUX.gpio[gpio_num].fun_wpd = 0;
+    IO_MUX.gpio[gpio_num].fun_wpd = 0;
 }
 
 /**
@@ -235,7 +235,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_ie = 0;
+    IO_MUX.gpio[gpio_num].fun_ie = 0;
 }
 
 /**
@@ -246,7 +246,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_ie = 1;
+    IO_MUX.gpio[gpio_num].fun_ie = 1;
 }
 
 /**
@@ -257,7 +257,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].filter_en = 1;
+    IO_MUX.gpio[gpio_num].filter_en = 1;
 }
 
 /**
@@ -268,7 +268,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].filter_en = 0;
+    IO_MUX.gpio[gpio_num].filter_en = 0;
 }
 
 /**
@@ -451,7 +451,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
 {
-    IOMUX.gpio[gpio_num].fun_drv = strength;
+    IO_MUX.gpio[gpio_num].fun_drv = strength;
 }
 
 /**
@@ -463,7 +463,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
   */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
+    *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
 }
 
 /**
@@ -547,7 +547,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
 }
 
 /**
-  * @brief Set pad input to a peripheral signal through the IOMUX.
+  * @brief Set pad input to a peripheral signal through the IO_MUX.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number of the pad.
@@ -557,7 +557,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
     hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
-    IOMUX.gpio[gpio].fun_ie = 1;
+    IO_MUX.gpio[gpio].fun_ie = 1;
 }
 
 /**
@@ -597,11 +597,11 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
     } else if (gpio_num == USB_OTG_INT_PHY_DM_GPIO_NUM || gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
         USB_WRAP.otg_conf.usb_pad_enable = 0;
     }
-    IOMUX.gpio[gpio_num].mcu_sel = func;
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 }
 
 /**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  * @brief Set peripheral output to an GPIO pad through the IO_MUX.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num gpio_num GPIO number of the pad.
@@ -685,7 +685,7 @@ static inline void gpio_ll_force_unhold_all(void)
   */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].slp_sel = 1;
+    IO_MUX.gpio[gpio_num].slp_sel = 1;
 }
 
 /**
@@ -697,7 +697,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].slp_sel = 0;
+    IO_MUX.gpio[gpio_num].slp_sel = 0;
 }
 
 /**
@@ -708,7 +708,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpu = 0;
+    IO_MUX.gpio[gpio_num].mcu_wpu = 0;
 }
 
 /**
@@ -719,7 +719,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpu = 1;
+    IO_MUX.gpio[gpio_num].mcu_wpu = 1;
 }
 
 /**
@@ -730,7 +730,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpd = 1;
+    IO_MUX.gpio[gpio_num].mcu_wpd = 1;
 }
 
 /**
@@ -741,7 +741,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpd = 0;
+    IO_MUX.gpio[gpio_num].mcu_wpd = 0;
 }
 
 /**
@@ -752,7 +752,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_ie = 0;
+    IO_MUX.gpio[gpio_num].mcu_ie = 0;
 }
 
 /**
@@ -763,7 +763,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
   */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_ie = 1;
+    IO_MUX.gpio[gpio_num].mcu_ie = 1;
 }
 
 /**
@@ -774,7 +774,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_oe = 0;
+    IO_MUX.gpio[gpio_num].mcu_oe = 0;
 }
 
 /**
@@ -785,7 +785,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
   */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_oe = 1;
+    IO_MUX.gpio[gpio_num].mcu_oe = 1;
 }
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h b/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
index ace0a983de..fdab268dfe 100644
--- a/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
@@ -34,7 +34,7 @@ typedef union {
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} iomux_pin_ctrl_reg_t;
+} io_mux_pin_ctrl_reg_t;
 
 /** Type of gpio register
  *  IO MUX Configure Register for pad XTAL_32K_P
@@ -102,13 +102,13 @@ typedef union {
         uint32_t hys_en:1;
         /** hys_sel : R/W; bitpos: [17]; default: 0;
          *  Select enabling signals of the pad from software and efuse hardware. 1: Select
-         *  enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
+         *  enabling signal from slftware. 0: Select enabling signal from efuse hardware.
          */
         uint32_t hys_sel:1;
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} iomux_gpio_reg_t;
+} io_mux_gpio_reg_t;
 
 /** Type of date register
  *  IO MUX Version Control Register
@@ -122,20 +122,20 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} iomux_date_reg_t;
+} io_mux_date_reg_t;
 
 
-typedef struct iomux_dev_t {
-    volatile iomux_pin_ctrl_reg_t pin_ctrl;
-    volatile iomux_gpio_reg_t gpio[27];
+typedef struct io_mux_dev_t {
+    volatile io_mux_pin_ctrl_reg_t pin_ctrl;
+    volatile io_mux_gpio_reg_t gpio[27];
     uint32_t reserved_070[35];
-    volatile iomux_date_reg_t date;
-} iomux_dev_t;
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
 
-extern iomux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(iomux_dev_t) == 0x100, "Invalid size of iomux_dev_t structure");
+_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
index 14d416ccc3..54c687aff3 100644
--- a/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
+++ b/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
@@ -41,7 +41,7 @@ PROVIDE ( DS                  = 0x6008C000 );
 PROVIDE ( HMAC                = 0x6008D000 );
 PROVIDE ( ECDSA               = 0x6008E000 );
 
-PROVIDE ( IOMUX               = 0x60090000 );
+PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
 PROVIDE ( GPIO_EXT            = 0x60091f00 );
 PROVIDE ( SDM                 = 0x60091f00 );
diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
index 347785282f..cb12a7c2fd 100644
--- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
@@ -111,17 +111,41 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
     bool
     default y
 
+config SOC_GPIO_PORT
+    int
+    default 1
+
 config SOC_GPIO_PIN_COUNT
     int
     default 29
 
+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
 config SOC_GPIO_IN_RANGE_MAX
     int
-    default 30
+    default 28
 
 config SOC_GPIO_OUT_RANGE_MAX
     int
-    default 30
+    default 28
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
+    hex
+    default 0x0000000001FFFF00
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
 
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
diff --git a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h b/components/soc/esp32c5/mp/include/soc/io_mux_reg.h
index c8bec06285..1a9dec1b88 100644
--- a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h
+++ b/components/soc/esp32c5/mp/include/soc/io_mux_reg.h
@@ -95,6 +95,36 @@ extern "C" {
 #define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
 #define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
 
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_MTMS
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_MTDI
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_MTCK
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_MTDO
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_GPIO10
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_U0TXD
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_U0RXD
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_GPIO14
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_SPICS1
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_SPICS0
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_SPIQ
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_SPIWP
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_VDD_SPI
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_SPIHD
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_SPICLK
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_SPID
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
+#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
+#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
+#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_PAD_GPIO27
+#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_PAD_GPIO28
+
 #define PIN_FUNC_GPIO								1
 
 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
@@ -102,21 +132,21 @@ extern "C" {
 #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
 
 // TODO: [ESP32C5] 	IDF-8698 need check
-#define SPI_HD_GPIO_NUM              22
-#define SPI_WP_GPIO_NUM              20
-#define SPI_CS0_GPIO_NUM             18
-#define SPI_CLK_GPIO_NUM             23
-#define SPI_D_GPIO_NUM               24
-#define SPI_Q_GPIO_NUM               19
+#define SPI_HD_GPIO_NUM              20
+#define SPI_WP_GPIO_NUM              18
+#define SPI_CS0_GPIO_NUM             16
+#define SPI_CLK_GPIO_NUM             21
+#define SPI_D_GPIO_NUM               22
+#define SPI_Q_GPIO_NUM               17
 
-#define USB_INT_PHY0_DM_GPIO_NUM              25
-#define USB_INT_PHY0_DP_GPIO_NUM              26
+#define USB_INT_PHY0_DM_GPIO_NUM              13
+#define USB_INT_PHY0_DP_GPIO_NUM              14
 
 #define EXT_OSC_SLOW_GPIO_NUM        0
 
 #define MAX_RTC_GPIO_NUM              8
-#define MAX_PAD_GPIO_NUM             26
-#define MAX_GPIO_NUM                 30
+#define MAX_PAD_GPIO_NUM             28
+#define MAX_GPIO_NUM                 32
 #define DIG_IO_HOLD_BIT_SHIFT        32
 
 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
@@ -137,4107 +167,127 @@ extern "C" {
 // definitions above are inherited from previous version of code, should double check
 
 // definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_XTAL_32K_P_U                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_XTAL_32K_P_GPIO0_0                                            0
-#define FUNC_XTAL_32K_P_GPIO0                                              1
+#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P            (REG_IO_MUX_BASE + 0x0)
+#define FUNC_XTAL_32K_P_GPIO0                                            1
+#define FUNC_XTAL_32K_P_GPIO0_0                                          0
 
-#define PERIPHS_IO_MUX_XTAL_32K_N_U                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_XTAL_32K_N_GPIO1_0                                            0
-#define FUNC_XTAL_32K_N_GPIO1                                              1
+#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N            (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_N_GPIO1                                            1
+#define FUNC_XTAL_32K_N_GPIO1_0                                          0
 
-// Strapping: Boot Mode select
-#define PERIPHS_IO_MUX_MTMS_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_MTMS_MTMS                                                     0
-#define FUNC_MTMS_GPIO2                                                    1
-#define FUNC_MTMS_FSPIQ                                                    2
+#define PERIPHS_IO_MUX_U_PAD_MTMS                  (REG_IO_MUX_BASE + 0x8)
+#define FUNC_MTMS_FSPIQ                                                  2
+#define FUNC_MTMS_GPIO2                                                  1
+#define FUNC_MTMS_MTMS                                                   0
 
-// Strapping: Boot Mode select
-#define PERIPHS_IO_MUX_MTDI_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_MTDI_MTDI                                                     0
-#define FUNC_MTDI_GPIO3                                                    1
+#define PERIPHS_IO_MUX_U_PAD_MTDI                  (REG_IO_MUX_BASE + 0xC)
+#define FUNC_MTDI_GPIO3                                                  1
+#define FUNC_MTDI_MTDI                                                   0
 
-#define PERIPHS_IO_MUX_MTCK_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_MTCK_MTCK                                                     0
-#define FUNC_MTCK_GPIO4                                                    1
-#define FUNC_MTCK_FSPIHD                                                   2
+#define PERIPHS_IO_MUX_U_PAD_MTCK                 (REG_IO_MUX_BASE + 0x10)
+#define FUNC_MTCK_FSPIHD                                                 2
+#define FUNC_MTCK_GPIO4                                                  1
+#define FUNC_MTCK_MTCK                                                   0
 
-#define PERIPHS_IO_MUX_MTDO_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_MTDO_MTDO                                                     0
-#define FUNC_MTDO_GPIO5                                                    1
-#define FUNC_MTDO_FSPIWP                                                   2
+#define PERIPHS_IO_MUX_U_PAD_MTDO                 (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTDO_FSPIWP                                                 2
+#define FUNC_MTDO_GPIO5                                                  1
+#define FUNC_MTDO_MTDO                                                   0
 
-#define PERIPHS_IO_MUX_GPIO6_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO6_GPIO6_0                                                 0
-#define FUNC_GPIO6_GPIO6                                                   1
-#define FUNC_GPIO6_FSPICLK                                                 2
+#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_GPIO6_FSPICLK                                               2
+#define FUNC_GPIO6_GPIO6                                                 1
+#define FUNC_GPIO6_GPIO6_0                                               0
 
-// Strapping: JTAG sel
-#define PERIPHS_IO_MUX_GPIO7_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO7_GPIO7_0                                                 0
-#define FUNC_GPIO7_GPIO7                                                   1
-#define FUNC_GPIO7_FSPID                                                   2
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO7_FSPID                                                 2
+#define FUNC_GPIO7_GPIO7                                                 1
+#define FUNC_GPIO7_GPIO7_0                                               0
 
-#define PERIPHS_IO_MUX_GPIO8_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO8_GPIO8_0                                                 0
-#define FUNC_GPIO8_GPIO8                                                   1
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO8_GPIO8                                                 1
+#define FUNC_GPIO8_GPIO8_0                                               0
 
-#define PERIPHS_IO_MUX_GPIO9_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO9_GPIO9_0                                                 0
-#define FUNC_GPIO9_GPIO9                                                   1
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO9_GPIO9                                                 1
+#define FUNC_GPIO9_GPIO9_0                                               0
 
-#define PERIPHS_IO_MUX_GPIO10_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO10_GPIO10_0                                               0
-#define FUNC_GPIO10_GPIO10                                                 1
-#define FUNC_GPIO10_FSPICS0                                                2
+#define PERIPHS_IO_MUX_U_PAD_GPIO10               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO10_FSPICS0                                              2
+#define FUNC_GPIO10_GPIO10                                               1
+#define FUNC_GPIO10_GPIO10_0                                             0
 
-#define PERIPHS_IO_MUX_U0TXD_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_U0TXD_U0TXD                                                   0
-#define FUNC_U0TXD_GPIO11                                                  1
+#define PERIPHS_IO_MUX_U_PAD_U0TXD                (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_U0TXD_GPIO11                                                1
+#define FUNC_U0TXD_U0TXD                                                 0
 
-#define PERIPHS_IO_MUX_U0RXD_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_U0RXD_U0RXD                                                   0
-#define FUNC_U0RXD_GPIO12                                                  1
+#define PERIPHS_IO_MUX_U_PAD_U0RXD                (REG_IO_MUX_BASE + 0x30)
+#define FUNC_U0RXD_GPIO12                                                1
+#define FUNC_U0RXD_U0RXD                                                 0
 
-#define PERIPHS_IO_MUX_GPIO13_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO13_GPIO13_0                                               0
-#define FUNC_GPIO13_GPIO13                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO13_GPIO13                                               1
+#define FUNC_GPIO13_GPIO13_0                                             0
 
-#define PERIPHS_IO_MUX_GPIO14_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO14_GPIO14_0                                               0
-#define FUNC_GPIO14_GPIO14                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO14               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO14_GPIO14                                               1
+#define FUNC_GPIO14_GPIO14_0                                             0
 
-#define PERIPHS_IO_MUX_SPICS1_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPICS1_SPICS1                                                 0
-#define FUNC_SPICS1_GPIO15                                                 1
+#define PERIPHS_IO_MUX_U_PAD_SPICS1               (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_SPICS1_GPIO15                                               1
+#define FUNC_SPICS1_SPICS1                                               0
 
-#define PERIPHS_IO_MUX_SPICS0_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPICS0_SPICS0                                                 0
-#define FUNC_SPICS0_GPIO16                                                 1
+#define PERIPHS_IO_MUX_U_PAD_SPICS0               (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICS0_GPIO16                                               1
+#define FUNC_SPICS0_SPICS0                                               0
 
-#define PERIPHS_IO_MUX_SPIQ_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPIQ_SPIQ                                                     0
-#define FUNC_SPIQ_GPIO17                                                   1
+#define PERIPHS_IO_MUX_U_PAD_SPIQ                 (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPIQ_GPIO17                                                 1
+#define FUNC_SPIQ_SPIQ                                                   0
 
-#define PERIPHS_IO_MUX_SPIWP_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPIWP_SPIWP                                                   0
-#define FUNC_SPIWP_GPIO18                                                  1
+#define PERIPHS_IO_MUX_U_PAD_SPIWP                (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIWP_GPIO18                                                1
+#define FUNC_SPIWP_SPIWP                                                 0
 
-#define PERIPHS_IO_MUX_VDD_SPI_U                     (REG_IO_MUX_BASE + 0x0)
-#define FUNC_VDD_SPI_GPIO19_0                                              0
-#define FUNC_VDD_SPI_GPIO19                                                1
+#define PERIPHS_IO_MUX_U_PAD_VDD_SPI              (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_VDD_SPI_GPIO19                                              1
+#define FUNC_VDD_SPI_GPIO19_0                                            0
 
-#define PERIPHS_IO_MUX_SPIHD_U                       (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPIHD_SPIHD                                                   0
-#define FUNC_SPIHD_GPIO20                                                  1
+#define PERIPHS_IO_MUX_U_PAD_SPIHD                (REG_IO_MUX_BASE + 0x50)
+#define FUNC_SPIHD_GPIO20                                                1
+#define FUNC_SPIHD_SPIHD                                                 0
 
-#define PERIPHS_IO_MUX_SPICLK_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPICLK_SPICLK                                                 0
-#define FUNC_SPICLK_GPIO21                                                 1
+#define PERIPHS_IO_MUX_U_PAD_SPICLK               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_SPICLK_GPIO21                                               1
+#define FUNC_SPICLK_SPICLK                                               0
 
-#define PERIPHS_IO_MUX_SPID_U                        (REG_IO_MUX_BASE + 0x0)
-#define FUNC_SPID_SPID                                                     0
-#define FUNC_SPID_GPIO22                                                   1
+#define PERIPHS_IO_MUX_U_PAD_SPID                 (REG_IO_MUX_BASE + 0x58)
+#define FUNC_SPID_GPIO22                                                 1
+#define FUNC_SPID_SPID                                                   0
 
-#define PERIPHS_IO_MUX_GPIO23_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO23_GPIO23_0                                               0
-#define FUNC_GPIO23_GPIO23                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO23_GPIO23                                               1
+#define FUNC_GPIO23_GPIO23_0                                             0
 
-#define PERIPHS_IO_MUX_GPIO24_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO24_GPIO24_0                                               0
-#define FUNC_GPIO24_GPIO24                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_GPIO24_GPIO24                                               1
+#define FUNC_GPIO24_GPIO24_0                                             0
 
-#define PERIPHS_IO_MUX_GPIO25_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO25_GPIO25_0                                               0
-#define FUNC_GPIO25_GPIO25                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x64)
+#define FUNC_GPIO25_GPIO25                                               1
+#define FUNC_GPIO25_GPIO25_0                                             0
 
-// Strapping: Boot Mode select (analog mode)
-#define PERIPHS_IO_MUX_GPIO26_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO26_GPIO26_0                                               0
-#define FUNC_GPIO26_GPIO26                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x68)
+#define FUNC_GPIO26_GPIO26                                               1
+#define FUNC_GPIO26_GPIO26_0                                             0
 
-// Strapping: Boot Mode select
-#define PERIPHS_IO_MUX_GPIO27_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO27_GPIO27_0                                               0
-#define FUNC_GPIO27_GPIO27                                                 1
+#define PERIPHS_IO_MUX_U_PAD_GPIO27               (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_GPIO27_GPIO27                                               1
+#define FUNC_GPIO27_GPIO27_0                                             0
 
-// Strapping: Boot Mode select
-#define PERIPHS_IO_MUX_GPIO28_U                      (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO28_GPIO28_0                                               0
-#define FUNC_GPIO28_GPIO28                                                 1
-
-
-/** IO_MUX_GPIO0_REG register
- *  IO MUX configuration register for GPIO0
- */
-#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x0)
-/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO0 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO0_MCU_OE_M  (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S)
-#define IO_MUX_GPIO0_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_OE_S  0
-/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO0.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO0_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO0_SLP_SEL_M  (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S)
-#define IO_MUX_GPIO0_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO0_SLP_SEL_S  1
-/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO0 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO0_MCU_WPD_M  (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S)
-#define IO_MUX_GPIO0_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPD_S  2
-/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO0 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO0_MCU_WPU_M  (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S)
-#define IO_MUX_GPIO0_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPU_S  3
-/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO0 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO0_MCU_IE_M  (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S)
-#define IO_MUX_GPIO0_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_IE_S  4
-/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO0 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO0_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_M  (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S)
-#define IO_MUX_GPIO0_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_S  5
-/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO0.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO0_FUN_WPD_M  (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S)
-#define IO_MUX_GPIO0_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPD_S  7
-/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO0.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO0_FUN_WPU_M  (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S)
-#define IO_MUX_GPIO0_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPU_S  8
-/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO0.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO0_FUN_IE_M  (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S)
-#define IO_MUX_GPIO0_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_IE_S  9
-/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO0. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO0_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_M  (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S)
-#define IO_MUX_GPIO0_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_S  10
-/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO0_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_M  (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S)
-#define IO_MUX_GPIO0_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_S  12
-/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO0_FILTER_EN_M  (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S)
-#define IO_MUX_GPIO0_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO0_FILTER_EN_S  15
-/** IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO0_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO0_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO0_HYS_EN_M  (IO_MUX_GPIO0_HYS_EN_V << IO_MUX_GPIO0_HYS_EN_S)
-#define IO_MUX_GPIO0_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO0_HYS_EN_S  16
-/** IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO0. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO0_HYS_EN\\
- */
-#define IO_MUX_GPIO0_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO0_HYS_SEL_M  (IO_MUX_GPIO0_HYS_SEL_V << IO_MUX_GPIO0_HYS_SEL_S)
-#define IO_MUX_GPIO0_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO0_HYS_SEL_S  17
-
-/** IO_MUX_GPIO1_REG register
- *  IO MUX configuration register for GPIO1
- */
-#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x4)
-/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO1 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO1_MCU_OE_M  (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S)
-#define IO_MUX_GPIO1_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_OE_S  0
-/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO1.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO1_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO1_SLP_SEL_M  (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S)
-#define IO_MUX_GPIO1_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO1_SLP_SEL_S  1
-/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO1 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO1_MCU_WPD_M  (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S)
-#define IO_MUX_GPIO1_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPD_S  2
-/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO1 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO1_MCU_WPU_M  (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S)
-#define IO_MUX_GPIO1_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPU_S  3
-/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO1 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO1_MCU_IE_M  (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S)
-#define IO_MUX_GPIO1_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_IE_S  4
-/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO1 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO1_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_M  (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S)
-#define IO_MUX_GPIO1_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_S  5
-/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO1_FUN_WPD_M  (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S)
-#define IO_MUX_GPIO1_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPD_S  7
-/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO1_FUN_WPU_M  (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S)
-#define IO_MUX_GPIO1_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPU_S  8
-/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO1_FUN_IE_M  (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S)
-#define IO_MUX_GPIO1_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_IE_S  9
-/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO1. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO1_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_M  (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S)
-#define IO_MUX_GPIO1_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_S  10
-/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO1_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_M  (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S)
-#define IO_MUX_GPIO1_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_S  12
-/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO1_FILTER_EN_M  (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S)
-#define IO_MUX_GPIO1_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO1_FILTER_EN_S  15
-/** IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO1_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO1_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO1_HYS_EN_M  (IO_MUX_GPIO1_HYS_EN_V << IO_MUX_GPIO1_HYS_EN_S)
-#define IO_MUX_GPIO1_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO1_HYS_EN_S  16
-/** IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO1. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO1_HYS_EN\\
- */
-#define IO_MUX_GPIO1_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO1_HYS_SEL_M  (IO_MUX_GPIO1_HYS_SEL_V << IO_MUX_GPIO1_HYS_SEL_S)
-#define IO_MUX_GPIO1_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO1_HYS_SEL_S  17
-
-/** IO_MUX_GPIO2_REG register
- *  IO MUX configuration register for GPIO2
- */
-#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0x8)
-/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO2 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO2_MCU_OE_M  (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S)
-#define IO_MUX_GPIO2_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_OE_S  0
-/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO2.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO2_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO2_SLP_SEL_M  (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S)
-#define IO_MUX_GPIO2_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO2_SLP_SEL_S  1
-/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO2 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO2_MCU_WPD_M  (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S)
-#define IO_MUX_GPIO2_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPD_S  2
-/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO2 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO2_MCU_WPU_M  (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S)
-#define IO_MUX_GPIO2_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPU_S  3
-/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO2 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO2_MCU_IE_M  (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S)
-#define IO_MUX_GPIO2_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_IE_S  4
-/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO2 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO2_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_M  (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S)
-#define IO_MUX_GPIO2_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_S  5
-/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO2.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO2_FUN_WPD_M  (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S)
-#define IO_MUX_GPIO2_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPD_S  7
-/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO2.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO2_FUN_WPU_M  (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S)
-#define IO_MUX_GPIO2_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPU_S  8
-/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO2.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO2_FUN_IE_M  (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S)
-#define IO_MUX_GPIO2_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_IE_S  9
-/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO2. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO2_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_M  (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S)
-#define IO_MUX_GPIO2_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_S  10
-/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO2_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_M  (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S)
-#define IO_MUX_GPIO2_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_S  12
-/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO2_FILTER_EN_M  (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S)
-#define IO_MUX_GPIO2_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO2_FILTER_EN_S  15
-/** IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO2_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO2_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO2_HYS_EN_M  (IO_MUX_GPIO2_HYS_EN_V << IO_MUX_GPIO2_HYS_EN_S)
-#define IO_MUX_GPIO2_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO2_HYS_EN_S  16
-/** IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO2. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO2_HYS_EN\\
- */
-#define IO_MUX_GPIO2_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO2_HYS_SEL_M  (IO_MUX_GPIO2_HYS_SEL_V << IO_MUX_GPIO2_HYS_SEL_S)
-#define IO_MUX_GPIO2_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO2_HYS_SEL_S  17
-
-/** IO_MUX_GPIO3_REG register
- *  IO MUX configuration register for GPIO3
- */
-#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0xc)
-/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO3 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO3_MCU_OE_M  (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S)
-#define IO_MUX_GPIO3_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_OE_S  0
-/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO3.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO3_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO3_SLP_SEL_M  (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S)
-#define IO_MUX_GPIO3_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO3_SLP_SEL_S  1
-/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO3 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO3_MCU_WPD_M  (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S)
-#define IO_MUX_GPIO3_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPD_S  2
-/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO3 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO3_MCU_WPU_M  (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S)
-#define IO_MUX_GPIO3_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPU_S  3
-/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO3 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO3_MCU_IE_M  (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S)
-#define IO_MUX_GPIO3_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_IE_S  4
-/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO3 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO3_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_M  (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S)
-#define IO_MUX_GPIO3_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_S  5
-/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO3.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO3_FUN_WPD_M  (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S)
-#define IO_MUX_GPIO3_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPD_S  7
-/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO3.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO3_FUN_WPU_M  (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S)
-#define IO_MUX_GPIO3_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPU_S  8
-/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO3.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO3_FUN_IE_M  (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S)
-#define IO_MUX_GPIO3_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_IE_S  9
-/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO3. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO3_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_M  (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S)
-#define IO_MUX_GPIO3_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_S  10
-/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO3_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_M  (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S)
-#define IO_MUX_GPIO3_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_S  12
-/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO3_FILTER_EN_M  (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S)
-#define IO_MUX_GPIO3_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO3_FILTER_EN_S  15
-/** IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO3_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO3_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO3_HYS_EN_M  (IO_MUX_GPIO3_HYS_EN_V << IO_MUX_GPIO3_HYS_EN_S)
-#define IO_MUX_GPIO3_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO3_HYS_EN_S  16
-/** IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO3. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO3_HYS_EN\\
- */
-#define IO_MUX_GPIO3_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO3_HYS_SEL_M  (IO_MUX_GPIO3_HYS_SEL_V << IO_MUX_GPIO3_HYS_SEL_S)
-#define IO_MUX_GPIO3_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO3_HYS_SEL_S  17
-
-/** IO_MUX_GPIO4_REG register
- *  IO MUX configuration register for GPIO4
- */
-#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x10)
-/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO4 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO4_MCU_OE_M  (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S)
-#define IO_MUX_GPIO4_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_OE_S  0
-/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO4.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO4_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO4_SLP_SEL_M  (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S)
-#define IO_MUX_GPIO4_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO4_SLP_SEL_S  1
-/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO4 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO4_MCU_WPD_M  (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S)
-#define IO_MUX_GPIO4_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPD_S  2
-/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO4 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO4_MCU_WPU_M  (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S)
-#define IO_MUX_GPIO4_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPU_S  3
-/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO4 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO4_MCU_IE_M  (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S)
-#define IO_MUX_GPIO4_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_IE_S  4
-/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO4 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO4_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_M  (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S)
-#define IO_MUX_GPIO4_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_S  5
-/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO4.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO4_FUN_WPD_M  (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S)
-#define IO_MUX_GPIO4_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPD_S  7
-/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO4.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO4_FUN_WPU_M  (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S)
-#define IO_MUX_GPIO4_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPU_S  8
-/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO4.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO4_FUN_IE_M  (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S)
-#define IO_MUX_GPIO4_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_IE_S  9
-/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO4. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO4_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_M  (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S)
-#define IO_MUX_GPIO4_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_S  10
-/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO4_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_M  (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S)
-#define IO_MUX_GPIO4_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_S  12
-/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO4_FILTER_EN_M  (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S)
-#define IO_MUX_GPIO4_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO4_FILTER_EN_S  15
-/** IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO4_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO4_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO4_HYS_EN_M  (IO_MUX_GPIO4_HYS_EN_V << IO_MUX_GPIO4_HYS_EN_S)
-#define IO_MUX_GPIO4_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO4_HYS_EN_S  16
-/** IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO4. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO4_HYS_EN\\
- */
-#define IO_MUX_GPIO4_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO4_HYS_SEL_M  (IO_MUX_GPIO4_HYS_SEL_V << IO_MUX_GPIO4_HYS_SEL_S)
-#define IO_MUX_GPIO4_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO4_HYS_SEL_S  17
-
-/** IO_MUX_GPIO5_REG register
- *  IO MUX configuration register for GPIO5
- */
-#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x14)
-/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO5 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO5_MCU_OE_M  (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S)
-#define IO_MUX_GPIO5_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_OE_S  0
-/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO5.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO5_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO5_SLP_SEL_M  (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S)
-#define IO_MUX_GPIO5_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO5_SLP_SEL_S  1
-/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO5 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO5_MCU_WPD_M  (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S)
-#define IO_MUX_GPIO5_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPD_S  2
-/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO5 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO5_MCU_WPU_M  (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S)
-#define IO_MUX_GPIO5_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPU_S  3
-/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO5 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO5_MCU_IE_M  (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S)
-#define IO_MUX_GPIO5_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_IE_S  4
-/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO5 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO5_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_M  (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S)
-#define IO_MUX_GPIO5_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_S  5
-/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO5.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO5_FUN_WPD_M  (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S)
-#define IO_MUX_GPIO5_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPD_S  7
-/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO5.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO5_FUN_WPU_M  (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S)
-#define IO_MUX_GPIO5_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPU_S  8
-/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO5.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO5_FUN_IE_M  (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S)
-#define IO_MUX_GPIO5_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_IE_S  9
-/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO5. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO5_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_M  (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S)
-#define IO_MUX_GPIO5_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_S  10
-/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO5_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_M  (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S)
-#define IO_MUX_GPIO5_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_S  12
-/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO5_FILTER_EN_M  (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S)
-#define IO_MUX_GPIO5_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO5_FILTER_EN_S  15
-/** IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO5_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO5_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO5_HYS_EN_M  (IO_MUX_GPIO5_HYS_EN_V << IO_MUX_GPIO5_HYS_EN_S)
-#define IO_MUX_GPIO5_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO5_HYS_EN_S  16
-/** IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO5. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO5_HYS_EN\\
- */
-#define IO_MUX_GPIO5_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO5_HYS_SEL_M  (IO_MUX_GPIO5_HYS_SEL_V << IO_MUX_GPIO5_HYS_SEL_S)
-#define IO_MUX_GPIO5_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO5_HYS_SEL_S  17
-
-/** IO_MUX_GPIO6_REG register
- *  IO MUX configuration register for GPIO6
- */
-#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x18)
-/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO6 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO6_MCU_OE_M  (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S)
-#define IO_MUX_GPIO6_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_OE_S  0
-/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO6.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO6_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO6_SLP_SEL_M  (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S)
-#define IO_MUX_GPIO6_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO6_SLP_SEL_S  1
-/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO6 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO6_MCU_WPD_M  (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S)
-#define IO_MUX_GPIO6_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPD_S  2
-/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO6 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO6_MCU_WPU_M  (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S)
-#define IO_MUX_GPIO6_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPU_S  3
-/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO6 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO6_MCU_IE_M  (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S)
-#define IO_MUX_GPIO6_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_IE_S  4
-/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO6 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO6_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_M  (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S)
-#define IO_MUX_GPIO6_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_S  5
-/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO6.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO6_FUN_WPD_M  (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S)
-#define IO_MUX_GPIO6_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPD_S  7
-/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO6.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO6_FUN_WPU_M  (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S)
-#define IO_MUX_GPIO6_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPU_S  8
-/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO6.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO6_FUN_IE_M  (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S)
-#define IO_MUX_GPIO6_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_IE_S  9
-/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO6. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO6_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_M  (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S)
-#define IO_MUX_GPIO6_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_S  10
-/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO6_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_M  (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S)
-#define IO_MUX_GPIO6_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_S  12
-/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO6_FILTER_EN_M  (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S)
-#define IO_MUX_GPIO6_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO6_FILTER_EN_S  15
-/** IO_MUX_GPIO6_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO6_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO6_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO6_HYS_EN_M  (IO_MUX_GPIO6_HYS_EN_V << IO_MUX_GPIO6_HYS_EN_S)
-#define IO_MUX_GPIO6_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO6_HYS_EN_S  16
-/** IO_MUX_GPIO6_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO6. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO6_HYS_EN\\
- */
-#define IO_MUX_GPIO6_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO6_HYS_SEL_M  (IO_MUX_GPIO6_HYS_SEL_V << IO_MUX_GPIO6_HYS_SEL_S)
-#define IO_MUX_GPIO6_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO6_HYS_SEL_S  17
-
-/** IO_MUX_GPIO7_REG register
- *  IO MUX configuration register for GPIO7
- */
-#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x1c)
-/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO7 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO7_MCU_OE_M  (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S)
-#define IO_MUX_GPIO7_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_OE_S  0
-/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO7.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO7_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO7_SLP_SEL_M  (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S)
-#define IO_MUX_GPIO7_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO7_SLP_SEL_S  1
-/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO7 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO7_MCU_WPD_M  (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S)
-#define IO_MUX_GPIO7_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPD_S  2
-/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO7 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO7_MCU_WPU_M  (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S)
-#define IO_MUX_GPIO7_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPU_S  3
-/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO7 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO7_MCU_IE_M  (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S)
-#define IO_MUX_GPIO7_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_IE_S  4
-/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO7 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO7_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_M  (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S)
-#define IO_MUX_GPIO7_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_S  5
-/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO7.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO7_FUN_WPD_M  (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S)
-#define IO_MUX_GPIO7_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPD_S  7
-/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO7.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO7_FUN_WPU_M  (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S)
-#define IO_MUX_GPIO7_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPU_S  8
-/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO7.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO7_FUN_IE_M  (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S)
-#define IO_MUX_GPIO7_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_IE_S  9
-/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO7. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO7_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_M  (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S)
-#define IO_MUX_GPIO7_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_S  10
-/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO7_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_M  (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S)
-#define IO_MUX_GPIO7_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_S  12
-/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO7_FILTER_EN_M  (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S)
-#define IO_MUX_GPIO7_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO7_FILTER_EN_S  15
-/** IO_MUX_GPIO7_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO7_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO7_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO7_HYS_EN_M  (IO_MUX_GPIO7_HYS_EN_V << IO_MUX_GPIO7_HYS_EN_S)
-#define IO_MUX_GPIO7_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO7_HYS_EN_S  16
-/** IO_MUX_GPIO7_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO7. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO7_HYS_EN\\
- */
-#define IO_MUX_GPIO7_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO7_HYS_SEL_M  (IO_MUX_GPIO7_HYS_SEL_V << IO_MUX_GPIO7_HYS_SEL_S)
-#define IO_MUX_GPIO7_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO7_HYS_SEL_S  17
-
-/** IO_MUX_GPIO8_REG register
- *  IO MUX configuration register for GPIO8
- */
-#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x20)
-/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO8 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO8_MCU_OE_M  (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S)
-#define IO_MUX_GPIO8_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_OE_S  0
-/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO8.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO8_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO8_SLP_SEL_M  (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S)
-#define IO_MUX_GPIO8_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO8_SLP_SEL_S  1
-/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO8 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO8_MCU_WPD_M  (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S)
-#define IO_MUX_GPIO8_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPD_S  2
-/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO8 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO8_MCU_WPU_M  (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S)
-#define IO_MUX_GPIO8_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPU_S  3
-/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO8 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO8_MCU_IE_M  (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S)
-#define IO_MUX_GPIO8_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_IE_S  4
-/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO8 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO8_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_M  (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S)
-#define IO_MUX_GPIO8_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_S  5
-/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO8.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO8_FUN_WPD_M  (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S)
-#define IO_MUX_GPIO8_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPD_S  7
-/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO8.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO8_FUN_WPU_M  (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S)
-#define IO_MUX_GPIO8_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPU_S  8
-/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO8.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO8_FUN_IE_M  (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S)
-#define IO_MUX_GPIO8_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_IE_S  9
-/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO8. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO8_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_M  (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S)
-#define IO_MUX_GPIO8_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_S  10
-/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO8_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_M  (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S)
-#define IO_MUX_GPIO8_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_S  12
-/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO8_FILTER_EN_M  (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S)
-#define IO_MUX_GPIO8_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO8_FILTER_EN_S  15
-/** IO_MUX_GPIO8_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO8_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO8_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO8_HYS_EN_M  (IO_MUX_GPIO8_HYS_EN_V << IO_MUX_GPIO8_HYS_EN_S)
-#define IO_MUX_GPIO8_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO8_HYS_EN_S  16
-/** IO_MUX_GPIO8_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO8. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO8_HYS_EN\\
- */
-#define IO_MUX_GPIO8_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO8_HYS_SEL_M  (IO_MUX_GPIO8_HYS_SEL_V << IO_MUX_GPIO8_HYS_SEL_S)
-#define IO_MUX_GPIO8_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO8_HYS_SEL_S  17
-
-/** IO_MUX_GPIO9_REG register
- *  IO MUX configuration register for GPIO9
- */
-#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x24)
-/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO9 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO9_MCU_OE_M  (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S)
-#define IO_MUX_GPIO9_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_OE_S  0
-/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO9.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO9_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO9_SLP_SEL_M  (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S)
-#define IO_MUX_GPIO9_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO9_SLP_SEL_S  1
-/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO9 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO9_MCU_WPD_M  (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S)
-#define IO_MUX_GPIO9_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPD_S  2
-/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO9 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO9_MCU_WPU_M  (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S)
-#define IO_MUX_GPIO9_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPU_S  3
-/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO9 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO9_MCU_IE_M  (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S)
-#define IO_MUX_GPIO9_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_IE_S  4
-/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO9 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO9_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_M  (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S)
-#define IO_MUX_GPIO9_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_S  5
-/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO9.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO9_FUN_WPD_M  (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S)
-#define IO_MUX_GPIO9_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPD_S  7
-/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO9.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO9_FUN_WPU_M  (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S)
-#define IO_MUX_GPIO9_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPU_S  8
-/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO9.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO9_FUN_IE_M  (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S)
-#define IO_MUX_GPIO9_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_IE_S  9
-/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO9. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO9_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_M  (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S)
-#define IO_MUX_GPIO9_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_S  10
-/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO9_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_M  (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S)
-#define IO_MUX_GPIO9_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_S  12
-/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO9_FILTER_EN_M  (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S)
-#define IO_MUX_GPIO9_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO9_FILTER_EN_S  15
-/** IO_MUX_GPIO9_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO9_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO9_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO9_HYS_EN_M  (IO_MUX_GPIO9_HYS_EN_V << IO_MUX_GPIO9_HYS_EN_S)
-#define IO_MUX_GPIO9_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO9_HYS_EN_S  16
-/** IO_MUX_GPIO9_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO9. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO9_HYS_EN\\
- */
-#define IO_MUX_GPIO9_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO9_HYS_SEL_M  (IO_MUX_GPIO9_HYS_SEL_V << IO_MUX_GPIO9_HYS_SEL_S)
-#define IO_MUX_GPIO9_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO9_HYS_SEL_S  17
-
-/** IO_MUX_GPIO10_REG register
- *  IO MUX configuration register for GPIO10
- */
-#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x28)
-/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO10 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO10_MCU_OE_M  (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S)
-#define IO_MUX_GPIO10_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_OE_S  0
-/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO10.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO10_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO10_SLP_SEL_M  (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S)
-#define IO_MUX_GPIO10_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO10_SLP_SEL_S  1
-/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO10 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO10_MCU_WPD_M  (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S)
-#define IO_MUX_GPIO10_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPD_S  2
-/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO10 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO10_MCU_WPU_M  (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S)
-#define IO_MUX_GPIO10_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPU_S  3
-/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO10 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO10_MCU_IE_M  (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S)
-#define IO_MUX_GPIO10_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_IE_S  4
-/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO10 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO10_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_M  (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S)
-#define IO_MUX_GPIO10_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_S  5
-/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO10.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO10_FUN_WPD_M  (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S)
-#define IO_MUX_GPIO10_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPD_S  7
-/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO10.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO10_FUN_WPU_M  (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S)
-#define IO_MUX_GPIO10_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPU_S  8
-/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO10.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO10_FUN_IE_M  (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S)
-#define IO_MUX_GPIO10_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_IE_S  9
-/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO10. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO10_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_M  (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S)
-#define IO_MUX_GPIO10_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_S  10
-/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO10_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_M  (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S)
-#define IO_MUX_GPIO10_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_S  12
-/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO10_FILTER_EN_M  (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S)
-#define IO_MUX_GPIO10_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO10_FILTER_EN_S  15
-/** IO_MUX_GPIO10_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO10_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO10_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO10_HYS_EN_M  (IO_MUX_GPIO10_HYS_EN_V << IO_MUX_GPIO10_HYS_EN_S)
-#define IO_MUX_GPIO10_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO10_HYS_EN_S  16
-/** IO_MUX_GPIO10_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO10. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO10_HYS_EN\\
- */
-#define IO_MUX_GPIO10_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO10_HYS_SEL_M  (IO_MUX_GPIO10_HYS_SEL_V << IO_MUX_GPIO10_HYS_SEL_S)
-#define IO_MUX_GPIO10_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO10_HYS_SEL_S  17
-
-/** IO_MUX_GPIO11_REG register
- *  IO MUX configuration register for GPIO11
- */
-#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x2c)
-/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO11 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO11_MCU_OE_M  (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S)
-#define IO_MUX_GPIO11_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_OE_S  0
-/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO11.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO11_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO11_SLP_SEL_M  (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S)
-#define IO_MUX_GPIO11_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO11_SLP_SEL_S  1
-/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO11 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO11_MCU_WPD_M  (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S)
-#define IO_MUX_GPIO11_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPD_S  2
-/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO11 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO11_MCU_WPU_M  (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S)
-#define IO_MUX_GPIO11_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPU_S  3
-/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO11 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO11_MCU_IE_M  (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S)
-#define IO_MUX_GPIO11_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_IE_S  4
-/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO11 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO11_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_M  (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S)
-#define IO_MUX_GPIO11_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_S  5
-/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO11.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO11_FUN_WPD_M  (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S)
-#define IO_MUX_GPIO11_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPD_S  7
-/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO11.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO11_FUN_WPU_M  (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S)
-#define IO_MUX_GPIO11_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPU_S  8
-/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO11.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO11_FUN_IE_M  (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S)
-#define IO_MUX_GPIO11_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_IE_S  9
-/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO11. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO11_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_M  (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S)
-#define IO_MUX_GPIO11_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_S  10
-/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO11_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_M  (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S)
-#define IO_MUX_GPIO11_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_S  12
-/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO11_FILTER_EN_M  (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S)
-#define IO_MUX_GPIO11_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO11_FILTER_EN_S  15
-/** IO_MUX_GPIO11_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO11_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO11_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO11_HYS_EN_M  (IO_MUX_GPIO11_HYS_EN_V << IO_MUX_GPIO11_HYS_EN_S)
-#define IO_MUX_GPIO11_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO11_HYS_EN_S  16
-/** IO_MUX_GPIO11_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO11. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO11_HYS_EN\\
- */
-#define IO_MUX_GPIO11_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO11_HYS_SEL_M  (IO_MUX_GPIO11_HYS_SEL_V << IO_MUX_GPIO11_HYS_SEL_S)
-#define IO_MUX_GPIO11_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO11_HYS_SEL_S  17
-
-/** IO_MUX_GPIO12_REG register
- *  IO MUX configuration register for GPIO12
- */
-#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x30)
-/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO12 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO12_MCU_OE_M  (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S)
-#define IO_MUX_GPIO12_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_OE_S  0
-/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO12.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO12_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO12_SLP_SEL_M  (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S)
-#define IO_MUX_GPIO12_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO12_SLP_SEL_S  1
-/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO12 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO12_MCU_WPD_M  (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S)
-#define IO_MUX_GPIO12_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPD_S  2
-/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO12 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO12_MCU_WPU_M  (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S)
-#define IO_MUX_GPIO12_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPU_S  3
-/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO12 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO12_MCU_IE_M  (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S)
-#define IO_MUX_GPIO12_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_IE_S  4
-/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO12 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO12_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_M  (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S)
-#define IO_MUX_GPIO12_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_S  5
-/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO12.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO12_FUN_WPD_M  (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S)
-#define IO_MUX_GPIO12_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPD_S  7
-/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO12.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO12_FUN_WPU_M  (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S)
-#define IO_MUX_GPIO12_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPU_S  8
-/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO12.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO12_FUN_IE_M  (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S)
-#define IO_MUX_GPIO12_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_IE_S  9
-/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO12. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO12_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_M  (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S)
-#define IO_MUX_GPIO12_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_S  10
-/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO12_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_M  (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S)
-#define IO_MUX_GPIO12_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_S  12
-/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO12_FILTER_EN_M  (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S)
-#define IO_MUX_GPIO12_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO12_FILTER_EN_S  15
-/** IO_MUX_GPIO12_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO12_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO12_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO12_HYS_EN_M  (IO_MUX_GPIO12_HYS_EN_V << IO_MUX_GPIO12_HYS_EN_S)
-#define IO_MUX_GPIO12_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO12_HYS_EN_S  16
-/** IO_MUX_GPIO12_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO12. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO12_HYS_EN\\
- */
-#define IO_MUX_GPIO12_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO12_HYS_SEL_M  (IO_MUX_GPIO12_HYS_SEL_V << IO_MUX_GPIO12_HYS_SEL_S)
-#define IO_MUX_GPIO12_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO12_HYS_SEL_S  17
-
-/** IO_MUX_GPIO13_REG register
- *  IO MUX configuration register for GPIO13
- */
-#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x34)
-/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO13 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO13_MCU_OE_M  (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S)
-#define IO_MUX_GPIO13_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_OE_S  0
-/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO13.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO13_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO13_SLP_SEL_M  (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S)
-#define IO_MUX_GPIO13_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO13_SLP_SEL_S  1
-/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO13 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO13_MCU_WPD_M  (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S)
-#define IO_MUX_GPIO13_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPD_S  2
-/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO13 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO13_MCU_WPU_M  (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S)
-#define IO_MUX_GPIO13_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPU_S  3
-/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO13 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO13_MCU_IE_M  (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S)
-#define IO_MUX_GPIO13_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_IE_S  4
-/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO13 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO13_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_M  (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S)
-#define IO_MUX_GPIO13_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_S  5
-/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO13.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO13_FUN_WPD_M  (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S)
-#define IO_MUX_GPIO13_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPD_S  7
-/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO13.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO13_FUN_WPU_M  (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S)
-#define IO_MUX_GPIO13_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPU_S  8
-/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO13.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO13_FUN_IE_M  (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S)
-#define IO_MUX_GPIO13_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_IE_S  9
-/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO13. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO13_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_M  (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S)
-#define IO_MUX_GPIO13_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_S  10
-/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO13_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_M  (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S)
-#define IO_MUX_GPIO13_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_S  12
-/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO13_FILTER_EN_M  (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S)
-#define IO_MUX_GPIO13_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO13_FILTER_EN_S  15
-/** IO_MUX_GPIO13_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO13_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO13_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO13_HYS_EN_M  (IO_MUX_GPIO13_HYS_EN_V << IO_MUX_GPIO13_HYS_EN_S)
-#define IO_MUX_GPIO13_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO13_HYS_EN_S  16
-/** IO_MUX_GPIO13_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO13. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO13_HYS_EN\\
- */
-#define IO_MUX_GPIO13_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO13_HYS_SEL_M  (IO_MUX_GPIO13_HYS_SEL_V << IO_MUX_GPIO13_HYS_SEL_S)
-#define IO_MUX_GPIO13_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO13_HYS_SEL_S  17
-
-/** IO_MUX_GPIO14_REG register
- *  IO MUX configuration register for GPIO14
- */
-#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x38)
-/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO14 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO14_MCU_OE_M  (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S)
-#define IO_MUX_GPIO14_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_OE_S  0
-/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO14.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO14_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO14_SLP_SEL_M  (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S)
-#define IO_MUX_GPIO14_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO14_SLP_SEL_S  1
-/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO14 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO14_MCU_WPD_M  (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S)
-#define IO_MUX_GPIO14_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPD_S  2
-/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO14 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO14_MCU_WPU_M  (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S)
-#define IO_MUX_GPIO14_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPU_S  3
-/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO14 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO14_MCU_IE_M  (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S)
-#define IO_MUX_GPIO14_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_IE_S  4
-/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO14 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO14_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_M  (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S)
-#define IO_MUX_GPIO14_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_S  5
-/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO14.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO14_FUN_WPD_M  (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S)
-#define IO_MUX_GPIO14_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPD_S  7
-/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO14.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO14_FUN_WPU_M  (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S)
-#define IO_MUX_GPIO14_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPU_S  8
-/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO14.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO14_FUN_IE_M  (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S)
-#define IO_MUX_GPIO14_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_IE_S  9
-/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO14. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO14_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_M  (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S)
-#define IO_MUX_GPIO14_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_S  10
-/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO14_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_M  (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S)
-#define IO_MUX_GPIO14_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_S  12
-/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO14_FILTER_EN_M  (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S)
-#define IO_MUX_GPIO14_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO14_FILTER_EN_S  15
-/** IO_MUX_GPIO14_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO14_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO14_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO14_HYS_EN_M  (IO_MUX_GPIO14_HYS_EN_V << IO_MUX_GPIO14_HYS_EN_S)
-#define IO_MUX_GPIO14_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO14_HYS_EN_S  16
-/** IO_MUX_GPIO14_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO14. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO14_HYS_EN\\
- */
-#define IO_MUX_GPIO14_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO14_HYS_SEL_M  (IO_MUX_GPIO14_HYS_SEL_V << IO_MUX_GPIO14_HYS_SEL_S)
-#define IO_MUX_GPIO14_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO14_HYS_SEL_S  17
-
-/** IO_MUX_GPIO15_REG register
- *  IO MUX configuration register for GPIO15
- */
-#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x3c)
-/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO15 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO15_MCU_OE_M  (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S)
-#define IO_MUX_GPIO15_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_OE_S  0
-/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO15.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO15_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO15_SLP_SEL_M  (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S)
-#define IO_MUX_GPIO15_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO15_SLP_SEL_S  1
-/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO15 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO15_MCU_WPD_M  (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S)
-#define IO_MUX_GPIO15_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPD_S  2
-/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO15 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO15_MCU_WPU_M  (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S)
-#define IO_MUX_GPIO15_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPU_S  3
-/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO15 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO15_MCU_IE_M  (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S)
-#define IO_MUX_GPIO15_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_IE_S  4
-/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO15 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO15_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_M  (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S)
-#define IO_MUX_GPIO15_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_S  5
-/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO15.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO15_FUN_WPD_M  (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S)
-#define IO_MUX_GPIO15_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPD_S  7
-/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO15.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO15_FUN_WPU_M  (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S)
-#define IO_MUX_GPIO15_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPU_S  8
-/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO15.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO15_FUN_IE_M  (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S)
-#define IO_MUX_GPIO15_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_IE_S  9
-/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO15. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO15_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_M  (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S)
-#define IO_MUX_GPIO15_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_S  10
-/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO15_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_M  (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S)
-#define IO_MUX_GPIO15_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_S  12
-/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO15_FILTER_EN_M  (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S)
-#define IO_MUX_GPIO15_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO15_FILTER_EN_S  15
-/** IO_MUX_GPIO15_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO15_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO15_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO15_HYS_EN_M  (IO_MUX_GPIO15_HYS_EN_V << IO_MUX_GPIO15_HYS_EN_S)
-#define IO_MUX_GPIO15_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO15_HYS_EN_S  16
-/** IO_MUX_GPIO15_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO15. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO15_HYS_EN\\
- */
-#define IO_MUX_GPIO15_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO15_HYS_SEL_M  (IO_MUX_GPIO15_HYS_SEL_V << IO_MUX_GPIO15_HYS_SEL_S)
-#define IO_MUX_GPIO15_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO15_HYS_SEL_S  17
-
-/** IO_MUX_GPIO16_REG register
- *  IO MUX configuration register for GPIO16
- */
-#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x40)
-/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO16 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO16_MCU_OE_M  (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S)
-#define IO_MUX_GPIO16_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_OE_S  0
-/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO16.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO16_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO16_SLP_SEL_M  (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S)
-#define IO_MUX_GPIO16_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO16_SLP_SEL_S  1
-/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO16 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO16_MCU_WPD_M  (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S)
-#define IO_MUX_GPIO16_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPD_S  2
-/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO16 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO16_MCU_WPU_M  (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S)
-#define IO_MUX_GPIO16_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPU_S  3
-/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO16 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO16_MCU_IE_M  (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S)
-#define IO_MUX_GPIO16_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_IE_S  4
-/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO16 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO16_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_M  (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S)
-#define IO_MUX_GPIO16_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_S  5
-/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO16.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO16_FUN_WPD_M  (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S)
-#define IO_MUX_GPIO16_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPD_S  7
-/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO16.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO16_FUN_WPU_M  (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S)
-#define IO_MUX_GPIO16_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPU_S  8
-/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO16.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO16_FUN_IE_M  (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S)
-#define IO_MUX_GPIO16_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_IE_S  9
-/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO16. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO16_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_M  (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S)
-#define IO_MUX_GPIO16_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_S  10
-/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO16_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_M  (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S)
-#define IO_MUX_GPIO16_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_S  12
-/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO16_FILTER_EN_M  (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S)
-#define IO_MUX_GPIO16_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO16_FILTER_EN_S  15
-/** IO_MUX_GPIO16_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO16_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO16_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO16_HYS_EN_M  (IO_MUX_GPIO16_HYS_EN_V << IO_MUX_GPIO16_HYS_EN_S)
-#define IO_MUX_GPIO16_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO16_HYS_EN_S  16
-/** IO_MUX_GPIO16_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO16. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO16_HYS_EN\\
- */
-#define IO_MUX_GPIO16_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO16_HYS_SEL_M  (IO_MUX_GPIO16_HYS_SEL_V << IO_MUX_GPIO16_HYS_SEL_S)
-#define IO_MUX_GPIO16_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO16_HYS_SEL_S  17
-
-/** IO_MUX_GPIO17_REG register
- *  IO MUX configuration register for GPIO17
- */
-#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x44)
-/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO17 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO17_MCU_OE_M  (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S)
-#define IO_MUX_GPIO17_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_OE_S  0
-/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO17.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO17_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO17_SLP_SEL_M  (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S)
-#define IO_MUX_GPIO17_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO17_SLP_SEL_S  1
-/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO17 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO17_MCU_WPD_M  (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S)
-#define IO_MUX_GPIO17_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPD_S  2
-/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO17 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO17_MCU_WPU_M  (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S)
-#define IO_MUX_GPIO17_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPU_S  3
-/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO17 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO17_MCU_IE_M  (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S)
-#define IO_MUX_GPIO17_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_IE_S  4
-/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO17 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO17_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_M  (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S)
-#define IO_MUX_GPIO17_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_S  5
-/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO17.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO17_FUN_WPD_M  (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S)
-#define IO_MUX_GPIO17_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPD_S  7
-/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO17.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO17_FUN_WPU_M  (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S)
-#define IO_MUX_GPIO17_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPU_S  8
-/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO17.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO17_FUN_IE_M  (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S)
-#define IO_MUX_GPIO17_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_IE_S  9
-/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO17. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO17_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_M  (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S)
-#define IO_MUX_GPIO17_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_S  10
-/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO17_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_M  (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S)
-#define IO_MUX_GPIO17_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_S  12
-/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO17_FILTER_EN_M  (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S)
-#define IO_MUX_GPIO17_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO17_FILTER_EN_S  15
-/** IO_MUX_GPIO17_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO17_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO17_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO17_HYS_EN_M  (IO_MUX_GPIO17_HYS_EN_V << IO_MUX_GPIO17_HYS_EN_S)
-#define IO_MUX_GPIO17_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO17_HYS_EN_S  16
-/** IO_MUX_GPIO17_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO17. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO17_HYS_EN\\
- */
-#define IO_MUX_GPIO17_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO17_HYS_SEL_M  (IO_MUX_GPIO17_HYS_SEL_V << IO_MUX_GPIO17_HYS_SEL_S)
-#define IO_MUX_GPIO17_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO17_HYS_SEL_S  17
-
-/** IO_MUX_GPIO18_REG register
- *  IO MUX configuration register for GPIO18
- */
-#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x48)
-/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO18 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO18_MCU_OE_M  (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S)
-#define IO_MUX_GPIO18_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_OE_S  0
-/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO18.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO18_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO18_SLP_SEL_M  (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S)
-#define IO_MUX_GPIO18_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO18_SLP_SEL_S  1
-/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO18 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO18_MCU_WPD_M  (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S)
-#define IO_MUX_GPIO18_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPD_S  2
-/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO18 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO18_MCU_WPU_M  (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S)
-#define IO_MUX_GPIO18_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPU_S  3
-/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO18 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO18_MCU_IE_M  (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S)
-#define IO_MUX_GPIO18_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_IE_S  4
-/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO18 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO18_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_M  (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S)
-#define IO_MUX_GPIO18_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_S  5
-/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO18.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO18_FUN_WPD_M  (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S)
-#define IO_MUX_GPIO18_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPD_S  7
-/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO18.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO18_FUN_WPU_M  (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S)
-#define IO_MUX_GPIO18_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPU_S  8
-/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO18.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO18_FUN_IE_M  (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S)
-#define IO_MUX_GPIO18_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_IE_S  9
-/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO18. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO18_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_M  (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S)
-#define IO_MUX_GPIO18_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_S  10
-/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO18_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_M  (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S)
-#define IO_MUX_GPIO18_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_S  12
-/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO18_FILTER_EN_M  (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S)
-#define IO_MUX_GPIO18_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO18_FILTER_EN_S  15
-/** IO_MUX_GPIO18_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO18_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO18_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO18_HYS_EN_M  (IO_MUX_GPIO18_HYS_EN_V << IO_MUX_GPIO18_HYS_EN_S)
-#define IO_MUX_GPIO18_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO18_HYS_EN_S  16
-/** IO_MUX_GPIO18_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO18. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO18_HYS_EN\\
- */
-#define IO_MUX_GPIO18_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO18_HYS_SEL_M  (IO_MUX_GPIO18_HYS_SEL_V << IO_MUX_GPIO18_HYS_SEL_S)
-#define IO_MUX_GPIO18_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO18_HYS_SEL_S  17
-
-/** IO_MUX_GPIO19_REG register
- *  IO MUX configuration register for GPIO19
- */
-#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x4c)
-/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO19 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO19_MCU_OE_M  (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S)
-#define IO_MUX_GPIO19_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_OE_S  0
-/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO19.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO19_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO19_SLP_SEL_M  (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S)
-#define IO_MUX_GPIO19_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO19_SLP_SEL_S  1
-/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO19 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO19_MCU_WPD_M  (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S)
-#define IO_MUX_GPIO19_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPD_S  2
-/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO19 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO19_MCU_WPU_M  (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S)
-#define IO_MUX_GPIO19_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPU_S  3
-/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO19 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO19_MCU_IE_M  (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S)
-#define IO_MUX_GPIO19_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_IE_S  4
-/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO19 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO19_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_M  (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S)
-#define IO_MUX_GPIO19_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_S  5
-/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO19.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO19_FUN_WPD_M  (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S)
-#define IO_MUX_GPIO19_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPD_S  7
-/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO19.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO19_FUN_WPU_M  (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S)
-#define IO_MUX_GPIO19_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPU_S  8
-/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO19.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO19_FUN_IE_M  (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S)
-#define IO_MUX_GPIO19_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_IE_S  9
-/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO19. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO19_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_M  (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S)
-#define IO_MUX_GPIO19_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_S  10
-/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO19_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_M  (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S)
-#define IO_MUX_GPIO19_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_S  12
-/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO19_FILTER_EN_M  (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S)
-#define IO_MUX_GPIO19_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO19_FILTER_EN_S  15
-/** IO_MUX_GPIO19_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO19_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO19_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO19_HYS_EN_M  (IO_MUX_GPIO19_HYS_EN_V << IO_MUX_GPIO19_HYS_EN_S)
-#define IO_MUX_GPIO19_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO19_HYS_EN_S  16
-/** IO_MUX_GPIO19_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO19. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO19_HYS_EN\\
- */
-#define IO_MUX_GPIO19_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO19_HYS_SEL_M  (IO_MUX_GPIO19_HYS_SEL_V << IO_MUX_GPIO19_HYS_SEL_S)
-#define IO_MUX_GPIO19_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO19_HYS_SEL_S  17
-
-/** IO_MUX_GPIO20_REG register
- *  IO MUX configuration register for GPIO20
- */
-#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x50)
-/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO20 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO20_MCU_OE_M  (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S)
-#define IO_MUX_GPIO20_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_OE_S  0
-/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO20.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO20_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO20_SLP_SEL_M  (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S)
-#define IO_MUX_GPIO20_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO20_SLP_SEL_S  1
-/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO20 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO20_MCU_WPD_M  (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S)
-#define IO_MUX_GPIO20_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPD_S  2
-/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO20 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO20_MCU_WPU_M  (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S)
-#define IO_MUX_GPIO20_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPU_S  3
-/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO20 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO20_MCU_IE_M  (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S)
-#define IO_MUX_GPIO20_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_IE_S  4
-/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO20 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO20_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_M  (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S)
-#define IO_MUX_GPIO20_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_S  5
-/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO20.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO20_FUN_WPD_M  (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S)
-#define IO_MUX_GPIO20_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPD_S  7
-/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO20.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO20_FUN_WPU_M  (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S)
-#define IO_MUX_GPIO20_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPU_S  8
-/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO20.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO20_FUN_IE_M  (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S)
-#define IO_MUX_GPIO20_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_IE_S  9
-/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO20. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO20_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_M  (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S)
-#define IO_MUX_GPIO20_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_S  10
-/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO20_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_M  (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S)
-#define IO_MUX_GPIO20_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_S  12
-/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO20_FILTER_EN_M  (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S)
-#define IO_MUX_GPIO20_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO20_FILTER_EN_S  15
-/** IO_MUX_GPIO20_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO20_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO20_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO20_HYS_EN_M  (IO_MUX_GPIO20_HYS_EN_V << IO_MUX_GPIO20_HYS_EN_S)
-#define IO_MUX_GPIO20_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO20_HYS_EN_S  16
-/** IO_MUX_GPIO20_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO20. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO20_HYS_EN\\
- */
-#define IO_MUX_GPIO20_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO20_HYS_SEL_M  (IO_MUX_GPIO20_HYS_SEL_V << IO_MUX_GPIO20_HYS_SEL_S)
-#define IO_MUX_GPIO20_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO20_HYS_SEL_S  17
-
-/** IO_MUX_GPIO21_REG register
- *  IO MUX configuration register for GPIO21
- */
-#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x54)
-/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO21 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO21_MCU_OE_M  (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S)
-#define IO_MUX_GPIO21_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_OE_S  0
-/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO21.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO21_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO21_SLP_SEL_M  (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S)
-#define IO_MUX_GPIO21_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO21_SLP_SEL_S  1
-/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO21 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO21_MCU_WPD_M  (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S)
-#define IO_MUX_GPIO21_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPD_S  2
-/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO21 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO21_MCU_WPU_M  (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S)
-#define IO_MUX_GPIO21_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPU_S  3
-/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO21 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO21_MCU_IE_M  (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S)
-#define IO_MUX_GPIO21_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_IE_S  4
-/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO21 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO21_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_M  (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S)
-#define IO_MUX_GPIO21_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_S  5
-/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO21.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO21_FUN_WPD_M  (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S)
-#define IO_MUX_GPIO21_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPD_S  7
-/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO21.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO21_FUN_WPU_M  (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S)
-#define IO_MUX_GPIO21_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPU_S  8
-/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO21.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO21_FUN_IE_M  (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S)
-#define IO_MUX_GPIO21_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_IE_S  9
-/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO21. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO21_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_M  (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S)
-#define IO_MUX_GPIO21_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_S  10
-/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO21_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_M  (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S)
-#define IO_MUX_GPIO21_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_S  12
-/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO21_FILTER_EN_M  (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S)
-#define IO_MUX_GPIO21_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO21_FILTER_EN_S  15
-/** IO_MUX_GPIO21_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO21_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO21_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO21_HYS_EN_M  (IO_MUX_GPIO21_HYS_EN_V << IO_MUX_GPIO21_HYS_EN_S)
-#define IO_MUX_GPIO21_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO21_HYS_EN_S  16
-/** IO_MUX_GPIO21_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO21. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO21_HYS_EN\\
- */
-#define IO_MUX_GPIO21_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO21_HYS_SEL_M  (IO_MUX_GPIO21_HYS_SEL_V << IO_MUX_GPIO21_HYS_SEL_S)
-#define IO_MUX_GPIO21_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO21_HYS_SEL_S  17
-
-/** IO_MUX_GPIO22_REG register
- *  IO MUX configuration register for GPIO22
- */
-#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x58)
-/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO22 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO22_MCU_OE_M  (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S)
-#define IO_MUX_GPIO22_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_OE_S  0
-/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO22.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO22_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO22_SLP_SEL_M  (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S)
-#define IO_MUX_GPIO22_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO22_SLP_SEL_S  1
-/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO22 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO22_MCU_WPD_M  (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S)
-#define IO_MUX_GPIO22_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPD_S  2
-/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO22 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO22_MCU_WPU_M  (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S)
-#define IO_MUX_GPIO22_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPU_S  3
-/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO22 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO22_MCU_IE_M  (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S)
-#define IO_MUX_GPIO22_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_IE_S  4
-/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO22 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO22_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_M  (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S)
-#define IO_MUX_GPIO22_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_S  5
-/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO22.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO22_FUN_WPD_M  (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S)
-#define IO_MUX_GPIO22_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPD_S  7
-/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO22.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO22_FUN_WPU_M  (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S)
-#define IO_MUX_GPIO22_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPU_S  8
-/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO22.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO22_FUN_IE_M  (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S)
-#define IO_MUX_GPIO22_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_IE_S  9
-/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO22. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO22_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_M  (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S)
-#define IO_MUX_GPIO22_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_S  10
-/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO22_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_M  (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S)
-#define IO_MUX_GPIO22_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_S  12
-/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO22_FILTER_EN_M  (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S)
-#define IO_MUX_GPIO22_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO22_FILTER_EN_S  15
-/** IO_MUX_GPIO22_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO22_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO22_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO22_HYS_EN_M  (IO_MUX_GPIO22_HYS_EN_V << IO_MUX_GPIO22_HYS_EN_S)
-#define IO_MUX_GPIO22_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO22_HYS_EN_S  16
-/** IO_MUX_GPIO22_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO22. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO22_HYS_EN\\
- */
-#define IO_MUX_GPIO22_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO22_HYS_SEL_M  (IO_MUX_GPIO22_HYS_SEL_V << IO_MUX_GPIO22_HYS_SEL_S)
-#define IO_MUX_GPIO22_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO22_HYS_SEL_S  17
-
-/** IO_MUX_GPIO23_REG register
- *  IO MUX configuration register for GPIO23
- */
-#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x5c)
-/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO23 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO23_MCU_OE_M  (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S)
-#define IO_MUX_GPIO23_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_OE_S  0
-/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO23.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO23_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO23_SLP_SEL_M  (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S)
-#define IO_MUX_GPIO23_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO23_SLP_SEL_S  1
-/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO23 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO23_MCU_WPD_M  (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S)
-#define IO_MUX_GPIO23_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPD_S  2
-/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO23 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO23_MCU_WPU_M  (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S)
-#define IO_MUX_GPIO23_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPU_S  3
-/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO23 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO23_MCU_IE_M  (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S)
-#define IO_MUX_GPIO23_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_IE_S  4
-/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO23 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO23_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_M  (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S)
-#define IO_MUX_GPIO23_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_S  5
-/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO23.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO23_FUN_WPD_M  (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S)
-#define IO_MUX_GPIO23_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPD_S  7
-/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO23.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO23_FUN_WPU_M  (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S)
-#define IO_MUX_GPIO23_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPU_S  8
-/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO23.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO23_FUN_IE_M  (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S)
-#define IO_MUX_GPIO23_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_IE_S  9
-/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO23. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO23_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_M  (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S)
-#define IO_MUX_GPIO23_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_S  10
-/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO23_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_M  (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S)
-#define IO_MUX_GPIO23_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_S  12
-/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO23_FILTER_EN_M  (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S)
-#define IO_MUX_GPIO23_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO23_FILTER_EN_S  15
-/** IO_MUX_GPIO23_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO23_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO23_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO23_HYS_EN_M  (IO_MUX_GPIO23_HYS_EN_V << IO_MUX_GPIO23_HYS_EN_S)
-#define IO_MUX_GPIO23_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO23_HYS_EN_S  16
-/** IO_MUX_GPIO23_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO23. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO23_HYS_EN\\
- */
-#define IO_MUX_GPIO23_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO23_HYS_SEL_M  (IO_MUX_GPIO23_HYS_SEL_V << IO_MUX_GPIO23_HYS_SEL_S)
-#define IO_MUX_GPIO23_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO23_HYS_SEL_S  17
-
-/** IO_MUX_GPIO24_REG register
- *  IO MUX configuration register for GPIO24
- */
-#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x60)
-/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO24 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO24_MCU_OE_M  (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S)
-#define IO_MUX_GPIO24_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_OE_S  0
-/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO24.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO24_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO24_SLP_SEL_M  (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S)
-#define IO_MUX_GPIO24_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO24_SLP_SEL_S  1
-/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO24 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO24_MCU_WPD_M  (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S)
-#define IO_MUX_GPIO24_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPD_S  2
-/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO24 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO24_MCU_WPU_M  (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S)
-#define IO_MUX_GPIO24_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPU_S  3
-/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO24 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO24_MCU_IE_M  (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S)
-#define IO_MUX_GPIO24_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_IE_S  4
-/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO24 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO24_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_M  (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S)
-#define IO_MUX_GPIO24_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_S  5
-/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO24.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO24_FUN_WPD_M  (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S)
-#define IO_MUX_GPIO24_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPD_S  7
-/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO24.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO24_FUN_WPU_M  (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S)
-#define IO_MUX_GPIO24_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPU_S  8
-/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO24.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO24_FUN_IE_M  (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S)
-#define IO_MUX_GPIO24_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_IE_S  9
-/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO24. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO24_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_M  (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S)
-#define IO_MUX_GPIO24_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_S  10
-/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO24_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_M  (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S)
-#define IO_MUX_GPIO24_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_S  12
-/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO24_FILTER_EN_M  (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S)
-#define IO_MUX_GPIO24_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO24_FILTER_EN_S  15
-/** IO_MUX_GPIO24_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO24_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO24_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO24_HYS_EN_M  (IO_MUX_GPIO24_HYS_EN_V << IO_MUX_GPIO24_HYS_EN_S)
-#define IO_MUX_GPIO24_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO24_HYS_EN_S  16
-/** IO_MUX_GPIO24_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO24. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO24_HYS_EN\\
- */
-#define IO_MUX_GPIO24_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO24_HYS_SEL_M  (IO_MUX_GPIO24_HYS_SEL_V << IO_MUX_GPIO24_HYS_SEL_S)
-#define IO_MUX_GPIO24_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO24_HYS_SEL_S  17
-
-/** IO_MUX_GPIO25_REG register
- *  IO MUX configuration register for GPIO25
- */
-#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x64)
-/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO25 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO25_MCU_OE_M  (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S)
-#define IO_MUX_GPIO25_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_OE_S  0
-/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO25.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO25_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO25_SLP_SEL_M  (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S)
-#define IO_MUX_GPIO25_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO25_SLP_SEL_S  1
-/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO25 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO25_MCU_WPD_M  (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S)
-#define IO_MUX_GPIO25_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPD_S  2
-/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO25 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO25_MCU_WPU_M  (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S)
-#define IO_MUX_GPIO25_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPU_S  3
-/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO25 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO25_MCU_IE_M  (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S)
-#define IO_MUX_GPIO25_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_IE_S  4
-/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO25 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO25_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_M  (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S)
-#define IO_MUX_GPIO25_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_S  5
-/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO25.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO25_FUN_WPD_M  (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S)
-#define IO_MUX_GPIO25_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPD_S  7
-/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO25.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO25_FUN_WPU_M  (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S)
-#define IO_MUX_GPIO25_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPU_S  8
-/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO25.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO25_FUN_IE_M  (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S)
-#define IO_MUX_GPIO25_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_IE_S  9
-/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO25. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO25_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_M  (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S)
-#define IO_MUX_GPIO25_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_S  10
-/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO25_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_M  (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S)
-#define IO_MUX_GPIO25_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_S  12
-/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO25_FILTER_EN_M  (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S)
-#define IO_MUX_GPIO25_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO25_FILTER_EN_S  15
-/** IO_MUX_GPIO25_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO25_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO25_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO25_HYS_EN_M  (IO_MUX_GPIO25_HYS_EN_V << IO_MUX_GPIO25_HYS_EN_S)
-#define IO_MUX_GPIO25_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO25_HYS_EN_S  16
-/** IO_MUX_GPIO25_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO25. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO25_HYS_EN\\
- */
-#define IO_MUX_GPIO25_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO25_HYS_SEL_M  (IO_MUX_GPIO25_HYS_SEL_V << IO_MUX_GPIO25_HYS_SEL_S)
-#define IO_MUX_GPIO25_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO25_HYS_SEL_S  17
-
-/** IO_MUX_GPIO26_REG register
- *  IO MUX configuration register for GPIO26
- */
-#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x68)
-/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO26 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO26_MCU_OE_M  (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S)
-#define IO_MUX_GPIO26_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_OE_S  0
-/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO26.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO26_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO26_SLP_SEL_M  (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S)
-#define IO_MUX_GPIO26_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO26_SLP_SEL_S  1
-/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO26 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO26_MCU_WPD_M  (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S)
-#define IO_MUX_GPIO26_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPD_S  2
-/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO26 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO26_MCU_WPU_M  (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S)
-#define IO_MUX_GPIO26_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPU_S  3
-/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO26 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO26_MCU_IE_M  (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S)
-#define IO_MUX_GPIO26_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_IE_S  4
-/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO26 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO26_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_M  (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S)
-#define IO_MUX_GPIO26_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_S  5
-/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO26.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO26_FUN_WPD_M  (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S)
-#define IO_MUX_GPIO26_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPD_S  7
-/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO26.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO26_FUN_WPU_M  (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S)
-#define IO_MUX_GPIO26_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPU_S  8
-/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO26.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO26_FUN_IE_M  (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S)
-#define IO_MUX_GPIO26_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_IE_S  9
-/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO26. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO26_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_M  (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S)
-#define IO_MUX_GPIO26_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_S  10
-/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO26_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_M  (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S)
-#define IO_MUX_GPIO26_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_S  12
-/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO26_FILTER_EN_M  (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S)
-#define IO_MUX_GPIO26_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO26_FILTER_EN_S  15
-/** IO_MUX_GPIO26_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO26_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO26_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO26_HYS_EN_M  (IO_MUX_GPIO26_HYS_EN_V << IO_MUX_GPIO26_HYS_EN_S)
-#define IO_MUX_GPIO26_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO26_HYS_EN_S  16
-/** IO_MUX_GPIO26_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO26. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO26_HYS_EN\\
- */
-#define IO_MUX_GPIO26_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO26_HYS_SEL_M  (IO_MUX_GPIO26_HYS_SEL_V << IO_MUX_GPIO26_HYS_SEL_S)
-#define IO_MUX_GPIO26_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO26_HYS_SEL_S  17
-
-/** IO_MUX_GPIO27_REG register
- *  IO MUX configuration register for GPIO27
- */
-#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x6c)
-/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO27 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO27_MCU_OE_M  (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S)
-#define IO_MUX_GPIO27_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_OE_S  0
-/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO27.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO27_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO27_SLP_SEL_M  (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S)
-#define IO_MUX_GPIO27_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO27_SLP_SEL_S  1
-/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO27 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO27_MCU_WPD_M  (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S)
-#define IO_MUX_GPIO27_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPD_S  2
-/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO27 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO27_MCU_WPU_M  (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S)
-#define IO_MUX_GPIO27_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPU_S  3
-/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO27 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO27_MCU_IE_M  (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S)
-#define IO_MUX_GPIO27_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_IE_S  4
-/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO27 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO27_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_M  (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S)
-#define IO_MUX_GPIO27_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_S  5
-/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO27.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO27_FUN_WPD_M  (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S)
-#define IO_MUX_GPIO27_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPD_S  7
-/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO27.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO27_FUN_WPU_M  (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S)
-#define IO_MUX_GPIO27_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPU_S  8
-/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO27.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO27_FUN_IE_M  (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S)
-#define IO_MUX_GPIO27_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_IE_S  9
-/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO27. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO27_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_M  (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S)
-#define IO_MUX_GPIO27_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_S  10
-/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO27_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_M  (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S)
-#define IO_MUX_GPIO27_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_S  12
-/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO27_FILTER_EN_M  (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S)
-#define IO_MUX_GPIO27_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO27_FILTER_EN_S  15
-/** IO_MUX_GPIO27_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO27_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO27_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO27_HYS_EN_M  (IO_MUX_GPIO27_HYS_EN_V << IO_MUX_GPIO27_HYS_EN_S)
-#define IO_MUX_GPIO27_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO27_HYS_EN_S  16
-/** IO_MUX_GPIO27_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO27. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO27_HYS_EN\\
- */
-#define IO_MUX_GPIO27_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO27_HYS_SEL_M  (IO_MUX_GPIO27_HYS_SEL_V << IO_MUX_GPIO27_HYS_SEL_S)
-#define IO_MUX_GPIO27_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO27_HYS_SEL_S  17
-
-/** IO_MUX_GPIO28_REG register
- *  IO MUX configuration register for GPIO28
- */
-#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x70)
-/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the output of GPIO28 in sleep mode.
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO28_MCU_OE_M  (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S)
-#define IO_MUX_GPIO28_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_OE_S  0
-/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enter sleep mode for GPIO28.\\
- *  0: Not enter\\
- *  1: Enter\\
- */
-#define IO_MUX_GPIO28_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO28_SLP_SEL_M  (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S)
-#define IO_MUX_GPIO28_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO28_SLP_SEL_S  1
-/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not to enable pull-down resistor of GPIO28 in sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO28_MCU_WPD_M  (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S)
-#define IO_MUX_GPIO28_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPD_S  2
-/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable pull-up resistor of GPIO28 during sleep mode. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO28_MCU_WPU_M  (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S)
-#define IO_MUX_GPIO28_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPU_S  3
-/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the input of GPIO28 during sleep mode.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO28_MCU_IE_M  (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S)
-#define IO_MUX_GPIO28_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_IE_S  4
-/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  Configures the drive strength of GPIO28 during sleep mode. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO28_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_M  (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S)
-#define IO_MUX_GPIO28_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_S  5
-/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable pull-down resistor of GPIO28.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO28_FUN_WPD_M  (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S)
-#define IO_MUX_GPIO28_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPD_S  7
-/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not enable pull-up resistor of GPIO28.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO28_FUN_WPU_M  (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S)
-#define IO_MUX_GPIO28_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPU_S  8
-/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable input of GPIO28.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO28_FUN_IE_M  (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S)
-#define IO_MUX_GPIO28_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_IE_S  9
-/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  Configures the drive strength of GPIO28. \\
- *  0: ~5 mA\\
- *  1: ~10 mA\\
- *  2: ~20 mA\\
- *  3: ~40 mA\\
- */
-#define IO_MUX_GPIO28_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_M  (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S)
-#define IO_MUX_GPIO28_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_S  10
-/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  Configures to select IO MUX function for this signal. \\
- *  0: Select Function 0\\
- *  1: Select Function 1\\
- *  ......\\
- */
-#define IO_MUX_GPIO28_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_M  (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S)
-#define IO_MUX_GPIO28_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_S  12
-/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable filter for pin input signals.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO28_FILTER_EN_M  (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S)
-#define IO_MUX_GPIO28_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO28_FILTER_EN_S  15
-/** IO_MUX_GPIO28_HYS_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the hysteresis function of the pin when
- *  IO_MUX_GPIO28_HYS_SEL is set to 1.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define IO_MUX_GPIO28_HYS_EN    (BIT(16))
-#define IO_MUX_GPIO28_HYS_EN_M  (IO_MUX_GPIO28_HYS_EN_V << IO_MUX_GPIO28_HYS_EN_S)
-#define IO_MUX_GPIO28_HYS_EN_V  0x00000001U
-#define IO_MUX_GPIO28_HYS_EN_S  16
-/** IO_MUX_GPIO28_HYS_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures to choose the signal for enabling the hysteresis function for GPIO28. \\
- *  0: Choose the output enable signal of eFuse\\
- *  1: Choose the output enable signal of IO_MUX_GPIO28_HYS_EN\\
- */
-#define IO_MUX_GPIO28_HYS_SEL    (BIT(17))
-#define IO_MUX_GPIO28_HYS_SEL_M  (IO_MUX_GPIO28_HYS_SEL_V << IO_MUX_GPIO28_HYS_SEL_S)
-#define IO_MUX_GPIO28_HYS_SEL_V  0x00000001U
-#define IO_MUX_GPIO28_HYS_SEL_S  17
+#define PERIPHS_IO_MUX_U_PAD_GPIO28               (REG_IO_MUX_BASE + 0x70)
+#define FUNC_GPIO28_GPIO28                                               1
+#define FUNC_GPIO28_GPIO28_0                                             0
 
 /** IO_MUX_DATE_REG register
  *  Version control register
diff --git a/components/soc/esp32c5/mp/include/soc/io_mux_struct.h b/components/soc/esp32c5/mp/include/soc/io_mux_struct.h
index bc32968ea0..2acfae5d3f 100644
--- a/components/soc/esp32c5/mp/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c5/mp/include/soc/io_mux_struct.h
@@ -134,7 +134,7 @@ typedef struct {
     volatile io_mux_date_reg_t date;
 } io_mux_dev_t;
 
-extern io_mux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h
index b635b7f239..f20d1b4a31 100644
--- a/components/soc/esp32c5/mp/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h
@@ -174,35 +174,35 @@
 // #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
-// TODO: [ESP32C5] IDF-8717
 // ESP32-C5 has 1 GPIO peripheral
-// #define SOC_GPIO_PORT                      1U
+#define SOC_GPIO_PORT                      1U
 #define SOC_GPIO_PIN_COUNT                 29
 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
+#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER      1
 
 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1
 
 // Target has the full LP IO subsystem
 // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
 // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
-// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719
 
 #define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
 
-#define SOC_GPIO_IN_RANGE_MAX           30
-#define SOC_GPIO_OUT_RANGE_MAX          30
+#define SOC_GPIO_IN_RANGE_MAX           28
+#define SOC_GPIO_OUT_RANGE_MAX          28
 
-// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
 
-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
-// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
 
 // Support to force hold all IOs
-// #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
+#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
index 53251653ed..7a60c63b9a 100644
--- a/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
+++ b/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
@@ -39,7 +39,7 @@ PROVIDE ( ECC                 = 0x6008B000 );
 PROVIDE ( DS                  = 0x6008C000 );
 PROVIDE ( HMAC                = 0x6008D000 );
 PROVIDE ( ECDSA               = 0x6008E000 );
-PROVIDE ( IOMUX               = 0x60090000 );
+PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
 PROVIDE ( GPIO_EXT            = 0x60091f00 );
 PROVIDE ( MEM_MONITOR         = 0x60092000 );
diff --git a/components/soc/esp32p4/include/soc/io_mux_struct.h b/components/soc/esp32p4/include/soc/io_mux_struct.h
index 5ddbc746b9..150d0d5c1e 100644
--- a/components/soc/esp32p4/include/soc/io_mux_struct.h
+++ b/components/soc/esp32p4/include/soc/io_mux_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +11,7 @@ extern "C" {
 #endif
 
 /** Type of GPIO register
- *  IOMUX gpio configuration register
+ *  IO MUX gpio configuration register
  */
 typedef union {
     struct {
@@ -36,7 +36,7 @@ typedef union {
          */
         uint32_t mcu_ie:1;
         /** mcu_drv : R/W; bitpos: [5:6]; default: 0;
-         *  select drive strenth on sleep mode
+         *  select drive strength on sleep mode
          */
         uint32_t mcu_drv:2;
         /** fun_wpd : R/W; bitpos: [7]; default: 0;
@@ -52,7 +52,7 @@ typedef union {
          */
         uint32_t fun_ie:1;
         /** fun_drv : R/W; bitpos: [10:11]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
          */
         uint32_t fun_drv:2;
         /** mcu_sel : R/W; bitpos: [12:14]; default: 0;
@@ -66,10 +66,10 @@ typedef union {
         uint32_t reserved16 :16;
     };
     uint32_t val;
-} iomux_gpio_reg_t;
+} io_mux_gpio_reg_t;
 
 /** Type of date register
- *  IOMUX version register
+ *  IO_MUX version register
  */
 typedef union {
     struct {
@@ -80,20 +80,20 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} iomux_date_reg_t;
+} io_mux_date_reg_t;
 
 
-typedef struct iomux_dev_t {
+typedef struct io_mux_dev_t {
     uint32_t reserved_0;
-    volatile iomux_gpio_reg_t gpio[57];
+    volatile io_mux_gpio_reg_t gpio[57];
     uint32_t reserved_e8[7];
-    volatile iomux_date_reg_t date;
-} iomux_dev_t;
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
 
-extern iomux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(iomux_dev_t) == 0x108, "Invalid size of iomux_dev_t structure");
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml
index 174a6caafd..45d6f5d9cd 100644
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@@ -39,10 +39,6 @@ examples/peripherals/dac/dac_cosine_wave:
     - esp_driver_dac
 
 examples/peripherals/gpio:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: GPIO is not supported on ESP32-C5  # TODO: [ESP32C5] IDF-8717
   depends_components:
     - esp_driver_gpio
 
diff --git a/examples/peripherals/gpio/generic_gpio/README.md b/examples/peripherals/gpio/generic_gpio/README.md
index 5b01af0508..e6ac34b725 100644
--- a/examples/peripherals/gpio/generic_gpio/README.md
+++ b/examples/peripherals/gpio/generic_gpio/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 
 # Example: GPIO
 
diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml
index 028df4eb16..d752460d34 100644
--- a/examples/storage/.build-test-rules.yml
+++ b/examples/storage/.build-test-rules.yml
@@ -46,10 +46,6 @@ examples/storage/nvs_rw_blob:
   depends_components:
     - nvs_flash
     - driver
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not supported yet  # TODO: [ESP32C5] IDF-8717
   disable_test:
     - if: IDF_TARGET not in ["esp32", "esp32c3"]
       reason: only one target per arch needed
diff --git a/examples/storage/nvs_rw_blob/README.md b/examples/storage/nvs_rw_blob/README.md
index 7563617da8..bdded9bfc5 100644
--- a/examples/storage/nvs_rw_blob/README.md
+++ b/examples/storage/nvs_rw_blob/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 
 # Non-Volatile Storage (NVS) Read and Write Example
 
diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml
index 5bc2392b62..2c83adc854 100644
--- a/examples/system/.build-test-rules.yml
+++ b/examples/system/.build-test-rules.yml
@@ -79,10 +79,6 @@ examples/system/freertos:
     - freertos
 
 examples/system/gcov:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not supported yet #TODO: IDF-8717
   disable_test:
     - if: IDF_TARGET != "esp32"
       temporary: true