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fix(pm): fix c5 tx pkt failed

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sibeibei
2025-07-02 21:27:33 +08:00
parent 22cfc7ef57
commit 2cb1fc4365
1 changed files with 22 additions and 4 deletions
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20
components/esp_hw_support/port/esp32c5/rtc_clk.c
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@@ -232,9 +232,21 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
// 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately. // 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately.
if (xtal_freq == SOC_XTAL_FREQ_48M && freq_mhz == 40) { if (xtal_freq == SOC_XTAL_FREQ_48M && freq_mhz == 40) {
real_freq_mhz = freq_mhz; real_freq_mhz = freq_mhz;
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
source = SOC_CPU_CLK_SRC_PLL_F240M;
source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
divider = 6;
#else
source = SOC_CPU_CLK_SRC_PLL_F160M; source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = 4; divider = 4;
#endif
} else {
source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = 4;
}
} else if (freq_mhz <= xtal_freq && freq_mhz != 0) { } else if (freq_mhz <= xtal_freq && freq_mhz != 0) {
divider = xtal_freq / freq_mhz; divider = xtal_freq / freq_mhz;
real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
@@ -257,12 +269,18 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
divider = 1; divider = 1;
} else if (freq_mhz == 80) { } else if (freq_mhz == 80) {
real_freq_mhz = freq_mhz; real_freq_mhz = freq_mhz;
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {
/* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M /* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
* For detailed information, refer to IDF-11064 */ * For detailed information, refer to IDF-11064 */
#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
source = SOC_CPU_CLK_SRC_PLL_F240M; source = SOC_CPU_CLK_SRC_PLL_F240M;
source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
divider = 3; divider = 3;
#else
source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = 2;
#endif
} else { } else {
source = SOC_CPU_CLK_SRC_PLL_F160M; source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;