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driver(uart): Fixed uart tx_empty interrupt wdt timeout bug.
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@@ -761,7 +761,6 @@ static void uart_rx_intr_handler_default(void *param)
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p_uart->tx_ptr = NULL;
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p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
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if(p_uart->tx_head->type == UART_DATA_BREAK) {
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p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
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p_uart->tx_brk_flg = 1;
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p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len;
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}
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@@ -809,7 +808,7 @@ static void uart_rx_intr_handler_default(void *param)
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p_uart->tx_ptr = NULL;
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//Sending item done, now we need to send break if there is a record.
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//Set TX break signal after FIFO is empty
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if(p_uart->tx_brk_flg == 1 && p_uart->tx_len_tot == 0) {
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if(p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) {
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UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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uart_reg->int_ena.tx_brk_done = 0;
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uart_reg->idle_conf.tx_brk_num = p_uart->tx_brk_len;
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@@ -818,6 +817,8 @@ static void uart_rx_intr_handler_default(void *param)
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uart_reg->int_ena.tx_brk_done = 1;
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UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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p_uart->tx_waiting_brk = 1;
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//do not enable TX empty interrupt
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en_tx_flg = false;
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} else {
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//enable TX empty interrupt
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en_tx_flg = true;
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