From 2df4ddf99836f13b15b7804e55aab5565eabfe96 Mon Sep 17 00:00:00 2001 From: Shu Chen Date: Fri, 18 Jun 2021 19:20:42 +0800 Subject: [PATCH] esp32h2: fixes after rebase --- .../subproject/main/ld/esp32h2/bootloader.ld | 2 +- components/bootloader_support/src/flash_encrypt.c | 14 ++------------ components/efuse/esp32h2/esp_efuse_utility.c | 2 +- components/hal/esp32h2/include/hal/memprot_ll.h | 5 +++-- .../esp32h2/include/hal/spi_flash_encrypted_ll.h | 4 ++-- components/hal/esp32h2/include/hal/spi_ll.h | 15 ++++++++------- components/hal/esp32h2/include/hal/systimer_ll.h | 4 ++-- components/hal/esp32h2/include/hal/timer_ll.h | 5 +++-- components/hal/esp32h2/rtc_cntl_hal.c | 12 ++++++------ 9 files changed, 28 insertions(+), 35 deletions(-) diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld index d016cd30df..832f653b68 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld @@ -170,7 +170,7 @@ SECTIONS } - +/* ESP32H2-TODO: IDF-3466 */ /** * Appendix: Memory Usage of ROM bootloader * diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index c6a9815c2f..45f40ba2d4 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -86,10 +86,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void) uint8_t dis_dl_enc = 0; uint8_t dis_dl_icache = 0; uint8_t dis_dl_dcache = 0; -#elif CONFIG_IDF_TARGET_ESP32C3 - uint8_t dis_dl_enc = 0; - uint8_t dis_dl_icache = 0; -#elif CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 uint8_t dis_dl_enc = 0; uint8_t dis_dl_icache = 0; #endif @@ -126,14 +123,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void) if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) { mode = ESP_FLASH_ENC_MODE_RELEASE; } -#elif CONFIG_IDF_TARGET_ESP32C3 - dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); - dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); - - if (dis_dl_enc && dis_dl_icache) { - mode = ESP_FLASH_ENC_MODE_RELEASE; - } -#elif CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); diff --git a/components/efuse/esp32h2/esp_efuse_utility.c b/components/efuse/esp32h2/esp_efuse_utility.c index 6ea6b16473..1faca45802 100644 --- a/components/efuse/esp32h2/esp_efuse_utility.c +++ b/components/efuse/esp32h2/esp_efuse_utility.c @@ -75,7 +75,7 @@ void esp_efuse_utility_clear_program_registers(void) } // Burn values written to the efuse write registers -void esp_efuse_utility_burn_efuses(void) +void esp_efuse_utility_burn_chip(void) { #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); diff --git a/components/hal/esp32h2/include/hal/memprot_ll.h b/components/hal/esp32h2/include/hal/memprot_ll.h index cc3fe68c7d..8ec634d752 100644 --- a/components/hal/esp32h2/include/hal/memprot_ll.h +++ b/components/hal/esp32h2/include/hal/memprot_ll.h @@ -16,6 +16,7 @@ #include "soc/sensitive_reg.h" #include "soc/cache_memory.h" +#include "hal/assert.h" #ifdef __cplusplus extern "C" { @@ -96,7 +97,7 @@ static inline uint32_t memprot_ll_iram0_get_intr_source_num(void) static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; - assert( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH ); + HAL_ASSERT( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH ); uint32_t category[3] = {0}; if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) { @@ -353,7 +354,7 @@ static inline uint32_t memprot_ll_dram0_get_intr_source_num(void) static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; - assert( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH ); + HAL_ASSERT( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH ); uint32_t category[3] = {0}; if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) { diff --git a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h index cc1e627b96..58cb186458 100644 --- a/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h @@ -20,11 +20,11 @@ // The Lowlevel layer for SPI Flash Encryption. +#include "hal/assert.h" #include "soc/system_reg.h" #include "soc/hwcrypto_reg.h" #include "soc/soc.h" #include "string.h" -#include "assert.h" #include #ifdef __cplusplus @@ -67,7 +67,7 @@ static inline void spi_flash_encrypt_ll_disable(void) static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) { // Our hardware only support flash encryption - assert(type == FLASH_ENCRYPTION_MANU); + HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); REG_WRITE(AES_XTS_DESTINATION_REG, type); } diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index f2bedc8e54..e4f462dc11 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -24,11 +24,12 @@ #include //for abs() #include -#include "hal/hal_defs.h" +#include "esp_attr.h" #include "esp_types.h" #include "soc/spi_periph.h" -#include "esp32h2/rom/lldesc.h" -#include "esp_attr.h" +#include "soc/lldesc.h" +#include "hal/assert.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -37,7 +38,7 @@ extern "C" { /// Interrupt not used. Don't use in app. #define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) /// Swap the bit order to its correct place to send -#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len)) +#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) /// This is the expected clock frequency #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000) #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2) @@ -351,9 +352,9 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s */ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) { - assert(byte_id+len <= 64); - assert(len > 0); - assert(byte_id >= 0); + HAL_ASSERT(byte_id+len <= 64); + HAL_ASSERT(len > 0); + HAL_ASSERT(byte_id >= 0); while (len > 0) { uint32_t word; diff --git a/components/hal/esp32h2/include/hal/systimer_ll.h b/components/hal/esp32h2/include/hal/systimer_ll.h index 9aa0c32da5..769f68703f 100644 --- a/components/hal/esp32h2/include/hal/systimer_ll.h +++ b/components/hal/esp32h2/include/hal/systimer_ll.h @@ -15,8 +15,8 @@ #include #include -#include #include "soc/systimer_struct.h" +#include "hal/assert.h" #define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time #define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick @@ -120,7 +120,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio __attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) { - assert(period < (1 << 26)); + HAL_ASSERT(period < (1 << 26)); dev->target_conf[alarm_id].target_period = period; } diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h index b08b2f1fc7..caa1eda89f 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -22,8 +22,9 @@ extern "C" { #endif #include -#include "hal/timer_types.h" #include "soc/timer_periph.h" +#include "hal/timer_types.h" +#include "hal/assert.h" _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); @@ -47,7 +48,7 @@ typedef struct { */ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) { - assert(divider >= 2 && divider <= 65536); + HAL_ASSERT(divider >= 2 && divider <= 65536); if (divider >= 65536) { divider = 0; } diff --git a/components/hal/esp32h2/rtc_cntl_hal.c b/components/hal/esp32h2/rtc_cntl_hal.c index e88fe73734..2fb14a5b2f 100644 --- a/components/hal/esp32h2/rtc_cntl_hal.c +++ b/components/hal/esp32h2/rtc_cntl_hal.c @@ -14,10 +14,10 @@ // The HAL layer for RTC CNTL (common part) -#include "hal/rtc_hal.h" #include "soc/soc_caps.h" -#include "esp32h2/rom/lldesc.h" -#include "esp_attr.h" +#include "soc/lldesc.h" +#include "hal/rtc_hal.h" +#include "hal/assert.h" #define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ @@ -27,9 +27,9 @@ typedef struct rtc_cntl_link_buf_conf { void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next) { - assert(elem != NULL); - assert(buff != NULL); - assert(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); + HAL_ASSERT(elem != NULL); + HAL_ASSERT(buff != NULL); + HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); lldesc_t *plink = (lldesc_t *)elem;