From 997c07c2ee97ccd44f26b46a532815016610c2c0 Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Wed, 5 May 2021 17:53:47 +1000
Subject: [PATCH 1/3] esp32s2 riscv ulp: Ensure reset vector is always at
 offset 0x0

Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
---
 components/ulp/ld/esp32s2.ulp.riscv.ld | 1 +
 components/ulp/ulp_riscv/start.S       | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/components/ulp/ld/esp32s2.ulp.riscv.ld b/components/ulp/ld/esp32s2.ulp.riscv.ld
index 983481df29..a0733bff7f 100644
--- a/components/ulp/ld/esp32s2.ulp.riscv.ld
+++ b/components/ulp/ld/esp32s2.ulp.riscv.ld
@@ -12,6 +12,7 @@ SECTIONS
     . = ORIGIN(ram);
     .text :
     {
+        *start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
         *(.text)
         *(.text*)
     } >ram
diff --git a/components/ulp/ulp_riscv/start.S b/components/ulp/ulp_riscv/start.S
index 1da9b755b0..949fd7fb48 100644
--- a/components/ulp/ulp_riscv/start.S
+++ b/components/ulp/ulp_riscv/start.S
@@ -1,4 +1,4 @@
-	.section .text
+	.section .text.vectors
 	.global irq_vector
 	.global reset_vector
 
@@ -11,6 +11,8 @@ reset_vector:
 irq_vector:
 	ret
 
+	.section .text
+
 __start:
 	/* setup the stack pointer */
 	la sp, __stack_top

From 228f875ada44e4c66f65e68536eb975e6c08eebb Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Wed, 5 May 2021 17:54:41 +1000
Subject: [PATCH 2/3] esp32s2 riscv ulp: Make re-linking depend on linker
 script file

---
 components/ulp/cmake/CMakeLists.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt
index 625ff97154..d1f4fecc21 100644
--- a/components/ulp/cmake/CMakeLists.txt
+++ b/components/ulp/cmake/CMakeLists.txt
@@ -149,3 +149,4 @@ add_custom_target(build
                 WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
 
 target_link_libraries(${ULP_APP_NAME} -T${CMAKE_CURRENT_BINARY_DIR}/${ULP_LD_SCRIPT} ${EXTRA_LINKER_ARGS})
+set_target_properties(${ULP_APP_NAME} PROPERTIES LINK_DEPENDS ${ULP_LD_SCRIPT})

From f6d96f33bb0e379b10dce3c4560c62fcc496bfbc Mon Sep 17 00:00:00 2001
From: fuzhibo <fuzhibo@espressif.com>
Date: Mon, 12 Apr 2021 14:29:13 +0800
Subject: [PATCH 3/3] bugfix: add .rodata section for riscv ulp for esp32s2

---
 components/ulp/ld/esp32s2.ulp.riscv.ld | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/ulp/ld/esp32s2.ulp.riscv.ld b/components/ulp/ld/esp32s2.ulp.riscv.ld
index a0733bff7f..2134f8dd17 100644
--- a/components/ulp/ld/esp32s2.ulp.riscv.ld
+++ b/components/ulp/ld/esp32s2.ulp.riscv.ld
@@ -17,6 +17,12 @@ SECTIONS
         *(.text*)
     } >ram
 
+    .rodata ALIGN(4):
+    {
+        *(.rodata)
+        *(.rodata*)
+    } > ram
+
     .data ALIGN(4):
     {
         *(.data)