mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-02 16:11:41 +01:00
intr_alloc: split interrupt allocator into common-code and platform-code
esp_system: removed repeated interrupt allocator code and moved common code to esp_system xtens: moved xtensa specific code from freertos to the xtensa component hal/interrupt_controller: added interrupt controller hal and ll files docs: update the doxyfile with new location of esp_itr_alloc.h file xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos docs: removed Xtensa reference from intr_allocator api-reference xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer esp_system/test: fixed platform dependent setting for intr_allocator tests hal: rename the functions used to manage non iram interrupt mask.
This commit is contained in:
Felipe Neves
committed by
Angus Gratton
Angus Gratton
parent
59b763bb9a
commit
2e826b7a8f
@@ -9,8 +9,6 @@ set(srcs
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"xtensa/portasm.S"
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"xtensa/xtensa_context.S"
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"xtensa/xtensa_init.c"
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"xtensa/xtensa_intr_asm.S"
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"xtensa/xtensa_intr.c"
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"xtensa/xtensa_overlay_os_hook.c"
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"xtensa/xtensa_vector_defaults.S"
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"xtensa/xtensa_vectors.S")
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@@ -86,13 +86,12 @@ extern "C" {
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#include <esp_heap_caps.h>
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#include "esp_rom_sys.h"
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#include "sdkconfig.h"
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#include "freertos/xtensa_api.h"
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#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
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#include "soc/soc_memory_layout.h"
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#endif
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//#include "xtensa_context.h"
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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@@ -1,130 +1,2 @@
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/*******************************************************************************
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Copyright (c) 2006-2015 Cadence Design Systems Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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||||
|
||||
The above copyright notice and this permission notice shall be included
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||||
in all copies or substantial portions of the Software.
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||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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******************************************************************************/
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/******************************************************************************
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Xtensa-specific API for RTOS ports.
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******************************************************************************/
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#ifndef __XTENSA_API_H__
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#define __XTENSA_API_H__
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#include <xtensa/hal.h>
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#include "xtensa_context.h"
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/* Typedef for C-callable interrupt handler function */
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typedef void (*xt_handler)(void *);
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/* Typedef for C-callable exception handler function */
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typedef void (*xt_exc_handler)(XtExcFrame *);
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/*
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-------------------------------------------------------------------------------
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Call this function to set a handler for the specified exception. The handler
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will be installed on the core that calls this function.
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n - Exception number (type)
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f - Handler function address, NULL to uninstall handler.
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The handler will be passed a pointer to the exception frame, which is created
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on the stack of the thread that caused the exception.
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If the handler returns, the thread context will be restored and the faulting
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instruction will be retried. Any values in the exception frame that are
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modified by the handler will be restored as part of the context. For details
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of the exception frame structure see xtensa_context.h.
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-------------------------------------------------------------------------------
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*/
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extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
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/*
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-------------------------------------------------------------------------------
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Call this function to set a handler for the specified interrupt. The handler
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will be installed on the core that calls this function.
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n - Interrupt number.
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f - Handler function address, NULL to uninstall handler.
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arg - Argument to be passed to handler.
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-------------------------------------------------------------------------------
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*/
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extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
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/*
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-------------------------------------------------------------------------------
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Call this function to enable the specified interrupts on the core that runs
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this code.
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mask - Bit mask of interrupts to be enabled.
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-------------------------------------------------------------------------------
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*/
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extern void xt_ints_on(unsigned int mask);
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/*
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-------------------------------------------------------------------------------
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Call this function to disable the specified interrupts on the core that runs
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this code.
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mask - Bit mask of interrupts to be disabled.
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-------------------------------------------------------------------------------
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*/
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extern void xt_ints_off(unsigned int mask);
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/*
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-------------------------------------------------------------------------------
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Call this function to set the specified (s/w) interrupt.
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-------------------------------------------------------------------------------
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*/
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static inline void xt_set_intset(unsigned int arg)
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{
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xthal_set_intset(arg);
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}
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/*
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-------------------------------------------------------------------------------
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Call this function to clear the specified (s/w or edge-triggered)
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interrupt.
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-------------------------------------------------------------------------------
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*/
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static inline void xt_set_intclear(unsigned int arg)
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{
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xthal_set_intclear(arg);
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}
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/*
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-------------------------------------------------------------------------------
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Call this function to get handler's argument for the specified interrupt.
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n - Interrupt number.
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-------------------------------------------------------------------------------
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*/
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extern void * xt_get_interrupt_handler_arg(int n);
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#endif /* __XTENSA_API_H__ */
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/* This header file has been moved, please include <xtensa/xtensa_api.h> in future */
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#include <xtensa/xtensa_api.h>
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@@ -1,387 +1,2 @@
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/*******************************************************************************
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Copyright (c) 2006-2015 Cadence Design Systems Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
|
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"Software"), to deal in the Software without restriction, including
|
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without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
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permit persons to whom the Software is furnished to do so, subject to
|
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the following conditions:
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|
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The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
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|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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--------------------------------------------------------------------------------
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XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
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This header contains definitions and macros for use primarily by Xtensa
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RTOS assembly coded source files. It includes and uses the Xtensa hardware
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abstraction layer (HAL) to deal with config specifics. It may also be
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included in C source files.
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!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
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NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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*******************************************************************************/
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#ifndef XTENSA_CONTEXT_H
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#define XTENSA_CONTEXT_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#endif
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#include <xtensa/config/tie.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/xtruntime-frames.h>
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/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
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#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
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/*
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-------------------------------------------------------------------------------
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Macros that help define structures for both C and assembler.
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-------------------------------------------------------------------------------
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*/
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#ifdef STRUCT_BEGIN
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#undef STRUCT_BEGIN
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#undef STRUCT_FIELD
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#undef STRUCT_AFIELD
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#undef STRUCT_END
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#endif
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#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
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#define STRUCT_BEGIN .pushsection .text; .struct 0
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#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
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#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
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#define STRUCT_END(sname) sname##Size:; .popsection
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#else
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#define STRUCT_BEGIN typedef struct {
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#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
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#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
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#define STRUCT_END(sname) } sname;
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#endif //_ASMLANGUAGE || __ASSEMBLER__
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/*
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-------------------------------------------------------------------------------
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INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
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A stack frame of this structure is allocated for any interrupt or exception.
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It goes on the current stack. If the RTOS has a system stack for handling
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interrupts, every thread stack must allow space for just one interrupt stack
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frame, then nested interrupt stack frames go on the system stack.
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The frame includes basic registers (explicit) and "extra" registers introduced
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by user TIE or the use of the MAC16 option in the user's Xtensa config.
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The frame size is minimized by omitting regs not applicable to user's config.
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For Windowed ABI, this stack frame includes the interruptee's base save area,
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another base save area to manage gcc nested functions, and a little temporary
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space to help manage the spilling of the register windows.
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-------------------------------------------------------------------------------
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*/
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STRUCT_BEGIN
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STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
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STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
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STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
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STRUCT_FIELD (long, 4, XT_STK_A0, a0)
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STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
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STRUCT_FIELD (long, 4, XT_STK_A2, a2)
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STRUCT_FIELD (long, 4, XT_STK_A3, a3)
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STRUCT_FIELD (long, 4, XT_STK_A4, a4)
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STRUCT_FIELD (long, 4, XT_STK_A5, a5)
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STRUCT_FIELD (long, 4, XT_STK_A6, a6)
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STRUCT_FIELD (long, 4, XT_STK_A7, a7)
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STRUCT_FIELD (long, 4, XT_STK_A8, a8)
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STRUCT_FIELD (long, 4, XT_STK_A9, a9)
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STRUCT_FIELD (long, 4, XT_STK_A10, a10)
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STRUCT_FIELD (long, 4, XT_STK_A11, a11)
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STRUCT_FIELD (long, 4, XT_STK_A12, a12)
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STRUCT_FIELD (long, 4, XT_STK_A13, a13)
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STRUCT_FIELD (long, 4, XT_STK_A14, a14)
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STRUCT_FIELD (long, 4, XT_STK_A15, a15)
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STRUCT_FIELD (long, 4, XT_STK_SAR, sar)
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STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
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STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
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#if XCHAL_HAVE_LOOPS
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STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
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STRUCT_FIELD (long, 4, XT_STK_LEND, lend)
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STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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/* Temporary space for saving stuff during window spill */
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STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)
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STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)
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STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)
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#endif
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#ifdef XT_USE_SWPRI
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/* Storage for virtual priority mask */
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STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)
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#endif
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#ifdef XT_USE_OVLY
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/* Storage for overlay state */
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STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)
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#endif
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STRUCT_END(XtExcFrame)
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#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
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#define XT_STK_NEXT1 XtExcFrameSize
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#else
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#define XT_STK_NEXT1 sizeof(XtExcFrame)
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#endif
|
||||
|
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/* Allocate extra storage if needed */
|
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#if XCHAL_EXTRA_SA_SIZE != 0
|
||||
|
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#if XCHAL_EXTRA_SA_ALIGN <= 16
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#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
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#else
|
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/* If need more alignment than stack, add space for dynamic alignment */
|
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#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
|
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#endif
|
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#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
|
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|
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#else
|
||||
|
||||
#define XT_STK_NEXT2 XT_STK_NEXT1
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
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This is the frame size. Add space for 4 registers (interruptee's base save
|
||||
area) and some space for gcc nested functions if any.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
SOLICITED STACK FRAME FOR A THREAD
|
||||
|
||||
A stack frame of this structure is allocated whenever a thread enters the
|
||||
RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
|
||||
It goes on the current thread's stack.
|
||||
|
||||
The solicited frame only includes registers that are required to be preserved
|
||||
by the callee according to the compiler's ABI conventions, some space to save
|
||||
the return address for returning to the caller, and the caller's PS register.
|
||||
|
||||
For Windowed ABI, this stack frame includes the caller's base save area.
|
||||
|
||||
Note on XT_SOL_EXIT field:
|
||||
It is necessary to distinguish a solicited from an interrupt stack frame.
|
||||
This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
|
||||
always at the same offset (0). It can be written with a code (usually 0)
|
||||
to distinguish a solicted frame from an interrupt frame. An RTOS port may
|
||||
opt to ignore this field if it has another way of distinguishing frames.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
STRUCT_BEGIN
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
|
||||
#else
|
||||
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
|
||||
STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
|
||||
#endif
|
||||
STRUCT_END(XtSolFrame)
|
||||
|
||||
/* Size of solicited stack frame */
|
||||
#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
CO-PROCESSOR STATE SAVE AREA FOR A THREAD
|
||||
|
||||
The RTOS must provide an area per thread to save the state of co-processors
|
||||
when that thread does not have control. Co-processors are context-switched
|
||||
lazily (on demand) only when a new thread uses a co-processor instruction,
|
||||
otherwise a thread retains ownership of the co-processor even when it loses
|
||||
control of the processor. An Xtensa co-processor exception is triggered when
|
||||
any co-processor instruction is executed by a thread that is not the owner,
|
||||
and the context switch of that co-processor is then peformed by the handler.
|
||||
Ownership represents which thread's state is currently in the co-processor.
|
||||
|
||||
Co-processors may not be used by interrupt or exception handlers. If an
|
||||
co-processor instruction is executed by an interrupt or exception handler,
|
||||
the co-processor exception handler will trigger a kernel panic and freeze.
|
||||
This restriction is introduced to reduce the overhead of saving and restoring
|
||||
co-processor state (which can be quite large) and in particular remove that
|
||||
overhead from interrupt handlers.
|
||||
|
||||
The co-processor state save area may be in any convenient per-thread location
|
||||
such as in the thread control block or above the thread stack area. It need
|
||||
not be in the interrupt stack frame since interrupts don't use co-processors.
|
||||
|
||||
Along with the save area for each co-processor, two bitmasks with flags per
|
||||
co-processor (laid out as in the CPENABLE reg) help manage context-switching
|
||||
co-processors as efficiently as possible:
|
||||
|
||||
XT_CPENABLE
|
||||
The contents of a non-running thread's CPENABLE register.
|
||||
It represents the co-processors owned (and whose state is still needed)
|
||||
by the thread. When a thread is preempted, its CPENABLE is saved here.
|
||||
When a thread solicits a context-swtich, its CPENABLE is cleared - the
|
||||
compiler has saved the (caller-saved) co-proc state if it needs to.
|
||||
When a non-running thread loses ownership of a CP, its bit is cleared.
|
||||
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
|
||||
Avoids co-processor exceptions when no change of ownership is needed.
|
||||
|
||||
XT_CPSTORED
|
||||
A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether the state of each co-processor is saved in the state
|
||||
save area. When a thread enters the kernel, only the state of co-procs
|
||||
still enabled in CPENABLE is saved. When the co-processor exception
|
||||
handler assigns ownership of a co-processor to a thread, it restores
|
||||
the saved state only if this bit is set, and clears this bit.
|
||||
|
||||
XT_CP_CS_ST
|
||||
A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether callee-saved state is saved in the state save area.
|
||||
Callee-saved state is saved by itself on a solicited context switch,
|
||||
and restored when needed by the coprocessor exception handler.
|
||||
Unsolicited switches will cause the entire coprocessor to be saved
|
||||
when necessary.
|
||||
|
||||
XT_CP_ASA
|
||||
Pointer to the aligned save area. Allows it to be aligned more than
|
||||
the overall save area (which might only be stack-aligned or TCB-aligned).
|
||||
Especially relevant for Xtensa cores configured with a very large data
|
||||
path that requires alignment greater than 16 bytes (ABI stack alignment).
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if XCHAL_CP_NUM > 0
|
||||
|
||||
/* Offsets of each coprocessor save area within the 'aligned save area': */
|
||||
#define XT_CP0_SA 0
|
||||
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
|
||||
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
|
||||
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
|
||||
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
|
||||
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
|
||||
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
|
||||
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
|
||||
#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
|
||||
|
||||
/* Offsets within the overall save area: */
|
||||
#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
|
||||
#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
|
||||
#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
|
||||
#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
|
||||
/* Overall size allows for dynamic alignment: */
|
||||
#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
|
||||
#else
|
||||
#define XT_CP_SIZE 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Macro to get the current core ID. Only uses the reg given as an argument.
|
||||
Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
|
||||
and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
|
||||
bit 13: it's 1 on the APP and 0 on the PRO processor.
|
||||
*/
|
||||
#ifdef __ASSEMBLER__
|
||||
.macro getcoreid reg
|
||||
rsr.prid \reg
|
||||
extui \reg,\reg,13,1
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use
|
||||
0 and 1 which are determined by checking bit 13 (see previous comment)
|
||||
*/
|
||||
#define CORE_ID_REGVAL_PRO 0xCDCD
|
||||
#define CORE_ID_REGVAL_APP 0xABAB
|
||||
|
||||
/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */
|
||||
#define CORE_ID_PRO CORE_ID_REGVAL_PRO
|
||||
|
||||
/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */
|
||||
#define CORE_ID_APP CORE_ID_REGVAL_APP
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
|
||||
|
||||
Convenient where the frame size requirements are the same for both ABIs.
|
||||
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
|
||||
ENTRY0, RET0 are for frameless functions (no locals, no calls).
|
||||
|
||||
where size = size of stack frame in bytes (must be >0 and aligned to 16).
|
||||
For framed functions the frame is created and the return address saved at
|
||||
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
|
||||
For frameless functions, there is no frame and return address remains in a0.
|
||||
Note: Because CPP macros expand to a single line, macros requiring multi-line
|
||||
expansions are implemented as assembler macros.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
/* Call0 */
|
||||
#define ENTRY(sz) entry1 sz
|
||||
.macro entry1 size=0x10
|
||||
addi sp, sp, -\size
|
||||
s32i a0, sp, 0
|
||||
.endm
|
||||
#define ENTRY0
|
||||
#define RET(sz) ret1 sz
|
||||
.macro ret1 size=0x10
|
||||
l32i a0, sp, 0
|
||||
addi sp, sp, \size
|
||||
ret
|
||||
.endm
|
||||
#define RET0 ret
|
||||
#else
|
||||
/* Windowed */
|
||||
#define ENTRY(sz) entry sp, sz
|
||||
#define ENTRY0 entry sp, 0x10
|
||||
#define RET(sz) retw
|
||||
#define RET0 retw
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* XTENSA_CONTEXT_H */
|
||||
|
||||
/* This header file has been moved, please include <xtensa/xtensa_context.h> in future */
|
||||
#include <xtensa/xtensa_context.h>
|
||||
@@ -386,7 +386,8 @@ _frxt_tick_timer_init:
|
||||
call0 xt_ints_on
|
||||
#else
|
||||
movi a6, XT_TIMER_INTEN
|
||||
call4 xt_ints_on
|
||||
movi a3, xt_ints_on
|
||||
callx4 a3
|
||||
#endif
|
||||
|
||||
RET(16)
|
||||
|
||||
@@ -1,158 +0,0 @@
|
||||
/*******************************************************************************
|
||||
Copyright (c) 2006-2015 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Xtensa-specific interrupt and exception functions for RTOS ports.
|
||||
Also see xtensa_intr_asm.S.
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
#include "freertos/portable.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
#if XCHAL_HAVE_EXCEPTIONS
|
||||
|
||||
/* Handler table is in xtensa_intr_asm.S */
|
||||
|
||||
extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM*portNUM_PROCESSORS];
|
||||
|
||||
|
||||
/*
|
||||
Default handler for unhandled exceptions.
|
||||
CHANGED: We do this in panic.c now
|
||||
*/
|
||||
|
||||
//void xt_unhandled_exception(XtExcFrame *frame)
|
||||
//{
|
||||
//exit(-1);
|
||||
//}
|
||||
extern void xt_unhandled_exception(XtExcFrame *frame);
|
||||
|
||||
|
||||
/*
|
||||
This function registers a handler for the specified exception.
|
||||
The function returns the address of the previous handler.
|
||||
On error, it returns 0.
|
||||
*/
|
||||
xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
|
||||
{
|
||||
xt_exc_handler old;
|
||||
|
||||
if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
|
||||
return 0; /* invalid exception number */
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
old = _xt_exception_table[n];
|
||||
|
||||
if (f) {
|
||||
_xt_exception_table[n] = f;
|
||||
}
|
||||
else {
|
||||
_xt_exception_table[n] = &xt_unhandled_exception;
|
||||
}
|
||||
|
||||
return ((old == &xt_unhandled_exception) ? 0 : old);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
|
||||
/* Handler table is in xtensa_intr_asm.S */
|
||||
|
||||
typedef struct xt_handler_table_entry {
|
||||
void * handler;
|
||||
void * arg;
|
||||
} xt_handler_table_entry;
|
||||
|
||||
extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];
|
||||
|
||||
|
||||
/*
|
||||
Default handler for unhandled interrupts.
|
||||
*/
|
||||
void xt_unhandled_interrupt(void * arg)
|
||||
{
|
||||
esp_rom_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, xPortGetCoreID());
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
This function registers a handler for the specified interrupt. The "arg"
|
||||
parameter specifies the argument to be passed to the handler when it is
|
||||
invoked. The function returns the address of the previous handler.
|
||||
On error, it returns 0.
|
||||
*/
|
||||
xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
|
||||
{
|
||||
xt_handler_table_entry * entry;
|
||||
xt_handler old;
|
||||
|
||||
if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
|
||||
return 0; /* invalid interrupt number */
|
||||
if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
|
||||
return 0; /* priority level too high to safely handle in C */
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
|
||||
entry = _xt_interrupt_table + n;
|
||||
old = entry->handler;
|
||||
|
||||
if (f) {
|
||||
entry->handler = f;
|
||||
entry->arg = arg;
|
||||
}
|
||||
else {
|
||||
entry->handler = &xt_unhandled_interrupt;
|
||||
entry->arg = (void*)n;
|
||||
}
|
||||
|
||||
return ((old == &xt_unhandled_interrupt) ? 0 : old);
|
||||
}
|
||||
|
||||
#if CONFIG_SYSVIEW_ENABLE
|
||||
void * xt_get_interrupt_handler_arg(int n)
|
||||
{
|
||||
xt_handler_table_entry * entry;
|
||||
|
||||
if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
|
||||
return 0; /* invalid interrupt number */
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
|
||||
entry = _xt_interrupt_table + n;
|
||||
return entry->arg;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* XCHAL_HAVE_INTERRUPTS */
|
||||
|
||||
@@ -1,225 +0,0 @@
|
||||
/*******************************************************************************
|
||||
Copyright (c) 2006-2015 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Xtensa interrupt handling data and assembly routines.
|
||||
Also see xtensa_intr.c and xtensa_vectors.S.
|
||||
******************************************************************************/
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#include "xtensa_context.h"
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
INTENABLE virtualization information.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#if XT_USE_SWPRI
|
||||
/* Warning - this is not multicore-compatible. */
|
||||
.data
|
||||
.global _xt_intdata
|
||||
.align 8
|
||||
_xt_intdata:
|
||||
.global _xt_intenable
|
||||
.type _xt_intenable,@object
|
||||
.size _xt_intenable,4
|
||||
.global _xt_vpri_mask
|
||||
.type _xt_vpri_mask,@object
|
||||
.size _xt_vpri_mask,4
|
||||
|
||||
_xt_intenable: .word 0 /* Virtual INTENABLE */
|
||||
_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
|
||||
#endif
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
Table of C-callable interrupt handlers for each interrupt. Note that not all
|
||||
slots can be filled, because interrupts at level > EXCM_LEVEL will not be
|
||||
dispatched to a C handler by default.
|
||||
|
||||
Stored as:
|
||||
int 0 cpu 0
|
||||
int 0 cpu 1
|
||||
...
|
||||
int 0 cpu n
|
||||
int 1 cpu 0
|
||||
int 1 cpu 1
|
||||
etc
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.data
|
||||
.global _xt_interrupt_table
|
||||
.align 8
|
||||
|
||||
_xt_interrupt_table:
|
||||
|
||||
.set i, 0
|
||||
.rept XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
|
||||
.word xt_unhandled_interrupt /* handler address */
|
||||
.word i /* handler arg (default: intnum) */
|
||||
.set i, i+1
|
||||
.endr
|
||||
|
||||
#endif /* XCHAL_HAVE_INTERRUPTS */
|
||||
|
||||
|
||||
#if XCHAL_HAVE_EXCEPTIONS
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
Table of C-callable exception handlers for each exception. Note that not all
|
||||
slots will be active, because some exceptions (e.g. coprocessor exceptions)
|
||||
are always handled by the OS and cannot be hooked by user handlers.
|
||||
|
||||
Stored as:
|
||||
exc 0 cpu 0
|
||||
exc 0 cpu 1
|
||||
...
|
||||
exc 0 cpu n
|
||||
exc 1 cpu 0
|
||||
exc 1 cpu 1
|
||||
etc
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.data
|
||||
.global _xt_exception_table
|
||||
.align 4
|
||||
|
||||
_xt_exception_table:
|
||||
.rept XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
|
||||
.word xt_unhandled_exception /* handler address */
|
||||
.endr
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
unsigned int xt_ints_on ( unsigned int mask )
|
||||
|
||||
Enables a set of interrupts. Does not simply set INTENABLE directly, but
|
||||
computes it as a function of the current virtual priority if XT_USE_SWPRI is
|
||||
enabled.
|
||||
Can be called from interrupt handlers.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.global xt_ints_on
|
||||
.type xt_ints_on,@function
|
||||
|
||||
xt_ints_on:
|
||||
|
||||
ENTRY0
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#if XT_USE_SWPRI
|
||||
movi a3, 0
|
||||
movi a4, _xt_intdata
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
l32i a3, a4, 0 /* a3 = _xt_intenable */
|
||||
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
|
||||
or a5, a3, a2 /* a5 = _xt_intenable | mask */
|
||||
s32i a5, a4, 0 /* _xt_intenable |= mask */
|
||||
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
|
||||
wsr a5, INTENABLE /* Reenable interrupts */
|
||||
mov a2, a3 /* Previous mask */
|
||||
#else
|
||||
movi a3, 0
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
or a2, a3, a2 /* set bits in mask */
|
||||
wsr a2, INTENABLE /* Re-enable ints */
|
||||
rsync
|
||||
mov a2, a3 /* return prev mask */
|
||||
#endif
|
||||
#else
|
||||
movi a2, 0 /* Return zero */
|
||||
#endif
|
||||
RET0
|
||||
|
||||
.size xt_ints_on, . - xt_ints_on
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
unsigned int xt_ints_off ( unsigned int mask )
|
||||
|
||||
Disables a set of interrupts. Does not simply set INTENABLE directly,
|
||||
but computes it as a function of the current virtual priority if XT_USE_SWPRI is
|
||||
enabled.
|
||||
Can be called from interrupt handlers.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.global xt_ints_off
|
||||
.type xt_ints_off,@function
|
||||
|
||||
xt_ints_off:
|
||||
|
||||
ENTRY0
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#if XT_USE_SWPRI
|
||||
movi a3, 0
|
||||
movi a4, _xt_intdata
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
l32i a3, a4, 0 /* a3 = _xt_intenable */
|
||||
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
|
||||
or a5, a3, a2 /* a5 = _xt_intenable | mask */
|
||||
xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
|
||||
s32i a5, a4, 0 /* _xt_intenable &= ~mask */
|
||||
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
|
||||
wsr a5, INTENABLE /* Reenable interrupts */
|
||||
mov a2, a3 /* Previous mask */
|
||||
#else
|
||||
movi a4, 0
|
||||
xsr a4, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
or a3, a4, a2 /* set bits in mask */
|
||||
xor a3, a3, a2 /* invert bits in mask set in mask, essentially clearing them */
|
||||
wsr a3, INTENABLE /* Re-enable ints */
|
||||
rsync
|
||||
mov a2, a4 /* return prev mask */
|
||||
#endif
|
||||
#else
|
||||
movi a2, 0 /* return zero */
|
||||
#endif
|
||||
RET0
|
||||
|
||||
.size xt_ints_off, . - xt_ints_off
|
||||
|
||||
|
||||
Reference in New Issue
Block a user