mirror of
https://github.com/espressif/esp-idf.git
synced 2026-06-11 11:42:39 +02:00
intr_alloc: split interrupt allocator into common-code and platform-code
esp_system: removed repeated interrupt allocator code and moved common code to esp_system xtens: moved xtensa specific code from freertos to the xtensa component hal/interrupt_controller: added interrupt controller hal and ll files docs: update the doxyfile with new location of esp_itr_alloc.h file xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos docs: removed Xtensa reference from intr_allocator api-reference xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer esp_system/test: fixed platform dependent setting for intr_allocator tests hal: rename the functions used to manage non iram interrupt mask.
This commit is contained in:
Felipe Neves
committed by
Angus Gratton
Angus Gratton
parent
59b763bb9a
commit
2e826b7a8f
@@ -30,7 +30,9 @@ if(NOT BOOTLOADER_BUILD)
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"spi_flash_hal.c"
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"spi_flash_hal_iram.c"
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"soc_hal.c"
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"twai_hal.c")
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"twai_hal.c"
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"interrupt_controller_hal.c"
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"${target}/interrupt_descriptor_table.c")
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if(${target} STREQUAL "esp32")
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list(APPEND srcs
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@@ -0,0 +1,105 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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#include "xtensa/xtensa_api.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief enable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be enabled
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*/
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static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
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{
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xt_ints_on(mask);
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}
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/**
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* @brief disable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be disabled
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*/
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static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
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{
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xt_ints_off(mask);
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}
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/**
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* @brief checks if given interrupt number has a valid handler
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
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* @return true for valid handler, false otherwise
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*/
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static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
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{
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return xt_int_has_handler(intr, cpu);
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}
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/**
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* @brief sets interrupt handler and optional argument of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param handler handler invoked when an interrupt occurs
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* @param arg optional argument to pass to the handler
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*/
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static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
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{
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xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
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}
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/**
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* @brief Gets argument passed to handler of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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*
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* @return argument used by handler of passed interrupt number
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*/
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static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
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{
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return xt_get_interrupt_handler_arg(intr);
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}
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/**
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* @brief Disables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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* @return oldmask where to store old interrupts state
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*/
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static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
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{
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return xt_int_disable_mask(newmask);
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}
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/**
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* @brief Enables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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*/
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static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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{
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xt_int_enable_mask(newmask);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,75 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "hal/interrupt_controller_hal.h"
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#include "hal/interrupt_controller_ll.h"
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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//We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
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//is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
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//the table below.
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#if CONFIG_FREERTOS_CORETIMER_0
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#define INT6RES INTDESC_RESVD
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#else
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#define INT6RES INTDESC_SPECIAL
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#endif
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#if CONFIG_FREERTOS_CORETIMER_1
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#define INT15RES INTDESC_RESVD
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#else
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#define INT15RES INTDESC_SPECIAL
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#endif
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//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
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const static int_desc_t interrupt_descriptor_table [32]={
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{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //0
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{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //1
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //2
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //3
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{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //4
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{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //5
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{ 1, INTTP_NA, {INT6RES, INT6RES } }, //6
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{ 1, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //7
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{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //8
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //9
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{ 1, INTTP_EDGE , {INTDESC_NORMAL, INTDESC_NORMAL} }, //10
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{ 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //11
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //12
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //13
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{ 7, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //14, NMI
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{ 3, INTTP_NA, {INT15RES, INT15RES } }, //15
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{ 5, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL} }, //16
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //17
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //18
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //19
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //20
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //21
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{ 3, INTTP_EDGE, {INTDESC_RESVD, INTDESC_NORMAL} }, //22
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //23
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{ 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //24
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{ 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //25
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{ 5, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_RESVD } }, //26
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{ 3, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //27
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{ 4, INTTP_EDGE, {INTDESC_NORMAL, INTDESC_NORMAL} }, //28
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{ 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //29
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{ 4, INTTP_EDGE, {INTDESC_RESVD, INTDESC_RESVD } }, //30
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{ 5, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //31
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};
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const int_desc_t *interrupt_controller_hal_desc_table(void)
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{
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return interrupt_descriptor_table;
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}
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@@ -0,0 +1,105 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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|
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
|
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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#include "xtensa/xtensa_api.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief enable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be enabled
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*/
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static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
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{
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xt_ints_on(mask);
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}
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/**
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* @brief disable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be disabled
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*/
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static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
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{
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xt_ints_off(mask);
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}
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/**
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* @brief checks if given interrupt number has a valid handler
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
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* @return true for valid handler, false otherwise
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*/
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static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
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{
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return xt_int_has_handler(intr, cpu);
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}
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/**
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* @brief sets interrupt handler and optional argument of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param handler handler invoked when an interrupt occurs
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* @param arg optional argument to pass to the handler
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*/
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static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
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{
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xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
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}
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/**
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* @brief Gets argument passed to handler of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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*
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* @return argument used by handler of passed interrupt number
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*/
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static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
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{
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return xt_get_interrupt_handler_arg(intr);
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}
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/**
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* @brief Disables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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* @return oldmask where to store old interrupts state
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*/
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static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
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{
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return xt_int_disable_mask(newmask);
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}
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/**
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* @brief Enables interrupts that are not located in iram
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*
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* @param newmask mask of interrupts needs to be disabled
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*/
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static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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{
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xt_int_enable_mask(newmask);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,75 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "sdkconfig.h"
|
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#include "hal/interrupt_controller_hal.h"
|
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#include "hal/interrupt_controller_ll.h"
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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|
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//We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
|
||||
//is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
|
||||
//the table below.
|
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#if CONFIG_FREERTOS_CORETIMER_0
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#define INT6RES INTDESC_RESVD
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#else
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#define INT6RES INTDESC_SPECIAL
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#endif
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#if CONFIG_FREERTOS_CORETIMER_1
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#define INT15RES INTDESC_RESVD
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#else
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#define INT15RES INTDESC_SPECIAL
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#endif
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//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
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const static int_desc_t interrupt_descriptor_table [32]={
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{ 1, INTTP_LEVEL, {INTDESC_RESVD} }, //0
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{ 1, INTTP_LEVEL, {INTDESC_RESVD} }, //1
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //2
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //3
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{ 1, INTTP_LEVEL, {INTDESC_RESVD} }, //4
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{ 1, INTTP_LEVEL, {INTDESC_RESVD} }, //5
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{ 1, INTTP_NA, {INT6RES} }, //6
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{ 1, INTTP_NA, {INTDESC_SPECIAL}}, //7
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{ 1, INTTP_LEVEL, {INTDESC_RESVD } }, //8
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //9
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{ 1, INTTP_EDGE , {INTDESC_NORMAL } }, //10
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{ 3, INTTP_NA, {INTDESC_SPECIAL }}, //11
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //12
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL} }, //13
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{ 7, INTTP_LEVEL, {INTDESC_RESVD} }, //14, NMI
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{ 3, INTTP_NA, {INT15RES} }, //15
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{ 5, INTTP_NA, {INTDESC_SPECIAL } }, //16
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //17
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //18
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //19
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //20
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21
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{ 3, INTTP_EDGE, {INTDESC_RESVD } }, //22
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25
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{ 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26
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{ 3, INTTP_LEVEL, {INTDESC_RESVD } }, //27
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{ 4, INTTP_EDGE, {INTDESC_NORMAL } }, //28
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{ 3, INTTP_NA, {INTDESC_SPECIAL }}, //29
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{ 4, INTTP_EDGE, {INTDESC_RESVD } }, //30
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{ 5, INTTP_LEVEL, {INTDESC_RESVD } }, //31
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};
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const int_desc_t *interrupt_controller_hal_desc_table(void)
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{
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return interrupt_descriptor_table;
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}
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@@ -0,0 +1,105 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/soc.h"
|
||||
#include "xtensa/xtensa_api.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief enable interrupts specified by the mask
|
||||
*
|
||||
* @param mask bitmask of interrupts that needs to be enabled
|
||||
*/
|
||||
static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
|
||||
{
|
||||
xt_ints_on(mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable interrupts specified by the mask
|
||||
*
|
||||
* @param mask bitmask of interrupts that needs to be disabled
|
||||
*/
|
||||
static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
|
||||
{
|
||||
xt_ints_off(mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief checks if given interrupt number has a valid handler
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
|
||||
* @return true for valid handler, false otherwise
|
||||
*/
|
||||
static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
|
||||
{
|
||||
return xt_int_has_handler(intr, cpu);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets interrupt handler and optional argument of a given interrupt number
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
* @param handler handler invoked when an interrupt occurs
|
||||
* @param arg optional argument to pass to the handler
|
||||
*/
|
||||
static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
|
||||
{
|
||||
xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets argument passed to handler of a given interrupt number
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
*
|
||||
* @return argument used by handler of passed interrupt number
|
||||
*/
|
||||
static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
|
||||
{
|
||||
return xt_get_interrupt_handler_arg(intr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables interrupts that are not located in iram
|
||||
*
|
||||
* @param newmask mask of interrupts needs to be disabled
|
||||
* @return oldmask where to store old interrupts state
|
||||
*/
|
||||
static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
|
||||
{
|
||||
return xt_int_disable_mask(newmask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables interrupts that are not located in iram
|
||||
*
|
||||
* @param newmask mask of interrupts needs to be disabled
|
||||
*/
|
||||
static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
|
||||
{
|
||||
xt_int_enable_mask(newmask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,75 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "hal/interrupt_controller_hal.h"
|
||||
#include "hal/interrupt_controller_ll.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
//We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
|
||||
//is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
|
||||
//the table below.
|
||||
#if CONFIG_FREERTOS_CORETIMER_0
|
||||
#define INT6RES INTDESC_RESVD
|
||||
#else
|
||||
#define INT6RES INTDESC_SPECIAL
|
||||
#endif
|
||||
|
||||
#if CONFIG_FREERTOS_CORETIMER_1
|
||||
#define INT15RES INTDESC_RESVD
|
||||
#else
|
||||
#define INT15RES INTDESC_SPECIAL
|
||||
#endif
|
||||
|
||||
//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
|
||||
const static int_desc_t interrupt_descriptor_table [32]={
|
||||
{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //0
|
||||
{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //1
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //2
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //3
|
||||
{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //4
|
||||
{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //5
|
||||
{ 1, INTTP_NA, {INT6RES, INT6RES } }, //6
|
||||
{ 1, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //7
|
||||
{ 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //8
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //9
|
||||
{ 1, INTTP_EDGE , {INTDESC_NORMAL, INTDESC_NORMAL} }, //10
|
||||
{ 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //11
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //12
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //13
|
||||
{ 7, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //14, NMI
|
||||
{ 3, INTTP_NA, {INT15RES, INT15RES } }, //15
|
||||
{ 5, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL} }, //16
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //17
|
||||
{ 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //18
|
||||
{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //19
|
||||
{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //20
|
||||
{ 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //21
|
||||
{ 3, INTTP_EDGE, {INTDESC_RESVD, INTDESC_NORMAL} }, //22
|
||||
{ 3, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //23
|
||||
{ 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //24
|
||||
{ 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //25
|
||||
{ 5, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_RESVD } }, //26
|
||||
{ 3, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //27
|
||||
{ 4, INTTP_EDGE, {INTDESC_NORMAL, INTDESC_NORMAL} }, //28
|
||||
{ 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //29
|
||||
{ 4, INTTP_EDGE, {INTDESC_RESVD, INTDESC_RESVD } }, //30
|
||||
{ 5, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //31
|
||||
};
|
||||
|
||||
const int_desc_t *interrupt_controller_hal_desc_table(void)
|
||||
{
|
||||
return interrupt_descriptor_table;
|
||||
}
|
||||
@@ -0,0 +1,170 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "hal/interrupt_controller_types.h"
|
||||
#include "hal/interrupt_controller_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Gets target platform interrupt descriptor table
|
||||
*
|
||||
* @return Address of interrupt descriptor table
|
||||
*/
|
||||
__attribute__((pure)) const int_desc_t *interrupt_controller_hal_desc_table(void);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt type given an interrupt number.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @return interrupt type
|
||||
*/
|
||||
__attribute__((pure)) int_type_t interrupt_controller_hal_desc_type(int interrupt_number);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt level given an interrupt number.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @return interrupt level bitmask
|
||||
*/
|
||||
__attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_number);
|
||||
|
||||
/**
|
||||
* @brief Gets the cpu flags given the interrupt number and target cpu.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1
|
||||
* @return flags for that interrupt number
|
||||
*/
|
||||
__attribute__((pure)) uint32_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number);
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt type given an interrupt number.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @return interrupt type
|
||||
*/
|
||||
static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number)
|
||||
{
|
||||
return interrupt_controller_hal_desc_type(interrupt_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt level given an interrupt number.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @return interrupt level bitmask
|
||||
*/
|
||||
static inline int interrupt_controller_hal_get_level(int interrupt_number)
|
||||
{
|
||||
return interrupt_controller_hal_desc_level(interrupt_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the cpu flags given the interrupt number and target cpu.
|
||||
*
|
||||
* @param interrupt_number Interrupt number 0 to 31
|
||||
* @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1
|
||||
* @return flags for that interrupt number
|
||||
*/
|
||||
static inline uint32_t interrupt_controller_hal_get_cpu_desc_flags(int interrupt_number, int cpu_number)
|
||||
{
|
||||
return interrupt_controller_hal_desc_flags(interrupt_number, cpu_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable interrupts specified by the mask
|
||||
*
|
||||
* @param mask bitmask of interrupts that needs to be enabled
|
||||
*/
|
||||
static inline void interrupt_controller_hal_enable_interrupts(uint32_t mask)
|
||||
{
|
||||
intr_cntrl_ll_enable_interrupts(mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable interrupts specified by the mask
|
||||
*
|
||||
* @param mask bitmask of interrupts that needs to be disabled
|
||||
*/
|
||||
static inline void interrupt_controller_hal_disable_interrupts(uint32_t mask)
|
||||
{
|
||||
intr_cntrl_ll_disable_interrupts(mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief checks if given interrupt number has a valid handler
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
|
||||
* @return true for valid handler, false otherwise
|
||||
*/
|
||||
static inline bool interrupt_controller_hal_has_handler(int intr, int cpu)
|
||||
{
|
||||
return intr_cntrl_ll_has_handler(intr, cpu);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets interrupt handler and optional argument of a given interrupt number
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
* @param handler handler invoked when an interrupt occurs
|
||||
* @param arg optional argument to pass to the handler
|
||||
*/
|
||||
static inline void interrupt_controller_hal_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
|
||||
{
|
||||
intr_cntrl_ll_set_int_handler(intr, handler, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets argument passed to handler of a given interrupt number
|
||||
*
|
||||
* @param intr interrupt number ranged from 0 to 31
|
||||
*
|
||||
* @return argument used by handler of passed interrupt number
|
||||
*/
|
||||
static inline void * interrupt_controller_hal_get_int_handler_arg(uint8_t intr)
|
||||
{
|
||||
return intr_cntrl_ll_get_int_handler_arg(intr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables interrupts that are not located in iram
|
||||
*
|
||||
* @param newmask mask of interrupts needs to be disabled
|
||||
* @return oldmask where to store old interrupts state
|
||||
*/
|
||||
static inline uint32_t interrupt_controller_hal_disable_int_mask(uint32_t newmask)
|
||||
{
|
||||
return intr_cntrl_ll_disable_int_mask(newmask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables interrupts that are not located in iram
|
||||
*
|
||||
* @param newmask mask of interrupts needs to be disabled
|
||||
*/
|
||||
static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask)
|
||||
{
|
||||
intr_cntrl_ll_enable_int_mask(newmask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
INTDESC_NORMAL=0,
|
||||
INTDESC_RESVD,
|
||||
INTDESC_SPECIAL
|
||||
} int_desc_flag_t;
|
||||
|
||||
typedef enum {
|
||||
INTTP_LEVEL=0,
|
||||
INTTP_EDGE,
|
||||
INTTP_NA
|
||||
} int_type_t;
|
||||
|
||||
typedef struct {
|
||||
int level;
|
||||
int_type_t type;
|
||||
int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM];
|
||||
} int_desc_t;
|
||||
|
||||
typedef void (*interrupt_handler_t)(void *arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "hal/interrupt_controller_hal.h"
|
||||
|
||||
int_type_t interrupt_controller_hal_desc_type(int interrupt_number)
|
||||
{
|
||||
const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
|
||||
return(int_desc[interrupt_number].type);
|
||||
}
|
||||
|
||||
int interrupt_controller_hal_desc_level(int interrupt_number)
|
||||
{
|
||||
const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
|
||||
return(int_desc[interrupt_number].level);
|
||||
}
|
||||
|
||||
int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number)
|
||||
{
|
||||
const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
|
||||
return(int_desc[interrupt_number].cpuflags[cpu_number]);
|
||||
}
|
||||
Reference in New Issue
Block a user