From 2ed2e7e1914d28febc87128f976b34af45fc0e9c Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 7 Mar 2023 11:13:18 +0800 Subject: [PATCH] bootloader: fixed super watchdog not enabled issue on C3, S3, H4 --- .../bootloader_support/src/esp32c3/bootloader_esp32c3.c | 6 +++--- components/bootloader_support/src/esp32c3/bootloader_soc.c | 6 +++--- .../bootloader_support/src/esp32s3/bootloader_esp32s3.c | 2 +- components/bootloader_support/src/esp32s3/bootloader_soc.c | 6 +++--- components/soc/esp32c3/include/soc/rtc_cntl_reg.h | 2 +- components/soc/esp32s3/include/soc/rtc_cntl_reg.h | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index fe9d94cfca..ac30fac100 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -276,20 +276,20 @@ static inline void bootloader_ana_reset_config(void) switch (efuse_hal_chip_revision()) { case 0: case 1: - //Enable WDT reset. Disable BOR and GLITCH reset + //Enable WDT reset. Disable BOD and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(false); bootloader_ana_clock_glitch_reset_config(false); break; case 2: - //Enable WDT and BOR reset. Disable GLITCH reset + //Enable WDT and BOD reset. Disable GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(false); break; case 3: default: - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32c3/bootloader_soc.c b/components/bootloader_support/src/esp32c3/bootloader_soc.c index 7104528a58..f808b72fd5 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32c3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index eaa655a6a2..732ff3a943 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -322,7 +322,7 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_ana_reset_config(void) { - //Enable WDT, BOR, and GLITCH reset + //Enable WDT, BOD, and GLITCH reset bootloader_ana_super_wdt_reset_config(true); bootloader_ana_bod_reset_config(true); bootloader_ana_clock_glitch_reset_config(true); diff --git a/components/bootloader_support/src/esp32s3/bootloader_soc.c b/components/bootloader_support/src/esp32s3/bootloader_soc.c index 7104528a58..f808b72fd5 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s3/bootloader_soc.c @@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable) REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); if (enable) { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); + } else { + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); } } void bootloader_ana_bod_reset_config(bool enable) { - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); + REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); if (enable) { REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index 1255f3994c..60940eb299 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -2361,7 +2361,7 @@ extern "C" { #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index e4ceaf0b62..de5d5ed572 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3577,7 +3577,7 @@ ork.*/ #define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOR_RST BIT(1) +#define RTC_CNTL_FIB_BOD_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C)