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uart: fixed reset logic on ESP32-S3

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songruojing
2022-01-17 20:32:39 +08:00
committed by Michael (XIAO Xufeng)
parent bdd7610e66
commit 2ef6b8845b
2 changed files with 13 additions and 0 deletions
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12
components/hal/esp32s3/include/hal/uart_ll.h
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@@ -62,6 +62,18 @@ typedef enum {
UART_INTR_CMD_CHAR_DET = (0x1 << 18), UART_INTR_CMD_CHAR_DET = (0x1 << 18),
} uart_intr_t; } uart_intr_t;
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
hw->clk_conf.rst_core = core_rst_en;
}
/** /**
* @brief Set the UART source clock. * @brief Set the UART source clock.

1
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -237,6 +237,7 @@
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_REQUIRE_CORE_RESET (1)
/*-------------------------- USB CAPS ----------------------------------------*/ /*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_PERIPH_NUM 1 #define SOC_USB_PERIPH_NUM 1