diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
index 7a4e36f9cc..7f34110666 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -55,6 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
index c12f5aad1b..33e8b9d2fe 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
@@ -52,6 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
diff --git a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5 b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5
index cf58113524..5df612aa4f 100644
--- a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5
+++ b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5
@@ -1,3 +1,3 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
diff --git a/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5 b/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5
index cf58113524..5df612aa4f 100644
--- a/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5
+++ b/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5
@@ -1,3 +1,3 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
diff --git a/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5 b/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5
index 49237a514f..492c21f549 100644
--- a/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5
+++ b/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5
@@ -1,5 +1,5 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 # Enabling the following configurations can help increase the PCLK frequency in the case when
 # the Frame Buffer is allocated from the PSRAM and fetched by EDMA
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y