Merge branch 'bugfix/spi_master_clear_error_fifo_status' into 'master'

spi_master: clear error fifo status before transaction starts

Closes IDF-3457 and IDF-3501

See merge request espressif/esp-idf!14210

.gitlab/ci/target-test.yml

@@ -652,6 +652,12 @@ UT_047:
     - ESP32S2_IDF
     - UT_T1_1
 
+UT_S2_SPI_DUAL:
+  extends: .unit_test_esp32s2_template
+  tags:
+    - ESP32S2_IDF
+    - Example_SPI_Multi_device
+
 UT_C3:
   extends: .unit_test_esp32c3_template
   parallel: 33
@@ -698,6 +704,12 @@ UT_S3:
     - ESP32S3_IDF
     - UT_T1_1
 
+UT_S3_SPI_DUAL:
+  extends: .unit_test_esp32s3_template
+  tags:
+    - ESP32S3_IDF
+    - Example_SPI_Multi_device
+
 .integration_test_template:
   extends:
     - .target_test_job_template

components/driver/test/include/test/test_common_spi.h

@@ -293,4 +293,8 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx);
 //then the cs_num of the 1st and 2nd devices are 0 and 1 respectively.
 void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_num);
 
+/**
+ * This function is used to get tx_buffer used in dual-board test
+ */
+void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size);
 #endif  //_TEST_COMMON_SPI_H_

components/driver/test/test_common_spi.c

@@ -238,3 +238,12 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev,
     GPIO.func_in_sel_cfg[FSPIQ_IN_IDX].sig_in_sel = 1;
 #endif
 }
+
+void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size)
+{
+    srand(seed);
+    for (int i = 0; i < send_buf_size; i++) {
+        slave_send_buf[i] = rand();
+        master_send_buf[i] = rand();
+    }
+}

components/driver/test/test_spi_master.c

@@ -1112,6 +1112,181 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
 //There is only one GPSPI controller, so single-board test is disabled.
 #endif  //#if !DISABLED_FOR_TARGETS(ESP32C3)
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)    //TODO: IDF-3494
+#define FD_TEST_BUF_SIZE    32
+#define TEST_NUM            4
+#define FD_SEED1            199
+#define FD_SEED2            29
+#define FD_SEED3            48
+#define FD_SEED4            327
+
+static void master_only_tx_trans(spi_device_handle_t spi, uint8_t *mst_send_buf, uint32_t length)
+{
+    ESP_LOGI(MASTER_TAG, "FD DMA, Only TX:");
+    spi_transaction_t trans = {0};
+    trans.tx_buffer = mst_send_buf;
+    trans.length = length * 8;
+    unity_wait_for_signal("Slave ready");
+    TEST_ESP_OK(spi_device_transmit(spi, &trans));
+    ESP_LOG_BUFFER_HEX("MASTER TX:", mst_send_buf, length);
+}
+
+static void master_only_rx_trans(spi_device_handle_t spi, uint8_t *mst_recv_buf, uint8_t *slv_send_buf, uint32_t length)
+{
+    ESP_LOGI(MASTER_TAG, "FD DMA, Only RX:");
+    spi_transaction_t trans = {0};
+    trans.tx_buffer = NULL;
+    trans.rx_buffer = mst_recv_buf;
+    trans.length = length * 8;
+    unity_wait_for_signal("Slave ready");
+    TEST_ESP_OK(spi_device_transmit(spi, &trans));
+    ESP_LOG_BUFFER_HEX("MASTER RX:", mst_recv_buf, length);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(slv_send_buf, mst_recv_buf, length);
+}
+
+static void master_both_trans(spi_device_handle_t spi, uint8_t *mst_send_buf, uint8_t *mst_recv_buf, uint8_t *slv_send_buf, uint32_t length)
+{
+    ESP_LOGI(MASTER_TAG, "FD DMA, Both TX and RX:");
+    spi_transaction_t trans = {0};
+    trans.tx_buffer = mst_send_buf;
+    trans.rx_buffer = mst_recv_buf;
+    trans.length = length * 8;
+    unity_wait_for_signal("Slave ready");
+    TEST_ESP_OK(spi_device_transmit(spi, &trans));
+    ESP_LOG_BUFFER_HEX("MASTER TX:", mst_send_buf, length);
+    ESP_LOG_BUFFER_HEX("MASTER RX:", mst_recv_buf, length);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(slv_send_buf, mst_recv_buf, length);
+}
+
+static void fd_master(void)
+{
+    spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
+
+    spi_device_handle_t spi;
+    spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
+
+    unity_send_signal("Master ready");
+
+    uint8_t *mst_send_buf = heap_caps_malloc(FD_TEST_BUF_SIZE, MALLOC_CAP_DMA);
+    uint8_t *mst_recv_buf = heap_caps_calloc(FD_TEST_BUF_SIZE, 1, MALLOC_CAP_DMA);
+    uint8_t *slv_send_buf = heap_caps_malloc(FD_TEST_BUF_SIZE, MALLOC_CAP_DMA);
+
+    //Master FD DMA, RX without TX Test
+    for (int i = 0; i < TEST_NUM; i++) {
+        // 1. Master FD DMA, only receive, with NULL tx_buffer
+        get_tx_buffer(FD_SEED1+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        master_only_rx_trans(spi, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+
+        //2. Master FD DMA with TX and RX
+        get_tx_buffer(FD_SEED2+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        master_both_trans(spi, mst_send_buf, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+    }
+
+    //Master FD DMA, TX without RX Test
+    for (int i = 0; i < TEST_NUM; i++) {
+        // 1. Master FD DMA, only send, with NULL rx_buffer
+        get_tx_buffer(FD_SEED3+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        master_only_tx_trans(spi, mst_send_buf, FD_TEST_BUF_SIZE);
+
+        //2. Master FD DMA with TX and RX
+        get_tx_buffer(FD_SEED4+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(mst_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        master_both_trans(spi, mst_send_buf, mst_recv_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+    }
+
+    free(mst_send_buf);
+    free(mst_recv_buf);
+    free(slv_send_buf);
+    master_free_device_bus(spi);
+}
+
+static void slave_only_tx_trans(uint8_t *slv_send_buf, uint32_t length)
+{
+    ESP_LOGI(SLAVE_TAG, "FD DMA, Only TX");
+    spi_slave_transaction_t trans = {0};
+    trans.tx_buffer = slv_send_buf;
+    trans.length = length * 8;
+    unity_send_signal("Slave ready");
+    TEST_ESP_OK(spi_slave_transmit(SPI2_HOST, &trans, portMAX_DELAY));
+    ESP_LOG_BUFFER_HEX("SLAVE TX:", slv_send_buf, length);
+}
+
+static void slave_only_rx_trans(uint8_t *slv_recv_buf, uint8_t *mst_send_buf, uint32_t length)
+{
+    ESP_LOGI(SLAVE_TAG, "FD DMA, Only RX");
+    spi_slave_transaction_t trans = {};
+    trans.tx_buffer = NULL;
+    trans.rx_buffer = slv_recv_buf;
+    trans.length = length * 8;
+    unity_send_signal("Slave ready");
+    TEST_ESP_OK(spi_slave_transmit(SPI2_HOST, &trans, portMAX_DELAY));
+    ESP_LOG_BUFFER_HEX("SLAVE RX:", slv_recv_buf, length);
+    TEST_ASSERT_EQUAL(length * 8, trans.trans_len);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(mst_send_buf, slv_recv_buf, length);
+}
+
+static void slave_both_trans(uint8_t *slv_send_buf, uint8_t *slv_recv_buf, uint8_t *mst_send_buf, uint32_t length)
+{
+    ESP_LOGI(SLAVE_TAG, "FD DMA, Both TX and RX:");
+    spi_slave_transaction_t trans = {0};
+    trans.tx_buffer = slv_send_buf;
+    trans.rx_buffer = slv_recv_buf;
+    trans.length = length * 8;
+    unity_send_signal("Slave ready");
+    TEST_ESP_OK(spi_slave_transmit(SPI2_HOST, &trans, portMAX_DELAY));
+    ESP_LOG_BUFFER_HEX("SLAVE TX:", slv_send_buf, length);
+    ESP_LOG_BUFFER_HEX("SLAVE RX:", slv_recv_buf, length);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(mst_send_buf, slv_recv_buf, length);
+}
+
+static void fd_slave(void)
+{
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
+
+    TEST_ESP_OK(spi_slave_initialize(SPI2_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
+
+    unity_wait_for_signal("Master ready");
+
+    uint8_t *slv_send_buf = heap_caps_malloc(FD_TEST_BUF_SIZE, MALLOC_CAP_DMA);
+    uint8_t *slv_recv_buf = heap_caps_calloc(FD_TEST_BUF_SIZE, 1, MALLOC_CAP_DMA);
+    uint8_t *mst_send_buf = heap_caps_malloc(FD_TEST_BUF_SIZE, MALLOC_CAP_DMA);
+
+    for (int i = 0; i < TEST_NUM; i++) {
+        //1. Slave TX without RX (rx_buffer == NULL)
+        get_tx_buffer(FD_SEED1+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        slave_only_tx_trans(slv_send_buf, FD_TEST_BUF_SIZE);
+
+        //2. Slave both TX and RX
+        get_tx_buffer(FD_SEED2+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        slave_both_trans(slv_send_buf, slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE);
+    }
+
+    for (int i = 0; i < TEST_NUM; i++) {
+        // 1. Slave RX without TX (tx_buffer == NULL)
+        get_tx_buffer(FD_SEED3+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        slave_only_rx_trans(slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE);
+
+        //2. Slave both TX and RX
+        get_tx_buffer(FD_SEED4+i, mst_send_buf, slv_send_buf, FD_TEST_BUF_SIZE);
+        memset(slv_recv_buf, 0x0, FD_TEST_BUF_SIZE);
+        slave_both_trans(slv_send_buf, slv_recv_buf, mst_send_buf, FD_TEST_BUF_SIZE);
+    }
+
+    free(slv_send_buf);
+    free(slv_recv_buf);
+    free(mst_send_buf);
+    TEST_ASSERT(spi_slave_free(SPI2_HOST) == ESP_OK);
+}
+
+TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test", "[spi_ms][test_env=Example_SPI_Multi_device]", fd_master, fd_slave);
+#endif  //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)    //TODO: IDF-3494
 
 /********************************************************************************
  *      Test SPI transaction interval

components/driver/test/test_spi_slave_hd.c

@@ -616,15 +616,6 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
 #include "unity.h"
 #include "test/test_common_spi.h"
 
-static void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size)
-{
-    srand(199);
-    for (int i = 0; i < send_buf_size * 2; i++) {
-        slave_send_buf[i] = rand();
-        master_send_buf[i] = rand();
-    }
-}
-
 static void hd_master(void)
 {
     spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();

components/hal/spi_hal_iram.c

@@ -150,7 +150,8 @@ void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *de
             lldesc_setup_link(hal->dmadesc_rx, trans->rcv_buffer, ((trans->rx_bitlen + 7) / 8), true);
 
             spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan);
-            spi_ll_dma_rx_fifo_reset(hal->dma_in);
+            spi_ll_dma_rx_fifo_reset(hal->hw);
+            spi_ll_infifo_full_clr(hal->hw);
             spi_ll_dma_rx_enable(hal->hw, 1);
             spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, hal->dmadesc_rx);
         }
@@ -174,7 +175,8 @@ void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *de
             lldesc_setup_link(hal->dmadesc_tx, trans->send_buffer, (trans->tx_bitlen + 7) / 8, false);
 
             spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan);
-            spi_ll_dma_tx_fifo_reset(hal->dma_in);
+            spi_ll_dma_tx_fifo_reset(hal->hw);
+            spi_ll_outfifo_empty_clr(hal->hw);
             spi_ll_dma_tx_enable(hal->hw, 1);
             spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, hal->dmadesc_tx);
         }