From 30a525aeb15f1f620dd07dd9cb0b6b8e83c0ce7f Mon Sep 17 00:00:00 2001 From: duyi Date: Tue, 7 Jan 2020 16:58:14 +0800 Subject: [PATCH] update cache config --- components/esp32s2beta/Kconfig | 36 -------------------- components/esp32s2beta/cpu_start.c | 8 +---- components/spi_flash/cache_utils.c | 53 +++++++++++------------------- components/spi_flash/cache_utils.h | 12 +++++-- 4 files changed, 29 insertions(+), 80 deletions(-) diff --git a/components/esp32s2beta/Kconfig b/components/esp32s2beta/Kconfig index f2cd260163..a2e7d6f1f7 100644 --- a/components/esp32s2beta/Kconfig +++ b/components/esp32s2beta/Kconfig @@ -65,18 +65,6 @@ menu "ESP32S2-specific" bool "16KB" endchoice - choice ESP32S2_INSTRUCTION_CACHE_WAYS - prompt "Instruction cache associated ways" - default ESP32S2_INSTRUCTION_CACHE_8WAYS - help - Instruction cache associated ways to be set on application startup. - - config ESP32S2_INSTRUCTION_CACHE_4WAYS - bool "4 ways" - config ESP32S2_INSTRUCTION_CACHE_8WAYS - bool "8 ways" - endchoice - choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE prompt "Instruction cache line size" default ESP32S2_INSTRUCTION_CACHE_LINE_32B @@ -87,8 +75,6 @@ menu "ESP32S2-specific" bool "16 Bytes" config ESP32S2_INSTRUCTION_CACHE_LINE_32B bool "32 Bytes" - config ESP32S2_INSTRUCTION_CACHE_LINE_64B - bool "64 Bytes" endchoice choice ESP32S2_DATA_CACHE_SIZE @@ -107,18 +93,6 @@ menu "ESP32S2-specific" bool "16KB" endchoice - choice ESP32S2_DATA_CACHE_ASSOCIATED_WAYS - prompt "Data cache associated ways" - default ESP32S2_DATA_CACHE_8WAYS - help - Data cache associated ways to be set on application startup. - - config ESP32S2_DATA_CACHE_4WAYS - bool "4 ways" - config ESP32S2_DATA_CACHE_8WAYS - bool "8 ways" - endchoice - choice ESP32S2_DATA_CACHE_LINE_SIZE prompt "Data cache line size" default ESP32S2_DATA_CACHE_LINE_32B @@ -129,18 +103,8 @@ menu "ESP32S2-specific" bool "16 Bytes" config ESP32S2_DATA_CACHE_LINE_32B bool "32 Bytes" - config ESP32S2_DATA_CACHE_LINE_64B - bool "64 Bytes" endchoice - config ESP32S2_RODATA_USE_DATA_CACHE - depends on ESP32S2_DATA_CACHE_8KB || ESP32S2_DATA_CACHE_16KB - bool "Use data cache rather than instruction cache to access read only data" - default "n" - help - If enabled, CPU will access rodata through data cache, which will reduce the overload - of instruction cache, however will increase the overload of data cache. - config ESP32S2_INSTRUCTION_CACHE_WRAP bool "Enable instruction cache wrap" default "n" diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c index 8fd2fc7a74..2fd53f4bb6 100644 --- a/components/esp32s2beta/cpu_start.c +++ b/components/esp32s2beta/cpu_start.c @@ -147,7 +147,7 @@ void IRAM_ATTR call_start_cpu0(void) /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache. Configure the mode of data : cache size, cache associated ways, cache line size. Enable data cache, so if we don't use SPIRAM, it just works. */ -#if CONFIG_SPIRAM_BOOT_INIT || CONFIG_ESP32S2_RODATA_USE_DATA_CACHE +#if CONFIG_SPIRAM_BOOT_INIT extern void esp_config_data_cache_mode(void); esp_config_data_cache_mode(); Cache_Enable_DCache(0); @@ -169,12 +169,6 @@ void IRAM_ATTR call_start_cpu0(void) } #endif - /* Start to use data cache to access rodata. */ -#if CONFIG_ESP32S2_RODATA_USE_DATA_CACHE - extern void esp_switch_rodata_to_dcache(void); - esp_switch_rodata_to_dcache(); -#endif - ESP_EARLY_LOGI(TAG, "Pro cpu up."); ESP_EARLY_LOGI(TAG, "Single core mode"); diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index de1ffec917..277e102820 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -326,11 +326,11 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) { #if CONFIG_IDF_TARGET_ESP32 bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); -#endif #if portNUM_PROCESSORS == 2 result = result && (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) != 0); +#endif +#elif CONFIG_IDF_TARGET_ESP32S2BETA + bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); #endif return result; } @@ -352,12 +352,10 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void) cache_ways = CACHE_4WAYS_ASSOC; #if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B cache_line_size = CACHE_LINE_SIZE_16B; -#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B - cache_line_size = CACHE_LINE_SIZE_32B; #else - cache_line_size = CACHE_LINE_SIZE_64B; + cache_line_size = CACHE_LINE_SIZE_32B; #endif - ESP_EARLY_LOGI(TAG, "Instruction cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); Cache_Suspend_ICache(); Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size); Cache_Invalidate_ICache_All(); @@ -391,21 +389,14 @@ IRAM_ATTR void esp_config_data_cache_mode(void) cache_ways = CACHE_4WAYS_ASSOC; #if CONFIG_ESP32S2_DATA_CACHE_LINE_16B cache_line_size = CACHE_LINE_SIZE_16B; -#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B - cache_line_size = CACHE_LINE_SIZE_32B; #else - cache_line_size = CACHE_LINE_SIZE_64B; + cache_line_size = CACHE_LINE_SIZE_32B; #endif - ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size); Cache_Invalidate_DCache_All(); } -void esp_switch_rodata_to_dcache(void) -{ - -} - static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) { uint32_t i_autoload, d_autoload; @@ -415,11 +406,7 @@ static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) if (dcache) { d_autoload = Cache_Suspend_DCache(); } -#if CONFIG_IDF_TARGET_ESP32S2BETA REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND); -#else - REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_FLASH_WRAP_AROUND); -#endif if (icache) { Cache_Resume_ICache(i_autoload); } @@ -438,7 +425,7 @@ static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) if (dcache) { d_autoload = Cache_Suspend_DCache(); } - REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND); + REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND); if (icache) { Cache_Resume_ICache(i_autoload); } @@ -456,27 +443,20 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable int flash_count = 0, spiram_count = 0; int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; -#if CONFIG_IDF_TARGET_ESP32S2BETA uint32_t drom0_in_icache = 1;//always 1 in esp32s2 -#else - uint32_t drom0_in_icache = Cache_Drom0_Using_ICache(); -#endif + if (icache_wrap_enable) { #if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B icache_wrap_size = 16; -#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B - icache_wrap_size = 32; #else - icache_wrap_size = 64; + icache_wrap_size = 32; #endif } if (dcache_wrap_enable) { #if CONFIG_ESP32S2_DATA_CACHE_LINE_16B dcache_wrap_size = 16; -#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B - dcache_wrap_size = 32; #else - dcache_wrap_size = 64; + dcache_wrap_size = 32; #endif } @@ -563,11 +543,16 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable return ESP_FAIL; } - extern bool spi_flash_support_wrap_size(uint32_t wrap_size); +#ifdef CONFIG_FLASHMODE_QIO + flash_support_wrap = true; +extern bool spi_flash_support_wrap_size(uint32_t wrap_size); if (!spi_flash_support_wrap_size(flash_wrap_size)) { flash_support_wrap = false; ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size); } +#else + ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap."); +#endif #ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT extern bool psram_support_wrap_size(uint32_t wrap_size); @@ -584,14 +569,14 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size); if (flash_support_wrap && flash_wrap_size > 0) { - ESP_EARLY_LOGI(TAG, "Flash wrap enabled."); + ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size); spi_flash_enable_wrap(flash_wrap_size); esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0)); } #if CONFIG_ESP32S2_SPIRAM_SUPPORT extern esp_err_t psram_enable_wrap(uint32_t wrap_size); if (spiram_support_wrap && spiram_wrap_size > 0) { - ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled."); + ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size); psram_enable_wrap(spiram_wrap_size); esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0)); } diff --git a/components/spi_flash/cache_utils.h b/components/spi_flash/cache_utils.h index e57494c5af..11bf35f73a 100644 --- a/components/spi_flash/cache_utils.h +++ b/components/spi_flash/cache_utils.h @@ -50,17 +50,23 @@ void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void); // This function is implied to be called when other CPU is not running or running code from IRAM. void spi_flash_enable_interrupts_caches_no_os(void); -// Flushes cache if address range has corresponding valid cache mappings -// Recommended to use post flash program operation (erase or write) +// Mark the pages containing a flash region as having been +// erased or written to. This means the flash cache needs +// to be evicted before these pages can be flash_mmap()ed again, +// as they may contain stale data +// // Only call this while holding spi_flash_op_lock() // Returns true if cache was flushed, false otherwise bool spi_flash_check_and_flush_cache(uint32_t start_addr, uint32_t length); //config cache mode #ifdef CONFIG_IDF_TARGET_ESP32S2BETA +//config instrcutin cache size and cache block size by menuconfig void esp_config_instruction_cache_mode(void); +//config data cache size and cache block size by menuconfig void esp_config_data_cache_mode(void); -void esp_switch_rodata_to_dcache(void); +//enable cache wrap mode for instruction cache and data cache +esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable); #endif