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Adjust the variable name &

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Add mapping support for different sizes of spi ram
This commit is contained in:
Wu Zheng Hui
2021-08-25 16:06:28 +08:00
parent e5766eb3d3
commit 3128a2544b
12 changed files with 190 additions and 131 deletions
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components/soc/esp32s2/include/soc/cache_memory.h
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@@ -67,7 +67,7 @@ extern "C" {
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT_CACHE)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0