Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

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Jeroen Domburg

2017-07-20 16:26:35 +08:00

parent 518edac42f

commit 34372a091c

22 changed files with 1412 additions and 198 deletions

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components/esp32/libstdcc++-cache-workaround.a

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