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Merge branch 'refactor/mcpwm_cleanup_meta_info' into 'master'

Browse Source 
mcpwm: fix wrong soc information

See merge request espressif/esp-idf!12429
This commit is contained in:
Michael (XIAO Xufeng)
2021-02-24 03:59:23 +00:00
parent db1c635db4 6dc7f95342
commit 34b4c88405
13 changed files with 326 additions and 376 deletions
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2
components/esp32s3/ld/esp32s3.peripherals.ld
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@@ -18,6 +18,8 @@ PROVIDE ( RMTMEM = 0x60016800 );
PROVIDE ( PCNT = 0x60017000 ); PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 ); PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 ); PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( MCPWM0 = 0x6001E000 );
PROVIDE ( MCPWM1 = 0x6002C000 );
PROVIDE ( MCP = 0x600c3000 ); PROVIDE ( MCP = 0x600c3000 );
PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 ); PROVIDE ( TIMERG1 = 0x60020000 );

8
components/hal/esp32/include/hal/clk_gate_ll.h
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@@ -52,10 +52,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return DPORT_PWM0_CLK_EN; return DPORT_PWM0_CLK_EN;
case PERIPH_PWM1_MODULE: case PERIPH_PWM1_MODULE:
return DPORT_PWM1_CLK_EN; return DPORT_PWM1_CLK_EN;
case PERIPH_PWM2_MODULE:
return DPORT_PWM2_CLK_EN;
case PERIPH_PWM3_MODULE:
return DPORT_PWM3_CLK_EN;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return DPORT_UHCI0_CLK_EN; return DPORT_UHCI0_CLK_EN;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:
@@ -130,10 +126,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return DPORT_PWM0_RST; return DPORT_PWM0_RST;
case PERIPH_PWM1_MODULE: case PERIPH_PWM1_MODULE:
return DPORT_PWM1_RST; return DPORT_PWM1_RST;
case PERIPH_PWM2_MODULE:
return DPORT_PWM2_RST;
case PERIPH_PWM3_MODULE:
return DPORT_PWM3_RST;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return DPORT_UHCI0_RST; return DPORT_UHCI0_RST;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:

16
components/hal/esp32s2/include/hal/clk_gate_ll.h
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@@ -49,14 +49,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return DPORT_TIMERGROUP_CLK_EN; return DPORT_TIMERGROUP_CLK_EN;
case PERIPH_TIMG1_MODULE: case PERIPH_TIMG1_MODULE:
return DPORT_TIMERGROUP1_CLK_EN; return DPORT_TIMERGROUP1_CLK_EN;
case PERIPH_PWM0_MODULE:
return DPORT_PWM0_CLK_EN;
case PERIPH_PWM1_MODULE:
return DPORT_PWM1_CLK_EN;
case PERIPH_PWM2_MODULE:
return DPORT_PWM2_CLK_EN;
case PERIPH_PWM3_MODULE:
return DPORT_PWM3_CLK_EN;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return DPORT_UHCI0_CLK_EN; return DPORT_UHCI0_CLK_EN;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:
@@ -129,14 +121,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return DPORT_TIMERGROUP_RST; return DPORT_TIMERGROUP_RST;
case PERIPH_TIMG1_MODULE: case PERIPH_TIMG1_MODULE:
return DPORT_TIMERGROUP1_RST; return DPORT_TIMERGROUP1_RST;
case PERIPH_PWM0_MODULE:
return DPORT_PWM0_RST;
case PERIPH_PWM1_MODULE:
return DPORT_PWM1_RST;
case PERIPH_PWM2_MODULE:
return DPORT_PWM2_RST;
case PERIPH_PWM3_MODULE:
return DPORT_PWM3_RST;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return DPORT_UHCI0_RST; return DPORT_UHCI0_RST;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:

8
components/hal/esp32s3/include/hal/clk_gate_ll.h
View File

@@ -57,10 +57,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_PWM0_CLK_EN; return SYSTEM_PWM0_CLK_EN;
case PERIPH_PWM1_MODULE: case PERIPH_PWM1_MODULE:
return SYSTEM_PWM1_CLK_EN; return SYSTEM_PWM1_CLK_EN;
case PERIPH_PWM2_MODULE:
return SYSTEM_PWM2_CLK_EN;
case PERIPH_PWM3_MODULE:
return SYSTEM_PWM3_CLK_EN;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return SYSTEM_UHCI0_CLK_EN; return SYSTEM_UHCI0_CLK_EN;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:
@@ -142,10 +138,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return SYSTEM_PWM0_RST; return SYSTEM_PWM0_RST;
case PERIPH_PWM1_MODULE: case PERIPH_PWM1_MODULE:
return SYSTEM_PWM1_RST; return SYSTEM_PWM1_RST;
case PERIPH_PWM2_MODULE:
return SYSTEM_PWM2_RST;
case PERIPH_PWM3_MODULE:
return SYSTEM_PWM3_RST;
case PERIPH_UHCI0_MODULE: case PERIPH_UHCI0_MODULE:
return SYSTEM_UHCI0_RST; return SYSTEM_UHCI0_RST;
case PERIPH_UHCI1_MODULE: case PERIPH_UHCI1_MODULE:

3
components/soc/esp32/include/soc/mcpwm_reg.h
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@@ -15,7 +15,8 @@
#define _SOC_MCPWM_REG_H_ #define _SOC_MCPWM_REG_H_
#include "soc.h" #include "soc.h"
#define REG_MCPWM_BASE(i) (DR_REG_PWM_BASE + i * (0xE000)) #define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000))
#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) #define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000)
/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ /*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/

21
components/soc/esp32/include/soc/mcpwm_struct.h
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@@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
// You may obtain a copy of the License at // You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
@@ -11,8 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#ifndef _SOC_MCPWM_STRUCT_H__ #pragma once
#define _SOC_MCPWM_STRUCT_H__
#include <stdint.h> #include <stdint.h>
@@ -51,7 +50,8 @@ typedef volatile struct mcpwm_dev_s {
uint32_t in_en : 1; /*when set timer reload with phase on sync input event is enabled*/ uint32_t in_en : 1; /*when set timer reload with phase on sync input event is enabled*/
uint32_t sync_sw : 1; /*write the negate value will trigger a software sync*/ uint32_t sync_sw : 1; /*write the negate value will trigger a software sync*/
uint32_t out_sel : 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ uint32_t out_sel : 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/
uint32_t timer_phase: 17; /*phase for timer reload on sync event*/ uint32_t timer_phase : 16; /*phase for timer reload on sync event*/
uint32_t phase_direct : 1; /*counter direction to apply on sync event*/
uint32_t reserved21 : 11; uint32_t reserved21 : 11;
}; };
uint32_t val; uint32_t val;
@@ -66,7 +66,6 @@ typedef volatile struct mcpwm_dev_s {
} status; } status;
} timer[3]; } timer[3];
union { union {
struct { struct {
uint32_t t0_in_sel : 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ uint32_t t0_in_sel : 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
@@ -89,7 +88,6 @@ typedef volatile struct mcpwm_dev_s {
uint32_t val; uint32_t val;
} timer_sel; } timer_sel;
struct { struct {
union { union {
struct { struct {
@@ -216,7 +214,7 @@ typedef volatile struct mcpwm_dev_s {
} tz_cfg0; } tz_cfg0;
union { union {
struct { struct {
uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/ uint32_t clr_ost : 1; /*a posedge will clear on going one-shot tripping*/
uint32_t cbcpulse : 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ uint32_t cbcpulse : 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/
uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/
uint32_t force_ost : 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ uint32_t force_ost : 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
@@ -239,8 +237,8 @@ typedef volatile struct mcpwm_dev_s {
uint32_t f0_en : 1; /*When set event_f0 generation is enabled*/ uint32_t f0_en : 1; /*When set event_f0 generation is enabled*/
uint32_t f1_en : 1; /*When set event_f1 generation is enabled*/ uint32_t f1_en : 1; /*When set event_f1 generation is enabled*/
uint32_t f2_en : 1; /*When set event_f2 generation is enabled*/ uint32_t f2_en : 1; /*When set event_f2 generation is enabled*/
uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ uint32_t f0_pole : 1; /*Set event_f0 trigger polarity on FAULT0 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ uint32_t f1_pole : 1; /*Set event_f1 trigger polarity on FAULT1 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f2_pole : 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ uint32_t f2_pole : 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t event_f0 : 1; /*Set and reset by hardware. If set event_f0 is on going*/ uint32_t event_f0 : 1; /*Set and reset by hardware. If set event_f0 is on going*/
uint32_t event_f1 : 1; /*Set and reset by hardware. If set event_f1 is on going*/ uint32_t event_f1 : 1; /*Set and reset by hardware. If set event_f1 is on going*/
@@ -454,11 +452,10 @@ typedef volatile struct mcpwm_dev_s {
uint32_t val; uint32_t val;
} version; } version;
} mcpwm_dev_t; } mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0; extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1; extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* _SOC_MCPWM_STRUCT_H__ */

2
components/soc/esp32/include/soc/periph_defs.h
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@@ -32,8 +32,6 @@ typedef enum {
PERIPH_TIMG1_MODULE, PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE, PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE, PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE, PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE, PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE, PERIPH_RMT_MODULE,

6
components/soc/esp32/include/soc/soc.h
View File

@@ -64,7 +64,7 @@
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_NRX_BASE 0x3ff5CC00 #define DR_REG_NRX_BASE 0x3ff5CC00
#define DR_REG_BB_BASE 0x3ff5D000 #define DR_REG_BB_BASE 0x3ff5D000
#define DR_REG_PWM_BASE 0x3ff5E000 #define DR_REG_PWM0_BASE 0x3ff5E000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_RTCMEM0_BASE 0x3ff61000 #define DR_REG_RTCMEM0_BASE 0x3ff61000
@@ -81,8 +81,6 @@
#define DR_REG_PWM1_BASE 0x3ff6C000 #define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000 #define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000 #define DR_REG_UART2_BASE 0x3ff6E000
#define DR_REG_PWM2_BASE 0x3ff6F000
#define DR_REG_PWM3_BASE 0x3ff70000
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
//Registers Operation {{ //Registers Operation {{
@@ -324,8 +322,6 @@
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ #define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ #define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ #define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ #define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ #define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
#define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/ #define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/

10
components/soc/esp32s2/include/soc/periph_defs.h
View File

@@ -30,10 +30,6 @@ typedef enum {
PERIPH_I2S1_MODULE, PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE, PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE, PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE, PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE, PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE, PERIPH_RMT_MODULE,
@@ -102,11 +98,7 @@ typedef enum {
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ ETS_LEDC_INTR_SOURCE = 45, /**< interrupt of LED PWM, level*/
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/

2
components/soc/esp32s3/include/soc/mcpwm_reg.h
View File

@@ -19,6 +19,8 @@ extern "C" {
#include "soc.h" #include "soc.h"
#define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000))
#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) #define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000)
/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */ /*description: */

9
components/soc/esp32s3/include/soc/mcpwm_struct.h
View File

@@ -13,13 +13,13 @@
// limitations under the License. // limitations under the License.
#pragma once #pragma once
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include <stdint.h> typedef volatile struct mcpwm_dev_s {
typedef volatile struct {
union { union {
struct { struct {
uint32_t prescale: 8; uint32_t prescale: 8;
@@ -50,7 +50,8 @@ typedef volatile struct {
uint32_t in_en: 1; uint32_t in_en: 1;
uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/ uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/
uint32_t out_sel: 2; uint32_t out_sel: 2;
uint32_t timer_phase: 17; uint32_t timer_phase: 16;
uint32_t phase_direct : 1;
uint32_t reserved21: 11; uint32_t reserved21: 11;
}; };
uint32_t val; uint32_t val;

9
components/soc/esp32s3/include/soc/periph_defs.h
View File

@@ -32,8 +32,6 @@ typedef enum {
PERIPH_TIMG1_MODULE, PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE, PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE, PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE, PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE, PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE, PERIPH_RMT_MODULE,
@@ -93,11 +91,8 @@ typedef enum {
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
ETS_PWM1_INTR_SOURCE = 32, /**< interrupt of PWM1, level, Reserved*/ ETS_LEDC_INTR_SOURCE = 35, /**< interrupt of LED PWM, level*/
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/
ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/

4
components/soc/esp32s3/include/soc/soc.h
View File

@@ -74,7 +74,7 @@
#define DR_REG_EFUSE_BASE 0x6001A000 #define DR_REG_EFUSE_BASE 0x6001A000
#define DR_REG_NRX_BASE 0x6001CC00 #define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000 #define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM_BASE 0x6001E000 #define DR_REG_PWM0_BASE 0x6001E000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000 #define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 #define DR_REG_RTC_SLOWMEM_BASE 0x60021000
@@ -89,8 +89,6 @@
#define DR_REG_PWM1_BASE 0x6002C000 #define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000 #define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000 #define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_PWM2_BASE 0x6002F000
#define DR_REG_PWM3_BASE 0x60030000
#define DR_REG_SPI4_BASE 0x60037000 #define DR_REG_SPI4_BASE 0x60037000
#define DR_REG_USB_WRAP_BASE 0x60039000 #define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_APB_SARADC_BASE 0x60040000 #define DR_REG_APB_SARADC_BASE 0x60040000