From 350e3c3d06cec8e58cd2a759f75a9952ca91f773 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Thu, 13 Mar 2025 15:40:47 +0800 Subject: [PATCH] fix(esp_system): update clk code for esp32h21 --- components/esp_system/port/soc/esp32h21/clk.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/components/esp_system/port/soc/esp32h21/clk.c b/components/esp_system/port/soc/esp32h21/clk.c index 40ced86a20..7b21b1cbd0 100644 --- a/components/esp_system/port/soc/esp32h21/clk.c +++ b/components/esp_system/port/soc/esp32h21/clk.c @@ -24,6 +24,7 @@ #include "soc/lp_clkrst_reg.h" #include "soc/pcr_reg.h" #include "hal/wdt_hal.h" +#include "esp_private/esp_modem_clock.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" #include "esp_private/esp_pmu.h" @@ -79,6 +80,7 @@ __attribute__((weak)) void esp_clk_init(void) wdt_hal_write_protect_enable(&rtc_wdt_ctx); #endif + modem_clock_deselect_all_module_lp_clock_source(); #if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS) select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K); #elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) @@ -118,9 +120,6 @@ __attribute__((weak)) void esp_clk_init(void) // Re calculate the ccount to make time calculation correct. esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz); - - // Set crypto clock (`clk_sec`) to use 96M PLL clock - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); } static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)