mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-30 18:57:19 +02:00
refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC
This commit is contained in:
@ -16,7 +16,7 @@ if(${target} STREQUAL "esp32c6")
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list(APPEND priv_requires hal)
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list(APPEND priv_requires hal)
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endif()
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endif()
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set(srcs "cpu.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
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set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
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if(NOT BOOTLOADER_BUILD)
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if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "esp_clk.c"
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list(APPEND srcs "esp_clk.c"
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"clk_ctrl_os.c"
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"clk_ctrl_os.c"
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@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -144,184 +144,6 @@ void esp_cpu_wait_for_intr(void)
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#endif // __XTENSA__
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#endif // __XTENSA__
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}
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}
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// ---------------- Interrupt Descriptors ------------------
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#if SOC_CPU_HAS_FLEXIBLE_INTC
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#if SOC_INT_CLIC_SUPPORTED
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static bool is_intr_num_resv(int ext_intr_num) {
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/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
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* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
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* in the case of this function, the parameter only refers to the external peripheral index, so if
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* `ext_intr_num` is 0, it refers to interrupt index 16.
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*
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* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
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return ext_intr_num == 6;
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}
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#else // !SOC_INT_CLIC_SUPPORTED
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static bool is_intr_num_resv(int intr_num)
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{
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// Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt"
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// [TODO: IDF-2465]
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uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8);
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// int_num 0,3,4,7 are unavailable for PULP cpu
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5728 replace with a better macro name
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reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7);
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#endif
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if (reserved & BIT(intr_num)) {
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return true;
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}
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extern int _vector_table;
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extern int _interrupt_handler;
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const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
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/* JAL instructions are relative to the PC there are executed from. */
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const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
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return destination != (intptr_t)&_interrupt_handler;
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}
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#endif // SOC_INT_CLIC_SUPPORTED
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void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
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{
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intr_desc_ret->priority = 1; //Todo: We should make this -1
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intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
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#if __riscv
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intr_desc_ret->flags = is_intr_num_resv(intr_num) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
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#else
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intr_desc_ret->flags = 0;
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#endif
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}
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#else // SOC_CPU_HAS_FLEXIBLE_INTC
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typedef struct {
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int priority;
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esp_cpu_intr_type_t type;
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uint32_t flags[SOC_CPU_CORES_NUM];
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} intr_desc_t;
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#if SOC_CPU_CORES_NUM > 1
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// Note: We currently only have dual core targets, so the table initializer is hard coded
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const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //2
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //3
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //4
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5
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#if CONFIG_FREERTOS_CORETIMER_0
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6
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#else
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6
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#endif
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //9
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{ 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //10
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //12
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //13
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{ 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI
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#if CONFIG_FREERTOS_CORETIMER_1
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15
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#else
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15
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#endif
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{ 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //17
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //18
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //19
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //20
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //21
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{ 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //22
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{ 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //23
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{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //24
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{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25
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{ 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //26
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{ 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27
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{ 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //28
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29
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{ 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30
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{ 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31
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};
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#else // SOC_CPU_CORES_NUM > 1
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const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //2
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //3
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //4
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5
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#if CONFIG_FREERTOS_CORETIMER_0
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6
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#else
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6
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#endif
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{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //9
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{ 1, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //10
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //12
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //13
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{ 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI
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#if CONFIG_FREERTOS_CORETIMER_1
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15
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#else
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15
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#endif
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{ 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //17
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{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //18
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //19
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //20
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{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //21
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{ 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //22
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{ 3, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //23
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{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //24
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{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25
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{ 5, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //26
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{ 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27
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{ 4, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //28
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{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29
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{ 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30
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{ 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31
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};
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#endif // SOC_CPU_CORES_NUM > 1
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void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
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{
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assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
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#if SOC_CPU_CORES_NUM == 1
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core_id = 0; //If this is a single core target, hard code CPU ID to 0
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#endif
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intr_desc_ret->priority = intr_desc_table[intr_num].priority;
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intr_desc_ret->type = intr_desc_table[intr_num].type;
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intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id];
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}
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#endif // SOC_CPU_HAS_FLEXIBLE_INTC
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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*
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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* ------------------------------------------------------------------------------------------------------------------ */
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@ -0,0 +1,41 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <stdint.h>
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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#include "esp_cpu.h"
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#include "riscv/instruction_decode.h"
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/**
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* @brief Checks whether the given interrupt number is reserved either in the given mask or in the
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* _vector_table, which contains the routines the CPU will jump to when an interrupt or an exception
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* occurs, on RISC-V targets.
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*
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* @param intr_num Interrupt number to check, in range 0~32
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* @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved.
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*
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* @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else
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*/
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static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask)
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{
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if (rsvd_mask & BIT(intr_num)) {
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return ESP_CPU_INTR_DESC_FLAG_RESVD;
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}
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extern int _vector_table;
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extern int _interrupt_handler;
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const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
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/* JAL instructions are relative to the PC they are executed from. */
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const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
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return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
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}
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#endif // CONFIG_IDF_TARGET_ARCH_RISCV
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75
components/esp_hw_support/port/esp32/esp_cpu_intr.c
Normal file
75
components/esp_hw_support/port/esp32/esp_cpu_intr.c
Normal file
@ -0,0 +1,75 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <assert.h>
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#include "soc/soc_caps.h"
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#include "esp_cpu.h"
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/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig,
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* timer2 is always set to SPECIAL in our configuration array */
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/**
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* @brief Type defined for the table below
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*/
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typedef struct {
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int priority;
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esp_cpu_intr_type_t type;
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uint32_t flags[SOC_CPU_CORES_NUM];
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} intr_desc_t;
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const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
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[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
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[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
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[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
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[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
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[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
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[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
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#if CONFIG_FREERTOS_CORETIMER_0
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[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
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#else
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[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
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#endif
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[7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
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[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
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[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
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|
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
|
||||||
|
[11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI
|
||||||
|
#if CONFIG_FREERTOS_CORETIMER_1
|
||||||
|
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
#else
|
||||||
|
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
#endif
|
||||||
|
[16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
|
||||||
|
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
|
||||||
|
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
|
||||||
|
[29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL);
|
||||||
|
intr_desc_ret->priority = intr_desc_table[intr_num].priority;
|
||||||
|
intr_desc_ret->type = intr_desc_table[intr_num].type;
|
||||||
|
intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id];
|
||||||
|
}
|
23
components/esp_hw_support/port/esp32c2/esp_cpu_intr.c
Normal file
23
components/esp_hw_support/port/esp32c2/esp_cpu_intr.c
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On the ESP32-C2, interrupt:
|
||||||
|
* - 1 is for Wi-Fi
|
||||||
|
* - 5 and 8 for Bluetooth
|
||||||
|
* - 6 for "permanently disabled interrupt"
|
||||||
|
*/
|
||||||
|
// [TODO: IDF-2465]
|
||||||
|
const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);
|
||||||
|
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
|
||||||
|
}
|
23
components/esp_hw_support/port/esp32c3/esp_cpu_intr.c
Normal file
23
components/esp_hw_support/port/esp32c3/esp_cpu_intr.c
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On the ESP32-C3, interrupt:
|
||||||
|
* - 1 is for Wi-Fi
|
||||||
|
* - 5 and 8 for Bluetooth
|
||||||
|
* - 6 for "permanently disabled interrupt"
|
||||||
|
*/
|
||||||
|
// [TODO: IDF-2465]
|
||||||
|
const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);
|
||||||
|
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
|
||||||
|
}
|
26
components/esp_hw_support/port/esp32c6/esp_cpu_intr.c
Normal file
26
components/esp_hw_support/port/esp32c6/esp_cpu_intr.c
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On the ESP32-C6, interrupt:
|
||||||
|
* - 1 is for Wi-Fi
|
||||||
|
* - 5 and 8 for Bluetooth
|
||||||
|
* - 6 for "permanently disabled interrupt"
|
||||||
|
*
|
||||||
|
* Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
|
||||||
|
*/
|
||||||
|
// [TODO: IDF-2465]
|
||||||
|
const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
|
||||||
|
BIT(5) | BIT(6) | BIT(7) | BIT(8);
|
||||||
|
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
|
||||||
|
}
|
26
components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
Normal file
26
components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On the ESP32-H2, interrupt:
|
||||||
|
* - 1 is for Wi-Fi
|
||||||
|
* - 5 and 8 for Bluetooth
|
||||||
|
* - 6 for "permanently disabled interrupt"
|
||||||
|
*
|
||||||
|
* Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
|
||||||
|
*/
|
||||||
|
// [TODO: IDF-2465]
|
||||||
|
const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
|
||||||
|
BIT(5) | BIT(6) | BIT(7) | BIT(8);
|
||||||
|
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
|
||||||
|
}
|
19
components/esp_hw_support/port/esp32p4/esp_cpu_intr.c
Normal file
19
components/esp_hw_support/port/esp32p4/esp_cpu_intr.c
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
|
||||||
|
* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
|
||||||
|
*
|
||||||
|
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
|
||||||
|
}
|
75
components/esp_hw_support/port/esp32s2/esp_cpu_intr.c
Normal file
75
components/esp_hw_support/port/esp32s2/esp_cpu_intr.c
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
#include <assert.h>
|
||||||
|
#include "soc/soc_caps.h"
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
|
||||||
|
/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig,
|
||||||
|
* timer2 is always set to SPECIAL in our configuration array */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type defined for the table below
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
int priority;
|
||||||
|
esp_cpu_intr_type_t type;
|
||||||
|
uint32_t flags;
|
||||||
|
} intr_desc_t;
|
||||||
|
|
||||||
|
|
||||||
|
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
|
||||||
|
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
#if CONFIG_FREERTOS_CORETIMER_0
|
||||||
|
[6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
#else
|
||||||
|
[6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
#endif
|
||||||
|
[7] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, 0 },
|
||||||
|
[11] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, // NMI
|
||||||
|
#if CONFIG_FREERTOS_CORETIMER_1
|
||||||
|
[15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
#else
|
||||||
|
[15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
#endif
|
||||||
|
[16] = { 5, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
[17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||||
|
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 },
|
||||||
|
[29] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
|
||||||
|
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
assert(core_id == 0 && intr_num < SOC_CPU_INTR_NUM && intr_desc_ret != NULL);
|
||||||
|
intr_desc_ret->priority = intr_desc_table[intr_num].priority;
|
||||||
|
intr_desc_ret->type = intr_desc_table[intr_num].type;
|
||||||
|
intr_desc_ret->flags = intr_desc_table[intr_num].flags;
|
||||||
|
}
|
65
components/esp_hw_support/port/esp32s3/esp_cpu_intr.c
Normal file
65
components/esp_hw_support/port/esp32s3/esp_cpu_intr.c
Normal file
@ -0,0 +1,65 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
|
||||||
|
/* The ESP32-S3 uses the SysTimer for the FreeRTOS system tick, there is no need to Xtensa core interrupts,
|
||||||
|
* which will be marked as ESP_CPU_INTR_DESC_FLAG_SPECIAL */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type defined for the table below
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
int priority;
|
||||||
|
esp_cpu_intr_type_t type;
|
||||||
|
uint32_t flags[SOC_CPU_CORES_NUM];
|
||||||
|
} intr_desc_t;
|
||||||
|
|
||||||
|
|
||||||
|
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
|
||||||
|
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
|
||||||
|
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
|
||||||
|
[11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI
|
||||||
|
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
|
||||||
|
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||||
|
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
|
||||||
|
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
|
||||||
|
[29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||||
|
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL);
|
||||||
|
intr_desc_ret->priority = intr_desc_table[intr_num].priority;
|
||||||
|
intr_desc_ret->type = intr_desc_table[intr_num].type;
|
||||||
|
intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id];
|
||||||
|
}
|
20
components/soc/esp32c6/esp_cpu_intr.c
Normal file
20
components/soc/esp32c6/esp_cpu_intr.c
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "esp_cpu.h"
|
||||||
|
#include "esp_riscv_intr.h"
|
||||||
|
|
||||||
|
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
|
||||||
|
{
|
||||||
|
/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
|
||||||
|
* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
|
||||||
|
*
|
||||||
|
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
|
||||||
|
/* TODO: IDF-8655, we may need to reserve more interrupts once we have Wifi and BT */
|
||||||
|
intr_desc_ret->priority = 1;
|
||||||
|
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
|
||||||
|
intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
|
||||||
|
}
|
Reference in New Issue
Block a user