From d68fcf1d7b36780bb9e14cd525314d1107ddfc1b Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Mon, 17 Feb 2025 19:59:10 +0800 Subject: [PATCH] feat(esp32h4): add soc register header files (stage2_2) generated soc headers from csv and ro_csv folder(part2) --- .../soc/esp32h4/include/soc/gpio_sig_map.h | 326 + .../soc/esp32h4/include/soc/interrupts.h | 116 + .../soc/esp32h4/include/soc/pmu_icg_mapping.h | 67 + components/soc/esp32h4/include/soc/reg_base.h | 79 + .../soc/esp32h4/include/soc/soc_etm_source.h | 401 + components/soc/esp32h4/interrupts.c | 100 + .../soc/esp32h4/ld/esp32h4.peripherals.ld | 78 + components/soc/esp32h4/register/soc/aes_reg.h | 462 + .../soc/esp32h4/register/soc/aes_struct.h | 354 + .../soc/esp32h4/register/soc/ecc_mult_reg.h | 210 + .../esp32h4/register/soc/ecc_mult_struct.h | 192 + .../soc/esp32h4/register/soc/ecdsa_reg.h | 360 + .../soc/esp32h4/register/soc/ecdsa_struct.h | 348 + .../soc/esp32h4/register/soc/hmac_reg.h | 282 + .../soc/esp32h4/register/soc/hmac_struct.h | 344 + components/soc/esp32h4/register/soc/huk_reg.h | 230 + .../soc/esp32h4/register/soc/huk_struct.h | 247 + .../soc/esp32h4/register/soc/io_mux_reg.h | 375 + .../soc/esp32h4/register/soc/keymng_reg.h | 395 + .../soc/esp32h4/register/soc/keymng_struct.h | 375 + .../esp32h4/register/soc/lp_analog_peri_reg.h | 469 + .../register/soc/lp_analog_peri_struct.h | 420 + .../soc/esp32h4/register/soc/lp_aon_reg.h | 683 + .../soc/esp32h4/register/soc/lp_aon_struct.h | 668 + .../soc/esp32h4/register/soc/lp_clkrst_reg.h | 762 + .../esp32h4/register/soc/lp_clkrst_struct.h | 646 + .../soc/esp32h4/register/soc/lp_gpio_reg.h | 778 + .../soc/esp32h4/register/soc/lp_gpio_struct.h | 375 + .../soc/esp32h4/register/soc/lp_iomux_reg.h | 850 + .../esp32h4/register/soc/lp_iomux_struct.h | 145 + .../soc/esp32h4/register/soc/lp_peri_reg.h | 215 + .../soc/esp32h4/register/soc/lp_peri_struct.h | 210 + .../soc/esp32h4/register/soc/lp_tee_reg.h | 1211 ++ .../soc/esp32h4/register/soc/lp_tee_struct.h | 968 + .../soc/esp32h4/register/soc/lp_timer_reg.h | 345 + .../esp32h4/register/soc/lp_timer_struct.h | 365 + .../soc/esp32h4/register/soc/lp_wdt_reg.h | 370 + .../soc/esp32h4/register/soc/lp_wdt_struct.h | 401 + components/soc/esp32h4/register/soc/rng_reg.h | 99 + .../soc/esp32h4/register/soc/rng_struct.h | 106 + components/soc/esp32h4/register/soc/sha_reg.h | 181 + .../soc/esp32h4/register/soc/sha_struct.h | 220 + components/soc/esp32h4/register/soc/tee_reg.h | 4488 +++++ .../soc/esp32h4/register/soc/tee_struct.h | 2940 +++ .../register/soc/usb_otgfs_core_ctrl_reg.h | 16130 ++++++++++++++++ .../register/soc/usb_otgfs_core_ctrl_struct.h | 14445 ++++++++++++++ .../register/soc/usb_serial_jtag_reg.h | 1229 ++ .../register/soc/usb_serial_jtag_struct.h | 982 + .../soc/esp32h4/register/soc/usb_wrap_reg.h | 168 + .../esp32h4/register/soc/usb_wrap_struct.h | 130 + 50 files changed, 56340 insertions(+) create mode 100644 components/soc/esp32h4/include/soc/gpio_sig_map.h create mode 100644 components/soc/esp32h4/include/soc/interrupts.h create mode 100644 components/soc/esp32h4/include/soc/pmu_icg_mapping.h create mode 100644 components/soc/esp32h4/include/soc/reg_base.h create mode 100644 components/soc/esp32h4/include/soc/soc_etm_source.h create mode 100644 components/soc/esp32h4/ld/esp32h4.peripherals.ld create mode 100644 components/soc/esp32h4/register/soc/aes_reg.h create mode 100644 components/soc/esp32h4/register/soc/aes_struct.h create mode 100644 components/soc/esp32h4/register/soc/ecc_mult_reg.h create mode 100644 components/soc/esp32h4/register/soc/ecc_mult_struct.h create mode 100644 components/soc/esp32h4/register/soc/ecdsa_reg.h create mode 100644 components/soc/esp32h4/register/soc/ecdsa_struct.h create mode 100644 components/soc/esp32h4/register/soc/hmac_reg.h create mode 100644 components/soc/esp32h4/register/soc/hmac_struct.h create mode 100644 components/soc/esp32h4/register/soc/huk_reg.h create mode 100644 components/soc/esp32h4/register/soc/huk_struct.h create mode 100644 components/soc/esp32h4/register/soc/io_mux_reg.h create mode 100644 components/soc/esp32h4/register/soc/keymng_reg.h create mode 100644 components/soc/esp32h4/register/soc/keymng_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_analog_peri_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_analog_peri_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_aon_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_aon_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_clkrst_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_clkrst_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_gpio_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_gpio_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_iomux_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_iomux_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_peri_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_peri_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_tee_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_tee_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_timer_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_timer_struct.h create mode 100644 components/soc/esp32h4/register/soc/lp_wdt_reg.h create mode 100644 components/soc/esp32h4/register/soc/lp_wdt_struct.h create mode 100644 components/soc/esp32h4/register/soc/rng_reg.h create mode 100644 components/soc/esp32h4/register/soc/rng_struct.h create mode 100644 components/soc/esp32h4/register/soc/sha_reg.h create mode 100644 components/soc/esp32h4/register/soc/sha_struct.h create mode 100644 components/soc/esp32h4/register/soc/tee_reg.h create mode 100644 components/soc/esp32h4/register/soc/tee_struct.h create mode 100644 components/soc/esp32h4/register/soc/usb_otgfs_core_ctrl_reg.h create mode 100644 components/soc/esp32h4/register/soc/usb_otgfs_core_ctrl_struct.h create mode 100644 components/soc/esp32h4/register/soc/usb_serial_jtag_reg.h create mode 100644 components/soc/esp32h4/register/soc/usb_serial_jtag_struct.h create mode 100644 components/soc/esp32h4/register/soc/usb_wrap_reg.h create mode 100644 components/soc/esp32h4/register/soc/usb_wrap_struct.h diff --git a/components/soc/esp32h4/include/soc/gpio_sig_map.h b/components/soc/esp32h4/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..fb9c494778 --- /dev/null +++ b/components/soc/esp32h4/include/soc/gpio_sig_map.h @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define TIMER_IN_IDX 0 // TODO: [ESP32H4] IDF-12499 need check +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define LEDC_LS_SIG_OUT6_IDX 6 +#define LEDC_LS_SIG_OUT7_IDX 7 +#define U0RXD_IN_IDX 8 +#define U0TXD_OUT_IDX 8 +#define U0CTS_IN_IDX 9 +#define U0RTS_OUT_IDX 9 +#define U0DSR_IN_IDX 10 +#define U0DTR_OUT_IDX 10 +#define U1RXD_IN_IDX 11 +#define U1TXD_OUT_IDX 11 +#define U1CTS_IN_IDX 12 +#define U1RTS_OUT_IDX 12 +#define U1DSR_IN_IDX 13 +#define U1DTR_OUT_IDX 13 +#define I2S_MCLK_IN_IDX 14 +#define I2S_MCLK_OUT_IDX 14 +#define I2SO_BCK_IN_IDX 15 +#define I2SO_BCK_OUT_IDX 15 +#define I2SO_WS_IN_IDX 16 +#define I2SO_WS_OUT_IDX 16 +#define I2SI_SD_IN_IDX 17 +#define I2SO_SD_OUT_IDX 17 +#define I2SI_BCK_IN_IDX 18 +#define I2SI_BCK_OUT_IDX 18 +#define I2SI_WS_IN_IDX 19 +#define I2SI_WS_OUT_IDX 19 +#define I2SO_SD1_OUT_IDX 20 +#define CPU0_TESTBUS0_IDX 21 +#define CPU0_TESTBUS1_IDX 22 +#define CPU0_TESTBUS2_IDX 23 +#define CPU0_TESTBUS3_IDX 24 +#define CPU0_TESTBUS4_IDX 25 +#define CPU0_TESTBUS5_IDX 26 +#define CPU0_TESTBUS6_IDX 27 +#define CPU0_TESTBUS7_IDX 28 +#define CPU0_GPIO_IN0_IDX 29 +#define CPU0_GPIO_OUT0_IDX 29 +#define CPU0_GPIO_IN1_IDX 30 +#define CPU0_GPIO_OUT1_IDX 30 +#define CPU0_GPIO_IN2_IDX 31 +#define CPU0_GPIO_OUT2_IDX 31 +#define CPU0_GPIO_IN3_IDX 32 +#define CPU0_GPIO_OUT3_IDX 32 +#define CPU0_GPIO_IN4_IDX 33 +#define CPU0_GPIO_OUT4_IDX 33 +#define CPU0_GPIO_IN5_IDX 34 +#define CPU0_GPIO_OUT5_IDX 34 +#define CPU0_GPIO_IN6_IDX 35 +#define CPU0_GPIO_OUT6_IDX 35 +#define CPU0_GPIO_IN7_IDX 36 +#define CPU0_GPIO_OUT7_IDX 36 +#define USB_JTAG_TDO_IDX 37 +#define USB_JTAG_TRST_IDX 37 +#define USB_JTAG_SRST_IDX 38 +#define USB_JTAG_TCK_IDX 39 +#define USB_JTAG_TMS_IDX 40 +#define USB_JTAG_TDI_IDX 41 +#define CPU_USB_JTAG_TDO_IDX 42 +#define USB_OTG_IDDIG_IN_IDX 43 +#define USB_SRP_DISCHRGVBUS_OUT_IDX 43 +#define USB_OTG_AVALID_IN_IDX 44 +#define USB_OTG_IDPULLUP_OUT_IDX 44 +#define USB_SRP_BVALID_IN_IDX 45 +#define USB_OTG_DPPULLDOWN_OUT_IDX 45 +#define USB_OTG_VBUSVALID_IN_IDX 46 +#define USB_OTG_DMPULLDOWN_OUT_IDX 46 +#define USB_SRP_SESSEND_IN_IDX 47 +#define USB_OTG_DRVVBUS_OUT_IDX 47 +#define USB_SRP_CHRGVBUS_OUT_IDX 48 +#define I2CEXT0_SCL_IN_IDX 49 +#define I2CEXT0_SCL_OUT_IDX 49 +#define I2CEXT0_SDA_IN_IDX 50 +#define I2CEXT0_SDA_OUT_IDX 50 +#define PARL_RX_DATA0_IDX 51 +#define PARL_TX_DATA0_IDX 51 +#define PARL_RX_DATA1_IDX 52 +#define PARL_TX_DATA1_IDX 52 +#define PARL_RX_DATA2_IDX 53 +#define PARL_TX_DATA2_IDX 53 +#define PARL_RX_DATA3_IDX 54 +#define PARL_TX_DATA3_IDX 54 +#define PARL_RX_DATA4_IDX 55 +#define PARL_TX_DATA4_IDX 55 +#define PARL_RX_DATA5_IDX 56 +#define PARL_TX_DATA5_IDX 56 +#define PARL_RX_DATA6_IDX 57 +#define PARL_TX_DATA6_IDX 57 +#define PARL_RX_DATA7_IDX 58 +#define PARL_TX_DATA7_IDX 58 +#define FSPICLK_IN_IDX 59 +#define FSPICLK_OUT_IDX 59 +#define FSPIQ_IN_IDX 60 +#define FSPIQ_OUT_IDX 60 +#define FSPID_IN_IDX 61 +#define FSPID_OUT_IDX 61 +#define FSPIHD_IN_IDX 62 +#define FSPIHD_OUT_IDX 62 +#define FSPIWP_IN_IDX 63 +#define FSPIWP_OUT_IDX 63 +#define FSPICS0_IN_IDX 64 +#define FSPICS0_OUT_IDX 64 +#define PARL_RX_CLK_IN_IDX 65 +#define PARL_RX_CLK_OUT_IDX 65 +#define PARL_TX_CLK_IN_IDX 66 +#define PARL_TX_CLK_OUT_IDX 66 +#define RMT_SIG_IN0_IDX 67 +#define RMT_SIG_OUT0_IDX 67 +#define RMT_SIG_IN1_IDX 68 +#define RMT_SIG_OUT1_IDX 68 +#define TWAI0_RX_IDX 69 +#define TWAI0_TX_IDX 69 +#define PARL_TX_CS_IDX 70 +#define EXTERN_PRIORITY_I_IDX 75 +#define EXTERN_PRIORITY_O_IDX 75 +#define EXTERN_ACTIVE_I_IDX 76 +#define EXTERN_ACTIVE_O_IDX 76 +#define PCNT_RST_IN0_IDX 77 +#define GPIO_SD0_OUT_IDX 77 +#define PCNT_RST_IN1_IDX 78 +#define GPIO_SD1_OUT_IDX 78 +#define PCNT_RST_IN2_IDX 79 +#define GPIO_SD2_OUT_IDX 79 +#define PCNT_RST_IN3_IDX 80 +#define GPIO_SD3_OUT_IDX 80 +#define PWM0_SYNC0_IN_IDX 81 +#define PWM0_OUT0A_IDX 81 +#define PWM0_SYNC1_IN_IDX 82 +#define PWM0_OUT0B_IDX 82 +#define PWM0_SYNC2_IN_IDX 83 +#define PWM0_OUT1A_IDX 83 +#define PWM0_F0_IN_IDX 84 +#define PWM0_OUT1B_IDX 84 +#define PWM0_F1_IN_IDX 85 +#define PWM0_OUT2A_IDX 85 +#define PWM0_F2_IN_IDX 86 +#define PWM0_OUT2B_IDX 86 +#define PWM0_CAP0_IN_IDX 87 +#define PWM0_CAP1_IN_IDX 88 +#define PWM0_CAP2_IN_IDX 89 +#define GPIO_EVENT_MATRIX_IN0_IDX 90 +#define GPIO_TASK_MATRIX_OUT0_IDX 90 +#define GPIO_EVENT_MATRIX_IN1_IDX 91 +#define GPIO_TASK_MATRIX_OUT1_IDX 91 +#define GPIO_EVENT_MATRIX_IN2_IDX 92 +#define GPIO_TASK_MATRIX_OUT2_IDX 92 +#define GPIO_EVENT_MATRIX_IN3_IDX 93 +#define GPIO_TASK_MATRIX_OUT3_IDX 93 +#define CLK_OUT_OUT1_IDX 94 +#define CLK_OUT_OUT2_IDX 95 +#define CLK_OUT_OUT3_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 102 +#define FSPICS1_OUT_IDX 102 +#define PCNT_SIG_CH1_IN0_IDX 103 +#define FSPICS2_OUT_IDX 103 +#define PCNT_CTRL_CH0_IN0_IDX 104 +#define FSPICS3_OUT_IDX 104 +#define PCNT_CTRL_CH1_IN0_IDX 105 +#define FSPICS4_OUT_IDX 105 +#define PCNT_SIG_CH0_IN1_IDX 106 +#define FSPICS5_OUT_IDX 106 +#define PCNT_SIG_CH1_IN1_IDX 107 +#define MODEM_DIAG0_IDX 107 +#define PCNT_CTRL_CH0_IN1_IDX 108 +#define MODEM_DIAG1_IDX 108 +#define PCNT_CTRL_CH1_IN1_IDX 109 +#define MODEM_DIAG2_IDX 109 +#define PCNT_SIG_CH0_IN2_IDX 110 +#define MODEM_DIAG3_IDX 110 +#define PCNT_SIG_CH1_IN2_IDX 111 +#define MODEM_DIAG4_IDX 111 +#define PCNT_CTRL_CH0_IN2_IDX 112 +#define MODEM_DIAG5_IDX 112 +#define PCNT_CTRL_CH1_IN2_IDX 113 +#define MODEM_DIAG6_IDX 113 +#define PCNT_SIG_CH0_IN3_IDX 114 +#define MODEM_DIAG7_IDX 114 +#define PCNT_SIG_CH1_IN3_IDX 115 +#define MODEM_DIAG8_IDX 115 +#define PCNT_CTRL_CH0_IN3_IDX 116 +#define MODEM_DIAG9_IDX 116 +#define PCNT_CTRL_CH1_IN3_IDX 117 +#define MODEM_DIAG10_IDX 117 +#define MODEM_DIAG11_IDX 118 +#define MODEM_DIAG12_IDX 119 +#define MODEM_DIAG13_IDX 120 +#define MODEM_DIAG14_IDX 121 +#define MODEM_DIAG15_IDX 122 +#define MODEM_DIAG16_IDX 123 +#define MODEM_DIAG17_IDX 124 +#define MODEM_DIAG18_IDX 125 +#define MODEM_DIAG19_IDX 126 +#define MODEM_DIAG20_IDX 127 +#define MODEM_DIAG21_IDX 128 +#define MODEM_DIAG22_IDX 129 +#define MODEM_DIAG23_IDX 130 +#define MODEM_DIAG24_IDX 131 +#define MODEM_DIAG25_IDX 132 +#define MODEM_DIAG26_IDX 133 +#define MODEM_DIAG27_IDX 134 +#define MODEM_DIAG28_IDX 135 +#define MODEM_DIAG29_IDX 136 +#define MODEM_DIAG30_IDX 137 +#define MODEM_DIAG31_IDX 138 +#define ANT_SEL0_IDX 139 +#define ANT_SEL1_IDX 140 +#define ANT_SEL2_IDX 141 +#define ANT_SEL3_IDX 142 +#define ANT_SEL4_IDX 143 +#define ANT_SEL5_IDX 144 +#define ANT_SEL6_IDX 145 +#define ANT_SEL7_IDX 146 +#define ANT_SEL8_IDX 147 +#define ANT_SEL9_IDX 148 +#define ANT_SEL10_IDX 149 +#define ANT_SEL11_IDX 150 +#define ANT_SEL12_IDX 151 +#define ANT_SEL13_IDX 152 +#define ANT_SEL14_IDX 153 +#define ANT_SEL15_IDX 154 +#define PWM1_SYNC0_IN_IDX 155 +#define PWM1_OUT0A_IDX 155 +#define PWM1_SYNC1_IN_IDX 156 +#define PWM1_OUT0B_IDX 156 +#define PWM1_SYNC2_IN_IDX 157 +#define PWM1_OUT1A_IDX 157 +#define PWM1_F0_IN_IDX 158 +#define PWM1_OUT1B_IDX 158 +#define PWM1_F1_IN_IDX 159 +#define PWM1_OUT2A_IDX 159 +#define PWM1_F2_IN_IDX 160 +#define PWM1_OUT2B_IDX 160 +#define PWM1_CAP0_IN_IDX 161 +#define PWM1_CAP1_IN_IDX 162 +#define PWM1_CAP2_IN_IDX 163 +#define I2CEXT1_SCL_IN_IDX 164 +#define I2CEXT1_SCL_OUT_IDX 164 +#define I2CEXT1_SDA_IN_IDX 165 +#define I2CEXT1_SDA_OUT_IDX 165 +#define FSPI3CLK_IN_IDX 166 +#define FSPI3CLK_OUT_IDX 166 +#define FSPI3Q_IN_IDX 167 +#define FSPI3Q_OUT_IDX 167 +#define FSPI3D_IN_IDX 168 +#define FSPI3D_OUT_IDX 168 +#define FSPI3HD_IN_IDX 169 +#define FSPI3HD_OUT_IDX 169 +#define FSPI3WP_IN_IDX 170 +#define FSPI3WP_OUT_IDX 170 +#define FSPI3CS0_IN_IDX 171 +#define FSPI3CS0_OUT_IDX 171 +#define FSPI3CS1_OUT_IDX 172 +#define FSPI3CS2_OUT_IDX 173 +#define CPU1_TESTBUS0_IDX 174 +#define CPU1_TESTBUS1_IDX 175 +#define CPU1_TESTBUS2_IDX 176 +#define CPU1_TESTBUS3_IDX 177 +#define CPU1_TESTBUS4_IDX 178 +#define CPU1_TESTBUS5_IDX 179 +#define CPU1_TESTBUS6_IDX 180 +#define CPU1_TESTBUS7_IDX 181 +#define CPU1_GPIO_IN0_IDX 182 +#define CPU1_GPIO_OUT0_IDX 182 +#define CPU1_GPIO_IN1_IDX 183 +#define CPU1_GPIO_OUT1_IDX 183 +#define CPU1_GPIO_IN2_IDX 184 +#define CPU1_GPIO_OUT2_IDX 184 +#define CPU1_GPIO_IN3_IDX 185 +#define CPU1_GPIO_OUT3_IDX 185 +#define CPU1_GPIO_IN4_IDX 186 +#define CPU1_GPIO_OUT4_IDX 186 +#define CPU1_GPIO_IN5_IDX 187 +#define CPU1_GPIO_OUT5_IDX 187 +#define CPU1_GPIO_IN6_IDX 188 +#define CPU1_GPIO_OUT6_IDX 188 +#define CPU1_GPIO_IN7_IDX 189 +#define CPU1_GPIO_OUT7_IDX 189 +#define DIAG_MODE0_OUT_MUX0_IDX 190 +#define DIAG_MODE0_OUT_MUX1_IDX 191 +#define DIAG_MODE0_OUT_MUX2_IDX 192 +#define DIAG_MODE0_OUT_MUX3_IDX 193 +#define DIAG_MODE0_OUT_MUX4_IDX 194 +#define DIAG_MODE0_OUT_MUX5_IDX 195 +#define DIAG_MODE0_OUT_MUX6_IDX 196 +#define DIAG_MODE0_OUT_MUX7_IDX 197 +#define PROBE_TOUCH_OUT_IDX 198 +#define PROBE_TOP_OUT0_IDX 199 +#define PROBE_TOP_OUT1_IDX 200 +#define PROBE_TOP_OUT2_IDX 201 +#define PROBE_TOP_OUT3_IDX 202 +#define PROBE_TOP_OUT4_IDX 203 +#define PROBE_TOP_OUT5_IDX 204 +#define PROBE_TOP_OUT6_IDX 205 +#define PROBE_TOP_OUT7_IDX 206 +#define PROBE_TOP_OUT8_IDX 207 +#define PROBE_TOP_OUT9_IDX 208 +#define PROBE_TOP_OUT10_IDX 209 +#define PROBE_TOP_OUT11_IDX 210 +#define PROBE_TOP_OUT12_IDX 211 +#define PROBE_TOP_OUT13_IDX 212 +#define PROBE_TOP_OUT14_IDX 213 +#define PROBE_TOP_OUT15_IDX 214 +// version date 2403250 +#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32h4/include/soc/interrupts.h b/components/soc/esp32h4/include/soc/interrupts.h new file mode 100644 index 0000000000..e6d379b855 --- /dev/null +++ b/components/soc/esp32h4/include/soc/interrupts.h @@ -0,0 +1,116 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE, + ETS_WIFI_MAC_NMI_SOURCE, + ETS_WIFI_PWR_INTR_SOURCE, + ETS_WIFI_BB_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MST_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_MODEM_APB_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INT1_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_RTC_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_TOUCH_INTR_SOURCE, + ETS_HUK_INTR_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_BUS_MONITOR_INTR_SOURCE, + ETS_CORE0_TRACE_INTR_SOURCE, + ETS_CORE1_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTERRUPT_2_SOURCE, + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_HP_APM_M4_INTR_SOURCE, + ETS_CPU_APM_M0_INTR_SOURCE, + ETS_CPU_APM_M1_INTR_SOURCE, + ETS_CPU_APM_M2_INTR_SOURCE, + ETS_CPU_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_TWAI0_INTR_SOURCE, + ETS_TWAI0_TIMER_INTR_SOURCE, + ETS_USB_SERIAL_JTAG_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_I2C_EXT1_INTR_SOURCE, + ETS_TG0_T0_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, + ETS_TG1_T0_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_PWM0_INTR_SOURCE, + ETS_PWM1_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_USB_OTG11_INTR_SOURCE, + ETS_ASRC_CHNL0_INTR_SOURCE, + ETS_ASRC_CHNL1_INTR_SOURCE, + ETS_ZERO_DET_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_IN_CH2_INTR_SOURCE, + ETS_DMA_IN_CH3_INTR_SOURCE, + ETS_DMA_IN_CH4_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH3_INTR_SOURCE, + ETS_DMA_OUT_CH4_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_GPSPI3_INTR_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_KM_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/include/soc/pmu_icg_mapping.h b/components/soc/esp32h4/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..60305183f8 --- /dev/null +++ b/components/soc/esp32h4/include/soc/pmu_icg_mapping.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_APB_ENA_TWAI0 18 +#define PMU_ICG_APB_ENA_TWAI1 19 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_TWAI1 30 +#define PMU_ICG_FUNC_ENA_TWAI0 31 diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h new file mode 100644 index 0000000000..a3fd3a1ed8 --- /dev/null +++ b/components/soc/esp32h4/include/soc/reg_base.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DR_REG_TRACE0_BASE 0x60000000 +#define DR_REG_TRACE1_BASE 0x60001000 +#define DR_REG_ASSIST_DEBUG_BASE 0x60002000 +#define DR_REG_INTPRI_BASE 0x60005000 +#define DR_REG_CACHE_BASE 0x60008000 +#define DR_REG_GPSPI2_BASE 0x60010000 +#define DR_REG_GPSPI3_BASE 0x60011000 +#define DR_REG_UART0_BASE 0x60012000 +#define DR_REG_UART1_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_I2C0_BASE 0x60015000 +#define DR_REG_I2C1_BASE 0x60016000 +#define DR_REG_I2S0_BASE 0x60017000 +#define DR_REG_PARL_IO_BASE 0x60018000 +#define DR_REG_MCPWM0_BASE 0x60019000 +#define DR_REG_MCPWM1_BASE 0x6001A000 +#define DR_REG_LEDC_BASE 0x6001B000 +#define DR_REG_TWAIFD_BASE 0x6001C000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6001D000 +#define DR_REG_RMT_BASE 0x6001E000 +#define DR_REG_AHB_DMA_BASE 0x6001F000 +#define DR_REG_PAU_BASE 0x60020000 +#define DR_REG_SOC_ETM_BASE 0x60021000 +#define DR_REG_APB_SARADC_BASE 0x60022000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_MEM_MONITOR_BASE 0x60025000 +#define DR_REG_PVT_BASE 0x60026000 +#define DR_REG_PCNT_BASE 0x60027000 +#define DR_REG_SAMPLE_RATE_CONVERTER_BASE 0x60028000 +#define DR_REG_ZERO_DET_BASE 0x60029000 +#define DR_REG_USB_OTG_FS_CORE0_BASE 0x60040000 +#define DR_REG_USB_OTG_FS_CORE1_BASE 0x6007F000 +#define DR_REG_USB_OTG_FS_PHY_BASE 0x60080000 +#define DR_REG_TIMERG0_BASE 0x60090000 +#define DR_REG_TIMERG1_BASE 0x60091000 +#define DR_REG_IO_MUX_BASE 0x60092000 +#define DR_REG_GPIO_BASE 0x60093000 +#define DR_REG_GPIO_EXT_BASE 0x60093E00 +#define DR_REG_PCR_BASE 0x60094000 +#define DR_REG_SPIMEM0_BASE 0x60098000 +#define DR_REG_SPIMEM1_BASE 0x60099000 +#define DR_REG_INTMTX0_BASE 0x6009A000 +#define DR_REG_INTMTX1_BASE 0x6009B000 +#define DR_REG_HP_SYSTEM_BASE 0x6009C000 +#define DR_REG_HP_APM_BASE 0x6009D000 +#define DR_REG_CPU_APM_REG_BASE 0x6009E000 +#define DR_REG_TEE_BASE 0x6009F000 +#define DR_REG_KEYMNG_BASE 0x600A5000 +#define DR_REG_AES_BASE 0x600A6000 +#define DR_REG_SHA_BASE 0x600A7000 +#define DR_REG_ECC_BASE 0x600A8000 +#define DR_REG_HMAC_BASE 0x600A9000 +#define DR_REG_ECDSA_BASE 0x600AA000 +#define DR_REG_HUK_BASE 0x600B1000 +#define DR_REG_LP_TEE_BASE 0x600B1400 +#define DR_REG_EFUSE_BASE 0x600B1800 +#define DR_REG_OTP_DEBUG_BASE 0x600B1C00 +#define DR_REG_TRNG_BASE 0x600B2000 +#define DR_REG_PMU_BASE 0x600B2400 +#define DR_REG_LP_AON_BASE 0x600B2800 +#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00 +#define DR_REG_LP_CLKRST_BASE 0x600B3000 +#define DR_REG_LPPERI_BASE 0x600B3400 +#define DR_REG_LP_IO_MUX_BASE 0x600B3800 +#define DR_REG_LP_GPIO_BASE 0x600B3C00 +#define DR_REG_LP_TIMER_BASE 0x600B5000 +#define DR_REG_LP_WDT_BASE 0x600B5400 +#define DR_REG_TOUCH_SENS_BASE 0x600B5800 +#define DR_REG_TOUCH_AON_BASE 0x600B5C00 + +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 // TODO: [ESP32H4] IDF-12315 inherit from verify code, need check diff --git a/components/soc/esp32h4/include/soc/soc_etm_source.h b/components/soc/esp32h4/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..a7b6791377 --- /dev/null +++ b/components/soc/esp32h4/include/soc/soc_etm_source.h @@ -0,0 +1,401 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define GPIO_EVT_ZERO_DET_POS0 25 +#define GPIO_EVT_ZERO_DET_NEG0 26 +#define LEDC_EVT_DUTY_CHNG_END_CH0 27 +#define LEDC_EVT_DUTY_CHNG_END_CH1 28 +#define LEDC_EVT_DUTY_CHNG_END_CH2 29 +#define LEDC_EVT_DUTY_CHNG_END_CH3 30 +#define LEDC_EVT_DUTY_CHNG_END_CH4 31 +#define LEDC_EVT_DUTY_CHNG_END_CH5 32 +#define LEDC_EVT_DUTY_CHNG_END_CH6 33 +#define LEDC_EVT_DUTY_CHNG_END_CH7 34 +#define LEDC_EVT_OVF_CNT_PLS_CH0 35 +#define LEDC_EVT_OVF_CNT_PLS_CH1 36 +#define LEDC_EVT_OVF_CNT_PLS_CH2 37 +#define LEDC_EVT_OVF_CNT_PLS_CH3 38 +#define LEDC_EVT_OVF_CNT_PLS_CH4 39 +#define LEDC_EVT_OVF_CNT_PLS_CH5 40 +#define LEDC_EVT_OVF_CNT_PLS_CH6 41 +#define LEDC_EVT_OVF_CNT_PLS_CH7 42 +#define LEDC_EVT_TIME_OVF_TIMER0 43 +#define LEDC_EVT_TIME_OVF_TIMER1 44 +#define LEDC_EVT_TIME_OVF_TIMER2 45 +#define LEDC_EVT_TIME_OVF_TIMER3 46 +#define LEDC_EVT_TIMER0_CMP 47 +#define LEDC_EVT_TIMER1_CMP 48 +#define LEDC_EVT_TIMER2_CMP 49 +#define LEDC_EVT_TIMER3_CMP 50 +#define TG0_EVT_CNT_CMP_TIMER0 51 +#define TG1_EVT_CNT_CMP_TIMER0 52 +#define SYSTIMER_EVT_CNT_CMP0 53 +#define SYSTIMER_EVT_CNT_CMP1 54 +#define SYSTIMER_EVT_CNT_CMP2 55 +#define MCPWM0_EVT_TIMER0_STOP 56 +#define MCPWM0_EVT_TIMER1_STOP 57 +#define MCPWM0_EVT_TIMER2_STOP 58 +#define MCPWM0_EVT_TIMER0_TEZ 59 +#define MCPWM0_EVT_TIMER1_TEZ 60 +#define MCPWM0_EVT_TIMER2_TEZ 61 +#define MCPWM0_EVT_TIMER0_TEP 62 +#define MCPWM0_EVT_TIMER1_TEP 63 +#define MCPWM0_EVT_TIMER2_TEP 64 +#define MCPWM0_EVT_OP0_TEA 65 +#define MCPWM0_EVT_OP1_TEA 66 +#define MCPWM0_EVT_OP2_TEA 67 +#define MCPWM0_EVT_OP0_TEB 68 +#define MCPWM0_EVT_OP1_TEB 69 +#define MCPWM0_EVT_OP2_TEB 70 +#define MCPWM0_EVT_F0 71 +#define MCPWM0_EVT_F1 72 +#define MCPWM0_EVT_F2 73 +#define MCPWM0_EVT_F0_CLR 74 +#define MCPWM0_EVT_F1_CLR 75 +#define MCPWM0_EVT_F2_CLR 76 +#define MCPWM0_EVT_TZ0_CBC 77 +#define MCPWM0_EVT_TZ1_CBC 78 +#define MCPWM0_EVT_TZ2_CBC 79 +#define MCPWM0_EVT_TZ0_OST 80 +#define MCPWM0_EVT_TZ1_OST 81 +#define MCPWM0_EVT_TZ2_OST 82 +#define MCPWM0_EVT_CAP0 83 +#define MCPWM0_EVT_CAP1 84 +#define MCPWM0_EVT_CAP2 85 +#define MCPWM0_EVT_OP0_TEE1 86 +#define MCPWM0_EVT_OP1_TEE1 87 +#define MCPWM0_EVT_OP2_TEE1 88 +#define MCPWM0_EVT_OP0_TEE2 89 +#define MCPWM0_EVT_OP1_TEE2 90 +#define MCPWM0_EVT_OP2_TEE2 91 +#define MCPWM1_EVT_TIMER0_STOP 92 +#define MCPWM1_EVT_TIMER1_STOP 93 +#define MCPWM1_EVT_TIMER2_STOP 94 +#define MCPWM1_EVT_TIMER0_TEZ 95 +#define MCPWM1_EVT_TIMER1_TEZ 96 +#define MCPWM1_EVT_TIMER2_TEZ 97 +#define MCPWM1_EVT_TIMER0_TEP 98 +#define MCPWM1_EVT_TIMER1_TEP 99 +#define MCPWM1_EVT_TIMER2_TEP 100 +#define MCPWM1_EVT_OP0_TEA 101 +#define MCPWM1_EVT_OP1_TEA 102 +#define MCPWM1_EVT_OP2_TEA 103 +#define MCPWM1_EVT_OP0_TEB 104 +#define MCPWM1_EVT_OP1_TEB 105 +#define MCPWM1_EVT_OP2_TEB 106 +#define MCPWM1_EVT_F0 107 +#define MCPWM1_EVT_F1 108 +#define MCPWM1_EVT_F2 109 +#define MCPWM1_EVT_F0_CLR 110 +#define MCPWM1_EVT_F1_CLR 111 +#define MCPWM1_EVT_F2_CLR 112 +#define MCPWM1_EVT_TZ0_CBC 113 +#define MCPWM1_EVT_TZ1_CBC 114 +#define MCPWM1_EVT_TZ2_CBC 115 +#define MCPWM1_EVT_TZ0_OST 116 +#define MCPWM1_EVT_TZ1_OST 117 +#define MCPWM1_EVT_TZ2_OST 118 +#define MCPWM1_EVT_CAP0 119 +#define MCPWM1_EVT_CAP1 120 +#define MCPWM1_EVT_CAP2 121 +#define MCPWM1_EVT_OP0_TEE1 122 +#define MCPWM1_EVT_OP1_TEE1 123 +#define MCPWM1_EVT_OP2_TEE1 124 +#define MCPWM1_EVT_OP0_TEE2 125 +#define MCPWM1_EVT_OP1_TEE2 126 +#define MCPWM1_EVT_OP2_TEE2 127 +#define ADC_EVT_CONV_CMPLT0 128 +#define ADC_EVT_EQ_ABOVE_THRESH0 129 +#define ADC_EVT_EQ_ABOVE_THRESH1 130 +#define ADC_EVT_EQ_BELOW_THRESH0 131 +#define ADC_EVT_EQ_BELOW_THRESH1 132 +#define ADC_EVT_RESULT_DONE0 133 +#define ADC_EVT_STOPPED0 134 +#define ADC_EVT_STARTED0 135 +#define REGDMA_EVT_DONE0 136 +#define REGDMA_EVT_DONE1 137 +#define REGDMA_EVT_DONE2 138 +#define REGDMA_EVT_DONE3 139 +#define REGDMA_EVT_ERR0 140 +#define REGDMA_EVT_ERR1 141 +#define REGDMA_EVT_ERR2 142 +#define REGDMA_EVT_ERR3 143 +#define TMPSNSR_EVT_OVER_LIMIT 144 +#define I2S0_EVT_RX_DONE 145 +#define I2S0_EVT_TX_DONE 146 +#define I2S0_EVT_X_WORDS_RECEIVED 147 +#define I2S0_EVT_X_WORDS_SENT 148 +#define ULP_EVT_ERR_INTR 149 +#define ULP_EVT_HALT 150 +#define ULP_EVT_START_INTR 151 +#define RTC_EVT_TICK 152 +#define RTC_EVT_OVF 153 +#define RTC_EVT_CMP 154 +#define GDMA_EVT_IN_DONE_CH0 155 +#define GDMA_EVT_IN_DONE_CH1 156 +#define GDMA_EVT_IN_DONE_CH2 157 +#define GDMA_EVT_IN_DONE_CH3 158 +#define GDMA_EVT_IN_DONE_CH4 159 +#define GDMA_EVT_IN_SUC_EOF_CH0 160 +#define GDMA_EVT_IN_SUC_EOF_CH1 161 +#define GDMA_EVT_IN_SUC_EOF_CH2 162 +#define GDMA_EVT_IN_SUC_EOF_CH3 163 +#define GDMA_EVT_IN_SUC_EOF_CH4 164 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 165 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 166 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 167 +#define GDMA_EVT_IN_FIFO_EMPTY_CH3 168 +#define GDMA_EVT_IN_FIFO_EMPTY_CH4 169 +#define GDMA_EVT_IN_FIFO_FULL_CH0 170 +#define GDMA_EVT_IN_FIFO_FULL_CH1 171 +#define GDMA_EVT_IN_FIFO_FULL_CH2 172 +#define GDMA_EVT_IN_FIFO_FULL_CH3 173 +#define GDMA_EVT_IN_FIFO_FULL_CH4 174 +#define GDMA_EVT_OUT_DONE_CH0 175 +#define GDMA_EVT_OUT_DONE_CH1 176 +#define GDMA_EVT_OUT_DONE_CH2 177 +#define GDMA_EVT_OUT_DONE_CH3 178 +#define GDMA_EVT_OUT_DONE_CH4 179 +#define GDMA_EVT_OUT_EOF_CH0 180 +#define GDMA_EVT_OUT_EOF_CH1 181 +#define GDMA_EVT_OUT_EOF_CH2 182 +#define GDMA_EVT_OUT_EOF_CH3 183 +#define GDMA_EVT_OUT_EOF_CH4 184 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 185 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 186 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 187 +#define GDMA_EVT_OUT_TOTAL_EOF_CH3 188 +#define GDMA_EVT_OUT_TOTAL_EOF_CH4 189 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 190 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 191 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 192 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH3 193 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH4 194 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 195 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 196 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 197 +#define GDMA_EVT_OUT_FIFO_FULL_CH3 198 +#define GDMA_EVT_OUT_FIFO_FULL_CH4 199 +#define PMU_EVT_SLEEP_WEEKUP 200 +#define MODEM_EVT_G0 201 +#define MODEM_EVT_G1 202 +#define MODEM_EVT_G2 203 +#define MODEM_EVT_G3 204 +#define ZERO_DET_EVT_CHANNEL_1_POS 205 +#define ZERO_DET_EVT_CHANNEL_2_POS 206 +#define ZERO_DET_EVT_CHANNEL_3_POS 207 +#define ZERO_DET_EVT_CHANNEL_1_NEG 208 +#define ZERO_DET_EVT_CHANNEL_2_NEG 209 +#define ZERO_DET_EVT_CHANNEL_3_NEG 210 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 35 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 36 +#define LEDC_TASK_TIMER0_CAP 37 +#define LEDC_TASK_TIMER1_CAP 38 +#define LEDC_TASK_TIMER2_CAP 39 +#define LEDC_TASK_TIMER3_CAP 40 +#define LEDC_TASK_SIG_OUT_DIS_CH0 41 +#define LEDC_TASK_SIG_OUT_DIS_CH1 42 +#define LEDC_TASK_SIG_OUT_DIS_CH2 43 +#define LEDC_TASK_SIG_OUT_DIS_CH3 44 +#define LEDC_TASK_SIG_OUT_DIS_CH4 45 +#define LEDC_TASK_SIG_OUT_DIS_CH5 46 +#define LEDC_TASK_SIG_OUT_DIS_CH6 47 +#define LEDC_TASK_SIG_OUT_DIS_CH7 48 +#define LEDC_TASK_OVF_CNT_RST_CH0 49 +#define LEDC_TASK_OVF_CNT_RST_CH1 50 +#define LEDC_TASK_OVF_CNT_RST_CH2 51 +#define LEDC_TASK_OVF_CNT_RST_CH3 52 +#define LEDC_TASK_OVF_CNT_RST_CH4 53 +#define LEDC_TASK_OVF_CNT_RST_CH5 54 +#define LEDC_TASK_OVF_CNT_RST_CH6 55 +#define LEDC_TASK_OVF_CNT_RST_CH7 56 +#define LEDC_TASK_TIMER0_RST 57 +#define LEDC_TASK_TIMER1_RST 58 +#define LEDC_TASK_TIMER2_RST 59 +#define LEDC_TASK_TIMER3_RST 60 +#define LEDC_TASK_TIMER0_RESUME 61 +#define LEDC_TASK_TIMER1_RESUME 62 +#define LEDC_TASK_TIMER2_RESUME 63 +#define LEDC_TASK_TIMER3_RESUME 64 +#define LEDC_TASK_TIMER0_PAUSE 65 +#define LEDC_TASK_TIMER1_PAUSE 66 +#define LEDC_TASK_TIMER2_PAUSE 67 +#define LEDC_TASK_TIMER3_PAUSE 68 +#define LEDC_TASK_FADE_RESTART_CH0 69 +#define LEDC_TASK_FADE_RESTART_CH1 70 +#define LEDC_TASK_FADE_RESTART_CH2 71 +#define LEDC_TASK_FADE_RESTART_CH3 72 +#define LEDC_TASK_FADE_RESTART_CH4 73 +#define LEDC_TASK_FADE_RESTART_CH5 74 +#define LEDC_TASK_FADE_RESTART_CH6 75 +#define LEDC_TASK_FADE_RESTART_CH7 76 +#define LEDC_TASK_FADE_PAUSE_CH0 77 +#define LEDC_TASK_FADE_PAUSE_CH1 78 +#define LEDC_TASK_FADE_PAUSE_CH2 79 +#define LEDC_TASK_FADE_PAUSE_CH3 80 +#define LEDC_TASK_FADE_PAUSE_CH4 81 +#define LEDC_TASK_FADE_PAUSE_CH5 82 +#define LEDC_TASK_FADE_PAUSE_CH6 83 +#define LEDC_TASK_FADE_PAUSE_CH7 84 +#define LEDC_TASK_FADE_RESUME_CH0 85 +#define LEDC_TASK_FADE_RESUME_CH1 86 +#define LEDC_TASK_FADE_RESUME_CH2 87 +#define LEDC_TASK_FADE_RESUME_CH3 88 +#define LEDC_TASK_FADE_RESUME_CH4 89 +#define LEDC_TASK_FADE_RESUME_CH5 90 +#define LEDC_TASK_FADE_RESUME_CH6 91 +#define LEDC_TASK_FADE_RESUME_CH7 92 +#define TG0_TASK_CNT_START_TIMER0 93 +#define TG0_TASK_ALARM_START_TIMER0 94 +#define TG0_TASK_CNT_STOP_TIMER0 95 +#define TG0_TASK_CNT_RELOAD_TIMER0 96 +#define TG0_TASK_CNT_CAP_TIMER0 97 +#define TG1_TASK_CNT_START_TIMER0 98 +#define TG1_TASK_ALARM_START_TIMER0 99 +#define TG1_TASK_CNT_STOP_TIMER0 100 +#define TG1_TASK_CNT_RELOAD_TIMER0 101 +#define TG1_TASK_CNT_CAP_TIMER0 102 +#define MCPWM0_TASK_CMPR0_A_UP 103 +#define MCPWM0_TASK_CMPR1_A_UP 104 +#define MCPWM0_TASK_CMPR2_A_UP 105 +#define MCPWM0_TASK_CMPR0_B_UP 106 +#define MCPWM0_TASK_CMPR1_B_UP 107 +#define MCPWM0_TASK_CMPR2_B_UP 108 +#define MCPWM0_TASK_GEN_STOP 109 +#define MCPWM0_TASK_TIMER0_SYN 110 +#define MCPWM0_TASK_TIMER1_SYN 111 +#define MCPWM0_TASK_TIMER2_SYN 112 +#define MCPWM0_TASK_TIMER0_PERIOD_UP 113 +#define MCPWM0_TASK_TIMER1_PERIOD_UP 114 +#define MCPWM0_TASK_TIMER2_PERIOD_UP 115 +#define MCPWM0_TASK_TZ0_OST 116 +#define MCPWM0_TASK_TZ1_OST 117 +#define MCPWM0_TASK_TZ2_OST 118 +#define MCPWM0_TASK_CLR0_OST 119 +#define MCPWM0_TASK_CLR1_OST 120 +#define MCPWM0_TASK_CLR2_OST 121 +#define MCPWM0_TASK_CAP0 122 +#define MCPWM0_TASK_CAP1 123 +#define MCPWM0_TASK_CAP2 124 +#define MCPWM1_TASK_CMPR0_A_UP 125 +#define MCPWM1_TASK_CMPR1_A_UP 126 +#define MCPWM1_TASK_CMPR2_A_UP 127 +#define MCPWM1_TASK_CMPR0_B_UP 128 +#define MCPWM1_TASK_CMPR1_B_UP 129 +#define MCPWM1_TASK_CMPR2_B_UP 130 +#define MCPWM1_TASK_GEN_STOP 131 +#define MCPWM1_TASK_TIMER0_SYN 132 +#define MCPWM1_TASK_TIMER1_SYN 133 +#define MCPWM1_TASK_TIMER2_SYN 134 +#define MCPWM1_TASK_TIMER0_PERIOD_UP 135 +#define MCPWM1_TASK_TIMER1_PERIOD_UP 136 +#define MCPWM1_TASK_TIMER2_PERIOD_UP 137 +#define MCPWM1_TASK_TZ0_OST 138 +#define MCPWM1_TASK_TZ1_OST 139 +#define MCPWM1_TASK_TZ2_OST 140 +#define MCPWM1_TASK_CLR0_OST 141 +#define MCPWM1_TASK_CLR1_OST 142 +#define MCPWM1_TASK_CLR2_OST 143 +#define MCPWM1_TASK_CAP0 144 +#define MCPWM1_TASK_CAP1 145 +#define MCPWM1_TASK_CAP2 146 +#define ADC_TASK_SAMPLE0 147 +#define ADC_TASK_SAMPLE1 148 +#define ADC_TASK_START0 149 +#define ADC_TASK_STOP0 150 +#define REGDMA_TASK_START0 151 +#define REGDMA_TASK_START1 152 +#define REGDMA_TASK_START2 153 +#define REGDMA_TASK_START3 154 +#define TMPSNSR_TASK_START_SAMPLE 155 +#define TMPSNSR_TASK_STOP_SAMPLE 156 +#define I2S0_TASK_START_RX 157 +#define I2S0_TASK_START_TX 158 +#define I2S0_TASK_STOP_RX 159 +#define I2S0_TASK_STOP_TX 160 +#define I2S0_TASK_SYNC_CHECK 161 +#define ULP_TASK_WAKEUP_CPU 162 +#define ULP_TASK_INT_CPU 163 +#define RTC_TASK_START 164 +#define RTC_TASK_STOP 165 +#define RTC_TASK_CLR 166 +#define RTC_TASK_TRIGGERFLW 167 +#define GDMA_TASK_IN_START_CH0 168 +#define GDMA_TASK_IN_START_CH1 169 +#define GDMA_TASK_IN_START_CH2 170 +#define GDMA_TASK_IN_START_CH3 171 +#define GDMA_TASK_IN_START_CH4 172 +#define GDMA_TASK_OUT_START_CH0 173 +#define GDMA_TASK_OUT_START_CH1 174 +#define GDMA_TASK_OUT_START_CH2 175 +#define GDMA_TASK_OUT_START_CH3 176 +#define GDMA_TASK_OUT_START_CH4 177 +#define PMU_TASK_SLEEP_REQ 178 +#define MODEM_TASK_G0 179 +#define MODEM_TASK_G1 180 +#define MODEM_TASK_G2 181 +#define MODEM_TASK_G3 182 +#define ZERO_DET_TASK_START 183 diff --git a/components/soc/esp32h4/interrupts.c b/components/soc/esp32h4/interrupts.c index e69de29bb2..5acc172a83 100644 --- a/components/soc/esp32h4/interrupts.c +++ b/components/soc/esp32h4/interrupts.c @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "WIFI_MAC", + [1] = "WIFI_MAC_NMI", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "LP_TIMER", + [8] = "COEX", + [9] = "BLE_TIMER", + [10] = "BLE_SEC", + [11] = "I2C_MST", + [12] = "ZB_MAC", + [13] = "MODEM_APB_TIMEOUT", + [14] = "BT_MAC_INT1", + [15] = "PMU", + [16] = "EFUSE", + [17] = "LP_RTC_TIMER", + [18] = "LP_RTC_BLE_TIMER", + [19] = "LP_WDT", + [20] = "TOUCH", + [21] = "HUK", + [22] = "CPU_FROM_CPU_0", + [23] = "CPU_FROM_CPU_1", + [24] = "CPU_FROM_CPU_2", + [25] = "CPU_FROM_CPU_3", + [26] = "BUS_MONITOR", + [27] = "CORE0_TRACE", + [28] = "CORE1_TRACE", + [29] = "CACHE", + [30] = "CPU_PERI_TIMEOUT", + [31] = "GPIO_INTERRUPT_PRO", + [32] = "GPIO_INTERRUPT_2", + [33] = "PAU", + [34] = "HP_PERI_TIMEOUT", + [35] = "HP_APM_M0", + [36] = "HP_APM_M1", + [37] = "HP_APM_M2", + [38] = "HP_APM_M3", + [39] = "HP_APM_M4", + [40] = "CPU_APM_M0", + [41] = "CPU_APM_M1", + [42] = "CPU_APM_M2", + [43] = "CPU_APM_M3", + [44] = "MSPI", + [45] = "I2S", + [46] = "UHCI0", + [47] = "UART0", + [48] = "UART1", + [49] = "LEDC", + [50] = "TWAI0", + [51] = "TWAI0_TIMER", + [52] = "USB_SERIAL_JTAG", + [53] = "RMT", + [54] = "I2C_EXT0", + [55] = "I2C_EXT1", + [56] = "TG0_T0", + [57] = "TG0_WDT", + [58] = "TG1_T0", + [59] = "TG1_WDT", + [60] = "SYSTIMER_TARGET0", + [61] = "SYSTIMER_TARGET1", + [62] = "SYSTIMER_TARGET2", + [63] = "APB_ADC", + [64] = "PWM0", + [65] = "PWM1", + [66] = "PCNT", + [67] = "PARL_IO_TX", + [68] = "PARL_IO_RX", + [69] = "USB_OTG11", + [70] = "ASRC_CHNL0", + [71] = "ASRC_CHNL1", + [72] = "ZERO_DET", + [73] = "DMA_IN_CH0", + [74] = "DMA_IN_CH1", + [75] = "DMA_IN_CH2", + [76] = "DMA_IN_CH3", + [77] = "DMA_IN_CH4", + [78] = "DMA_OUT_CH0", + [79] = "DMA_OUT_CH1", + [80] = "DMA_OUT_CH2", + [81] = "DMA_OUT_CH3", + [82] = "DMA_OUT_CH4", + [83] = "GPSPI2", + [84] = "GPSPI3", + [85] = "AES", + [86] = "SHA", + [87] = "ECC", + [88] = "ECDSA", + [89] = "KM", +}; diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld new file mode 100644 index 0000000000..62c9e1bb44 --- /dev/null +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( TRACE0 = 0x60000000 ); +PROVIDE ( TRACE1 = 0x60001000 ); +PROVIDE ( ASSIST_DEBUG = 0x60002000 ); +PROVIDE ( INTPRI = 0x60005000 ); +PROVIDE ( CACHE = 0x60008000 ); +PROVIDE ( GPSPI2 = 0x60010000 ); +PROVIDE ( GPSPI3 = 0x60011000 ); +PROVIDE ( UART0 = 0x60012000 ); +PROVIDE ( UART1 = 0x60013000 ); +PROVIDE ( UHCI0 = 0x60014000 ); +PROVIDE ( I2C0 = 0x60015000 ); +PROVIDE ( I2C1 = 0x60016000 ); +PROVIDE ( I2S0 = 0x60017000 ); +PROVIDE ( PARL_IO = 0x60018000 ); +PROVIDE ( MCPWM0 = 0x60019000 ); +PROVIDE ( MCPWM1 = 0x6001A000 ); +PROVIDE ( LEDC = 0x6001B000 ); +PROVIDE ( TWAI0 = 0x6001C000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 ); +PROVIDE ( RMT = 0x6001E000 ); +PROVIDE ( GDMA = 0x6001F000 ); +PROVIDE ( PAU = 0x60020000 ); +PROVIDE ( SOC_ETM = 0x60021000 ); +PROVIDE ( ADC = 0x60022000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); +PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */ +PROVIDE ( MEM_MONITOR = 0x60025000 ); +PROVIDE ( PVT = 0x60026000 ); +PROVIDE ( PCNT = 0x60027000 ); +PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 ); +PROVIDE ( ZERO_DET = 0x60029000 ); +PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 ); +PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 ); +PROVIDE ( USB_OTG_FS_PHY = 0x60080000 ); +PROVIDE ( TIMERG0 = 0x60090000 ); +PROVIDE ( TIMERG1 = 0x60091000 ); +PROVIDE ( IO_MUX = 0x60092000 ); +PROVIDE ( GPIO = 0x60093000 ); +PROVIDE ( GPIO_EXT = 0x60093E00 ); +PROVIDE ( PCR = 0x60094000 ); +PROVIDE ( SPIMEM0 = 0x60098000 ); +PROVIDE ( SPIMEM1 = 0x60099000 ); +PROVIDE ( INTMTX0 = 0x6009A000 ); +PROVIDE ( INTMTX1 = 0x6009B000 ); +PROVIDE ( HP_SYSTEM = 0x6009C000 ); +PROVIDE ( HP_APM = 0x6009D000 ); +PROVIDE ( CPU_APM_REG = 0x6009E000 ); +PROVIDE ( TEE = 0x6009F000 ); +PROVIDE ( KEYMNG = 0x600A5000 ); +PROVIDE ( AES = 0x600A6000 ); +PROVIDE ( SHA = 0x600A7000 ); +PROVIDE ( ECC = 0x600A8000 ); +PROVIDE ( HMAC = 0x600A9000 ); +PROVIDE ( ECDSA = 0x600AA000 ); +PROVIDE ( HUK = 0x600B1000 ); +PROVIDE ( LP_TEE = 0x600B1400 ); +PROVIDE ( EFUSE = 0x600B1800 ); +PROVIDE ( OTP_DEBUG = 0x600B1C00 ); +PROVIDE ( TRNG = 0x600B2000 ); +PROVIDE ( PMU = 0x600B2400 ); +PROVIDE ( LP_AON = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_CLKRST = 0x600B3000 ); +PROVIDE ( LPPERI = 0x600B3400 ); +PROVIDE ( LP_IO_MUX = 0x600B3800 ); +PROVIDE ( LP_GPIO = 0x600B3C00 ); +PROVIDE ( LP_TIMER = 0x600B5000 ); +PROVIDE ( LP_WDT = 0x600B5400 ); +PROVIDE ( TOUCH_SENS = 0x600B5800 ); +PROVIDE ( TOUCH_AON = 0x600B5C00 ); + +PROVIDE ( LP_UART = 0x600B1400 ); /* TODO: IDF-12445 [ESP32H4] inherit from verify code, need remove */ diff --git a/components/soc/esp32h4/register/soc/aes_reg.h b/components/soc/esp32h4/register/soc/aes_reg.h new file mode 100644 index 0000000000..5d8b0b9a53 --- /dev/null +++ b/components/soc/esp32h4/register/soc/aes_reg.h @@ -0,0 +1,462 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AES_KEY_0_REG register + * AES key data register 0 + */ +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_1_REG register + * AES key data register 1 + */ +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_2_REG register + * AES key data register 2 + */ +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_3_REG register + * AES key data register 3 + */ +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_4_REG register + * AES key data register 4 + */ +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_5_REG register + * AES key data register 5 + */ +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_6_REG register + * AES key data register 6 + */ +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_7_REG register + * AES key data register 7 + */ +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_TEXT_IN_0_REG register + * Source text data register 0 + */ +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_1_REG register + * Source text data register 1 + */ +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_2_REG register + * Source text data register 2 + */ +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_3_REG register + * Source text data register 3 + */ +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_OUT_0_REG register + * Result text data register 0 + */ +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_1_REG register + * Result text data register 1 + */ +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_2_REG register + * Result text data register 2 + */ +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_3_REG register + * Result text data register 3 + */ +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_MODE_REG register + * Defines key length and encryption / decryption + */ +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) +/** AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Configures the key length and encryption / decryption of the AES accelerator. + * 0: AES-128 encryption + * 1: AES-192 encryption + * 2: AES-256 encryption + * 3: Reserved + * 4: AES-128 decryption + * 5: AES-192 decryption + * 6: AES-256 decryption + * 7: Reserved + */ +#define AES_MODE 0x00000007U +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007U +#define AES_MODE_S 0 + +/** AES_TRIGGER_REG register + * Operation start controlling register + */ +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) +/** AES_TRIGGER : WT; bitpos: [0]; default: 0; + * Configures whether or not to start AES operation. + * 0: No effect + * 1: Start + */ +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001U +#define AES_TRIGGER_S 0 + +/** AES_STATE_REG register + * Operation status register + */ +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) +/** AES_STATE : RO; bitpos: [1:0]; default: 0; + * Represents the working status of the AES accelerator. + * In Typical AES working mode: + * 0: IDLE + * 1: WORK + * 2: No effect + * 3: No effect + * In DMA-AES working mode: + * 0: IDLE + * 1: WORK + * 2: DONE + * 3: No effect + */ +#define AES_STATE 0x00000003U +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003U +#define AES_STATE_S 0 + +/** AES_IV_MEM register + * The memory that stores initialization vector + */ +#define AES_IV_MEM (DR_REG_AES_BASE + 0x50) +#define AES_IV_MEM_SIZE_BYTES 16 + +/** AES_H_MEM register + * The memory that stores GCM hash subkey + */ +#define AES_H_MEM (DR_REG_AES_BASE + 0x60) +#define AES_H_MEM_SIZE_BYTES 16 + +/** AES_J0_MEM register + * The memory that stores J0 + */ +#define AES_J0_MEM (DR_REG_AES_BASE + 0x70) +#define AES_J0_MEM_SIZE_BYTES 16 + +/** AES_T0_MEM register + * The memory that stores T0 + */ +#define AES_T0_MEM (DR_REG_AES_BASE + 0x80) +#define AES_T0_MEM_SIZE_BYTES 16 + +/** AES_DMA_ENABLE_REG register + * Selects the working mode of the AES accelerator + */ +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) +/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Configures the working mode of the AES accelerator. + * 0: Typical AES + * 1: DMA-AES + */ +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001U +#define AES_DMA_ENABLE_S 0 + +/** AES_BLOCK_MODE_REG register + * Defines the block cipher mode + */ +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) +/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Configures the block cipher mode of the AES accelerator operating under the DMA-AES + * working mode. + * 0: ECB (Electronic Code Block) + * 1: CBC (Cipher Block Chaining) + * 2: OFB (Output FeedBack) + * 3: CTR (Counter) + * 4: CFB8 (8-bit Cipher FeedBack) + * 5: CFB128 (128-bit Cipher FeedBack) + * 6: GCM + * 7: Reserved + */ +#define AES_BLOCK_MODE 0x00000007U +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007U +#define AES_BLOCK_MODE_S 0 + +/** AES_BLOCK_NUM_REG register + * Block number configuration register + */ +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) +/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Represents the Block Number of plaintext or ciphertext when the AES accelerator + * operates under the DMA-AES working mode. For details, see Section . " + */ +#define AES_BLOCK_NUM 0xFFFFFFFFU +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_BLOCK_NUM_S 0 + +/** AES_INC_SEL_REG register + * Standard incrementing function register + */ +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) +/** AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Configures the Standard Incrementing Function for CTR block operation. + * 0: INC_32 + * 1: INC_128 + */ +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001U +#define AES_INC_SEL_S 0 + +/** AES_INT_CLEAR_REG register + * DMA-AES interrupt clear register + */ +#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) +/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear AES interrupt. + * 0: No effect + * 1: Clear + */ +#define AES_INT_CLEAR (BIT(0)) +#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) +#define AES_INT_CLEAR_V 0x00000001U +#define AES_INT_CLEAR_S 0 + +/** AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) +/** AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable AES interrupt. + * 0: Disable + * 1: Enable + */ +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001U +#define AES_INT_ENA_S 0 + +/** AES_DATE_REG register + * AES version control register + */ +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) +/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000; + * This bits stores the version information of AES. + */ +#define AES_DATE 0x0FFFFFFFU +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x0FFFFFFFU +#define AES_DATE_S 0 + +/** AES_DMA_EXIT_REG register + * Operation exit controlling register + */ +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) +/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; + * Configures whether or not to exit AES operation. + * 0: No effect + * 1: Exit + * Only valid for DMA-AES operation. + */ +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001U +#define AES_DMA_EXIT_S 0 + +/** AES_RX_RESET_REG register + * AES-DMA reset rx-fifo register + */ +#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0) +/** AES_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset rx_fifo under dma_aes working mode. + */ +#define AES_RX_RESET (BIT(0)) +#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S) +#define AES_RX_RESET_V 0x00000001U +#define AES_RX_RESET_S 0 + +/** AES_TX_RESET_REG register + * AES-DMA reset tx-fifo register + */ +#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4) +/** AES_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset tx_fifo under dma_aes working mode. + */ +#define AES_TX_RESET (BIT(0)) +#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S) +#define AES_TX_RESET_V 0x00000001U +#define AES_TX_RESET_S 0 + +/** AES_PSEUDO_REG register + * AES PSEUDO function configure register + */ +#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0) +/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0; + * This bit decides whether the pseudo round function is enable or not. + */ +#define AES_PSEUDO_EN (BIT(0)) +#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S) +#define AES_PSEUDO_EN_V 0x00000001U +#define AES_PSEUDO_EN_S 0 +/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2; + * Those bits decides the basic number of pseudo round number. + */ +#define AES_PSEUDO_BASE 0x0000000FU +#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S) +#define AES_PSEUDO_BASE_V 0x0000000FU +#define AES_PSEUDO_BASE_S 1 +/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2; + * Those bits decides the increment number of pseudo round number + */ +#define AES_PSEUDO_INC 0x00000003U +#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S) +#define AES_PSEUDO_INC_V 0x00000003U +#define AES_PSEUDO_INC_S 5 +/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7; + * Those bits decides the update frequency of the pseudo-key. + */ +#define AES_PSEUDO_RNG_CNT 0x00000007U +#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S) +#define AES_PSEUDO_RNG_CNT_V 0x00000007U +#define AES_PSEUDO_RNG_CNT_S 7 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/aes_struct.h b/components/soc/esp32h4/register/soc/aes_struct.h new file mode 100644 index 0000000000..3065c238f2 --- /dev/null +++ b/components/soc/esp32h4/register/soc/aes_struct.h @@ -0,0 +1,354 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Key Registers */ +/** Type of key_n register + * AES key data register n + */ +typedef union { + struct { + /** key_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ + uint32_t key_0:32; + }; + uint32_t val; +} aes_key_n_reg_t; + + +/** Group: TEXT_IN Registers */ +/** Type of text_in_n register + * Source text data register n + */ +typedef union { + struct { + /** text_in_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ + uint32_t text_in_0:32; + }; + uint32_t val; +} aes_text_in_n_reg_t; + + +/** Group: TEXT_OUT Registers */ +/** Type of text_out_n register + * Result text data register n + */ +typedef union { + struct { + /** text_out_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ + uint32_t text_out_0:32; + }; + uint32_t val; +} aes_text_out_n_reg_t; + + +/** Group: Control / Configuration Registers */ +/** Type of mode register + * Defines key length and encryption / decryption + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Configures the key length and encryption / decryption of the AES accelerator. + * 0: AES-128 encryption + * 1: AES-192 encryption + * 2: AES-256 encryption + * 3: Reserved + * 4: AES-128 decryption + * 5: AES-192 decryption + * 6: AES-256 decryption + * 7: Reserved + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_mode_reg_t; + +/** Type of trigger register + * Operation start controlling register + */ +typedef union { + struct { + /** trigger : WT; bitpos: [0]; default: 0; + * Configures whether or not to start AES operation. + * 0: No effect + * 1: Start + */ + uint32_t trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_trigger_reg_t; + +/** Type of dma_enable register + * Selects the working mode of the AES accelerator + */ +typedef union { + struct { + /** dma_enable : R/W; bitpos: [0]; default: 0; + * Configures the working mode of the AES accelerator. + * 0: Typical AES + * 1: DMA-AES + */ + uint32_t dma_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_enable_reg_t; + +/** Type of block_mode register + * Defines the block cipher mode + */ +typedef union { + struct { + /** block_mode : R/W; bitpos: [2:0]; default: 0; + * Configures the block cipher mode of the AES accelerator operating under the DMA-AES + * working mode. + * 0: ECB (Electronic Code Block) + * 1: CBC (Cipher Block Chaining) + * 2: OFB (Output FeedBack) + * 3: CTR (Counter) + * 4: CFB8 (8-bit Cipher FeedBack) + * 5: CFB128 (128-bit Cipher FeedBack) + * 6: GCM + * 7: Reserved + */ + uint32_t block_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_block_mode_reg_t; + +/** Type of block_num register + * Block number configuration register + */ +typedef union { + struct { + /** block_num : R/W; bitpos: [31:0]; default: 0; + * Represents the Block Number of plaintext or ciphertext when the AES accelerator + * operates under the DMA-AES working mode. For details, see Section . " + */ + uint32_t block_num:32; + }; + uint32_t val; +} aes_block_num_reg_t; + +/** Type of inc_sel register + * Standard incrementing function register + */ +typedef union { + struct { + /** inc_sel : R/W; bitpos: [0]; default: 0; + * Configures the Standard Incrementing Function for CTR block operation. + * 0: INC_32 + * 1: INC_128 + */ + uint32_t inc_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_inc_sel_reg_t; + +/** Type of dma_exit register + * Operation exit controlling register + */ +typedef union { + struct { + /** dma_exit : WT; bitpos: [0]; default: 0; + * Configures whether or not to exit AES operation. + * 0: No effect + * 1: Exit + * Only valid for DMA-AES operation. + */ + uint32_t dma_exit:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_exit_reg_t; + +/** Type of rx_reset register + * AES-DMA reset rx-fifo register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset rx_fifo under dma_aes working mode. + */ + uint32_t rx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_rx_reset_reg_t; + +/** Type of tx_reset register + * AES-DMA reset tx-fifo register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset tx_fifo under dma_aes working mode. + */ + uint32_t tx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_tx_reset_reg_t; + + +/** Group: Configuration register */ +/** Type of pseudo register + * AES PSEUDO function configure register + */ +typedef union { + struct { + /** pseudo_en : R/W; bitpos: [0]; default: 0; + * This bit decides whether the pseudo round function is enable or not. + */ + uint32_t pseudo_en:1; + /** pseudo_base : R/W; bitpos: [4:1]; default: 2; + * Those bits decides the basic number of pseudo round number. + */ + uint32_t pseudo_base:4; + /** pseudo_inc : R/W; bitpos: [6:5]; default: 2; + * Those bits decides the increment number of pseudo round number + */ + uint32_t pseudo_inc:2; + /** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7; + * Those bits decides the update frequency of the pseudo-key. + */ + uint32_t pseudo_rng_cnt:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} aes_pseudo_reg_t; + + +/** Group: Status Register */ +/** Type of state register + * Operation status register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * Represents the working status of the AES accelerator. + * In Typical AES working mode: + * 0: IDLE + * 1: WORK + * 2: No effect + * 3: No effect + * In DMA-AES working mode: + * 0: IDLE + * 1: WORK + * 2: DONE + * 3: No effect + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} aes_state_reg_t; + + +/** Group: memory type */ + +/** Group: Interrupt Registers */ +/** Type of int_clear register + * DMA-AES interrupt clear register + */ +typedef union { + struct { + /** int_clear : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear AES interrupt. + * 0: No effect + * 1: Clear + */ + uint32_t int_clear:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_clear_reg_t; + +/** Type of int_ena register + * DMA-AES interrupt enable register + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable AES interrupt. + * 0: Disable + * 1: Enable + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_ena_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * AES version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36774000; + * This bits stores the version information of AES. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} aes_date_reg_t; + + +typedef struct { + volatile aes_key_n_reg_t key_n[8]; + volatile aes_text_in_n_reg_t text_in_n[4]; + volatile aes_text_out_n_reg_t text_out_n[4]; + volatile aes_mode_reg_t mode; + uint32_t reserved_044; + volatile aes_trigger_reg_t trigger; + volatile aes_state_reg_t state; + volatile uint32_t iv[4]; + volatile uint32_t h[4]; + volatile uint32_t j0[4]; + volatile uint32_t t0[4]; + volatile aes_dma_enable_reg_t dma_enable; + volatile aes_block_mode_reg_t block_mode; + volatile aes_block_num_reg_t block_num; + volatile aes_inc_sel_reg_t inc_sel; + uint32_t reserved_0a0[3]; + volatile aes_int_clear_reg_t int_clear; + volatile aes_int_ena_reg_t int_ena; + volatile aes_date_reg_t date; + volatile aes_dma_exit_reg_t dma_exit; + uint32_t reserved_0bc; + volatile aes_rx_reset_reg_t rx_reset; + volatile aes_tx_reset_reg_t tx_reset; + uint32_t reserved_0c8[2]; + volatile aes_pseudo_reg_t pseudo; +} aes_dev_t; + +extern aes_dev_t AES; + +#ifndef __cplusplus +_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/ecc_mult_reg.h b/components/soc/esp32h4/register/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..7be529b9af --- /dev/null +++ b/components/soc/esp32h4/register/soc/ecc_mult_reg.h @@ -0,0 +1,210 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC raw interrupt status register + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC masked interrupt status register + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configuration register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to start calculation of ECC Accelerator. This bit will be + * self-cleared after the calculation is done. + * 0: No effect + * 1: Start calculation of ECC Accelerator + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Configures whether to reset ECC Accelerator. + * 0: No effect + * 1: Reset + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. + * 0: P-192 + * 1: P-256 + * 2: P-384 + * 3: SM2. + */ +#define ECC_MULT_KEY_LENGTH 0x00000003U +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000003U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. + * 0: n(order of curve) + * 1: p(mod base of curve) + */ +#define ECC_MULT_MOD_BASE (BIT(4)) +#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) +#define ECC_MULT_MOD_BASE_V 0x00000001U +#define ECC_MULT_MOD_BASE_S 4 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0; + * Configures the work mode of ECC Accelerator. + * 0: Point Multi mode + * 1: Reserved + * 2: Point Verif mode + * 3: Point Verif + Multi mode + * 4: Jacobian Point Multi mode + * 5: Reserved + * 6: Jacobian Point Verif mode + * 7: Point Verif + Jacobian Point Multi mode + * 8: Mod Add mode + * 9. Mod Sub mode + * 10: Mod Multi mode + * 11: Mod Div mode + */ +#define ECC_MULT_WORK_MODE 0x0000000FU +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x0000000FU +#define ECC_MULT_WORK_MODE_S 5 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0; + * Configures the security mode of ECC Accelerator. + * 0: no secure function enabled. + * 1: enable constant-time calculation in all point multiplication modes. + */ +#define ECC_MULT_SECURITY_MODE (BIT(9)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 9 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; + * Represents the verification result of ECC Accelerator, valid only when calculation + * is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(29)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 29 +/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; + * Configures whether to force on register clock gate. + * 0: No effect + * 1: Force on + */ +#define ECC_MULT_CLK_EN (BIT(30)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 30 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0; + * Configures whether to force on ECC memory clock gate. + * 0: No effect + * 1: Force on + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 48 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_BASE + 0x130) +#define ECC_MULT_PX_MEM_SIZE_BYTES 48 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_BASE + 0x160) +#define ECC_MULT_PY_MEM_SIZE_BYTES 48 + +/** ECC_MULT_QX_MEM register + * The memory that stores Qx. + */ +#define ECC_MULT_QX_MEM (DR_REG_ECC_BASE + 0x190) +#define ECC_MULT_QX_MEM_SIZE_BYTES 48 + +/** ECC_MULT_QY_MEM register + * The memory that stores Qy. + */ +#define ECC_MULT_QY_MEM (DR_REG_ECC_BASE + 0x1c0) +#define ECC_MULT_QY_MEM_SIZE_BYTES 48 + +/** ECC_MULT_QZ_MEM register + * The memory that stores Qz. + */ +#define ECC_MULT_QZ_MEM (DR_REG_ECC_BASE + 0x1f0) +#define ECC_MULT_QZ_MEM_SIZE_BYTES 48 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/ecc_mult_struct.h b/components/soc/esp32h4/register/soc/ecc_mult_struct.h new file mode 100644 index 0000000000..1aeb47caa8 --- /dev/null +++ b/components/soc/esp32h4/register/soc/ecc_mult_struct.h @@ -0,0 +1,192 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of mult_int_raw register + * ECC raw interrupt status register + */ +typedef union { + struct { + /** mult_calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of the ECC_CALC_DONE_INT interrupt. + */ + uint32_t mult_calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of mult_int_st register + * ECC masked interrupt status register + */ +typedef union { + struct { + /** mult_calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of the ECC_CALC_DONE_INT interrupt. + */ + uint32_t mult_calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of mult_int_ena register + * ECC interrupt enable register + */ +typedef union { + struct { + /** mult_calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the ECC_CALC_DONE_INT interrupt. + */ + uint32_t mult_calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of mult_int_clr register + * ECC interrupt clear register + */ +typedef union { + struct { + /** mult_calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear the ECC_CALC_DONE_INT interrupt. + */ + uint32_t mult_calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of mult_conf register + * ECC configuration register + */ +typedef union { + struct { + /** mult_start : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to start calculation of ECC Accelerator. This bit will be + * self-cleared after the calculation is done. + * 0: No effect + * 1: Start calculation of ECC Accelerator + */ + uint32_t mult_start:1; + /** mult_reset : WT; bitpos: [1]; default: 0; + * Configures whether to reset ECC Accelerator. + * 0: No effect + * 1: Reset + */ + uint32_t mult_reset:1; + /** mult_key_length : R/W; bitpos: [3:2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. + * 0: P-192 + * 1: P-256 + * 2: P-384 + * 3: SM2. + */ + uint32_t mult_key_length:2; + /** mult_mod_base : R/W; bitpos: [4]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. + * 0: n(order of curve) + * 1: p(mod base of curve) + */ + uint32_t mult_mod_base:1; + /** mult_work_mode : R/W; bitpos: [8:5]; default: 0; + * Configures the work mode of ECC Accelerator. + * 0: Point Multi mode + * 1: Reserved + * 2: Point Verif mode + * 3: Point Verif + Multi mode + * 4: Jacobian Point Multi mode + * 5: Reserved + * 6: Jacobian Point Verif mode + * 7: Point Verif + Jacobian Point Multi mode + * 8: Mod Add mode + * 9. Mod Sub mode + * 10: Mod Multi mode + * 11: Mod Div mode + */ + uint32_t mult_work_mode:4; + /** mult_security_mode : R/W; bitpos: [9]; default: 0; + * Configures the security mode of ECC Accelerator. + * 0: no secure function enabled. + * 1: enable constant-time calculation in all point multiplication modes. + */ + uint32_t mult_security_mode:1; + uint32_t reserved_10:19; + /** mult_verification_result : RO/SS; bitpos: [29]; default: 0; + * Represents the verification result of ECC Accelerator, valid only when calculation + * is done. + */ + uint32_t mult_verification_result:1; + /** mult_clk_en : R/W; bitpos: [30]; default: 0; + * Configures whether to force on register clock gate. + * 0: No effect + * 1: Force on + */ + uint32_t mult_clk_en:1; + /** mult_mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0; + * Configures whether to force on ECC memory clock gate. + * 0: No effect + * 1: Force on + */ + uint32_t mult_mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of mult_date register + * Version control register + */ +typedef union { + struct { + /** mult_date : R/W; bitpos: [27:0]; default: 37781792; + * ECC mult version control register + */ + uint32_t mult_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t mult_int_raw; + volatile ecc_mult_int_st_reg_t mult_int_st; + volatile ecc_mult_int_ena_reg_t mult_int_ena; + volatile ecc_mult_int_clr_reg_t mult_int_clr; + volatile ecc_mult_conf_reg_t mult_conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t mult_date; + volatile uint32_t mult_k[12]; + volatile uint32_t mult_px[12]; + volatile uint32_t mult_py[12]; + volatile uint32_t mult_qx[12]; + volatile uint32_t mult_qy[12]; + volatile uint32_t mult_qz[12]; +} ecc_dev_t; + +extern ecc_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_dev_t) == 0x220, "Invalid size of ecc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/ecdsa_reg.h b/components/soc/esp32h4/register/soc/ecdsa_reg.h new file mode 100644 index 0000000000..401786a165 --- /dev/null +++ b/components/soc/esp32h4/register/soc/ecdsa_reg.h @@ -0,0 +1,360 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ +#define ECDSA_WORK_MODE 0x00000003U +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000003U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. + */ +#define ECDSA_ECC_CURVE 0x00000003U +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000003U +#define ECDSA_ECC_CURVE_S 2 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(4)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 4 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(5)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 5 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ +#define ECDSA_DETERMINISTIC_K (BIT(6)) +#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) +#define ECDSA_DETERMINISTIC_K_V 0x00000001U +#define ECDSA_DETERMINISTIC_K_S 6 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) +#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) +#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PREP_DONE_INT_RAW_S 0 +/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) +#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) +#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PROC_DONE_INT_RAW_S 1 +/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_RAW (BIT(2)) +#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) +#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U +#define ECDSA_POST_DONE_INT_RAW_S 2 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 3 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ST (BIT(0)) +#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) +#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ST_S 0 +/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ST (BIT(1)) +#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) +#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ST_S 1 +/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ST (BIT(2)) +#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) +#define ECDSA_POST_DONE_INT_ST_V 0x00000001U +#define ECDSA_POST_DONE_INT_ST_S 2 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 3 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) +#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) +#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ENA_S 0 +/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) +#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) +#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ENA_S 1 +/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ENA (BIT(2)) +#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) +#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U +#define ECDSA_POST_DONE_INT_ENA_S 2 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 3 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) +#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) +#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PREP_DONE_INT_CLR_S 0 +/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) +#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) +#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PROC_DONE_INT_CLR_S 1 +/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_CLR (BIT(2)) +#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) +#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U +#define ECDSA_POST_DONE_INT_CLR_S 2 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 3 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. + */ +#define ECDSA_SHA_MODE 0x0000000FU +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x0000000FU +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) +#define ECDSA_R_MEM_SIZE_BYTES 48 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) +#define ECDSA_S_MEM_SIZE_BYTES 48 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) +#define ECDSA_Z_MEM_SIZE_BYTES 48 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) +#define ECDSA_QAX_MEM_SIZE_BYTES 48 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) +#define ECDSA_QAY_MEM_SIZE_BYTES 48 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/ecdsa_struct.h b/components/soc/esp32h4/register/soc/ecdsa_struct.h new file mode 100644 index 0000000000..6659f30a90 --- /dev/null +++ b/components/soc/esp32h4/register/soc/ecdsa_struct.h @@ -0,0 +1,348 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ + uint32_t work_mode:2; + /** ecc_curve : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. + */ + uint32_t ecc_curve:2; + /** software_set_k : R/W; bitpos: [4]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [5]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + /** deterministic_k : R/W; bitpos: [6]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ + uint32_t deterministic_k:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. + */ + uint32_t sha_mode:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37785984; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[16]; + uint32_t reserved_2c0[72]; + volatile uint32_t r[12]; + volatile uint32_t s[12]; + volatile uint32_t z[12]; + volatile uint32_t qax[12]; + volatile uint32_t qay[12]; +} ecdsa_dev_t; + +extern ecdsa_dev_t ECDSA; + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/hmac_reg.h b/components/soc/esp32h4/register/soc/hmac_reg.h new file mode 100644 index 0000000000..bba02c8bb6 --- /dev/null +++ b/components/soc/esp32h4/register/soc/hmac_reg.h @@ -0,0 +1,282 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HMAC_SET_START_REG register + * HMAC start control register + */ +#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40) +/** HMAC_SET_START : WS; bitpos: [0]; default: 0; + * Configures whether or not to enable HMAC. + * + * 0: Disable HMAC + * + * 1: Enable HMAC + */ +#define HMAC_SET_START (BIT(0)) +#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S) +#define HMAC_SET_START_V 0x00000001U +#define HMAC_SET_START_S 0 + +/** HMAC_SET_PARA_PURPOSE_REG register + * HMAC parameter configuration register + */ +#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44) +/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0; + * Configures the HMAC purpose, refer to the Table . " + */ +#define HMAC_PURPOSE_SET 0x0000000FU +#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S) +#define HMAC_PURPOSE_SET_V 0x0000000FU +#define HMAC_PURPOSE_SET_S 0 + +/** HMAC_SET_PARA_KEY_REG register + * HMAC parameters configuration register + */ +#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48) +/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0; + * Configures HMAC key. There are six keys with index 0~5. Write the index of the + * selected key to this field. + */ +#define HMAC_KEY_SET 0x00000007U +#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S) +#define HMAC_KEY_SET_V 0x00000007U +#define HMAC_KEY_SET_S 0 + +/** HMAC_SET_PARA_FINISH_REG register + * HMAC configuration completion register + */ +#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c) +/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0; + * Configures whether to finish HMAC configuration. + * + * 0: No effect + * + * 1: Finish configuration + */ +#define HMAC_SET_PARA_END (BIT(0)) +#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S) +#define HMAC_SET_PARA_END_V 0x00000001U +#define HMAC_SET_PARA_END_S 0 + +/** HMAC_SET_MESSAGE_ONE_REG register + * HMAC message control register + */ +#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50) +/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0; + * Calls SHA to calculate one message block. + */ +#define HMAC_SET_TEXT_ONE (BIT(0)) +#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S) +#define HMAC_SET_TEXT_ONE_V 0x00000001U +#define HMAC_SET_TEXT_ONE_S 0 + +/** HMAC_SET_MESSAGE_ING_REG register + * HMAC message continue register + */ +#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54) +/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0; + * Configures whether or not there are unprocessed message blocks. + * + * 0: No unprocessed message block + * + * 1: There are still some message blocks to be processed. + */ +#define HMAC_SET_TEXT_ING (BIT(0)) +#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S) +#define HMAC_SET_TEXT_ING_V 0x00000001U +#define HMAC_SET_TEXT_ING_S 0 + +/** HMAC_SET_MESSAGE_END_REG register + * HMAC message end register + */ +#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58) +/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0; + * Configures whether to start hardware padding. + * + * 0: No effect + * + * 1: Start hardware padding + */ +#define HMAC_SET_TEXT_END (BIT(0)) +#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S) +#define HMAC_SET_TEXT_END_V 0x00000001U +#define HMAC_SET_TEXT_END_S 0 + +/** HMAC_SET_RESULT_FINISH_REG register + * HMAC result reading finish register + */ +#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c) +/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0; + * Configures whether to exit upstream mode and clear calculation results. + * + * 0: Not exit + * + * 1: Exit upstream mode and clear calculation results. + */ +#define HMAC_SET_RESULT_END (BIT(0)) +#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S) +#define HMAC_SET_RESULT_END_V 0x00000001U +#define HMAC_SET_RESULT_END_S 0 + +/** HMAC_SET_INVALIDATE_JTAG_REG register + * Invalidate JTAG result register + */ +#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60) +/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0; + * Configures whether or not to clear calculation results when re-enabling JTAG in + * downstream mode. + * + * 0: Not clear + * + * 1: Clear calculation results + */ +#define HMAC_SET_INVALIDATE_JTAG (BIT(0)) +#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S) +#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U +#define HMAC_SET_INVALIDATE_JTAG_S 0 + +/** HMAC_SET_INVALIDATE_DS_REG register + * Invalidate digital signature result register + */ +#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64) +/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0; + * Configures whether or not to clear calculation results of the DS module in + * downstream mode. + * + * 0: Not clear + * + * 1: Clear calculation results + */ +#define HMAC_SET_INVALIDATE_DS (BIT(0)) +#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S) +#define HMAC_SET_INVALIDATE_DS_V 0x00000001U +#define HMAC_SET_INVALIDATE_DS_S 0 + +/** HMAC_QUERY_ERROR_REG register + * Stores matching results between keys generated by users and corresponding purposes + */ +#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68) +/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0; + * Represents whether or not an HMAC key matches the purpose. + * + * 0: Match + * + * 1: Error + */ +#define HMAC_QUREY_CHECK (BIT(0)) +#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S) +#define HMAC_QUREY_CHECK_V 0x00000001U +#define HMAC_QUREY_CHECK_S 0 + +/** HMAC_QUERY_BUSY_REG register + * Busy state of HMAC module + */ +#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c) +/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Represents whether or not HMAC is in a busy state. Before configuring HMAC, please + * make sure HMAC is in an IDLE state. + * + * 0: Idle + * + * 1: HMAC is still working on the calculation + */ +#define HMAC_BUSY_STATE (BIT(0)) +#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S) +#define HMAC_BUSY_STATE_V 0x00000001U +#define HMAC_BUSY_STATE_S 0 + +/** HMAC_WR_MESSAGE_MEM register + * Message block memory. + */ +#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80) +#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64 + +/** HMAC_RD_RESULT_MEM register + * Result from upstream. + */ +#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0) +#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32 + +/** HMAC_SET_MESSAGE_PAD_REG register + * Software padding register + */ +#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0) +/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0; + * Configures whether or not the padding is applied by software. + * + * 0: Not applied by software + * + * 1: Applied by software + */ +#define HMAC_SET_TEXT_PAD (BIT(0)) +#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S) +#define HMAC_SET_TEXT_PAD_V 0x00000001U +#define HMAC_SET_TEXT_PAD_S 0 + +/** HMAC_ONE_BLOCK_REG register + * One block message register + */ +#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4) +/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0; + * Write 1 to indicate there is only one block which already contains padding bits and + * there is no need for padding. + */ +#define HMAC_SET_ONE_BLOCK (BIT(0)) +#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S) +#define HMAC_SET_ONE_BLOCK_V 0x00000001U +#define HMAC_SET_ONE_BLOCK_S 0 + +/** HMAC_SOFT_JTAG_CTRL_REG register + * Jtag register 0. + */ +#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8) +/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0; + * Configures whether or not to enable JTAG authentication mode. + * + * 0: Disable + * + * 1: Enable + * + */ +#define HMAC_SOFT_JTAG_CTRL (BIT(0)) +#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S) +#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U +#define HMAC_SOFT_JTAG_CTRL_S 0 + +/** HMAC_WR_JTAG_REG register + * Re-enable JTAG register 1 + */ +#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc) +/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0; + * Writes the comparing input used for re-enabling JTAG. + */ +#define HMAC_WR_JTAG 0xFFFFFFFFU +#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S) +#define HMAC_WR_JTAG_V 0xFFFFFFFFU +#define HMAC_WR_JTAG_S 0 + +/** HMAC_DATE_REG register + * Version control register + */ +#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc) +/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977; + * Hmac date information/ hmac version information. + */ +#define HMAC_DATE 0x3FFFFFFFU +#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S) +#define HMAC_DATE_V 0x3FFFFFFFU +#define HMAC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/hmac_struct.h b/components/soc/esp32h4/register/soc/hmac_struct.h new file mode 100644 index 0000000000..9003f4d58f --- /dev/null +++ b/components/soc/esp32h4/register/soc/hmac_struct.h @@ -0,0 +1,344 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control/Status Registers */ +/** Type of set_start register + * HMAC start control register + */ +typedef union { + struct { + /** set_start : WS; bitpos: [0]; default: 0; + * Configures whether or not to enable HMAC. + * + * 0: Disable HMAC + * + * 1: Enable HMAC + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_start_reg_t; + +/** Type of set_para_finish register + * HMAC configuration completion register + */ +typedef union { + struct { + /** set_para_end : WS; bitpos: [0]; default: 0; + * Configures whether to finish HMAC configuration. + * + * 0: No effect + * + * 1: Finish configuration + */ + uint32_t set_para_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_para_finish_reg_t; + +/** Type of set_message_one register + * HMAC message control register + */ +typedef union { + struct { + /** set_text_one : WS; bitpos: [0]; default: 0; + * Calls SHA to calculate one message block. + */ + uint32_t set_text_one:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_one_reg_t; + +/** Type of set_message_ing register + * HMAC message continue register + */ +typedef union { + struct { + /** set_text_ing : WS; bitpos: [0]; default: 0; + * Configures whether or not there are unprocessed message blocks. + * + * 0: No unprocessed message block + * + * 1: There are still some message blocks to be processed. + */ + uint32_t set_text_ing:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_ing_reg_t; + +/** Type of set_message_end register + * HMAC message end register + */ +typedef union { + struct { + /** set_text_end : WS; bitpos: [0]; default: 0; + * Configures whether to start hardware padding. + * + * 0: No effect + * + * 1: Start hardware padding + */ + uint32_t set_text_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_end_reg_t; + +/** Type of set_result_finish register + * HMAC result reading finish register + */ +typedef union { + struct { + /** set_result_end : WS; bitpos: [0]; default: 0; + * Configures whether to exit upstream mode and clear calculation results. + * + * 0: Not exit + * + * 1: Exit upstream mode and clear calculation results. + */ + uint32_t set_result_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_result_finish_reg_t; + +/** Type of set_invalidate_jtag register + * Invalidate JTAG result register + */ +typedef union { + struct { + /** set_invalidate_jtag : WS; bitpos: [0]; default: 0; + * Configures whether or not to clear calculation results when re-enabling JTAG in + * downstream mode. + * + * 0: Not clear + * + * 1: Clear calculation results + */ + uint32_t set_invalidate_jtag:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_jtag_reg_t; + +/** Type of set_invalidate_ds register + * Invalidate digital signature result register + */ +typedef union { + struct { + /** set_invalidate_ds : WS; bitpos: [0]; default: 0; + * Configures whether or not to clear calculation results of the DS module in + * downstream mode. + * + * 0: Not clear + * + * 1: Clear calculation results + */ + uint32_t set_invalidate_ds:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_ds_reg_t; + +/** Type of query_error register + * Stores matching results between keys generated by users and corresponding purposes + */ +typedef union { + struct { + /** qurey_check : RO; bitpos: [0]; default: 0; + * Represents whether or not an HMAC key matches the purpose. + * + * 0: Match + * + * 1: Error + */ + uint32_t qurey_check:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_error_reg_t; + +/** Type of query_busy register + * Busy state of HMAC module + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Represents whether or not HMAC is in a busy state. Before configuring HMAC, please + * make sure HMAC is in an IDLE state. + * + * 0: Idle + * + * 1: HMAC is still working on the calculation + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_busy_reg_t; + +/** Type of set_message_pad register + * Software padding register + */ +typedef union { + struct { + /** set_text_pad : WO; bitpos: [0]; default: 0; + * Configures whether or not the padding is applied by software. + * + * 0: Not applied by software + * + * 1: Applied by software + */ + uint32_t set_text_pad:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_pad_reg_t; + +/** Type of one_block register + * One block message register + */ +typedef union { + struct { + /** set_one_block : WS; bitpos: [0]; default: 0; + * Write 1 to indicate there is only one block which already contains padding bits and + * there is no need for padding. + */ + uint32_t set_one_block:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_one_block_reg_t; + + +/** Group: Configuration Registers */ +/** Type of set_para_purpose register + * HMAC parameter configuration register + */ +typedef union { + struct { + /** purpose_set : WO; bitpos: [3:0]; default: 0; + * Configures the HMAC purpose, refer to the Table . " + */ + uint32_t purpose_set:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} hmac_set_para_purpose_reg_t; + +/** Type of set_para_key register + * HMAC parameters configuration register + */ +typedef union { + struct { + /** key_set : WO; bitpos: [2:0]; default: 0; + * Configures HMAC key. There are six keys with index 0~5. Write the index of the + * selected key to this field. + */ + uint32_t key_set:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} hmac_set_para_key_reg_t; + +/** Type of wr_jtag register + * Re-enable JTAG register 1 + */ +typedef union { + struct { + /** wr_jtag : WO; bitpos: [31:0]; default: 0; + * Writes the comparing input used for re-enabling JTAG. + */ + uint32_t wr_jtag:32; + }; + uint32_t val; +} hmac_wr_jtag_reg_t; + + +/** Group: Memory Type */ + +/** Group: Configuration Register */ +/** Type of soft_jtag_ctrl register + * Jtag register 0. + */ +typedef union { + struct { + /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0; + * Configures whether or not to enable JTAG authentication mode. + * + * 0: Disable + * + * 1: Enable + * + */ + uint32_t soft_jtag_ctrl:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_soft_jtag_ctrl_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 539166977; + * Hmac date information/ hmac version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} hmac_date_reg_t; + + +typedef struct { + uint32_t reserved_000[16]; + volatile hmac_set_start_reg_t set_start; + volatile hmac_set_para_purpose_reg_t set_para_purpose; + volatile hmac_set_para_key_reg_t set_para_key; + volatile hmac_set_para_finish_reg_t set_para_finish; + volatile hmac_set_message_one_reg_t set_message_one; + volatile hmac_set_message_ing_reg_t set_message_ing; + volatile hmac_set_message_end_reg_t set_message_end; + volatile hmac_set_result_finish_reg_t set_result_finish; + volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag; + volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds; + volatile hmac_query_error_reg_t query_error; + volatile hmac_query_busy_reg_t query_busy; + uint32_t reserved_070[4]; + volatile uint32_t wr_message[16]; + volatile uint32_t rd_result[8]; + uint32_t reserved_0e0[4]; + volatile hmac_set_message_pad_reg_t set_message_pad; + volatile hmac_one_block_reg_t one_block; + volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl; + volatile hmac_wr_jtag_reg_t wr_jtag; + uint32_t reserved_100[63]; + volatile hmac_date_reg_t date; +} hmac_dev_t; + +extern hmac_dev_t HMAC; + +#ifndef __cplusplus +_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/huk_reg.h b/components/soc/esp32h4/register/soc/huk_reg.h new file mode 100644 index 0000000000..20c44c4d3d --- /dev/null +++ b/components/soc/esp32h4/register/soc/huk_reg.h @@ -0,0 +1,230 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HUK_CLK_REG register + * HUK Generator clock gate control register + */ +#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4) +/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define HUK_CLK_EN (BIT(0)) +#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S) +#define HUK_CLK_EN_V 0x00000001U +#define HUK_CLK_EN_S 0 +/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define HUK_MEM_CG_FORCE_ON (BIT(1)) +#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S) +#define HUK_MEM_CG_FORCE_ON_V 0x00000001U +#define HUK_MEM_CG_FORCE_ON_S 1 + +/** HUK_INT_RAW_REG register + * HUK Generator interrupt raw register, valid in level. + */ +#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8) +/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_RAW (BIT(0)) +#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S) +#define HUK_PREP_DONE_INT_RAW_V 0x00000001U +#define HUK_PREP_DONE_INT_RAW_S 0 +/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_RAW (BIT(1)) +#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S) +#define HUK_PROC_DONE_INT_RAW_V 0x00000001U +#define HUK_PROC_DONE_INT_RAW_S 1 +/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_RAW (BIT(2)) +#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S) +#define HUK_POST_DONE_INT_RAW_V 0x00000001U +#define HUK_POST_DONE_INT_RAW_S 2 + +/** HUK_INT_ST_REG register + * HUK Generator interrupt status register. + */ +#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc) +/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ST (BIT(0)) +#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S) +#define HUK_PREP_DONE_INT_ST_V 0x00000001U +#define HUK_PREP_DONE_INT_ST_S 0 +/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ST (BIT(1)) +#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S) +#define HUK_PROC_DONE_INT_ST_V 0x00000001U +#define HUK_PROC_DONE_INT_ST_S 1 +/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ST (BIT(2)) +#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S) +#define HUK_POST_DONE_INT_ST_V 0x00000001U +#define HUK_POST_DONE_INT_ST_S 2 + +/** HUK_INT_ENA_REG register + * HUK Generator interrupt enable register. + */ +#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10) +/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ENA (BIT(0)) +#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S) +#define HUK_PREP_DONE_INT_ENA_V 0x00000001U +#define HUK_PREP_DONE_INT_ENA_S 0 +/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ENA (BIT(1)) +#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S) +#define HUK_PROC_DONE_INT_ENA_V 0x00000001U +#define HUK_PROC_DONE_INT_ENA_S 1 +/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ENA (BIT(2)) +#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S) +#define HUK_POST_DONE_INT_ENA_V 0x00000001U +#define HUK_POST_DONE_INT_ENA_S 2 + +/** HUK_INT_CLR_REG register + * HUK Generator interrupt clear register. + */ +#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14) +/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_CLR (BIT(0)) +#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S) +#define HUK_PREP_DONE_INT_CLR_V 0x00000001U +#define HUK_PREP_DONE_INT_CLR_S 0 +/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_CLR (BIT(1)) +#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S) +#define HUK_PROC_DONE_INT_CLR_V 0x00000001U +#define HUK_PROC_DONE_INT_CLR_S 1 +/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_CLR (BIT(2)) +#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S) +#define HUK_POST_DONE_INT_CLR_V 0x00000001U +#define HUK_POST_DONE_INT_CLR_S 2 + +/** HUK_CONF_REG register + * HUK Generator configuration register + */ +#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20) +/** HUK_MODE : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ +#define HUK_MODE (BIT(0)) +#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S) +#define HUK_MODE_V 0x00000001U +#define HUK_MODE_S 0 + +/** HUK_START_REG register + * HUK Generator control register + */ +#define HUK_START_REG (DR_REG_HUK_BASE + 0x24) +/** HUK_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ +#define HUK_START (BIT(0)) +#define HUK_START_M (HUK_START_V << HUK_START_S) +#define HUK_START_V 0x00000001U +#define HUK_START_S 0 +/** HUK_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ +#define HUK_CONTINUE (BIT(1)) +#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S) +#define HUK_CONTINUE_V 0x00000001U +#define HUK_CONTINUE_S 1 + +/** HUK_STATE_REG register + * HUK Generator state register + */ +#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28) +/** HUK_STATE : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define HUK_STATE 0x00000003U +#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S) +#define HUK_STATE_V 0x00000003U +#define HUK_STATE_S 0 + +/** HUK_STATUS_REG register + * HUK Generator HUK status register + */ +#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34) +/** HUK_STATUS : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ +#define HUK_STATUS 0x00000003U +#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S) +#define HUK_STATUS_V 0x00000003U +#define HUK_STATUS_S 0 +/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ +#define HUK_RISK_LEVEL 0x00000007U +#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S) +#define HUK_RISK_LEVEL_V 0x00000007U +#define HUK_RISK_LEVEL_S 2 +/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0; + * The update request of HUK info. 0: User can update HUK info according to the risk + * level. 1: The HUK info is expired, and user need to update it. + */ +#define HUK_UPDATE_REQ (BIT(5)) +#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S) +#define HUK_UPDATE_REQ_V 0x00000001U +#define HUK_UPDATE_REQ_S 5 + +/** HUK_DATE_REG register + * Version control register + */ +#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc) +/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232; + * HUK Generator version control register. + */ +#define HUK_DATE 0x0FFFFFFFU +#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S) +#define HUK_DATE_V 0x0FFFFFFFU +#define HUK_DATE_S 0 + +/** HUK_INFO_MEM register + * The memory that stores HUK info. + */ +#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100) +#define HUK_INFO_MEM_SIZE_BYTES 384 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/huk_struct.h b/components/soc/esp32h4/register/soc/huk_struct.h new file mode 100644 index 0000000000..95d3837f07 --- /dev/null +++ b/components/soc/esp32h4/register/soc/huk_struct.h @@ -0,0 +1,247 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * HUK Generator clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * HUK Generator interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_raw_reg_t; + +/** Type of int_st register + * HUK Generator interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_st_reg_t; + +/** Type of int_ena register + * HUK Generator interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_ena_reg_t; + +/** Type of int_clr register + * HUK Generator interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_clr_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * HUK Generator configuration register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ + uint32_t mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} huk_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * HUK Generator control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * HUK Generator state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_state_reg_t; + + +/** Group: Result registers */ +/** Type of status register + * HUK Generator HUK status register + */ +typedef union { + struct { + /** status : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ + uint32_t status:2; + /** risk_level : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ + uint32_t risk_level:3; + /** update_req : RO; bitpos: [5]; default: 0; + * The update request of HUK info. 0: User can update HUK info according to the risk + * level. 1: The HUK info is expired, and user need to update it. + */ + uint32_t update_req:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} huk_status_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37765232; + * HUK Generator version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} huk_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile huk_clk_reg_t clk; + volatile huk_int_raw_reg_t int_raw; + volatile huk_int_st_reg_t int_st; + volatile huk_int_ena_reg_t int_ena; + volatile huk_int_clr_reg_t int_clr; + uint32_t reserved_018[2]; + volatile huk_conf_reg_t conf; + volatile huk_start_reg_t start; + volatile huk_state_reg_t state; + uint32_t reserved_02c[2]; + volatile huk_status_reg_t status; + uint32_t reserved_038[49]; + volatile huk_date_reg_t date; + volatile uint32_t info[96]; +} huk_dev_t; + +extern huk_dev_t HUK; + +#ifndef __cplusplus +_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/io_mux_reg.h b/components/soc/esp32h4/register/soc/io_mux_reg.h new file mode 100644 index 0000000000..2254ec5c4d --- /dev/null +++ b/components/soc/esp32h4/register/soc/io_mux_reg.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 +/* Configures whether or not to enable the hysteresis function of the pin when IO_MUX_GPIO$n_HYS_SEL is set to 1. */ +#define HYS_EN (BIT(16)) +#define HYS_EN_M (HYS_EN_V << HYS_EN_S) +#define HYS_EN_V 1 +#define HYS_EN_S 16 +/* Configures to choose the signal for enabling the hysteresis function for GPIO$n. */ +#define HYS_SEL (BIT(17)) +#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S) +#define HYS_SEL_V 1 +#define HYS_SEL_S 17 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0 +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1 +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2 +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_GPIO3 +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_SPICS1 +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_SPICS0 +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_SPIQ +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_SPIWP +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_SPIHD +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_SPICLK +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_SPID +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14 +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_GPIO15 +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_GPIO16 +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17 +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18 +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_GPIO19 +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_GPIO20 +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_GPIO21 +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22 +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_U0RXD +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_U0TXD +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_GPIO25 +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_PAD_GPIO26 +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_U_PAD_GPIO27 +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_U_PAD_MTMS +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_U_PAD_MTDI +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_U_PAD_MTCK +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_U_PAD_MTDO +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_U_PAD_GPIO32 +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_U_PAD_GPIO33 +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_U_PAD_GPIO34 +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_U_PAD_GPIO35 +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_U_PAD_GPIO36 +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_U_PAD_GPIO37 +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_U_PAD_GPIO38 +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_U_PAD_GPIO39 + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define EXT_OSC_SLOW_GPIO_NUM 0 +#define MAX_RTC_GPIO_NUM 5 +#define MAX_PAD_GPIO_NUM 39 +#define MAX_GPIO_NUM 43 +#define HIGH_IO_HOLD_BIT_SHIFT 32 + +#define GPIO_NUM_IN_FORCE_0 0x60 +#define GPIO_NUM_IN_FORCE_1 0x40 +#define GPIO_NUM_IN_INVALID 0x50 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 0x0000000F +#define CLK_OUT3_V 0xF +#define CLK_OUT3_S 8 +#define CLK_OUT3_M ((0xF)<<(8)) +#define CLK_OUT2 0x0000000F +#define CLK_OUT2_V 0xF +#define CLK_OUT2_S 8 +#define CLK_OUT2_M ((0xF)<<(8)) +#define CLK_OUT1 0x0000000F +#define CLK_OUT1_V 0xF +#define CLK_OUT1_S 8 +#define CLK_OUT1_M ((0xF)<<(8)) +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x4) +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0xC) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x10) +#define FUNC_XTAL_32K_N_GPIO4 1 +#define FUNC_XTAL_32K_N_GPIO4_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x14) +#define FUNC_XTAL_32K_P_GPIO5 1 +#define FUNC_XTAL_32K_P_GPIO5_0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x18) +#define FUNC_SPICS1_GPIO6 1 +#define FUNC_SPICS1_SPICS1 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x1C) +#define FUNC_SPICS0_GPIO7 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x20) +#define FUNC_SPIQ_GPIO8 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x24) +#define FUNC_SPIWP_GPIO9 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x28) +#define FUNC_SPIHD_GPIO10 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x2C) +#define FUNC_SPICLK_GPIO11 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x30) +#define FUNC_SPID_GPIO12 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x3C) +#define FUNC_GPIO15_FSPIQ 2 +#define FUNC_GPIO15_GPIO15 1 +#define FUNC_GPIO15_GPIO15_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x40) +#define FUNC_GPIO16_FSPICLK 2 +#define FUNC_GPIO16_GPIO16 1 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x44) +#define FUNC_GPIO17_FSPID 2 +#define FUNC_GPIO17_GPIO17 1 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x48) +#define FUNC_GPIO18_FSPIWP 2 +#define FUNC_GPIO18_GPIO18 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x4C) +#define FUNC_GPIO19_FSPIHD 2 +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x50) +#define FUNC_GPIO20_FSPICS0 2 +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x54) +#define FUNC_GPIO21_GPIO21 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58) +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x5C) +#define FUNC_U0RXD_GPIO23 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x60) +#define FUNC_U0TXD_GPIO24 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x64) +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x68) +#define FUNC_GPIO26_GPIO26 1 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x6C) +#define FUNC_GPIO27_GPIO27 1 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x70) +#define FUNC_MTMS_GPIO28 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x74) +#define FUNC_MTDI_GPIO29 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x78) +#define FUNC_MTCK_GPIO30 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x7C) +#define FUNC_MTDO_GPIO31 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x80) +#define FUNC_GPIO32_FSPICLK 2 +#define FUNC_GPIO32_GPIO32 1 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x84) +#define FUNC_GPIO33_FSPID 2 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x88) +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x8C) +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x90) +#define FUNC_GPIO36_FSPIQ 2 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x94) +#define FUNC_GPIO37_FSPIWP 2 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x98) +#define FUNC_GPIO38_FSPIHD 2 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0x9C) +#define FUNC_GPIO39_FSPICS0 2 +#define FUNC_GPIO39_GPIO39 1 +#define FUNC_GPIO39_GPIO39_0 0 + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC) +/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2412160 ; */ +/*description: Version control register.*/ +#define IO_MUX_REG_DATE 0x0FFFFFFF +#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S)) +#define IO_MUX_REG_DATE_V 0xFFFFFFF +#define IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/keymng_reg.h b/components/soc/esp32h4/register/soc/keymng_reg.h new file mode 100644 index 0000000000..a385df2586 --- /dev/null +++ b/components/soc/esp32h4/register/soc/keymng_reg.h @@ -0,0 +1,395 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_REG_CG_FORCE_ON (BIT(0)) +#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S) +#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_REG_CG_FORCE_ON_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) +/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ +#define KEYMNG_USE_EFUSE_KEY 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) +#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_S 0 +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 5 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(10)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 10 +/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_FLASH_KEY_LEN (BIT(11)) +#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S) +#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_S 11 +/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_PSRAM_KEY_LEN (BIT(12)) +#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S) +#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_S 12 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) +/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6 +/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ +#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7)) +#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S) +#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7 +/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ +#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8)) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S) +#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_192_VLD_S 0 +/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1)) +#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S) +#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_256_VLD_S 1 +/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_FLASH_VLD (BIT(2)) +#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S) +#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U +#define KEYMNG_KEY_FLASH_VLD_S 2 +/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_HMAC_VLD (BIT(3)) +#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S) +#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U +#define KEYMNG_KEY_HMAC_VLD_S 3 +/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_DS_VLD (BIT(4)) +#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S) +#define KEYMNG_KEY_DS_VLD_V 0x00000001U +#define KEYMNG_KEY_DS_VLD_S 4 +/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_PSRAM_VLD (BIT(5)) +#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S) +#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U +#define KEYMNG_KEY_PSRAM_VLD_S 5 +/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6)) +#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S) +#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_384_VLD_S 6 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/keymng_struct.h b/components/soc/esp32h4/register/soc/keymng_struct.h new file mode 100644 index 0000000000..db97cead75 --- /dev/null +++ b/components/soc/esp32h4/register/soc/keymng_struct.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * Key Manager clock gate control register + */ +typedef union { + struct { + /** reg_cg_force_on : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t reg_cg_force_on:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Key Manager interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_raw_reg_t; + +/** Type of int_st register + * Key Manager interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_st_reg_t; + +/** Type of int_ena register + * Key Manager interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_ena_reg_t; + +/** Type of int_clr register + * Key Manager interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_clr_reg_t; + + +/** Group: Static configuration registers */ +/** Type of static register + * Key Manager static configuration register + */ +typedef union { + struct { + /** use_efuse_key : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ + uint32_t use_efuse_key:5; + /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ + uint32_t rnd_switch_cycle:5; + /** use_sw_init_key : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ + uint32_t use_sw_init_key:1; + /** flash_key_len : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t flash_key_len:1; + /** psram_key_len : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t psram_key_len:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} keymng_static_reg_t; + +/** Type of lock register + * Key Manager static configuration locker register + */ +typedef union { + struct { + /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ + uint32_t use_efuse_key_lock:5; + /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ + uint32_t rnd_switch_cycle_lock:1; + /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ + uint32_t use_sw_init_key_lock:1; + /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ + uint32_t flash_key_len_lock:1; + /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ + uint32_t psram_key_len_lock:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} keymng_lock_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** kgen_mode : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ + uint32_t kgen_mode:3; + /** key_purpose : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ + uint32_t key_purpose:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * Key Manager control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * Key Manager state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * Key Manager operation result register + */ +typedef union { + struct { + /** proc_result : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ + uint32_t proc_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_result_reg_t; + +/** Type of key_vld register + * Key Manager key status register + */ +typedef union { + struct { + /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_192_vld:1; + /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_256_vld:1; + /** key_flash_vld : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_flash_vld:1; + /** key_hmac_vld : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_hmac_vld:1; + /** key_ds_vld : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ds_vld:1; + /** key_psram_vld : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_psram_vld:1; + /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_384_vld:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_key_vld_reg_t; + +/** Type of huk_vld register + * Key Manager HUK status register + */ +typedef union { + struct { + /** huk_valid : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ + uint32_t huk_valid:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_huk_vld_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} keymng_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile keymng_clk_reg_t clk; + volatile keymng_int_raw_reg_t int_raw; + volatile keymng_int_st_reg_t int_st; + volatile keymng_int_ena_reg_t int_ena; + volatile keymng_int_clr_reg_t int_clr; + volatile keymng_static_reg_t static; + volatile keymng_lock_reg_t lock; + volatile keymng_conf_reg_t conf; + volatile keymng_start_reg_t start; + volatile keymng_state_reg_t state; + volatile keymng_result_reg_t result; + volatile keymng_key_vld_reg_t key_vld; + volatile keymng_huk_vld_reg_t huk_vld; + uint32_t reserved_038[49]; + volatile keymng_date_reg_t date; + volatile uint32_t assist_info[16]; + volatile uint32_t public_info[16]; + volatile uint32_t sw_init_key[8]; +} keymng_dev_t; + +extern keymng_dev_t KEYMNG; + +#ifndef __cplusplus +_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_analog_peri_reg.h b/components/soc/esp32h4/register/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..575fb87e4e --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_analog_peri_reg.h @@ -0,0 +1,469 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_VDD_SOURCE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_ANA_DETMODE_SEL 0x000000FFU +#define LP_ANA_DETMODE_SEL_M (LP_ANA_DETMODE_SEL_V << LP_ANA_DETMODE_SEL_S) +#define LP_ANA_DETMODE_SEL_V 0x000000FFU +#define LP_ANA_DETMODE_SEL_S 0 +/** LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define LP_ANA_VGOOD_EVENT_RECORD 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_M (LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANA_VGOOD_EVENT_RECORD_S) +#define LP_ANA_VGOOD_EVENT_RECORD_V 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_S 8 +/** LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_ANA_VBAT_EVENT_RECORD_CLR 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_M (LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANA_VBAT_EVENT_RECORD_CLR_S) +#define LP_ANA_VBAT_EVENT_RECORD_CLR_V 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_S 16 +/** LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LP_ANA_BOD_SOURCE_ENA 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_M (LP_ANA_BOD_SOURCE_ENA_V << LP_ANA_BOD_SOURCE_ENA_S) +#define LP_ANA_BOD_SOURCE_ENA_V 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_S 24 + +/** LP_ANA_VDDBAT_BOD_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGER_M (LP_ANA_VDDBAT_CHARGER_V << LP_ANA_VDDBAT_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGER_S 10 +/** LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CNT_CLR_M (LP_ANA_VDDBAT_CNT_CLR_V << LP_ANA_VDDBAT_CNT_CLR_S) +#define LP_ANA_VDDBAT_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_VDDBAT_CHARGE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_M (LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANA_VDDBAT_CHARGE_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CHARGER_S 10 +/** LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_M (LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANA_VDDBAT_CHARGE_CNT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_PG_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define LP_ANA_POWER_GLITCH_RESET_ENA 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S) +#define LP_ANA_POWER_GLITCH_RESET_ENA_V 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_S 26 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_S 24 + +#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30 +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S 30 +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30 +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30 +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37818752; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_analog_peri_struct.h b/components/soc/esp32h4/register/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..1fb1923ce2 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_analog_peri_struct.h @@ -0,0 +1,420 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of ana_bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** ana_bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_close_flash_ena:1; + /** ana_bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_pd_rf_ena:1; + /** ana_bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t ana_bod_mode0_intr_wait:10; + /** ana_bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t ana_bod_mode0_reset_wait:10; + /** ana_bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_cnt_clr:1; + /** ana_bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_intr_ena:1; + /** ana_bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_sel:1; + /** ana_bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of ana_bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ana_vdd_source_cntl register + * need_des + */ +typedef union { + struct { + /** ana_detmode_sel : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t ana_detmode_sel:8; + /** ana_vgood_event_record : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t ana_vgood_event_record:8; + /** ana_vbat_event_record_clr : WT; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t ana_vbat_event_record_clr:8; + /** ana_bod_source_ena : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t ana_bod_source_ena:8; + }; + uint32_t val; +} lp_ana_vdd_source_cntl_reg_t; + +/** Type of ana_vddbat_bod_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charger:1; + /** ana_vddbat_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_cnt_clr:1; + /** ana_vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_target:10; + /** ana_vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_bod_cntl_reg_t; + +/** Type of ana_vddbat_charge_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charge_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_charger:1; + /** ana_vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_cnt_clr:1; + /** ana_vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_target:10; + /** ana_vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_charge_cntl_reg_t; + +/** Type of ana_ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of ana_pg_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** ana_power_glitch_reset_ena : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t ana_power_glitch_reset_ena:6; + }; + uint32_t val; +} lp_ana_pg_glitch_cntl_reg_t; + +/** Type of ana_fib_enable register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** ana_ana_fib_ena : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t ana_ana_fib_ena:8; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of ana_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_raw:1; + /** ana_vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_raw:1; + /** ana_vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_raw:1; + /** ana_vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_raw:1; + /** ana_bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of ana_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_st:1; + /** ana_vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_st:1; + /** ana_vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_st:1; + /** ana_vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_st:1; + /** ana_bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of ana_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_ena:1; + /** ana_vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_ena:1; + /** ana_vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_ena:1; + /** ana_vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_ena:1; + /** ana_bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of ana_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_clr:1; + /** ana_vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_clr:1; + /** ana_vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_clr:1; + /** ana_vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_clr:1; + /** ana_bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of ana_lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of ana_lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of ana_lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of ana_lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of ana_date register + * need_des + */ +typedef union { + struct { + /** ana_lp_ana_date : R/W; bitpos: [30:0]; default: 37818752; + * need_des + */ + uint32_t ana_lp_ana_date:31; + /** ana_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t ana_bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t ana_bod_mode1_cntl; + volatile lp_ana_vdd_source_cntl_reg_t ana_vdd_source_cntl; + volatile lp_ana_vddbat_bod_cntl_reg_t ana_vddbat_bod_cntl; + volatile lp_ana_vddbat_charge_cntl_reg_t ana_vddbat_charge_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ana_ck_glitch_cntl; + volatile lp_ana_pg_glitch_cntl_reg_t ana_pg_glitch_cntl; + volatile lp_ana_fib_enable_reg_t ana_fib_enable; + volatile lp_ana_int_raw_reg_t ana_int_raw; + volatile lp_ana_int_st_reg_t ana_int_st; + volatile lp_ana_int_ena_reg_t ana_int_ena; + volatile lp_ana_int_clr_reg_t ana_int_clr; + volatile lp_ana_lp_int_raw_reg_t ana_lp_int_raw; + volatile lp_ana_lp_int_st_reg_t ana_lp_int_st; + volatile lp_ana_lp_int_ena_reg_t ana_lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t ana_lp_int_clr; + uint32_t reserved_040[239]; + volatile lp_ana_date_reg_t ana_date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_aon_reg.h b/components/soc/esp32h4/register/soc/lp_aon_reg.h new file mode 100644 index 0000000000..e2d1e33565 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_aon_reg.h @@ -0,0 +1,683 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * store the software massege0 in always-on field + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * store the software massege0 in always-on field + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * store the software massege1 in always-on field + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * store the software massege1 in always-on field + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * store the software massege2 in always-on field + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * store the software massege2 in always-on field + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * store the software massege3 in always-on field + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * store the software massege3 in always-on field + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * store the software massege4 in always-on field + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * store the software massege4 in always-on field + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * store the software massege5 in always-on field + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * store the software massege5 in always-on field + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * store the software massege6 in always-on field + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * store the software massege6 in always-on field + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * store the software massege7 in always-on field + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * store the software massege7 in always-on field + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * store the software massege8 in always-on field + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * store the software massege8 in always-on field + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * store the software massege9 in always-on field + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * store the software massege9 in always-on field + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * select the lp io controlled by hp iomux or lp iomux + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [5:0]; default: 0; + * select the lp io 0~5 controlled by hp iomux or lp iomux + * 1: controlled by lp iomux + * 0: controlled by hp iomux + */ +#define LP_AON_GPIO_MUX_SEL 0x0000003FU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x0000003FU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * configure all io hold + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * configure io0~28 hold enable,when io in hold status, all io configure and output + * will be latch , input function is useful + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_SYS_CFG_REG register + * configure system register + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_FIB_REG : RO; bitpos: [7:0]; default: 255; + * get fib reg information + */ +#define LP_AON_FIB_REG 0x000000FFU +#define LP_AON_FIB_REG_M (LP_AON_FIB_REG_V << LP_AON_FIB_REG_S) +#define LP_AON_FIB_REG_V 0x000000FFU +#define LP_AON_FIB_REG_S 0 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * enable hp system reset by software or not + * 1: reset + * 0: no operation + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE_CFG_REG register + * configure core reset register + */ +#define LP_AON_CPUCORE_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * enable cpu 0 entry stall status + * 0x86: entry stall status + * Others : no operation + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [8]; default: 0; + * enable core 0 reset by software + * 1: reset + * 0: no operation + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(8)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 8 +/** LP_AON_CPU_CORE1_SW_STALL : R/W; bitpos: [23:16]; default: 0; + * enable core 1 entry stall status + * 0x86: entry stall status + * Others : no operation + */ +#define LP_AON_CPU_CORE1_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE1_SW_STALL_M (LP_AON_CPU_CORE1_SW_STALL_V << LP_AON_CPU_CORE1_SW_STALL_S) +#define LP_AON_CPU_CORE1_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE1_SW_STALL_S 16 +/** LP_AON_CPU_CORE1_SW_RESET : WT; bitpos: [24]; default: 0; + * enable core1 reset by software + * 1: reset + * 0: no operation + */ +#define LP_AON_CPU_CORE1_SW_RESET (BIT(24)) +#define LP_AON_CPU_CORE1_SW_RESET_M (LP_AON_CPU_CORE1_SW_RESET_V << LP_AON_CPU_CORE1_SW_RESET_S) +#define LP_AON_CPU_CORE1_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE1_SW_RESET_S 24 +/** LP_AON_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0; + * delete which core run_stall to lp_timer + * 1: core1 + * 0: core0 + */ +#define LP_AON_SYSTIMER_STALL_SEL (BIT(31)) +#define LP_AON_SYSTIMER_STALL_SEL_M (LP_AON_SYSTIMER_STALL_SEL_V << LP_AON_SYSTIMER_STALL_SEL_S) +#define LP_AON_SYSTIMER_STALL_SEL_V 0x00000001U +#define LP_AON_SYSTIMER_STALL_SEL_S 31 + +/** LP_AON_IO_MUX_REG register + * configure hp iomux reset bypass + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S) +#define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_S 28 +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * bypass hp iomux reset from hp system reset event + * 1: bypass + * 0: no operation + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * configure alwayson external io wakeup + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [15:0]; default: 0; + * enable io0~15 bit map use to external wakeup + * 1: enable + * 0: disable + */ +#define LP_AON_EXT_WAKEUP_SEL 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_SEL_S 0 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [31:16]; default: 0; + * select external wakeup io level + * 1: io high level wakeup + * 0: io low level wakeup + */ +#define LP_AON_EXT_WAKEUP_LV 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_LV_S 16 + +/** LP_AON_EXT_WAKEUP_CNTL1_REG register + * configure alwayson external io wakeup + */ +#define LP_AON_EXT_WAKEUP_CNTL1_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [15:0]; default: 0; + * get external wakeup status bitmap + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x0000FFFFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [30]; default: 0; + * clear external wakeup status + * 1: clear + * 0: no operation + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(30)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 30 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * enable external filter or not + * 1: enable + * 0: disable + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * configure usb reset bypass + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * bypass usb reset from hp system reset event + * 1: bypass + * 0: no operation + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * Select lp memory bus + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; + * get current lp memory bus fsm status + */ +#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 +/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; + * get current lp memory bus mode + */ +#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 +/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; + * enable reg_fast_mem_sel configure + * 1: enable + * 0: no operation + */ +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 +/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; + * select lp memory bus is high speed mode or low speed mode + * 1: high speed from hp system ahb + * 0: low speed from lp system + */ +#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) +#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) +#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_S 31 + +/** LP_AON_BACKUP_DMA_CFG0_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70) +/** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ +#define LP_AON_BURST_LIMIT_AON 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_M (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S) +#define LP_AON_BURST_LIMIT_AON_V 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_S 0 +/** LP_AON_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ +#define LP_AON_READ_INTERVAL_AON 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_M (LP_AON_READ_INTERVAL_AON_V << LP_AON_READ_INTERVAL_AON_S) +#define LP_AON_READ_INTERVAL_AON_V 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_S 5 +/** LP_AON_BRANCH_LINK_LENGTH_AON : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_BRANCH_LINK_LENGTH_AON 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_M (LP_AON_BRANCH_LINK_LENGTH_AON_V << LP_AON_BRANCH_LINK_LENGTH_AON_S) +#define LP_AON_BRANCH_LINK_LENGTH_AON_V 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_S 12 +/** LP_AON_REGDMA_ERROR : RO; bitpos: [18:16]; default: 0; + * regdma error code + */ +#define LP_AON_REGDMA_ERROR 0x00000007U +#define LP_AON_REGDMA_ERROR_M (LP_AON_REGDMA_ERROR_V << LP_AON_REGDMA_ERROR_S) +#define LP_AON_REGDMA_ERROR_V 0x00000007U +#define LP_AON_REGDMA_ERROR_S 16 + +/** LP_AON_BACKUP_DMA_CFG1_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG1_REG (DR_REG_LP_AON_BASE + 0x74) +/** LP_AON_LINK_WAIT_TOUT_THRES_AON : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ +#define LP_AON_LINK_WAIT_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_M (LP_AON_LINK_WAIT_TOUT_THRES_AON_V << LP_AON_LINK_WAIT_TOUT_THRES_AON_S) +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_S 0 +/** LP_AON_LINK_WORK_TOUT_THRES_AON : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ +#define LP_AON_LINK_WORK_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_M (LP_AON_LINK_WORK_TOUT_THRES_AON_V << LP_AON_LINK_WORK_TOUT_THRES_AON_S) +#define LP_AON_LINK_WORK_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_S 10 +/** LP_AON_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_M (LP_AON_LINK_BACKUP_TOUT_THRES_AON_V << LP_AON_LINK_BACKUP_TOUT_THRES_AON_S) +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20 + +/** LP_AON_BACKUP_DMA_CFG2_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG2_REG (DR_REG_LP_AON_BASE + 0x78) +/** LP_AON_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_LINK_ADDR_AON 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_M (LP_AON_LINK_ADDR_AON_V << LP_AON_LINK_ADDR_AON_S) +#define LP_AON_LINK_ADDR_AON_V 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_S 0 + +/** LP_AON_MEM_CTRL_REG register + * configure rmemory power in lp system register + */ +#define LP_AON_MEM_CTRL_REG (DR_REG_LP_AON_BASE + 0x7c) +/** LP_AON_EFUSE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures efuse memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define LP_AON_EFUSE_MEM_LP_MODE 0x00000003U +#define LP_AON_EFUSE_MEM_LP_MODE_M (LP_AON_EFUSE_MEM_LP_MODE_V << LP_AON_EFUSE_MEM_LP_MODE_S) +#define LP_AON_EFUSE_MEM_LP_MODE_V 0x00000003U +#define LP_AON_EFUSE_MEM_LP_MODE_S 0 +/** LP_AON_EFUSE_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down efuse memory. + */ +#define LP_AON_EFUSE_MEM_LP_EN (BIT(2)) +#define LP_AON_EFUSE_MEM_LP_EN_M (LP_AON_EFUSE_MEM_LP_EN_V << LP_AON_EFUSE_MEM_LP_EN_S) +#define LP_AON_EFUSE_MEM_LP_EN_V 0x00000001U +#define LP_AON_EFUSE_MEM_LP_EN_S 2 +/** LP_AON_EFUSE_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control efuse memory, disable hardware control. + */ +#define LP_AON_EFUSE_MEM_FORCE_CTRL (BIT(3)) +#define LP_AON_EFUSE_MEM_FORCE_CTRL_M (LP_AON_EFUSE_MEM_FORCE_CTRL_V << LP_AON_EFUSE_MEM_FORCE_CTRL_S) +#define LP_AON_EFUSE_MEM_FORCE_CTRL_V 0x00000001U +#define LP_AON_EFUSE_MEM_FORCE_CTRL_S 3 +/** LP_AON_HUK_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 2; + * Configures huk memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ +#define LP_AON_HUK_MEM_LP_MODE 0x00000003U +#define LP_AON_HUK_MEM_LP_MODE_M (LP_AON_HUK_MEM_LP_MODE_V << LP_AON_HUK_MEM_LP_MODE_S) +#define LP_AON_HUK_MEM_LP_MODE_V 0x00000003U +#define LP_AON_HUK_MEM_LP_MODE_S 4 +/** LP_AON_HUK_MEM_LP_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to power down huk memory. + */ +#define LP_AON_HUK_MEM_LP_EN (BIT(6)) +#define LP_AON_HUK_MEM_LP_EN_M (LP_AON_HUK_MEM_LP_EN_V << LP_AON_HUK_MEM_LP_EN_S) +#define LP_AON_HUK_MEM_LP_EN_V 0x00000001U +#define LP_AON_HUK_MEM_LP_EN_S 6 +/** LP_AON_HUK_MEM_FORCE_CTRL : R/W; bitpos: [7]; default: 0; + * Set this bit to force software control huk memory, disable hardware control. + */ +#define LP_AON_HUK_MEM_FORCE_CTRL (BIT(7)) +#define LP_AON_HUK_MEM_FORCE_CTRL_M (LP_AON_HUK_MEM_FORCE_CTRL_V << LP_AON_HUK_MEM_FORCE_CTRL_S) +#define LP_AON_HUK_MEM_FORCE_CTRL_V 0x00000001U +#define LP_AON_HUK_MEM_FORCE_CTRL_S 7 + +/** LP_AON_HP_MEM_CTRL_REG register + * configure rmemory power in lp system register + */ +#define LP_AON_HP_MEM_CTRL_REG (DR_REG_LP_AON_BASE + 0x80) +/** LP_AON_MODEM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures modem memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define LP_AON_MODEM_MEM_LP_MODE 0x00000003U +#define LP_AON_MODEM_MEM_LP_MODE_M (LP_AON_MODEM_MEM_LP_MODE_V << LP_AON_MODEM_MEM_LP_MODE_S) +#define LP_AON_MODEM_MEM_LP_MODE_V 0x00000003U +#define LP_AON_MODEM_MEM_LP_MODE_S 0 +/** LP_AON_MODEM_MEM_LP_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to power down modem memory. + */ +#define LP_AON_MODEM_MEM_LP_EN (BIT(2)) +#define LP_AON_MODEM_MEM_LP_EN_M (LP_AON_MODEM_MEM_LP_EN_V << LP_AON_MODEM_MEM_LP_EN_S) +#define LP_AON_MODEM_MEM_LP_EN_V 0x00000001U +#define LP_AON_MODEM_MEM_LP_EN_S 2 +/** LP_AON_MODEM_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control modem memory, disable hardware control. + */ +#define LP_AON_MODEM_MEM_FORCE_CTRL (BIT(3)) +#define LP_AON_MODEM_MEM_FORCE_CTRL_M (LP_AON_MODEM_MEM_FORCE_CTRL_V << LP_AON_MODEM_MEM_FORCE_CTRL_S) +#define LP_AON_MODEM_MEM_FORCE_CTRL_V 0x00000001U +#define LP_AON_MODEM_MEM_FORCE_CTRL_S 3 +/** LP_AON_MMU_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 0; + * Configures mmu memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ +#define LP_AON_MMU_MEM_LP_MODE 0x00000003U +#define LP_AON_MMU_MEM_LP_MODE_M (LP_AON_MMU_MEM_LP_MODE_V << LP_AON_MMU_MEM_LP_MODE_S) +#define LP_AON_MMU_MEM_LP_MODE_V 0x00000003U +#define LP_AON_MMU_MEM_LP_MODE_S 4 +/** LP_AON_MMU_MEM_LP_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to power down mmu memory. + */ +#define LP_AON_MMU_MEM_LP_EN (BIT(6)) +#define LP_AON_MMU_MEM_LP_EN_M (LP_AON_MMU_MEM_LP_EN_V << LP_AON_MMU_MEM_LP_EN_S) +#define LP_AON_MMU_MEM_LP_EN_V 0x00000001U +#define LP_AON_MMU_MEM_LP_EN_S 6 +/** LP_AON_MMU_MEM_FORCE_CTRL : R/W; bitpos: [7]; default: 0; + * Set this bit to force software control mmu memory, disable hardware control. + */ +#define LP_AON_MMU_MEM_FORCE_CTRL (BIT(7)) +#define LP_AON_MMU_MEM_FORCE_CTRL_M (LP_AON_MMU_MEM_FORCE_CTRL_V << LP_AON_MMU_MEM_FORCE_CTRL_S) +#define LP_AON_MMU_MEM_FORCE_CTRL_V 0x00000001U +#define LP_AON_MMU_MEM_FORCE_CTRL_S 7 +/** LP_AON_HP_SRAM_MEM_LP_MODE : R/W; bitpos: [17:16]; default: 0; + * Configures hp_sram memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ +#define LP_AON_HP_SRAM_MEM_LP_MODE 0x00000003U +#define LP_AON_HP_SRAM_MEM_LP_MODE_M (LP_AON_HP_SRAM_MEM_LP_MODE_V << LP_AON_HP_SRAM_MEM_LP_MODE_S) +#define LP_AON_HP_SRAM_MEM_LP_MODE_V 0x00000003U +#define LP_AON_HP_SRAM_MEM_LP_MODE_S 16 +/** LP_AON_HP_SRAM_MEM_LP_EN : R/W; bitpos: [24:18]; default: 0; + * Set this bit to power down hp_sram memory. + */ +#define LP_AON_HP_SRAM_MEM_LP_EN 0x0000007FU +#define LP_AON_HP_SRAM_MEM_LP_EN_M (LP_AON_HP_SRAM_MEM_LP_EN_V << LP_AON_HP_SRAM_MEM_LP_EN_S) +#define LP_AON_HP_SRAM_MEM_LP_EN_V 0x0000007FU +#define LP_AON_HP_SRAM_MEM_LP_EN_S 18 +/** LP_AON_HP_SRAM_MEM_FORCE_CTRL : R/W; bitpos: [31:25]; default: 0; + * Set this bit to force software control hp_sram memory, disable hardware control. + */ +#define LP_AON_HP_SRAM_MEM_FORCE_CTRL 0x0000007FU +#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_M (LP_AON_HP_SRAM_MEM_FORCE_CTRL_V << LP_AON_HP_SRAM_MEM_FORCE_CTRL_S) +#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_V 0x0000007FU +#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_S 25 + +/** LP_AON_IO_LDO_CFG_REG register + * need_des + */ +#define LP_AON_IO_LDO_CFG_REG (DR_REG_LP_AON_BASE + 0x84) +/** LP_AON_IO_LDO_3P3_SW : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define LP_AON_IO_LDO_3P3_SW (BIT(21)) +#define LP_AON_IO_LDO_3P3_SW_M (LP_AON_IO_LDO_3P3_SW_V << LP_AON_IO_LDO_3P3_SW_S) +#define LP_AON_IO_LDO_3P3_SW_V 0x00000001U +#define LP_AON_IO_LDO_3P3_SW_S 21 +/** LP_AON_IO_LDO_3P3_SW_EN : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define LP_AON_IO_LDO_3P3_SW_EN (BIT(22)) +#define LP_AON_IO_LDO_3P3_SW_EN_M (LP_AON_IO_LDO_3P3_SW_EN_V << LP_AON_IO_LDO_3P3_SW_EN_S) +#define LP_AON_IO_LDO_3P3_SW_EN_V 0x00000001U +#define LP_AON_IO_LDO_3P3_SW_EN_S 22 +/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_IO_LDO_ADJUST_SW 0x000000FFU +#define LP_AON_IO_LDO_ADJUST_SW_M (LP_AON_IO_LDO_ADJUST_SW_V << LP_AON_IO_LDO_ADJUST_SW_S) +#define LP_AON_IO_LDO_ADJUST_SW_V 0x000000FFU +#define LP_AON_IO_LDO_ADJUST_SW_S 23 +/** LP_AON_IO_LDO_ADJUST_SW_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_LDO_ADJUST_SW_EN (BIT(31)) +#define LP_AON_IO_LDO_ADJUST_SW_EN_M (LP_AON_IO_LDO_ADJUST_SW_EN_V << LP_AON_IO_LDO_ADJUST_SW_EN_S) +#define LP_AON_IO_LDO_ADJUST_SW_EN_V 0x00000001U +#define LP_AON_IO_LDO_ADJUST_SW_EN_S 31 + +/** LP_AON_LP_GPIO_SECURITY_REG register + * need des + */ +#define LP_AON_LP_GPIO_SECURITY_REG (DR_REG_LP_AON_BASE + 0x8c) +/** LP_AON_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0; + * This field decides whether lp_gpio_config can be locked, or not. 0 (default): + * unlocked. 1: locked. + */ +#define LP_AON_LP_GPIO_LOCK 0x0000003FU +#define LP_AON_LP_GPIO_LOCK_M (LP_AON_LP_GPIO_LOCK_V << LP_AON_LP_GPIO_LOCK_S) +#define LP_AON_LP_GPIO_LOCK_V 0x0000003FU +#define LP_AON_LP_GPIO_LOCK_S 0 + +/** LP_AON_HP_GPIO_SECURITY_1_REG register + * need des + */ +#define LP_AON_HP_GPIO_SECURITY_1_REG (DR_REG_LP_AON_BASE + 0x90) +/** LP_AON_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0; + * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ +#define LP_AON_HP_GPIO_LOCK_P1 0xFFFFFFFFU +#define LP_AON_HP_GPIO_LOCK_P1_M (LP_AON_HP_GPIO_LOCK_P1_V << LP_AON_HP_GPIO_LOCK_P1_S) +#define LP_AON_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU +#define LP_AON_HP_GPIO_LOCK_P1_S 0 + +/** LP_AON_HP_GPIO_SECURITY_2_REG register + * need des + */ +#define LP_AON_HP_GPIO_SECURITY_2_REG (DR_REG_LP_AON_BASE + 0x94) +/** LP_AON_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0; + * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ +#define LP_AON_HP_GPIO_LOCK_P2 0x000000FFU +#define LP_AON_HP_GPIO_LOCK_P2_M (LP_AON_HP_GPIO_LOCK_P2_V << LP_AON_HP_GPIO_LOCK_P2_S) +#define LP_AON_HP_GPIO_LOCK_P2_V 0x000000FFU +#define LP_AON_HP_GPIO_LOCK_P2_S 0 + +/** LP_AON_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define LP_AON_SRAM_USAGE_CONF_REG (DR_REG_LP_AON_BASE + 0x98) +/** LP_AON_DCACHE_USAGE : R/W; bitpos: [0]; default: 0; + * hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is + * used to control the first layer(Layer0) usage. 0: cpu use hp-memory. 1: dcache use + * hp-mmory. + * By default, dcache is closed, and typically users can enable dcache after + * boot-loader, but before user's BIN start running. + */ +#define LP_AON_DCACHE_USAGE (BIT(0)) +#define LP_AON_DCACHE_USAGE_M (LP_AON_DCACHE_USAGE_V << LP_AON_DCACHE_USAGE_S) +#define LP_AON_DCACHE_USAGE_V 0x00000001U +#define LP_AON_DCACHE_USAGE_S 0 +/** LP_AON_ICACHE1_USAGE : R/W; bitpos: [1]; default: 1; + * hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is + * used to control the last layer(Layer6) usage. 0: cpu use hp-memory. 1: icache1 use + * hp-mmory. + * By default, icache1 is not disabled, and the last layer memory belongs to icache1. + * Typically users can set this bit to 0 to disable icache1 in boot-loader. + */ +#define LP_AON_ICACHE1_USAGE (BIT(1)) +#define LP_AON_ICACHE1_USAGE_M (LP_AON_ICACHE1_USAGE_V << LP_AON_ICACHE1_USAGE_S) +#define LP_AON_ICACHE1_USAGE_V 0x00000001U +#define LP_AON_ICACHE1_USAGE_S 1 + +/** LP_AON_DATE_REG register + * reserved + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823056; + * version register + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * version register + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_aon_struct.h b/components/soc/esp32h4/register/soc/lp_aon_struct.h new file mode 100644 index 0000000000..bd5bedef86 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_aon_struct.h @@ -0,0 +1,668 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of aon_store0 register + * store the software massege0 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store0 : R/W; bitpos: [31:0]; default: 0; + * store the software massege0 in always-on field + */ + uint32_t aon_lp_aon_store0:32; + }; + uint32_t val; +} lp_aon_store0_reg_t; + +/** Type of aon_store1 register + * store the software massege1 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store1 : R/W; bitpos: [31:0]; default: 0; + * store the software massege1 in always-on field + */ + uint32_t aon_lp_aon_store1:32; + }; + uint32_t val; +} lp_aon_store1_reg_t; + +/** Type of aon_store2 register + * store the software massege2 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store2 : R/W; bitpos: [31:0]; default: 0; + * store the software massege2 in always-on field + */ + uint32_t aon_lp_aon_store2:32; + }; + uint32_t val; +} lp_aon_store2_reg_t; + +/** Type of aon_store3 register + * store the software massege3 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store3 : R/W; bitpos: [31:0]; default: 0; + * store the software massege3 in always-on field + */ + uint32_t aon_lp_aon_store3:32; + }; + uint32_t val; +} lp_aon_store3_reg_t; + +/** Type of aon_store4 register + * store the software massege4 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store4 : R/W; bitpos: [31:0]; default: 0; + * store the software massege4 in always-on field + */ + uint32_t aon_lp_aon_store4:32; + }; + uint32_t val; +} lp_aon_store4_reg_t; + +/** Type of aon_store5 register + * store the software massege5 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store5 : R/W; bitpos: [31:0]; default: 0; + * store the software massege5 in always-on field + */ + uint32_t aon_lp_aon_store5:32; + }; + uint32_t val; +} lp_aon_store5_reg_t; + +/** Type of aon_store6 register + * store the software massege6 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store6 : R/W; bitpos: [31:0]; default: 0; + * store the software massege6 in always-on field + */ + uint32_t aon_lp_aon_store6:32; + }; + uint32_t val; +} lp_aon_store6_reg_t; + +/** Type of aon_store7 register + * store the software massege7 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store7 : R/W; bitpos: [31:0]; default: 0; + * store the software massege7 in always-on field + */ + uint32_t aon_lp_aon_store7:32; + }; + uint32_t val; +} lp_aon_store7_reg_t; + +/** Type of aon_store8 register + * store the software massege8 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store8 : R/W; bitpos: [31:0]; default: 0; + * store the software massege8 in always-on field + */ + uint32_t aon_lp_aon_store8:32; + }; + uint32_t val; +} lp_aon_store8_reg_t; + +/** Type of aon_store9 register + * store the software massege9 in always-on field + */ +typedef union { + struct { + /** aon_lp_aon_store9 : R/W; bitpos: [31:0]; default: 0; + * store the software massege9 in always-on field + */ + uint32_t aon_lp_aon_store9:32; + }; + uint32_t val; +} lp_aon_store9_reg_t; + +/** Type of aon_gpio_mux register + * select the lp io controlled by hp iomux or lp iomux + */ +typedef union { + struct { + /** aon_gpio_mux_sel : R/W; bitpos: [5:0]; default: 0; + * select the lp io 0~5 controlled by hp iomux or lp iomux + * 1: controlled by lp iomux + * 0: controlled by hp iomux + */ + uint32_t gpio_mux_sel:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of aon_gpio_hold0 register + * configure all io hold + */ +typedef union { + struct { + /** aon_gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * configure io0~28 hold enable,when io in hold status, all io configure and output + * will be latch , input function is useful + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of aon_sys_cfg register + * configure system register + */ +typedef union { + struct { + /** aon_fib_reg : RO; bitpos: [7:0]; default: 255; + * get fib reg information + */ + uint32_t aon_fib_reg:8; + uint32_t reserved_8:23; + /** aon_hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * enable hp system reset by software or not + * 1: reset + * 0: no operation + */ + uint32_t aon_hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of aon_cpucore_cfg register + * configure core reset register + */ +typedef union { + struct { + /** aon_cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * enable cpu 0 entry stall status + * 0x86: entry stall status + * Others : no operation + */ + uint32_t aon_cpu_core0_sw_stall:8; + /** aon_cpu_core0_sw_reset : WT; bitpos: [8]; default: 0; + * enable core 0 reset by software + * 1: reset + * 0: no operation + */ + uint32_t aon_cpu_core0_sw_reset:1; + uint32_t reserved_9:7; + /** aon_cpu_core1_sw_stall : R/W; bitpos: [23:16]; default: 0; + * enable core 1 entry stall status + * 0x86: entry stall status + * Others : no operation + */ + uint32_t aon_cpu_core1_sw_stall:8; + /** aon_cpu_core1_sw_reset : WT; bitpos: [24]; default: 0; + * enable core1 reset by software + * 1: reset + * 0: no operation + */ + uint32_t aon_cpu_core1_sw_reset:1; + uint32_t reserved_25:6; + /** aon_systimer_stall_sel : R/W; bitpos: [31]; default: 0; + * delete which core run_stall to lp_timer + * 1: core1 + * 0: core0 + */ + uint32_t aon_systimer_stall_sel:1; + }; + uint32_t val; +} lp_aon_cpucore_cfg_reg_t; + +/** Type of aon_io_mux register + * configure hp iomux reset bypass + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t aon_io_mux_pull_ldo:3; + /** aon_io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * bypass hp iomux reset from hp system reset event + * 1: bypass + * 0: no operation + */ + uint32_t aon_io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of aon_ext_wakeup_cntl register + * configure alwayson external io wakeup + */ +typedef union { + struct { + /** aon_ext_wakeup_sel : R/W; bitpos: [15:0]; default: 0; + * enable io0~15 bit map use to external wakeup + * 1: enable + * 0: disable + */ + uint32_t aon_ext_wakeup_sel:16; + /** aon_ext_wakeup_lv : R/W; bitpos: [31:16]; default: 0; + * select external wakeup io level + * 1: io high level wakeup + * 0: io low level wakeup + */ + uint32_t aon_ext_wakeup_lv:16; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of aon_ext_wakeup_cntl1 register + * configure alwayson external io wakeup + */ +typedef union { + struct { + /** aon_ext_wakeup_status : RO; bitpos: [15:0]; default: 0; + * get external wakeup status bitmap + */ + uint32_t aon_ext_wakeup_status:16; + uint32_t reserved_16:14; + /** aon_ext_wakeup_status_clr : WT; bitpos: [30]; default: 0; + * clear external wakeup status + * 1: clear + * 0: no operation + */ + uint32_t aon_ext_wakeup_status_clr:1; + /** aon_ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * enable external filter or not + * 1: enable + * 0: disable + */ + uint32_t aon_ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl1_reg_t; + +/** Type of aon_usb register + * configure usb reset bypass + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_usb_reset_disable : R/W; bitpos: [31]; default: 0; + * bypass usb reset from hp system reset event + * 1: bypass + * 0: no operation + */ + uint32_t aon_usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of aon_lpbus register + * Select lp memory bus + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1; + * get current lp memory bus fsm status + */ + uint32_t aon_fast_mem_mux_fsm_idle:1; + /** aon_fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1; + * get current lp memory bus mode + */ + uint32_t aon_fast_mem_mux_sel_status:1; + /** aon_fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0; + * enable reg_fast_mem_sel configure + * 1: enable + * 0: no operation + */ + uint32_t aon_fast_mem_mux_sel_update:1; + /** aon_fast_mem_mux_sel : R/W; bitpos: [31]; default: 1; + * select lp memory bus is high speed mode or low speed mode + * 1: high speed from hp system ahb + * 0: low speed from lp system + */ + uint32_t aon_fast_mem_mux_sel:1; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of aon_backup_dma_cfg0 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_burst_limit_aon : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ + uint32_t aon_burst_limit_aon:5; + /** aon_read_interval_aon : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ + uint32_t aon_read_interval_aon:7; + /** aon_branch_link_length_aon : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_branch_link_length_aon:4; + /** aon_regdma_error : RO; bitpos: [18:16]; default: 0; + * regdma error code + */ + uint32_t aon_regdma_error:3; + uint32_t reserved_19:13; + }; + uint32_t val; +} lp_aon_backup_dma_cfg0_reg_t; + +/** Type of aon_backup_dma_cfg1 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ + uint32_t aon_link_wait_tout_thres_aon:10; + /** aon_link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ + uint32_t aon_link_work_tout_thres_aon:10; + /** aon_link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ + uint32_t aon_link_backup_tout_thres_aon:10; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_aon_backup_dma_cfg1_reg_t; + +/** Type of aon_backup_dma_cfg2 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_addr_aon : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_link_addr_aon:32; + }; + uint32_t val; +} lp_aon_backup_dma_cfg2_reg_t; + +/** Type of aon_mem_ctrl register + * configure rmemory power in lp system register + */ +typedef union { + struct { + /** aon_efuse_mem_lp_mode : R/W; bitpos: [1:0]; default: 0; + * Configures efuse memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ + uint32_t aon_efuse_mem_lp_mode:2; + /** aon_efuse_mem_lp_en : R/W; bitpos: [2]; default: 0; + * Set this bit to power down efuse memory. + */ + uint32_t aon_efuse_mem_lp_en:1; + /** aon_efuse_mem_force_ctrl : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control efuse memory, disable hardware control. + */ + uint32_t aon_efuse_mem_force_ctrl:1; + /** aon_huk_mem_lp_mode : R/W; bitpos: [5:4]; default: 2; + * Configures huk memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ + uint32_t aon_huk_mem_lp_mode:2; + /** aon_huk_mem_lp_en : R/W; bitpos: [6]; default: 0; + * Set this bit to power down huk memory. + */ + uint32_t aon_huk_mem_lp_en:1; + /** aon_huk_mem_force_ctrl : R/W; bitpos: [7]; default: 0; + * Set this bit to force software control huk memory, disable hardware control. + */ + uint32_t aon_huk_mem_force_ctrl:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_mem_ctrl_reg_t; + +/** Type of aon_hp_mem_ctrl register + * configure rmemory power in lp system register + */ +typedef union { + struct { + /** aon_modem_mem_lp_mode : R/W; bitpos: [1:0]; default: 0; + * Configures modem memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ + uint32_t aon_modem_mem_lp_mode:2; + /** aon_modem_mem_lp_en : R/W; bitpos: [2]; default: 0; + * Set this bit to power down modem memory. + */ + uint32_t aon_modem_mem_lp_en:1; + /** aon_modem_mem_force_ctrl : R/W; bitpos: [3]; default: 0; + * Set this bit to force software control modem memory, disable hardware control. + */ + uint32_t aon_modem_mem_force_ctrl:1; + /** aon_mmu_mem_lp_mode : R/W; bitpos: [5:4]; default: 0; + * Configures mmu memory low power mode in low power stage. + * 0: deep sleep + * 1: light sleep + * 2(default): shut down + * 3: disable low power stage + */ + uint32_t aon_mmu_mem_lp_mode:2; + /** aon_mmu_mem_lp_en : R/W; bitpos: [6]; default: 0; + * Set this bit to power down mmu memory. + */ + uint32_t aon_mmu_mem_lp_en:1; + /** aon_mmu_mem_force_ctrl : R/W; bitpos: [7]; default: 0; + * Set this bit to force software control mmu memory, disable hardware control. + */ + uint32_t aon_mmu_mem_force_ctrl:1; + uint32_t reserved_8:8; + /** aon_hp_sram_mem_lp_mode : R/W; bitpos: [17:16]; default: 0; + * Configures hp_sram memory low power mode in low power stage. + * 0(default): deep sleep + * 1: light sleep + * 2: shut down + * 3: disable low power stage + */ + uint32_t aon_hp_sram_mem_lp_mode:2; + /** aon_hp_sram_mem_lp_en : R/W; bitpos: [24:18]; default: 0; + * Set this bit to power down hp_sram memory. + */ + uint32_t aon_hp_sram_mem_lp_en:7; + /** aon_hp_sram_mem_force_ctrl : R/W; bitpos: [31:25]; default: 0; + * Set this bit to force software control hp_sram memory, disable hardware control. + */ + uint32_t aon_hp_sram_mem_force_ctrl:7; + }; + uint32_t val; +} lp_aon_hp_mem_ctrl_reg_t; + +/** Type of aon_io_ldo_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** aon_io_ldo_3p3_sw : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t aon_io_ldo_3p3_sw:1; + /** aon_io_ldo_3p3_sw_en : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t aon_io_ldo_3p3_sw_en:1; + /** aon_io_ldo_adjust_sw : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t aon_io_ldo_adjust_sw:8; + /** aon_io_ldo_adjust_sw_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_io_ldo_adjust_sw_en:1; + }; + uint32_t val; +} lp_aon_io_ldo_cfg_reg_t; + +/** Type of aon_lp_gpio_security register + * need des + */ +typedef union { + struct { + /** aon_lp_gpio_lock : R/W; bitpos: [5:0]; default: 0; + * This field decides whether lp_gpio_config can be locked, or not. 0 (default): + * unlocked. 1: locked. + */ + uint32_t aon_lp_gpio_lock:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_aon_lp_gpio_security_reg_t; + +/** Type of aon_hp_gpio_security_1 register + * need des + */ +typedef union { + struct { + /** aon_hp_gpio_lock_p1 : R/W; bitpos: [31:0]; default: 0; + * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ + uint32_t aon_hp_gpio_lock_p1:32; + }; + uint32_t val; +} lp_aon_hp_gpio_security_1_reg_t; + +/** Type of aon_hp_gpio_security_2 register + * need des + */ +typedef union { + struct { + /** aon_hp_gpio_lock_p2 : R/W; bitpos: [7:0]; default: 0; + * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ + uint32_t aon_hp_gpio_lock_p2:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_hp_gpio_security_2_reg_t; + +/** Type of aon_sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + /** aon_dcache_usage : R/W; bitpos: [0]; default: 0; + * hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is + * used to control the first layer(Layer0) usage. 0: cpu use hp-memory. 1: dcache use + * hp-mmory. + * By default, dcache is closed, and typically users can enable dcache after + * boot-loader, but before user's BIN start running. + */ + uint32_t aon_dcache_usage:1; + /** aon_icache1_usage : R/W; bitpos: [1]; default: 1; + * hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is + * used to control the last layer(Layer6) usage. 0: cpu use hp-memory. 1: icache1 use + * hp-mmory. + * By default, icache1 is not disabled, and the last layer memory belongs to icache1. + * Typically users can set this bit to 0 to disable icache1 in boot-loader. + */ + uint32_t aon_icache1_usage:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_aon_sram_usage_conf_reg_t; + +/** Type of aon_date register + * reserved + */ +typedef union { + struct { + /** aon_date : R/W; bitpos: [30:0]; default: 37823056; + * version register + */ + uint32_t aon_date:31; + /** aon_clk_en : R/W; bitpos: [31]; default: 0; + * version register + */ + uint32_t aon_clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +typedef struct { + volatile lp_aon_store0_reg_t store0; + volatile lp_aon_store1_reg_t store1; + volatile lp_aon_store2_reg_t store2; + volatile lp_aon_store3_reg_t store3; + volatile lp_aon_store4_reg_t store4; + volatile lp_aon_store5_reg_t store5; + volatile lp_aon_store6_reg_t store6; + volatile lp_aon_store7_reg_t store7; + volatile lp_aon_store8_reg_t store8; + volatile lp_aon_store9_reg_t store9; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + uint32_t reserved_030; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore_cfg_reg_t cpucore_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_ext_wakeup_cntl1_reg_t ext_wakeup_cntl1; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + uint32_t reserved_050[8]; + volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0; + volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1; + volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2; + volatile lp_aon_mem_ctrl_reg_t mem_ctrl; + volatile lp_aon_hp_mem_ctrl_reg_t hp_mem_ctrl; + volatile lp_aon_io_ldo_cfg_reg_t io_ldo_cfg; + uint32_t reserved_088; + volatile lp_aon_lp_gpio_security_reg_t lp_gpio_security; + volatile lp_aon_hp_gpio_security_1_reg_t hp_gpio_security_1; + volatile lp_aon_hp_gpio_security_2_reg_t hp_gpio_security_2; + volatile lp_aon_sram_usage_conf_reg_t sram_usage_conf; + uint32_t reserved_09c[216]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_clkrst_reg.h b/components/soc/esp32h4/register/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..6b33916513 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_clkrst_reg.h @@ -0,0 +1,762 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * Configures the root clk of LP system + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the source of LP_SLOW_CLK. + * 0: RC_SLOW_CLK + * 1: XTAL32K_CLK + * 2: RC32K_CLK + * 3:OSC_SLOW_CLK + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1; + * configures the source of LP_FAST_CLK. + * 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + */ +#define LP_CLKRST_FAST_CLK_SEL (BIT(2)) +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0; + * reserved + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 3 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * Configures the clk gate to pad + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * Configures the clock gate to pad of the LP_DYN_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * Configures the clock gate to pad of the LP_DYN_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * Configures the clock gate to pad of the OSC_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * Configures the clock gate to pad of the RC_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * Configures the clock gate to pad of the RC32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * Configures the clock gate to pad of the XTAL32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * Configures the clock gate to pad of the EFUSE_CTRL clock. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * Configures the clock gate to pad of the LP_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * Configures the clock gate to pad of the LP_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * Configures the clock gate to pad of the RNG clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * Configures the clock gate to pad of the LP bus clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * Configure LP root clk source gate + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_BASE + 0x8) +/** LP_CLKRST_RTC_BLE_TIMER_APB_GATE : R/W; bitpos: [27]; default: 1; + * Configures the clock gate to RTC_BLE_TIMER_APB_CLK + * 0: Invalid. The clock gate controlled + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE (BIT(27)) +#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_M (LP_CLKRST_RTC_BLE_TIMER_APB_GATE_V << LP_CLKRST_RTC_BLE_TIMER_APB_GATE_S) +#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_V 0x00000001U +#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_S 27 +/** LP_CLKRST_TOTAL_CORE_EFUSE_GATE : R/W; bitpos: [28]; default: 1; + * Configures the clock gate to TOTAL_EFUSE_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE (BIT(28)) +#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_M (LP_CLKRST_TOTAL_CORE_EFUSE_GATE_V << LP_CLKRST_TOTAL_CORE_EFUSE_GATE_S) +#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_V 0x00000001U +#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_S 28 +/** LP_CLKRST_AON_CORE_EFUSE_GATE : R/W; bitpos: [29]; default: 1; + * Configures the clock gate to CORE_EFUSE_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_AON_CORE_EFUSE_GATE (BIT(29)) +#define LP_CLKRST_AON_CORE_EFUSE_GATE_M (LP_CLKRST_AON_CORE_EFUSE_GATE_V << LP_CLKRST_AON_CORE_EFUSE_GATE_S) +#define LP_CLKRST_AON_CORE_EFUSE_GATE_V 0x00000001U +#define LP_CLKRST_AON_CORE_EFUSE_GATE_S 29 +/** LP_CLKRST_AON_TOUCH_GATE : R/W; bitpos: [30]; default: 1; + * Configures the clock gate to TOUCH_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_AON_TOUCH_GATE (BIT(30)) +#define LP_CLKRST_AON_TOUCH_GATE_M (LP_CLKRST_AON_TOUCH_GATE_V << LP_CLKRST_AON_TOUCH_GATE_S) +#define LP_CLKRST_AON_TOUCH_GATE_V 0x00000001U +#define LP_CLKRST_AON_TOUCH_GATE_S 30 +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * Configures the clock gate to LP_FAST_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * Configures the peri of LP system software reset + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_BASE + 0xc) +/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to reset HUK + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_HUK_RESET_EN (BIT(25)) +#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S) +#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U +#define LP_CLKRST_HUK_RESET_EN_S 25 +/** LP_CLKRST_AON_BLETIMER_RESET_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to reset bletimer part + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_AON_BLETIMER_RESET_EN (BIT(26)) +#define LP_CLKRST_AON_BLETIMER_RESET_EN_M (LP_CLKRST_AON_BLETIMER_RESET_EN_V << LP_CLKRST_AON_BLETIMER_RESET_EN_S) +#define LP_CLKRST_AON_BLETIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_BLETIMER_RESET_EN_S 26 +/** LP_CLKRST_AON_TOUCH_RESET_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to reset TOUCH part + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_AON_TOUCH_RESET_EN (BIT(27)) +#define LP_CLKRST_AON_TOUCH_RESET_EN_M (LP_CLKRST_AON_TOUCH_RESET_EN_V << LP_CLKRST_AON_TOUCH_RESET_EN_S) +#define LP_CLKRST_AON_TOUCH_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_TOUCH_RESET_EN_S 27 +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to reset EFUSE_CTRL always-on part + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to reset LP_TIMER + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to reset LP_WDT and super watch dog + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to reset analog peri, include brownout controller + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CORE0_CAUSE_REG register + * Represents the reset cause + */ +#define LP_CLKRST_RESET_CORE0_CAUSE_REG (DR_REG_LP_BASE + 0x10) +/** LP_CLKRST_CORE0_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ +#define LP_CLKRST_CORE0_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_CORE0_RESET_CAUSE_M (LP_CLKRST_CORE0_RESET_CAUSE_V << LP_CLKRST_CORE0_RESET_CAUSE_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_CORE0_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * 0: no operation + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_RESET_CORE1_CAUSE_REG register + * Represents the reset cause + */ +#define LP_CLKRST_RESET_CORE1_CAUSE_REG (DR_REG_LP_BASE + 0x14) +/** LP_CLKRST_CORE1_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ +#define LP_CLKRST_CORE1_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_CORE1_RESET_CAUSE_M (LP_CLKRST_CORE1_RESET_CAUSE_V << LP_CLKRST_CORE1_RESET_CAUSE_S) +#define LP_CLKRST_CORE1_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_CORE1_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE1_RESET_FLAG : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ +#define LP_CLKRST_CORE1_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE1_RESET_FLAG_M (LP_CLKRST_CORE1_RESET_FLAG_V << LP_CLKRST_CORE1_RESET_FLAG_S) +#define LP_CLKRST_CORE1_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE1_RESET_FLAG_S 5 +/** LP_CLKRST_CORE1_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * 0: no operation + */ +#define LP_CLKRST_CORE1_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_M (LP_CLKRST_CORE1_RESET_CAUSE_CLR_V << LP_CLKRST_CORE1_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE1_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ +#define LP_CLKRST_CORE1_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE1_RESET_FLAG_SET_M (LP_CLKRST_CORE1_RESET_FLAG_SET_V << LP_CLKRST_CORE1_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE1_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE1_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ +#define LP_CLKRST_CORE1_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE1_RESET_FLAG_CLR_M (LP_CLKRST_CORE1_RESET_FLAG_CLR_V << LP_CLKRST_CORE1_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE1_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE1_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_CORE0_RESET_REG register + * Configures CPU reset + */ +#define LP_CLKRST_CPU_CORE0_RESET_REG (DR_REG_LP_BASE + 0x18) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21 +/** LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_S 25 +/** LP_CLKRST_CPU_CORE0_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_CPU_CORE0_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_CORE0_STALL_WAIT_M (LP_CLKRST_CPU_CORE0_STALL_WAIT_V << LP_CLKRST_CPU_CORE0_STALL_WAIT_S) +#define LP_CLKRST_CPU_CORE0_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_CORE0_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_CORE0_STALL_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ +#define LP_CLKRST_CPU_CORE0_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_CORE0_STALL_EN_M (LP_CLKRST_CPU_CORE0_STALL_EN_V << LP_CLKRST_CPU_CORE0_STALL_EN_S) +#define LP_CLKRST_CPU_CORE0_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_CORE0_STALL_EN_S 31 + +/** LP_CLKRST_CPU_CORE1_RESET_REG register + * Configures CPU reset + */ +#define LP_CLKRST_CPU_CORE1_RESET_REG (DR_REG_LP_BASE + 0x1c) +/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(21)) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 21 +/** LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_S 25 +/** LP_CLKRST_CPU_CORE1_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_CPU_CORE1_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_CORE1_STALL_WAIT_M (LP_CLKRST_CPU_CORE1_STALL_WAIT_V << LP_CLKRST_CPU_CORE1_STALL_WAIT_S) +#define LP_CLKRST_CPU_CORE1_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_CORE1_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_CORE1_STALL_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ +#define LP_CLKRST_CPU_CORE1_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_CORE1_STALL_EN_M (LP_CLKRST_CPU_CORE1_STALL_EN_V << LP_CLKRST_CPU_CORE1_STALL_EN_S) +#define LP_CLKRST_CPU_CORE1_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_CORE1_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * Configures the RC_FAST_CLK frequency + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_BASE + 0x20) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 547; + * Configures the RC_FAST_CLK frequency,the clock frequency will increase with this + * field + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_SOSC_CNTL_REG register + * Configures the RC_SLOW_CLK frequency + */ +#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_BASE + 0x24) +/** LP_CLKRST_SLOW_DFREQ : R/W; bitpos: [31:26]; default: 10; + * Configures the RC_SLOW_CLK frequency,the clock frequency will increase with this + * field + */ +#define LP_CLKRST_SLOW_DFREQ 0x0000003FU +#define LP_CLKRST_SLOW_DFREQ_M (LP_CLKRST_SLOW_DFREQ_V << LP_CLKRST_SLOW_DFREQ_S) +#define LP_CLKRST_SLOW_DFREQ_V 0x0000003FU +#define LP_CLKRST_SLOW_DFREQ_S 26 + +/** LP_CLKRST_RC32K_CNTL_REG register + * Configures the RC32K_CLK frequency + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_BASE + 0x28) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; + * Configures the RC32K_CLK frequency, the clock frequency will increase with this + * field + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * Configures the clk gate of LP clk to HP system + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_BASE + 0x2c) +/** LP_CLKRST_CLK_PWR_FOSC_EN : R/W; bitpos: [25]; default: 1; + * Configures the clock gate to modem of the fosc clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_CLK_PWR_FOSC_EN (BIT(25)) +#define LP_CLKRST_CLK_PWR_FOSC_EN_M (LP_CLKRST_CLK_PWR_FOSC_EN_V << LP_CLKRST_CLK_PWR_FOSC_EN_S) +#define LP_CLKRST_CLK_PWR_FOSC_EN_V 0x00000001U +#define LP_CLKRST_CLK_PWR_FOSC_EN_S 25 +/** LP_CLKRST_CLK_PWR_XTAL_EN : R/W; bitpos: [26]; default: 1; + * Configures the clock gate to modem of the xtal clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_CLK_PWR_XTAL_EN (BIT(26)) +#define LP_CLKRST_CLK_PWR_XTAL_EN_M (LP_CLKRST_CLK_PWR_XTAL_EN_V << LP_CLKRST_CLK_PWR_XTAL_EN_S) +#define LP_CLKRST_CLK_PWR_XTAL_EN_V 0x00000001U +#define LP_CLKRST_CLK_PWR_XTAL_EN_S 26 +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * Configures the clk gate of XTAL32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * Configures the clk gate of RC_SLOW_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * Configures the clk gate of RC32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * Configures the clk gate of RC_FAST_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * Configures the LP_MEM clk gate force parameter + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_BASE + 0x30) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * Configures whether ot not force open the clock gate of LP MEM + * 0: Invalid. The clock gate controlled by hardware FSM + * 1: Force open clock gate of LP MEM + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * Configures the XTAL32K parameter + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_BASE + 0x34) +/** LP_CLKRST_RTC_SEL_POWER_XTAL32K : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K (BIT(21)) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_M (LP_CLKRST_RTC_SEL_POWER_XTAL32K_V << LP_CLKRST_RTC_SEL_POWER_XTAL32K_S) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_V 0x00000001U +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_S 21 +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * Configures DRES + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * Configures DGM + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * Configures DBUF + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * Configures DAC + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_CALI0_REG register + * need_des + */ +#define LP_CLKRST_CALI0_REG (DR_REG_LP_BASE + 0x38) +/** LP_CLKRST_LP_CALI_DIV_CYCLE : R/W; bitpos: [7:0]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_CYCLE 0x000000FFU +#define LP_CLKRST_LP_CALI_DIV_CYCLE_M (LP_CLKRST_LP_CALI_DIV_CYCLE_V << LP_CLKRST_LP_CALI_DIV_CYCLE_S) +#define LP_CLKRST_LP_CALI_DIV_CYCLE_V 0x000000FFU +#define LP_CLKRST_LP_CALI_DIV_CYCLE_S 0 +/** LP_CLKRST_LP_CALI_FULL_CNT_DONE : RO; bitpos: [8]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE (BIT(8)) +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_M (LP_CLKRST_LP_CALI_FULL_CNT_DONE_V << LP_CLKRST_LP_CALI_FULL_CNT_DONE_S) +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_V 0x00000001U +#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_S 8 +/** LP_CLKRST_LP_CALI_DIV_CALI_CNT : RO; bitpos: [24:9]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_M (LP_CLKRST_LP_CALI_DIV_CALI_CNT_V << LP_CLKRST_LP_CALI_DIV_CALI_CNT_S) +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_S 9 +/** LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE (BIT(25)) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V 0x00000001U +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S 25 +/** LP_CLKRST_LP_CALI_DIV_NUM : RO; bitpos: [31:26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUM 0x0000003FU +#define LP_CLKRST_LP_CALI_DIV_NUM_M (LP_CLKRST_LP_CALI_DIV_NUM_V << LP_CLKRST_LP_CALI_DIV_NUM_S) +#define LP_CLKRST_LP_CALI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_CALI_DIV_NUM_S 26 + +/** LP_CLKRST_CALI1_REG register + * need_des + */ +#define LP_CLKRST_CALI1_REG (DR_REG_LP_BASE + 0x3c) +/** LP_CLKRST_LP_CALI_DIV_NUMERATOR : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_S) +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_S 0 +/** LP_CLKRST_LP_CALI_DIV_DENOMINATOR : RO; bitpos: [31:16]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_M (LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V << LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S) +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S 16 + +/** LP_CLKRST_CALI2_REG register + * need_des + */ +#define LP_CLKRST_CALI2_REG (DR_REG_LP_BASE + 0x40) +/** LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD : R/W; bitpos: [8:0]; default: 255; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD 0x000001FFU +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_M (LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V << LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S) +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V 0x000001FFU +#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S 0 +/** LP_CLKRST_LP_CALI_DIV_SLP_VAL : R/W; bitpos: [30:15]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_M (LP_CLKRST_LP_CALI_DIV_SLP_VAL_V << LP_CLKRST_LP_CALI_DIV_SLP_VAL_S) +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_V 0x0000FFFFU +#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_S 15 +/** LP_CLKRST_LP_CALI_DIV_TIMER_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN (BIT(31)) +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_M (LP_CLKRST_LP_CALI_DIV_TIMER_EN_V << LP_CLKRST_LP_CALI_DIV_TIMER_EN_S) +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_V 0x00000001U +#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_BASE + 0x44) +/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [11]; default: 1; + * Configures the source clk of HUK + * 0: 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + */ +#define LP_CLKRST_HUK_CLK_SEL (BIT(11)) +#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S) +#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U +#define LP_CLKRST_HUK_CLK_SEL_S 11 +/** LP_CLKRST_LP_BLETIMER_DIV_NUM : R/W; bitpos: [23:12]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_DIV_NUM 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_M (LP_CLKRST_LP_BLETIMER_DIV_NUM_V << LP_CLKRST_LP_BLETIMER_DIV_NUM_S) +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_V 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_S 12 +/** LP_CLKRST_LP_BLETIMER_32K_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_32K_SEL 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_M (LP_CLKRST_LP_BLETIMER_32K_SEL_V << LP_CLKRST_LP_BLETIMER_32K_SEL_S) +#define LP_CLKRST_LP_BLETIMER_32K_SEL_V 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_S 24 +/** LP_CLKRST_LP_SEL_OSC_SLOW : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_SLOW (BIT(26)) +#define LP_CLKRST_LP_SEL_OSC_SLOW_M (LP_CLKRST_LP_SEL_OSC_SLOW_V << LP_CLKRST_LP_SEL_OSC_SLOW_S) +#define LP_CLKRST_LP_SEL_OSC_SLOW_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_SLOW_S 26 +/** LP_CLKRST_LP_SEL_OSC_FAST : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_FAST (BIT(27)) +#define LP_CLKRST_LP_SEL_OSC_FAST_M (LP_CLKRST_LP_SEL_OSC_FAST_V << LP_CLKRST_LP_SEL_OSC_FAST_S) +#define LP_CLKRST_LP_SEL_OSC_FAST_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_FAST_S 27 +/** LP_CLKRST_LP_SEL_XTAL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL (BIT(28)) +#define LP_CLKRST_LP_SEL_XTAL_M (LP_CLKRST_LP_SEL_XTAL_V << LP_CLKRST_LP_SEL_XTAL_S) +#define LP_CLKRST_LP_SEL_XTAL_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL_S 28 +/** LP_CLKRST_LP_SEL_XTAL32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL32K (BIT(29)) +#define LP_CLKRST_LP_SEL_XTAL32K_M (LP_CLKRST_LP_SEL_XTAL32K_V << LP_CLKRST_LP_SEL_XTAL32K_S) +#define LP_CLKRST_LP_SEL_XTAL32K_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * Version control register + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37818640; + * Version control register + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * configure register clk bypass clk gate + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_clkrst_struct.h b/components/soc/esp32h4/register/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..a036d8073f --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_clkrst_struct.h @@ -0,0 +1,646 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * Configures the root clk of LP system + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the source of LP_SLOW_CLK. + * 0: RC_SLOW_CLK + * 1: XTAL32K_CLK + * 2: RC32K_CLK + * 3:OSC_SLOW_CLK + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [2]; default: 1; + * configures the source of LP_FAST_CLK. + * 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + */ + uint32_t fast_clk_sel:1; + /** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0; + * reserved + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * Configures the clk gate to pad + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * Configures the clock gate to pad of the LP_DYN_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * Configures the clock gate to pad of the LP_DYN_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * Configures the clock gate to pad of the OSC_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * Configures the clock gate to pad of the RC_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * Configures the clock gate to pad of the RC32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * Configures the clock gate to pad of the XTAL32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * Configures the clock gate to pad of the EFUSE_CTRL clock. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * Configures the clock gate to pad of the LP_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * Configures the clock gate to pad of the LP_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * Configures the clock gate to pad of the RNG clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * Configures the clock gate to pad of the LP bus clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * Configure LP root clk source gate + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** rtc_ble_timer_apb_gate : R/W; bitpos: [27]; default: 1; + * Configures the clock gate to RTC_BLE_TIMER_APB_CLK + * 0: Invalid. The clock gate controlled + * 1: Force the clk pass clock gate + */ + uint32_t rtc_ble_timer_apb_gate:1; + /** total_core_efuse_gate : R/W; bitpos: [28]; default: 1; + * Configures the clock gate to TOTAL_EFUSE_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ + uint32_t total_core_efuse_gate:1; + /** aon_core_efuse_gate : R/W; bitpos: [29]; default: 1; + * Configures the clock gate to CORE_EFUSE_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ + uint32_t aon_core_efuse_gate:1; + /** aon_touch_gate : R/W; bitpos: [30]; default: 1; + * Configures the clock gate to TOUCH_AON_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ + uint32_t aon_touch_gate:1; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * Configures the clock gate to LP_FAST_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * Configures the peri of LP system software reset + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** huk_reset_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to reset HUK + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t huk_reset_en:1; + /** aon_bletimer_reset_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to reset bletimer part + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t aon_bletimer_reset_en:1; + /** aon_touch_reset_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to reset TOUCH part + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t aon_touch_reset_en:1; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to reset EFUSE_CTRL always-on part + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to reset LP_TIMER + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to reset LP_WDT and super watch dog + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to reset analog peri, include brownout controller + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_core0_cause register + * Represents the reset cause + */ +typedef union { + struct { + /** core0_reset_cause : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ + uint32_t core0_reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * 0: no operation + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_core0_cause_reg_t; + +/** Type of reset_core1_cause register + * Represents the reset cause + */ +typedef union { + struct { + /** core1_reset_cause : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ + uint32_t core1_reset_cause:5; + /** core1_reset_flag : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ + uint32_t core1_reset_flag:1; + uint32_t reserved_6:23; + /** core1_reset_cause_clr : WT; bitpos: [29]; default: 0; + * 0: no operation + */ + uint32_t core1_reset_cause_clr:1; + /** core1_reset_flag_set : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ + uint32_t core1_reset_flag_set:1; + /** core1_reset_flag_clr : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ + uint32_t core1_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_core1_cause_reg_t; + +/** Type of cpu_core0_reset register + * Configures CPU reset + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ + uint32_t hpcore0_lockup_reset_en:1; + /** rtc_wdt_cpu_core0_reset_length : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t rtc_wdt_cpu_core0_reset_length:3; + /** rtc_wdt_cpu_core0_reset_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ + uint32_t rtc_wdt_cpu_core0_reset_en:1; + /** cpu_core0_stall_wait : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t cpu_core0_stall_wait:5; + /** cpu_core0_stall_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ + uint32_t cpu_core0_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_core0_reset_reg_t; + +/** Type of cpu_core1_reset register + * Configures CPU reset + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hpcore1_lockup_reset_en : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ + uint32_t hpcore1_lockup_reset_en:1; + /** rtc_wdt_cpu_core1_reset_length : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t rtc_wdt_cpu_core1_reset_length:3; + /** rtc_wdt_cpu_core1_reset_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ + uint32_t rtc_wdt_cpu_core1_reset_en:1; + /** cpu_core1_stall_wait : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t cpu_core1_stall_wait:5; + /** cpu_core1_stall_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ + uint32_t cpu_core1_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_core1_reset_reg_t; + +/** Type of fosc_cntl register + * Configures the RC_FAST_CLK frequency + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 547; + * Configures the RC_FAST_CLK frequency,the clock frequency will increase with this + * field + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of sosc_cntl register + * Configures the RC_SLOW_CLK frequency + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** slow_dfreq : R/W; bitpos: [31:26]; default: 10; + * Configures the RC_SLOW_CLK frequency,the clock frequency will increase with this + * field + */ + uint32_t slow_dfreq:6; + }; + uint32_t val; +} lp_clkrst_sosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * Configures the RC32K_CLK frequency + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + * Configures the RC32K_CLK frequency, the clock frequency will increase with this + * field + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * Configures the clk gate of LP clk to HP system + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** clk_pwr_fosc_en : R/W; bitpos: [25]; default: 1; + * Configures the clock gate to modem of the fosc clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t clk_pwr_fosc_en:1; + /** clk_pwr_xtal_en : R/W; bitpos: [26]; default: 1; + * Configures the clock gate to modem of the xtal clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t clk_pwr_xtal_en:1; + uint32_t reserved_27:1; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * Configures the clk gate of XTAL32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * Configures the clk gate of RC_SLOW_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * Configures the clk gate of RC32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * Configures the clk gate of RC_FAST_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * Configures the LP_MEM clk gate force parameter + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * Configures whether ot not force open the clock gate of LP MEM + * 0: Invalid. The clock gate controlled by hardware FSM + * 1: Force open clock gate of LP MEM + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of xtal32k register + * Configures the XTAL32K parameter + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** rtc_sel_power_xtal32k : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t rtc_sel_power_xtal32k:1; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * Configures DRES + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * Configures DGM + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * Configures DBUF + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * Configures DAC + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of cali0 register + * need_des + */ +typedef union { + struct { + /** lp_cali_div_cycle : R/W; bitpos: [7:0]; default: 1; + * need_des + */ + uint32_t lp_cali_div_cycle:8; + /** lp_cali_full_cnt_done : RO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t lp_cali_full_cnt_done:1; + /** lp_cali_div_cali_cnt : RO; bitpos: [24:9]; default: 0; + * need_des + */ + uint32_t lp_cali_div_cali_cnt:16; + /** lp_cali_div_numerator_type : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_cali_div_numerator_type:1; + /** lp_cali_div_num : RO; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t lp_cali_div_num:6; + }; + uint32_t val; +} lp_clkrst_cali0_reg_t; + +/** Type of cali1 register + * need_des + */ +typedef union { + struct { + /** lp_cali_div_numerator : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cali_div_numerator:16; + /** lp_cali_div_denominator : RO; bitpos: [31:16]; default: 0; + * need_des + */ + uint32_t lp_cali_div_denominator:16; + }; + uint32_t val; +} lp_clkrst_cali1_reg_t; + +/** Type of cali2 register + * need_des + */ +typedef union { + struct { + /** lp_cali_div_wait_pwr_good : R/W; bitpos: [8:0]; default: 255; + * need_des + */ + uint32_t lp_cali_div_wait_pwr_good:9; + uint32_t reserved_9:6; + /** lp_cali_div_slp_val : R/W; bitpos: [30:15]; default: 1; + * need_des + */ + uint32_t lp_cali_div_slp_val:16; + /** lp_cali_div_timer_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cali_div_timer_en:1; + }; + uint32_t val; +} lp_clkrst_cali2_reg_t; + +/** Type of lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** huk_clk_sel : R/W; bitpos: [11]; default: 1; + * Configures the source clk of HUK + * 0: 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + */ + uint32_t huk_clk_sel:1; + /** lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0; + * need_des + */ + uint32_t lp_bletimer_div_num:12; + /** lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t lp_bletimer_32k_sel:2; + /** lp_sel_osc_slow : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_sel_osc_slow:1; + /** lp_sel_osc_fast : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sel_osc_fast:1; + /** lp_sel_xtal : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sel_xtal:1; + /** lp_sel_xtal32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sel_xtal32k:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 37818640; + * Version control register + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * configure register clk bypass clk gate + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_core0_cause_reg_t reset_core0_cause; + volatile lp_clkrst_reset_core1_cause_reg_t reset_core1_cause; + volatile lp_clkrst_cpu_core0_reset_reg_t cpu_core0_reset; + volatile lp_clkrst_cpu_core1_reset_reg_t cpu_core1_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + volatile lp_clkrst_cali0_reg_t cali0; + volatile lp_clkrst_cali1_reg_t cali1; + volatile lp_clkrst_cali2_reg_t cali2; + volatile lp_clkrst_lpperi_reg_t lpperi; + uint32_t reserved_048[237]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_gpio_reg.h b/components/soc/esp32h4/register/soc/lp_gpio_reg.h new file mode 100644 index 0000000000..60b0d0921c --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_gpio_reg.h @@ -0,0 +1,778 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_GPIO_OUT_REG register + * LP_GPIO output register + */ +#define LP_GPIO_OUT_REG (DR_REG_LP_BASE + 0x4) +/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [5:0]; default: 0; + * Configures the output value of LP_GPIO0 ~ 5 output in simple LP_GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit0 ~ bit5 correspond to the output value of LP_GPIO0 ~ LP_GPIO5 + * respectively. Bitxx ~ bitxx is invalid. + */ +#define LP_GPIO_OUT_DATA_ORIG 0x0000003FU +#define LP_GPIO_OUT_DATA_ORIG_M (LP_GPIO_OUT_DATA_ORIG_V << LP_GPIO_OUT_DATA_ORIG_S) +#define LP_GPIO_OUT_DATA_ORIG_V 0x0000003FU +#define LP_GPIO_OUT_DATA_ORIG_S 0 + +/** LP_GPIO_OUT_W1TS_REG register + * LP_GPIO output set register + */ +#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_BASE + 0x8) +/** LP_GPIO_OUT_W1TS : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~ + * LP_GPIO5. + * 0: Not set + * 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1 + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set LP_GPIO_OUT_REG. + */ +#define LP_GPIO_OUT_W1TS 0x0000003FU +#define LP_GPIO_OUT_W1TS_M (LP_GPIO_OUT_W1TS_V << LP_GPIO_OUT_W1TS_S) +#define LP_GPIO_OUT_W1TS_V 0x0000003FU +#define LP_GPIO_OUT_W1TS_S 0 + +/** LP_GPIO_OUT_W1TC_REG register + * LP_GPIO output clear register + */ +#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_BASE + 0xc) +/** LP_GPIO_OUT_W1TC : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0 + * ~ LP_GPIO5 output. + * 0: Not clear + * 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared. + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear LP_GPIO_OUT_REG. + */ +#define LP_GPIO_OUT_W1TC 0x0000003FU +#define LP_GPIO_OUT_W1TC_M (LP_GPIO_OUT_W1TC_V << LP_GPIO_OUT_W1TC_S) +#define LP_GPIO_OUT_W1TC_V 0x0000003FU +#define LP_GPIO_OUT_W1TC_S 0 + +/** LP_GPIO_ENABLE_REG register + * LP_GPIO output enable register + */ +#define LP_GPIO_ENABLE_REG (DR_REG_LP_BASE + 0x10) +/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [5:0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO5. + * 0: Not enable + * 1: Enable + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + */ +#define LP_GPIO_ENABLE_DATA 0x0000003FU +#define LP_GPIO_ENABLE_DATA_M (LP_GPIO_ENABLE_DATA_V << LP_GPIO_ENABLE_DATA_S) +#define LP_GPIO_ENABLE_DATA_V 0x0000003FU +#define LP_GPIO_ENABLE_DATA_S 0 + +/** LP_GPIO_ENABLE_W1TS_REG register + * LP_GPIO output enable set register + */ +#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_BASE + 0x14) +/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO5. + * 0: Not set + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1 + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set LP_GPIO_ENABLE_REG. + */ +#define LP_GPIO_ENABLE_W1TS 0x0000003FU +#define LP_GPIO_ENABLE_W1TS_M (LP_GPIO_ENABLE_W1TS_V << LP_GPIO_ENABLE_W1TS_S) +#define LP_GPIO_ENABLE_W1TS_V 0x0000003FU +#define LP_GPIO_ENABLE_W1TS_S 0 + +/** LP_GPIO_ENABLE_W1TC_REG register + * LP_GPIO output enable clear register + */ +#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_BASE + 0x18) +/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO5. + * 0: Not clear + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear LP_GPIO_ENABLE_REG. + */ +#define LP_GPIO_ENABLE_W1TC 0x0000003FU +#define LP_GPIO_ENABLE_W1TC_M (LP_GPIO_ENABLE_W1TC_V << LP_GPIO_ENABLE_W1TC_S) +#define LP_GPIO_ENABLE_W1TC_V 0x0000003FU +#define LP_GPIO_ENABLE_W1TC_S 0 + +/** LP_GPIO_IN_REG register + * LP_GPIO input register + */ +#define LP_GPIO_IN_REG (DR_REG_LP_BASE + 0x1c) +/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [5:0]; default: 0; + * Represents the input value of LP_GPIO0 ~ LP_GPIO5. Each bit represents a pin input + * value: + * 0: Low level + * 1: High level + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + */ +#define LP_GPIO_IN_DATA_NEXT 0x0000003FU +#define LP_GPIO_IN_DATA_NEXT_M (LP_GPIO_IN_DATA_NEXT_V << LP_GPIO_IN_DATA_NEXT_S) +#define LP_GPIO_IN_DATA_NEXT_V 0x0000003FU +#define LP_GPIO_IN_DATA_NEXT_S 0 + +/** LP_GPIO_STATUS_REG register + * LP_GPIO interrupt status register + */ +#define LP_GPIO_STATUS_REG (DR_REG_LP_BASE + 0x20) +/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [5:0]; default: 0; + * The interrupt status of LP_GPIO0 ~ LP_GPIO5, can be configured by the software. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - Each bit represents the status of its corresponding LP_GPIO: + * + * - 0: Represents the LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the LP_GPIO generates the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software. + * + */ +#define LP_GPIO_STATUS_INTERRUPT 0x0000003FU +#define LP_GPIO_STATUS_INTERRUPT_M (LP_GPIO_STATUS_INTERRUPT_V << LP_GPIO_STATUS_INTERRUPT_S) +#define LP_GPIO_STATUS_INTERRUPT_V 0x0000003FU +#define LP_GPIO_STATUS_INTERRUPT_S 0 + +/** LP_GPIO_STATUS_W1TS_REG register + * LP_GPIO interrupt status set register + */ +#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_BASE + 0x24) +/** LP_GPIO_STATUS_W1TS : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set LP_GPIO_STATUS_INTERRUPT. + */ +#define LP_GPIO_STATUS_W1TS 0x0000003FU +#define LP_GPIO_STATUS_W1TS_M (LP_GPIO_STATUS_W1TS_V << LP_GPIO_STATUS_W1TS_S) +#define LP_GPIO_STATUS_W1TS_V 0x0000003FU +#define LP_GPIO_STATUS_W1TS_S 0 + +/** LP_GPIO_STATUS_W1TC_REG register + * LP_GPIO interrupt status clear register + */ +#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_BASE + 0x28) +/** LP_GPIO_STATUS_W1TC : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear LP_GPIO_STATUS_INTERRUPT. + */ +#define LP_GPIO_STATUS_W1TC 0x0000003FU +#define LP_GPIO_STATUS_W1TC_M (LP_GPIO_STATUS_W1TC_V << LP_GPIO_STATUS_W1TC_S) +#define LP_GPIO_STATUS_W1TC_V 0x0000003FU +#define LP_GPIO_STATUS_W1TC_S 0 + +/** LP_GPIO_STATUS_NEXT_REG register + * LP_GPIO interrupt source register + */ +#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_BASE + 0x2c) +/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [5:0]; default: 0; + * Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO5. + * Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Each bit represents: + * 0: The LP_GPIO does not generate the interrupt configured by LP_GPIO_PIN$n_INT_TYPE. + * 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE. + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt. + */ +#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x0000003FU +#define LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_STATUS_INTERRUPT_NEXT_S) +#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x0000003FU +#define LP_GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_GPIO_PIN0_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN0_REG (DR_REG_LP_BASE + 0x30) +/** LP_GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN0_SYNC2_BYPASS_M (LP_GPIO_PIN0_SYNC2_BYPASS_V << LP_GPIO_PIN0_SYNC2_BYPASS_S) +#define LP_GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN0_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_PIN0_PAD_DRIVER_S) +#define LP_GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN0_PAD_DRIVER_S 2 +/** LP_GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN0_SYNC1_BYPASS_M (LP_GPIO_PIN0_SYNC1_BYPASS_V << LP_GPIO_PIN0_SYNC1_BYPASS_S) +#define LP_GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN0_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN0_INT_TYPE 0x00000007U +#define LP_GPIO_PIN0_INT_TYPE_M (LP_GPIO_PIN0_INT_TYPE_V << LP_GPIO_PIN0_INT_TYPE_S) +#define LP_GPIO_PIN0_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN0_INT_TYPE_S 7 +/** LP_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_PIN0_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN1_REG register + * LP_GPIO1 configuration register + */ +#define LP_GPIO_PIN1_REG (DR_REG_LP_BASE + 0x34) +/** LP_GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN1_SYNC2_BYPASS_M (LP_GPIO_PIN1_SYNC2_BYPASS_V << LP_GPIO_PIN1_SYNC2_BYPASS_S) +#define LP_GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN1_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_PIN1_PAD_DRIVER_S) +#define LP_GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN1_PAD_DRIVER_S 2 +/** LP_GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN1_SYNC1_BYPASS_M (LP_GPIO_PIN1_SYNC1_BYPASS_V << LP_GPIO_PIN1_SYNC1_BYPASS_S) +#define LP_GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN1_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN1_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN1_INT_TYPE 0x00000007U +#define LP_GPIO_PIN1_INT_TYPE_M (LP_GPIO_PIN1_INT_TYPE_V << LP_GPIO_PIN1_INT_TYPE_S) +#define LP_GPIO_PIN1_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN1_INT_TYPE_S 7 +/** LP_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_PIN1_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN2_REG register + * LP_GPIO2 configuration register + */ +#define LP_GPIO_PIN2_REG (DR_REG_LP_BASE + 0x38) +/** LP_GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN2_SYNC2_BYPASS_M (LP_GPIO_PIN2_SYNC2_BYPASS_V << LP_GPIO_PIN2_SYNC2_BYPASS_S) +#define LP_GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN2_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_PIN2_PAD_DRIVER_S) +#define LP_GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN2_PAD_DRIVER_S 2 +/** LP_GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN2_SYNC1_BYPASS_M (LP_GPIO_PIN2_SYNC1_BYPASS_V << LP_GPIO_PIN2_SYNC1_BYPASS_S) +#define LP_GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN2_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN2_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN2_INT_TYPE 0x00000007U +#define LP_GPIO_PIN2_INT_TYPE_M (LP_GPIO_PIN2_INT_TYPE_V << LP_GPIO_PIN2_INT_TYPE_S) +#define LP_GPIO_PIN2_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN2_INT_TYPE_S 7 +/** LP_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_PIN2_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN3_REG register + * LP_GPIO3 configuration register + */ +#define LP_GPIO_PIN3_REG (DR_REG_LP_BASE + 0x3c) +/** LP_GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN3_SYNC2_BYPASS_M (LP_GPIO_PIN3_SYNC2_BYPASS_V << LP_GPIO_PIN3_SYNC2_BYPASS_S) +#define LP_GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN3_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_PIN3_PAD_DRIVER_S) +#define LP_GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN3_PAD_DRIVER_S 2 +/** LP_GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN3_SYNC1_BYPASS_M (LP_GPIO_PIN3_SYNC1_BYPASS_V << LP_GPIO_PIN3_SYNC1_BYPASS_S) +#define LP_GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN3_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN3_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN3_INT_TYPE 0x00000007U +#define LP_GPIO_PIN3_INT_TYPE_M (LP_GPIO_PIN3_INT_TYPE_V << LP_GPIO_PIN3_INT_TYPE_S) +#define LP_GPIO_PIN3_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN3_INT_TYPE_S 7 +/** LP_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_PIN3_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN4_REG register + * LP_GPIO4 configuration register + */ +#define LP_GPIO_PIN4_REG (DR_REG_LP_BASE + 0x40) +/** LP_GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN4_SYNC2_BYPASS_M (LP_GPIO_PIN4_SYNC2_BYPASS_V << LP_GPIO_PIN4_SYNC2_BYPASS_S) +#define LP_GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN4_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_PIN4_PAD_DRIVER_S) +#define LP_GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN4_PAD_DRIVER_S 2 +/** LP_GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN4_SYNC1_BYPASS_M (LP_GPIO_PIN4_SYNC1_BYPASS_V << LP_GPIO_PIN4_SYNC1_BYPASS_S) +#define LP_GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN4_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN4_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN4_INT_TYPE 0x00000007U +#define LP_GPIO_PIN4_INT_TYPE_M (LP_GPIO_PIN4_INT_TYPE_V << LP_GPIO_PIN4_INT_TYPE_S) +#define LP_GPIO_PIN4_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN4_INT_TYPE_S 7 +/** LP_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_PIN4_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN5_REG register + * LP_GPIO5 configuration register + */ +#define LP_GPIO_PIN5_REG (DR_REG_LP_BASE + 0x44) +/** LP_GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN5_SYNC2_BYPASS_M (LP_GPIO_PIN5_SYNC2_BYPASS_V << LP_GPIO_PIN5_SYNC2_BYPASS_S) +#define LP_GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN5_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ +#define LP_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_PIN5_PAD_DRIVER_S) +#define LP_GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN5_PAD_DRIVER_S 2 +/** LP_GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ +#define LP_GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN5_SYNC1_BYPASS_M (LP_GPIO_PIN5_SYNC1_BYPASS_V << LP_GPIO_PIN5_SYNC1_BYPASS_S) +#define LP_GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN5_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN5_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ +#define LP_GPIO_PIN5_INT_TYPE 0x00000007U +#define LP_GPIO_PIN5_INT_TYPE_M (LP_GPIO_PIN5_INT_TYPE_V << LP_GPIO_PIN5_INT_TYPE_S) +#define LP_GPIO_PIN5_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN5_INT_TYPE_S 7 +/** LP_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ +#define LP_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_PIN5_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO0 output + */ +#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b0) +/** LP_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC0_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_FUNC0_OUT_INV_SEL_S) +#define LP_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC0_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC0_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_FUNC0_OE_INV_SEL_S) +#define LP_GPIO_FUNC0_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC0_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO1 output + */ +#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b4) +/** LP_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC1_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_FUNC1_OUT_INV_SEL_S) +#define LP_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC1_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC1_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_FUNC1_OE_INV_SEL_S) +#define LP_GPIO_FUNC1_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC1_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO2 output + */ +#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b8) +/** LP_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC2_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_FUNC2_OUT_INV_SEL_S) +#define LP_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC2_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC2_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_FUNC2_OE_INV_SEL_S) +#define LP_GPIO_FUNC2_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC2_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO3 output + */ +#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2bc) +/** LP_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC3_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_FUNC3_OUT_INV_SEL_S) +#define LP_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC3_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC3_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_FUNC3_OE_INV_SEL_S) +#define LP_GPIO_FUNC3_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC3_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO4 output + */ +#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2c0) +/** LP_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC4_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_FUNC4_OUT_INV_SEL_S) +#define LP_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC4_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC4_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_FUNC4_OE_INV_SEL_S) +#define LP_GPIO_FUNC4_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC4_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO5 output + */ +#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2c4) +/** LP_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC5_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_FUNC5_OUT_INV_SEL_S) +#define LP_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC5_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ +#define LP_GPIO_FUNC5_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_FUNC5_OE_INV_SEL_S) +#define LP_GPIO_FUNC5_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC5_OE_INV_SEL_S 2 + +/** LP_GPIO_CLOCK_GATE_REG register + * LP_GPIO clock gate register + */ +#define LP_GPIO_CLOCK_GATE_REG (DR_REG_LP_BASE + 0x3f8) +/** LP_GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate. + * 0: Not enable + * 1: Enable, the clock is free running. + */ +#define LP_GPIO_CLK_EN (BIT(0)) +#define LP_GPIO_CLK_EN_M (LP_GPIO_CLK_EN_V << LP_GPIO_CLK_EN_S) +#define LP_GPIO_CLK_EN_V 0x00000001U +#define LP_GPIO_CLK_EN_S 0 + +/** LP_GPIO_DATE_REG register + * LP_GPIO version register + */ +#define LP_GPIO_DATE_REG (DR_REG_LP_BASE + 0x3fc) +/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 37769744; + * Version control register. + */ +#define LP_GPIO_DATE 0x0FFFFFFFU +#define LP_GPIO_DATE_M (LP_GPIO_DATE_V << LP_GPIO_DATE_S) +#define LP_GPIO_DATE_V 0x0FFFFFFFU +#define LP_GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_gpio_struct.h b/components/soc/esp32h4/register/soc/lp_gpio_struct.h new file mode 100644 index 0000000000..86661924d8 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_gpio_struct.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of gpio_out register + * LP_GPIO output register + */ +typedef union { + struct { + /** gpio_out_data_orig : R/W/WTC; bitpos: [5:0]; default: 0; + * Configures the output value of LP_GPIO0 ~ 5 output in simple LP_GPIO output mode. + * 0: Low level + * 1: High level + * The value of bit0 ~ bit5 correspond to the output value of LP_GPIO0 ~ LP_GPIO5 + * respectively. Bitxx ~ bitxx is invalid. + */ + uint32_t gpio_out_data_orig:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_out_reg_t; + +/** Type of gpio_out_w1ts register + * LP_GPIO output set register + */ +typedef union { + struct { + /** gpio_out_w1ts : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~ + * LP_GPIO5. + * 0: Not set + * 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1 + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set LP_GPIO_OUT_REG. + */ + uint32_t gpio_out_w1ts:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_out_w1ts_reg_t; + +/** Type of gpio_out_w1tc register + * LP_GPIO output clear register + */ +typedef union { + struct { + /** gpio_out_w1tc : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0 + * ~ LP_GPIO5 output. + * 0: Not clear + * 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared. + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear LP_GPIO_OUT_REG. + */ + uint32_t gpio_out_w1tc:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_out_w1tc_reg_t; + +/** Type of gpio_enable register + * LP_GPIO output enable register + */ +typedef union { + struct { + /** gpio_enable_data : R/W/WTC; bitpos: [5:0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO5. + * 0: Not enable + * 1: Enable + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + */ + uint32_t gpio_enable_data:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_enable_reg_t; + +/** Type of gpio_enable_w1ts register + * LP_GPIO output enable set register + */ +typedef union { + struct { + /** gpio_enable_w1ts : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO5. + * 0: Not set + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1 + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to set LP_GPIO_ENABLE_REG. + */ + uint32_t gpio_enable_w1ts:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_enable_w1ts_reg_t; + +/** Type of gpio_enable_w1tc register + * LP_GPIO output enable clear register + */ +typedef union { + struct { + /** gpio_enable_w1tc : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO5. + * 0: Not clear + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Recommended operation: use this register to clear LP_GPIO_ENABLE_REG. + */ + uint32_t gpio_enable_w1tc:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_enable_w1tc_reg_t; + +/** Type of gpio_in register + * LP_GPIO input register + */ +typedef union { + struct { + /** gpio_in_data_next : RO; bitpos: [5:0]; default: 0; + * Represents the input value of LP_GPIO0 ~ LP_GPIO5. Each bit represents a pin input + * value: + * 0: Low level + * 1: High level + * Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + */ + uint32_t gpio_in_data_next:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_in_reg_t; + + +/** Group: Interrupt Status Registers */ +/** Type of gpio_status register + * LP_GPIO interrupt status register + */ +typedef union { + struct { + /** gpio_status_interrupt : R/W/WTC; bitpos: [5:0]; default: 0; + * The interrupt status of LP_GPIO0 ~ LP_GPIO5, can be configured by the software. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - Each bit represents the status of its corresponding LP_GPIO: + * + * - 0: Represents the LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the LP_GPIO generates the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software. + * + */ + uint32_t gpio_status_interrupt:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_status_reg_t; + +/** Type of gpio_status_w1ts register + * LP_GPIO interrupt status set register + */ +typedef union { + struct { + /** gpio_status_w1ts : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to set the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set LP_GPIO_STATUS_INTERRUPT. + */ + uint32_t gpio_status_w1ts:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_status_w1ts_reg_t; + +/** Type of gpio_status_w1tc register + * LP_GPIO interrupt status clear register + */ +typedef union { + struct { + /** gpio_status_w1tc : WT; bitpos: [5:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5. + * + * - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear LP_GPIO_STATUS_INTERRUPT. + */ + uint32_t gpio_status_w1tc:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_status_w1tc_reg_t; + +/** Type of gpio_status_next register + * LP_GPIO interrupt source register + */ +typedef union { + struct { + /** gpio_status_interrupt_next : RO; bitpos: [5:0]; default: 0; + * Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO5. + * Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid. + * Each bit represents: + * 0: The LP_GPIO does not generate the interrupt configured by LP_GPIO_PIN$n_INT_TYPE. + * 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE. + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt. + */ + uint32_t gpio_status_interrupt_next:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_status_next_reg_t; + + +/** Group: Pin Configuration Registers */ +/** Type of gpio_pinn register + * LP_GPIOn configuration register + */ +typedef union { + struct { + /** gpio_pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ + uint32_t gpio_pinn_sync2_bypass:2; + /** gpio_pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. + * 0: Normal output + * 1: Open drain output + */ + uint32_t gpio_pinn_pad_driver:1; + /** gpio_pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization. + * 0: Not synchronize + * 1: Synchronize on falling edge + * 2: Synchronize on rising edge + * 3: Synchronize on rising edge + */ + uint32_t gpio_pinn_sync1_bypass:2; + /** gpio_pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ + uint32_t gpio_pinn_edge_wakeup_clr:1; + uint32_t reserved_6:1; + /** gpio_pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type. + * 0: LP_GPIO interrupt disabled + * 1: Rising edge trigger + * 2: Falling edge trigger + * 3: Any edge trigger + * 4: Low level trigger + * 5: High level trigger + */ + uint32_t gpio_pinn_int_type:3; + /** gpio_pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function. + * 0: Disable + * 1: Enable + * This function only wakes up the CPU from Light-sleep. + */ + uint32_t gpio_pinn_wakeup_enable:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_gpio_pinn_reg_t; + + +/** Group: Output Configuration Registers */ +/** Type of gpio_funcn_out_sel_cfg register + * Configuration register for LP_GPIOn output + */ +typedef union { + struct { + /** gpio_funcn_out_inv_sel : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value. + * 0: Not invert + * 1: Invert + */ + uint32_t gpio_funcn_out_inv_sel:1; + uint32_t reserved_1:1; + /** gpio_funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal. + * 0: Not invert + * 1: Invert + */ + uint32_t gpio_funcn_oe_inv_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_gpio_funcn_out_sel_cfg_reg_t; + + +/** Group: Clock Gate Register */ +/** Type of gpio_clock_gate register + * LP_GPIO clock gate register + */ +typedef union { + struct { + /** gpio_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate. + * 0: Not enable + * 1: Enable, the clock is free running. + */ + uint32_t gpio_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_gpio_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of gpio_date register + * LP_GPIO version register + */ +typedef union { + struct { + /** gpio_date : R/W; bitpos: [27:0]; default: 37769744; + * Version control register. + */ + uint32_t gpio_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_gpio_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile lp_gpio_out_reg_t gpio_out; + volatile lp_gpio_out_w1ts_reg_t gpio_out_w1ts; + volatile lp_gpio_out_w1tc_reg_t gpio_out_w1tc; + volatile lp_gpio_enable_reg_t gpio_enable; + volatile lp_gpio_enable_w1ts_reg_t gpio_enable_w1ts; + volatile lp_gpio_enable_w1tc_reg_t gpio_enable_w1tc; + volatile lp_gpio_in_reg_t gpio_in; + volatile lp_gpio_status_reg_t gpio_status; + volatile lp_gpio_status_w1ts_reg_t gpio_status_w1ts; + volatile lp_gpio_status_w1tc_reg_t gpio_status_w1tc; + volatile lp_gpio_status_next_reg_t gpio_status_next; + volatile lp_gpio_pinn_reg_t gpio_pinn[6]; + uint32_t reserved_048[154]; + volatile lp_gpio_funcn_out_sel_cfg_reg_t gpio_funcn_out_sel_cfg[6]; + uint32_t reserved_2c8[76]; + volatile lp_gpio_clock_gate_reg_t gpio_clock_gate; + volatile lp_gpio_date_reg_t gpio_date; +} lp_gpio_dev_t; + +extern lp_gpio_dev_t LP_GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_iomux_reg.h b/components/soc/esp32h4/register/soc/lp_iomux_reg.h new file mode 100644 index 0000000000..d9557af304 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_iomux_reg.h @@ -0,0 +1,850 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IO_MUX_GPIO0_REG register + * LP IO MUX configuration register for LP_GPIO0 + */ +#define LP_IO_MUX_GPIO0_REG (DR_REG_LP_BASE + 0x0) +/** LP_IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO0_MCU_OE_M (LP_IO_MUX_GPIO0_MCU_OE_V << LP_IO_MUX_GPIO0_MCU_OE_S) +#define LP_IO_MUX_GPIO0_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_OE_S 0 +/** LP_IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO0. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO0_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO0_SLP_SEL_M (LP_IO_MUX_GPIO0_SLP_SEL_V << LP_IO_MUX_GPIO0_SLP_SEL_S) +#define LP_IO_MUX_GPIO0_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO0_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO0 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO0_MCU_WPD_M (LP_IO_MUX_GPIO0_MCU_WPD_V << LP_IO_MUX_GPIO0_MCU_WPD_S) +#define LP_IO_MUX_GPIO0_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO0 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO0_MCU_WPU_M (LP_IO_MUX_GPIO0_MCU_WPU_V << LP_IO_MUX_GPIO0_MCU_WPU_S) +#define LP_IO_MUX_GPIO0_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO0 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO0_MCU_IE_M (LP_IO_MUX_GPIO0_MCU_IE_V << LP_IO_MUX_GPIO0_MCU_IE_S) +#define LP_IO_MUX_GPIO0_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_IE_S 4 +/** LP_IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO0 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO0_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO0_MCU_DRV_M (LP_IO_MUX_GPIO0_MCU_DRV_V << LP_IO_MUX_GPIO0_MCU_DRV_S) +#define LP_IO_MUX_GPIO0_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO0_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO0. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO0_FUN_WPD_M (LP_IO_MUX_GPIO0_FUN_WPD_V << LP_IO_MUX_GPIO0_FUN_WPD_S) +#define LP_IO_MUX_GPIO0_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO0. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO0_FUN_WPU_M (LP_IO_MUX_GPIO0_FUN_WPU_V << LP_IO_MUX_GPIO0_FUN_WPU_S) +#define LP_IO_MUX_GPIO0_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO0. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO0_FUN_IE_M (LP_IO_MUX_GPIO0_FUN_IE_V << LP_IO_MUX_GPIO0_FUN_IE_S) +#define LP_IO_MUX_GPIO0_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_IE_S 9 +/** LP_IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO0. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO0_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO0_FUN_DRV_M (LP_IO_MUX_GPIO0_FUN_DRV_V << LP_IO_MUX_GPIO0_FUN_DRV_S) +#define LP_IO_MUX_GPIO0_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO0_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO0_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO0_MCU_SEL_M (LP_IO_MUX_GPIO0_MCU_SEL_V << LP_IO_MUX_GPIO0_MCU_SEL_S) +#define LP_IO_MUX_GPIO0_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO0_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO0_FILTER_EN_M (LP_IO_MUX_GPIO0_FILTER_EN_V << LP_IO_MUX_GPIO0_FILTER_EN_S) +#define LP_IO_MUX_GPIO0_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO0_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO0_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO0_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO0_HYS_EN_M (LP_IO_MUX_GPIO0_HYS_EN_V << LP_IO_MUX_GPIO0_HYS_EN_S) +#define LP_IO_MUX_GPIO0_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO0_HYS_EN_S 16 +/** LP_IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO0. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO0_HYS_EN + */ +#define LP_IO_MUX_GPIO0_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO0_HYS_SEL_M (LP_IO_MUX_GPIO0_HYS_SEL_V << LP_IO_MUX_GPIO0_HYS_SEL_S) +#define LP_IO_MUX_GPIO0_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO0_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO1_REG register + * LP IO MUX configuration register for LP_GPIO1 + */ +#define LP_IO_MUX_GPIO1_REG (DR_REG_LP_BASE + 0x4) +/** LP_IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO1 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO1_MCU_OE_M (LP_IO_MUX_GPIO1_MCU_OE_V << LP_IO_MUX_GPIO1_MCU_OE_S) +#define LP_IO_MUX_GPIO1_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_OE_S 0 +/** LP_IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO1. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO1_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO1_SLP_SEL_M (LP_IO_MUX_GPIO1_SLP_SEL_V << LP_IO_MUX_GPIO1_SLP_SEL_S) +#define LP_IO_MUX_GPIO1_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO1_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO1 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO1_MCU_WPD_M (LP_IO_MUX_GPIO1_MCU_WPD_V << LP_IO_MUX_GPIO1_MCU_WPD_S) +#define LP_IO_MUX_GPIO1_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO1 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO1_MCU_WPU_M (LP_IO_MUX_GPIO1_MCU_WPU_V << LP_IO_MUX_GPIO1_MCU_WPU_S) +#define LP_IO_MUX_GPIO1_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO1 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO1_MCU_IE_M (LP_IO_MUX_GPIO1_MCU_IE_V << LP_IO_MUX_GPIO1_MCU_IE_S) +#define LP_IO_MUX_GPIO1_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_IE_S 4 +/** LP_IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO1 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO1_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO1_MCU_DRV_M (LP_IO_MUX_GPIO1_MCU_DRV_V << LP_IO_MUX_GPIO1_MCU_DRV_S) +#define LP_IO_MUX_GPIO1_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO1_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO1_FUN_WPD_M (LP_IO_MUX_GPIO1_FUN_WPD_V << LP_IO_MUX_GPIO1_FUN_WPD_S) +#define LP_IO_MUX_GPIO1_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO1_FUN_WPU_M (LP_IO_MUX_GPIO1_FUN_WPU_V << LP_IO_MUX_GPIO1_FUN_WPU_S) +#define LP_IO_MUX_GPIO1_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO1_FUN_IE_M (LP_IO_MUX_GPIO1_FUN_IE_V << LP_IO_MUX_GPIO1_FUN_IE_S) +#define LP_IO_MUX_GPIO1_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_IE_S 9 +/** LP_IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO1. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO1_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO1_FUN_DRV_M (LP_IO_MUX_GPIO1_FUN_DRV_V << LP_IO_MUX_GPIO1_FUN_DRV_S) +#define LP_IO_MUX_GPIO1_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO1_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO1_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO1_MCU_SEL_M (LP_IO_MUX_GPIO1_MCU_SEL_V << LP_IO_MUX_GPIO1_MCU_SEL_S) +#define LP_IO_MUX_GPIO1_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO1_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO1_FILTER_EN_M (LP_IO_MUX_GPIO1_FILTER_EN_V << LP_IO_MUX_GPIO1_FILTER_EN_S) +#define LP_IO_MUX_GPIO1_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO1_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO1_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO1_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO1_HYS_EN_M (LP_IO_MUX_GPIO1_HYS_EN_V << LP_IO_MUX_GPIO1_HYS_EN_S) +#define LP_IO_MUX_GPIO1_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO1_HYS_EN_S 16 +/** LP_IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO1. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO1_HYS_EN + */ +#define LP_IO_MUX_GPIO1_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO1_HYS_SEL_M (LP_IO_MUX_GPIO1_HYS_SEL_V << LP_IO_MUX_GPIO1_HYS_SEL_S) +#define LP_IO_MUX_GPIO1_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO1_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO2_REG register + * LP IO MUX configuration register for LP_GPIO2 + */ +#define LP_IO_MUX_GPIO2_REG (DR_REG_LP_BASE + 0x8) +/** LP_IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO2 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO2_MCU_OE_M (LP_IO_MUX_GPIO2_MCU_OE_V << LP_IO_MUX_GPIO2_MCU_OE_S) +#define LP_IO_MUX_GPIO2_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_OE_S 0 +/** LP_IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO2. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO2_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO2_SLP_SEL_M (LP_IO_MUX_GPIO2_SLP_SEL_V << LP_IO_MUX_GPIO2_SLP_SEL_S) +#define LP_IO_MUX_GPIO2_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO2_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO2 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO2_MCU_WPD_M (LP_IO_MUX_GPIO2_MCU_WPD_V << LP_IO_MUX_GPIO2_MCU_WPD_S) +#define LP_IO_MUX_GPIO2_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO2 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO2_MCU_WPU_M (LP_IO_MUX_GPIO2_MCU_WPU_V << LP_IO_MUX_GPIO2_MCU_WPU_S) +#define LP_IO_MUX_GPIO2_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO2 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO2_MCU_IE_M (LP_IO_MUX_GPIO2_MCU_IE_V << LP_IO_MUX_GPIO2_MCU_IE_S) +#define LP_IO_MUX_GPIO2_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_IE_S 4 +/** LP_IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO2 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO2_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO2_MCU_DRV_M (LP_IO_MUX_GPIO2_MCU_DRV_V << LP_IO_MUX_GPIO2_MCU_DRV_S) +#define LP_IO_MUX_GPIO2_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO2_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO2. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO2_FUN_WPD_M (LP_IO_MUX_GPIO2_FUN_WPD_V << LP_IO_MUX_GPIO2_FUN_WPD_S) +#define LP_IO_MUX_GPIO2_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO2. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO2_FUN_WPU_M (LP_IO_MUX_GPIO2_FUN_WPU_V << LP_IO_MUX_GPIO2_FUN_WPU_S) +#define LP_IO_MUX_GPIO2_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO2. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO2_FUN_IE_M (LP_IO_MUX_GPIO2_FUN_IE_V << LP_IO_MUX_GPIO2_FUN_IE_S) +#define LP_IO_MUX_GPIO2_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_IE_S 9 +/** LP_IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO2. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO2_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO2_FUN_DRV_M (LP_IO_MUX_GPIO2_FUN_DRV_V << LP_IO_MUX_GPIO2_FUN_DRV_S) +#define LP_IO_MUX_GPIO2_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO2_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO2_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO2_MCU_SEL_M (LP_IO_MUX_GPIO2_MCU_SEL_V << LP_IO_MUX_GPIO2_MCU_SEL_S) +#define LP_IO_MUX_GPIO2_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO2_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO2_FILTER_EN_M (LP_IO_MUX_GPIO2_FILTER_EN_V << LP_IO_MUX_GPIO2_FILTER_EN_S) +#define LP_IO_MUX_GPIO2_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO2_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO2_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO2_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO2_HYS_EN_M (LP_IO_MUX_GPIO2_HYS_EN_V << LP_IO_MUX_GPIO2_HYS_EN_S) +#define LP_IO_MUX_GPIO2_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO2_HYS_EN_S 16 +/** LP_IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO2. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO2_HYS_EN + */ +#define LP_IO_MUX_GPIO2_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO2_HYS_SEL_M (LP_IO_MUX_GPIO2_HYS_SEL_V << LP_IO_MUX_GPIO2_HYS_SEL_S) +#define LP_IO_MUX_GPIO2_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO2_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO3_REG register + * LP IO MUX configuration register for LP_GPIO3 + */ +#define LP_IO_MUX_GPIO3_REG (DR_REG_LP_BASE + 0xc) +/** LP_IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO3 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO3_MCU_OE_M (LP_IO_MUX_GPIO3_MCU_OE_V << LP_IO_MUX_GPIO3_MCU_OE_S) +#define LP_IO_MUX_GPIO3_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_OE_S 0 +/** LP_IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO3. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO3_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO3_SLP_SEL_M (LP_IO_MUX_GPIO3_SLP_SEL_V << LP_IO_MUX_GPIO3_SLP_SEL_S) +#define LP_IO_MUX_GPIO3_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO3_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO3 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO3_MCU_WPD_M (LP_IO_MUX_GPIO3_MCU_WPD_V << LP_IO_MUX_GPIO3_MCU_WPD_S) +#define LP_IO_MUX_GPIO3_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO3 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO3_MCU_WPU_M (LP_IO_MUX_GPIO3_MCU_WPU_V << LP_IO_MUX_GPIO3_MCU_WPU_S) +#define LP_IO_MUX_GPIO3_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO3 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO3_MCU_IE_M (LP_IO_MUX_GPIO3_MCU_IE_V << LP_IO_MUX_GPIO3_MCU_IE_S) +#define LP_IO_MUX_GPIO3_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_IE_S 4 +/** LP_IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO3 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO3_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO3_MCU_DRV_M (LP_IO_MUX_GPIO3_MCU_DRV_V << LP_IO_MUX_GPIO3_MCU_DRV_S) +#define LP_IO_MUX_GPIO3_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO3_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO3. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO3_FUN_WPD_M (LP_IO_MUX_GPIO3_FUN_WPD_V << LP_IO_MUX_GPIO3_FUN_WPD_S) +#define LP_IO_MUX_GPIO3_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO3. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO3_FUN_WPU_M (LP_IO_MUX_GPIO3_FUN_WPU_V << LP_IO_MUX_GPIO3_FUN_WPU_S) +#define LP_IO_MUX_GPIO3_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO3. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO3_FUN_IE_M (LP_IO_MUX_GPIO3_FUN_IE_V << LP_IO_MUX_GPIO3_FUN_IE_S) +#define LP_IO_MUX_GPIO3_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_IE_S 9 +/** LP_IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO3. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO3_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO3_FUN_DRV_M (LP_IO_MUX_GPIO3_FUN_DRV_V << LP_IO_MUX_GPIO3_FUN_DRV_S) +#define LP_IO_MUX_GPIO3_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO3_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO3_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO3_MCU_SEL_M (LP_IO_MUX_GPIO3_MCU_SEL_V << LP_IO_MUX_GPIO3_MCU_SEL_S) +#define LP_IO_MUX_GPIO3_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO3_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO3_FILTER_EN_M (LP_IO_MUX_GPIO3_FILTER_EN_V << LP_IO_MUX_GPIO3_FILTER_EN_S) +#define LP_IO_MUX_GPIO3_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO3_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO3_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO3_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO3_HYS_EN_M (LP_IO_MUX_GPIO3_HYS_EN_V << LP_IO_MUX_GPIO3_HYS_EN_S) +#define LP_IO_MUX_GPIO3_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO3_HYS_EN_S 16 +/** LP_IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO3. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO3_HYS_EN + */ +#define LP_IO_MUX_GPIO3_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO3_HYS_SEL_M (LP_IO_MUX_GPIO3_HYS_SEL_V << LP_IO_MUX_GPIO3_HYS_SEL_S) +#define LP_IO_MUX_GPIO3_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO3_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO4_REG register + * LP IO MUX configuration register for LP_GPIO4 + */ +#define LP_IO_MUX_GPIO4_REG (DR_REG_LP_BASE + 0x10) +/** LP_IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO4 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO4_MCU_OE_M (LP_IO_MUX_GPIO4_MCU_OE_V << LP_IO_MUX_GPIO4_MCU_OE_S) +#define LP_IO_MUX_GPIO4_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_OE_S 0 +/** LP_IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO4. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO4_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO4_SLP_SEL_M (LP_IO_MUX_GPIO4_SLP_SEL_V << LP_IO_MUX_GPIO4_SLP_SEL_S) +#define LP_IO_MUX_GPIO4_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO4_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO4 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO4_MCU_WPD_M (LP_IO_MUX_GPIO4_MCU_WPD_V << LP_IO_MUX_GPIO4_MCU_WPD_S) +#define LP_IO_MUX_GPIO4_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO4 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO4_MCU_WPU_M (LP_IO_MUX_GPIO4_MCU_WPU_V << LP_IO_MUX_GPIO4_MCU_WPU_S) +#define LP_IO_MUX_GPIO4_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO4 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO4_MCU_IE_M (LP_IO_MUX_GPIO4_MCU_IE_V << LP_IO_MUX_GPIO4_MCU_IE_S) +#define LP_IO_MUX_GPIO4_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_IE_S 4 +/** LP_IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO4 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO4_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO4_MCU_DRV_M (LP_IO_MUX_GPIO4_MCU_DRV_V << LP_IO_MUX_GPIO4_MCU_DRV_S) +#define LP_IO_MUX_GPIO4_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO4_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO4. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO4_FUN_WPD_M (LP_IO_MUX_GPIO4_FUN_WPD_V << LP_IO_MUX_GPIO4_FUN_WPD_S) +#define LP_IO_MUX_GPIO4_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO4. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO4_FUN_WPU_M (LP_IO_MUX_GPIO4_FUN_WPU_V << LP_IO_MUX_GPIO4_FUN_WPU_S) +#define LP_IO_MUX_GPIO4_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO4. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO4_FUN_IE_M (LP_IO_MUX_GPIO4_FUN_IE_V << LP_IO_MUX_GPIO4_FUN_IE_S) +#define LP_IO_MUX_GPIO4_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_IE_S 9 +/** LP_IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO4. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO4_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO4_FUN_DRV_M (LP_IO_MUX_GPIO4_FUN_DRV_V << LP_IO_MUX_GPIO4_FUN_DRV_S) +#define LP_IO_MUX_GPIO4_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO4_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO4_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO4_MCU_SEL_M (LP_IO_MUX_GPIO4_MCU_SEL_V << LP_IO_MUX_GPIO4_MCU_SEL_S) +#define LP_IO_MUX_GPIO4_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO4_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO4_FILTER_EN_M (LP_IO_MUX_GPIO4_FILTER_EN_V << LP_IO_MUX_GPIO4_FILTER_EN_S) +#define LP_IO_MUX_GPIO4_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO4_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO4_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO4_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO4_HYS_EN_M (LP_IO_MUX_GPIO4_HYS_EN_V << LP_IO_MUX_GPIO4_HYS_EN_S) +#define LP_IO_MUX_GPIO4_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO4_HYS_EN_S 16 +/** LP_IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO4. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO4_HYS_EN + */ +#define LP_IO_MUX_GPIO4_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO4_HYS_SEL_M (LP_IO_MUX_GPIO4_HYS_SEL_V << LP_IO_MUX_GPIO4_HYS_SEL_S) +#define LP_IO_MUX_GPIO4_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO4_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO5_REG register + * LP IO MUX configuration register for LP_GPIO5 + */ +#define LP_IO_MUX_GPIO5_REG (DR_REG_LP_BASE + 0x14) +/** LP_IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO5 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO5_MCU_OE_M (LP_IO_MUX_GPIO5_MCU_OE_V << LP_IO_MUX_GPIO5_MCU_OE_S) +#define LP_IO_MUX_GPIO5_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_OE_S 0 +/** LP_IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO5. + * 0: Not enter + * 1: Enter + */ +#define LP_IO_MUX_GPIO5_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO5_SLP_SEL_M (LP_IO_MUX_GPIO5_SLP_SEL_V << LP_IO_MUX_GPIO5_SLP_SEL_S) +#define LP_IO_MUX_GPIO5_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO5_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO5 in sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO5_MCU_WPD_M (LP_IO_MUX_GPIO5_MCU_WPD_V << LP_IO_MUX_GPIO5_MCU_WPD_S) +#define LP_IO_MUX_GPIO5_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO5 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO5_MCU_WPU_M (LP_IO_MUX_GPIO5_MCU_WPU_V << LP_IO_MUX_GPIO5_MCU_WPU_S) +#define LP_IO_MUX_GPIO5_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO5 during sleep mode. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO5_MCU_IE_M (LP_IO_MUX_GPIO5_MCU_IE_V << LP_IO_MUX_GPIO5_MCU_IE_S) +#define LP_IO_MUX_GPIO5_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_IE_S 4 +/** LP_IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO5 during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO5_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO5_MCU_DRV_M (LP_IO_MUX_GPIO5_MCU_DRV_V << LP_IO_MUX_GPIO5_MCU_DRV_S) +#define LP_IO_MUX_GPIO5_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO5_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO5. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO5_FUN_WPD_M (LP_IO_MUX_GPIO5_FUN_WPD_V << LP_IO_MUX_GPIO5_FUN_WPD_S) +#define LP_IO_MUX_GPIO5_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO5. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO5_FUN_WPU_M (LP_IO_MUX_GPIO5_FUN_WPU_V << LP_IO_MUX_GPIO5_FUN_WPU_S) +#define LP_IO_MUX_GPIO5_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO5. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO5_FUN_IE_M (LP_IO_MUX_GPIO5_FUN_IE_V << LP_IO_MUX_GPIO5_FUN_IE_S) +#define LP_IO_MUX_GPIO5_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_IE_S 9 +/** LP_IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO5. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ +#define LP_IO_MUX_GPIO5_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO5_FUN_DRV_M (LP_IO_MUX_GPIO5_FUN_DRV_V << LP_IO_MUX_GPIO5_FUN_DRV_S) +#define LP_IO_MUX_GPIO5_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO5_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ +#define LP_IO_MUX_GPIO5_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO5_MCU_SEL_M (LP_IO_MUX_GPIO5_MCU_SEL_V << LP_IO_MUX_GPIO5_MCU_SEL_S) +#define LP_IO_MUX_GPIO5_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO5_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO5_FILTER_EN_M (LP_IO_MUX_GPIO5_FILTER_EN_V << LP_IO_MUX_GPIO5_FILTER_EN_S) +#define LP_IO_MUX_GPIO5_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO5_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO5_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ +#define LP_IO_MUX_GPIO5_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO5_HYS_EN_M (LP_IO_MUX_GPIO5_HYS_EN_V << LP_IO_MUX_GPIO5_HYS_EN_S) +#define LP_IO_MUX_GPIO5_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO5_HYS_EN_S 16 +/** LP_IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO5. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIO5_HYS_EN + */ +#define LP_IO_MUX_GPIO5_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO5_HYS_SEL_M (LP_IO_MUX_GPIO5_HYS_SEL_V << LP_IO_MUX_GPIO5_HYS_SEL_S) +#define LP_IO_MUX_GPIO5_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO5_HYS_SEL_S 17 + +/** LP_IO_MUX_DATE_REG register + * Version control register + */ +#define LP_IO_MUX_DATE_REG (DR_REG_LP_BASE + 0x1fc) +/** LP_IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 37769744; + * Version control register + */ +#define LP_IO_MUX_REG_DATE 0x0FFFFFFFU +#define LP_IO_MUX_REG_DATE_M (LP_IO_MUX_REG_DATE_V << LP_IO_MUX_REG_DATE_S) +#define LP_IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define LP_IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_iomux_struct.h b/components/soc/esp32h4/register/soc/lp_iomux_struct.h new file mode 100644 index 0000000000..bbdec85ee7 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_iomux_struct.h @@ -0,0 +1,145 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of io_mux_gpion register + * LP IO MUX configuration register for LP_GPIOn + */ +typedef union { + struct { + /** io_mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIOn in sleep mode. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_mcu_oe:1; + /** io_mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIOn. + * 0: Not enter + * 1: Enter + */ + uint32_t io_mux_gpion_slp_sel:1; + /** io_mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIOn in sleep mode. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_mcu_wpd:1; + /** io_mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIOn during sleep mode. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_mcu_wpu:1; + /** io_mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIOn during sleep mode. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_mcu_ie:1; + /** io_mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIOn during sleep mode. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ + uint32_t io_mux_gpion_mcu_drv:2; + /** io_mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIOn. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_fun_wpd:1; + /** io_mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIOn. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_fun_wpu:1; + /** io_mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIOn. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_fun_ie:1; + /** io_mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIOn. + * 0: ~5 mA + * 1: ~10 mA + * 2: ~20 mA + * 3: ~40 mA + */ + uint32_t io_mux_gpion_fun_drv:2; + /** io_mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * Configures to select LP IO MUX function for this signal. + * 0: Select Function 0 + * 1: Select Function 1 + * ...... + */ + uint32_t io_mux_gpion_mcu_sel:3; + /** io_mux_gpion_filter_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_filter_en:1; + /** io_mux_gpion_hys_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIOn_HYS_SEL is set to 1. + * 0: Disable + * 1: Enable + */ + uint32_t io_mux_gpion_hys_en:1; + /** io_mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIOn. + * 0: Choose the output enable signal of eFuse + * 1: Choose the output enable signal of LP_IO_MUX_GPIOn_HYS_EN + */ + uint32_t io_mux_gpion_hys_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} lp_io_mux_gpion_reg_t; + + +/** Group: Version Register */ +/** Type of io_mux_date register + * Version control register + */ +typedef union { + struct { + /** io_mux_reg_date : R/W; bitpos: [27:0]; default: 37769744; + * Version control register + */ + uint32_t io_mux_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_io_mux_date_reg_t; + + +typedef struct { + volatile lp_io_mux_gpion_reg_t io_mux_gpion[6]; + uint32_t reserved_018[121]; + volatile lp_io_mux_date_reg_t io_mux_date; +} lp_iomux_dev_t; + +extern lp_iomux_dev_t LP_IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_iomux_dev_t) == 0x200, "Invalid size of lp_iomux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_peri_reg.h b/components/soc/esp32h4/register/soc/lp_peri_reg.h new file mode 100644 index 0000000000..e37a668a69 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_peri_reg.h @@ -0,0 +1,215 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * configure peri in lp system clk enable + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_APB_CK_EN : R/W; bitpos: [23]; default: 1; + * lp rng apb clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_RNG_APB_CK_EN (BIT(23)) +#define LPPERI_RNG_APB_CK_EN_M (LPPERI_RNG_APB_CK_EN_V << LPPERI_RNG_APB_CK_EN_S) +#define LPPERI_RNG_APB_CK_EN_V 0x00000001U +#define LPPERI_RNG_APB_CK_EN_S 23 +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * lp rng clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * lp optdebug clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_TOUCH_CK_EN : R/W; bitpos: [26]; default: 1; + * lp touch clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_LP_TOUCH_CK_EN (BIT(26)) +#define LPPERI_LP_TOUCH_CK_EN_M (LPPERI_LP_TOUCH_CK_EN_V << LPPERI_LP_TOUCH_CK_EN_S) +#define LPPERI_LP_TOUCH_CK_EN_V 0x00000001U +#define LPPERI_LP_TOUCH_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * lp io clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * efuse core clk enable + * 1: enable clock + * 0: disable clock + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 + +/** LPPERI_RESET_EN_REG register + * configure peri in lp system reset enable + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * lp bus reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_RNG_APB_RESET_EN : R/W; bitpos: [24]; default: 0; + * lp rng apb reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_LP_RNG_APB_RESET_EN (BIT(24)) +#define LPPERI_LP_RNG_APB_RESET_EN_M (LPPERI_LP_RNG_APB_RESET_EN_V << LPPERI_LP_RNG_APB_RESET_EN_S) +#define LPPERI_LP_RNG_APB_RESET_EN_V 0x00000001U +#define LPPERI_LP_RNG_APB_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * lp optdebug reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_TOUCH_RESET_EN : R/W; bitpos: [26]; default: 0; + * lp touch reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_LP_TOUCH_RESET_EN (BIT(26)) +#define LPPERI_LP_TOUCH_RESET_EN_M (LPPERI_LP_TOUCH_RESET_EN_V << LPPERI_LP_TOUCH_RESET_EN_S) +#define LPPERI_LP_TOUCH_RESET_EN_V 0x00000001U +#define LPPERI_LP_TOUCH_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * lp io reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * efuse core reset enable + * 1: enable reset + * 0: disable reset + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 + +/** LPPERI_LP_PERI_PMS_CONF_REG register + * LP Peripherals PMS configuration register + */ +#define LPPERI_LP_PERI_PMS_CONF_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear lp peri_pms_record_reg. + * 0: No clear + * 1: Clear peri_pms_record_reg + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR (BIT(0)) +#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_M (LPPERI_LP_PERI_PMS_EXCEPTION_CLR_V << LPPERI_LP_PERI_PMS_EXCEPTION_CLR_S) +#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_V 0x00000001U +#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_S 0 + +/** LPPERI_LP_PERI_PMS_EXCEPTION_INFO_REG register + * LP Peripherals PMS exception info record register + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0; + * Represents whether the lp peripheral pms has been triggered. + * 0: No triggered + * 1: Has been triggered + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_DET (BIT(0)) +#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_M (LPPERI_LP_PERI_PMS_EXCEPTION_DET_V << LPPERI_LP_PERI_PMS_EXCEPTION_DET_S) +#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_V 0x00000001U +#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_S 0 +/** LPPERI_LP_PERI_PMS_EXCEPTION_ID : RO; bitpos: [5:1]; default: 0; + * Represents the master id when lp peripheral pms has been triggered. + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_ID 0x0000001FU +#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_M (LPPERI_LP_PERI_PMS_EXCEPTION_ID_V << LPPERI_LP_PERI_PMS_EXCEPTION_ID_S) +#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_V 0x0000001FU +#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_S 1 +/** LPPERI_LP_PERI_PMS_EXCEPTION_MODE : RO; bitpos: [7:6]; default: 0; + * Represents the security mode when lp peripheral pms has been triggered. + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE 0x00000003U +#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_M (LPPERI_LP_PERI_PMS_EXCEPTION_MODE_V << LPPERI_LP_PERI_PMS_EXCEPTION_MODE_S) +#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_V 0x00000003U +#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_S 6 +/** LPPERI_LP_PERI_PMS_EXCEPTION_ADDR : RO; bitpos: [31:8]; default: 0; + * Represents the access address (bit23~bit0) when lp peripheral pms has been + * triggered. + */ +#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR 0x00FFFFFFU +#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_M (LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V << LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S) +#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU +#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S 8 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * record the lp cpu interrupt + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [4:0]; default: 0; + * BIT4~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_analog_peri_int, lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000001FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000001FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DATE_REG register + * version register + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37819136; + * version register + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * force on reg clk + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_peri_struct.h b/components/soc/esp32h4/register/soc/lp_peri_struct.h new file mode 100644 index 0000000000..e6150996eb --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_peri_struct.h @@ -0,0 +1,210 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * configure peri in lp system clk enable + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** rng_apb_ck_en : R/W; bitpos: [23]; default: 1; + * lp rng apb clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t rng_apb_ck_en:1; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * lp rng clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * lp optdebug clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t otp_dbg_ck_en:1; + /** lp_touch_ck_en : R/W; bitpos: [26]; default: 1; + * lp touch clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t lp_touch_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * lp io clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t lp_io_ck_en:1; + uint32_t reserved_28:2; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * efuse core clk enable + * 1: enable clock + * 0: disable clock + */ + uint32_t efuse_ck_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * configure peri in lp system reset enable + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * lp bus reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t bus_reset_en:1; + /** lp_rng_apb_reset_en : R/W; bitpos: [24]; default: 0; + * lp rng apb reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t lp_rng_apb_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * lp optdebug reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t otp_dbg_reset_en:1; + /** lp_touch_reset_en : R/W; bitpos: [26]; default: 0; + * lp touch reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t lp_touch_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * lp io reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t lp_io_reset_en:1; + uint32_t reserved_28:2; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * efuse core reset enable + * 1: enable reset + * 0: disable reset + */ + uint32_t efuse_reset_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of interrupt_source register + * record the lp cpu interrupt + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [4:0]; default: 0; + * BIT4~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_analog_peri_int, lp_io_int + */ + uint32_t lp_interrupt_source:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + + +/** Group: PMS Register */ +/** Type of lp_peri_pms_conf register + * LP Peripherals PMS configuration register + */ +typedef union { + struct { + /** lp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear lp peri_pms_record_reg. + * 0: No clear + * 1: Clear peri_pms_record_reg + */ + uint32_t lp_peri_pms_exception_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lpperi_lp_peri_pms_conf_reg_t; + +/** Type of lp_peri_pms_exception_info register + * LP Peripherals PMS exception info record register + */ +typedef union { + struct { + /** lp_peri_pms_exception_det : RO; bitpos: [0]; default: 0; + * Represents whether the lp peripheral pms has been triggered. + * 0: No triggered + * 1: Has been triggered + */ + uint32_t lp_peri_pms_exception_det:1; + /** lp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; + * Represents the master id when lp peripheral pms has been triggered. + */ + uint32_t lp_peri_pms_exception_id:5; + /** lp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; + * Represents the security mode when lp peripheral pms has been triggered. + */ + uint32_t lp_peri_pms_exception_mode:2; + /** lp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; + * Represents the access address (bit23~bit0) when lp peripheral pms has been + * triggered. + */ + uint32_t lp_peri_pms_exception_addr:24; + }; + uint32_t val; +} lpperi_lp_peri_pms_exception_info_reg_t; + + +/** Group: Version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37819136; + * version register + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * force on reg clk + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + uint32_t reserved_008[2]; + volatile lpperi_lp_peri_pms_conf_reg_t lp_peri_pms_conf; + volatile lpperi_lp_peri_pms_exception_info_reg_t lp_peri_pms_exception_info; + uint32_t reserved_018[2]; + volatile lpperi_interrupt_source_reg_t interrupt_source; + uint32_t reserved_024[246]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_tee_reg.h b/components/soc/esp32h4/register/soc/lp_tee_reg.h new file mode 100644 index 0000000000..3c94229aa6 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_tee_reg.h @@ -0,0 +1,1211 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TEE_TRNG_CTRL_REG register + * trng read/write control register + */ +#define LP_TEE_TRNG_CTRL_REG (DR_REG_LP_BASE + 0x0) +/** LP_TEE_READ_TEE_TRNG : R/W; bitpos: [0]; default: 1; + * Configures trng registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_TRNG (BIT(0)) +#define LP_TEE_READ_TEE_TRNG_M (LP_TEE_READ_TEE_TRNG_V << LP_TEE_READ_TEE_TRNG_S) +#define LP_TEE_READ_TEE_TRNG_V 0x00000001U +#define LP_TEE_READ_TEE_TRNG_S 0 +/** LP_TEE_READ_REE0_TRNG : R/W; bitpos: [1]; default: 0; + * Configures trng registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_TRNG (BIT(1)) +#define LP_TEE_READ_REE0_TRNG_M (LP_TEE_READ_REE0_TRNG_V << LP_TEE_READ_REE0_TRNG_S) +#define LP_TEE_READ_REE0_TRNG_V 0x00000001U +#define LP_TEE_READ_REE0_TRNG_S 1 +/** LP_TEE_READ_REE1_TRNG : R/W; bitpos: [2]; default: 0; + * Configures trng registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_TRNG (BIT(2)) +#define LP_TEE_READ_REE1_TRNG_M (LP_TEE_READ_REE1_TRNG_V << LP_TEE_READ_REE1_TRNG_S) +#define LP_TEE_READ_REE1_TRNG_V 0x00000001U +#define LP_TEE_READ_REE1_TRNG_S 2 +/** LP_TEE_READ_REE2_TRNG : R/W; bitpos: [3]; default: 0; + * Configures trng registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_TRNG (BIT(3)) +#define LP_TEE_READ_REE2_TRNG_M (LP_TEE_READ_REE2_TRNG_V << LP_TEE_READ_REE2_TRNG_S) +#define LP_TEE_READ_REE2_TRNG_V 0x00000001U +#define LP_TEE_READ_REE2_TRNG_S 3 +/** LP_TEE_WRITE_TEE_TRNG : R/W; bitpos: [4]; default: 1; + * Configures trng registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_TRNG (BIT(4)) +#define LP_TEE_WRITE_TEE_TRNG_M (LP_TEE_WRITE_TEE_TRNG_V << LP_TEE_WRITE_TEE_TRNG_S) +#define LP_TEE_WRITE_TEE_TRNG_V 0x00000001U +#define LP_TEE_WRITE_TEE_TRNG_S 4 +/** LP_TEE_WRITE_REE0_TRNG : R/W; bitpos: [5]; default: 0; + * Configures trng registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_TRNG (BIT(5)) +#define LP_TEE_WRITE_REE0_TRNG_M (LP_TEE_WRITE_REE0_TRNG_V << LP_TEE_WRITE_REE0_TRNG_S) +#define LP_TEE_WRITE_REE0_TRNG_V 0x00000001U +#define LP_TEE_WRITE_REE0_TRNG_S 5 +/** LP_TEE_WRITE_REE1_TRNG : R/W; bitpos: [6]; default: 0; + * Configures trng registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_TRNG (BIT(6)) +#define LP_TEE_WRITE_REE1_TRNG_M (LP_TEE_WRITE_REE1_TRNG_V << LP_TEE_WRITE_REE1_TRNG_S) +#define LP_TEE_WRITE_REE1_TRNG_V 0x00000001U +#define LP_TEE_WRITE_REE1_TRNG_S 6 +/** LP_TEE_WRITE_REE2_TRNG : R/W; bitpos: [7]; default: 0; + * Configures trng registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_TRNG (BIT(7)) +#define LP_TEE_WRITE_REE2_TRNG_M (LP_TEE_WRITE_REE2_TRNG_V << LP_TEE_WRITE_REE2_TRNG_S) +#define LP_TEE_WRITE_REE2_TRNG_V 0x00000001U +#define LP_TEE_WRITE_REE2_TRNG_S 7 + +/** LP_TEE_EFUSE_CTRL_REG register + * efuse read/write control register + */ +#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_BASE + 0x4) +/** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; + * Configures efuse registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_EFUSE (BIT(0)) +#define LP_TEE_READ_TEE_EFUSE_M (LP_TEE_READ_TEE_EFUSE_V << LP_TEE_READ_TEE_EFUSE_S) +#define LP_TEE_READ_TEE_EFUSE_V 0x00000001U +#define LP_TEE_READ_TEE_EFUSE_S 0 +/** LP_TEE_READ_REE0_EFUSE : R/W; bitpos: [1]; default: 0; + * Configures efuse registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_EFUSE (BIT(1)) +#define LP_TEE_READ_REE0_EFUSE_M (LP_TEE_READ_REE0_EFUSE_V << LP_TEE_READ_REE0_EFUSE_S) +#define LP_TEE_READ_REE0_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE0_EFUSE_S 1 +/** LP_TEE_READ_REE1_EFUSE : R/W; bitpos: [2]; default: 0; + * Configures efuse registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_EFUSE (BIT(2)) +#define LP_TEE_READ_REE1_EFUSE_M (LP_TEE_READ_REE1_EFUSE_V << LP_TEE_READ_REE1_EFUSE_S) +#define LP_TEE_READ_REE1_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE1_EFUSE_S 2 +/** LP_TEE_READ_REE2_EFUSE : R/W; bitpos: [3]; default: 0; + * Configures efuse registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_EFUSE (BIT(3)) +#define LP_TEE_READ_REE2_EFUSE_M (LP_TEE_READ_REE2_EFUSE_V << LP_TEE_READ_REE2_EFUSE_S) +#define LP_TEE_READ_REE2_EFUSE_V 0x00000001U +#define LP_TEE_READ_REE2_EFUSE_S 3 +/** LP_TEE_WRITE_TEE_EFUSE : R/W; bitpos: [4]; default: 1; + * Configures efuse registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_EFUSE (BIT(4)) +#define LP_TEE_WRITE_TEE_EFUSE_M (LP_TEE_WRITE_TEE_EFUSE_V << LP_TEE_WRITE_TEE_EFUSE_S) +#define LP_TEE_WRITE_TEE_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_TEE_EFUSE_S 4 +/** LP_TEE_WRITE_REE0_EFUSE : R/W; bitpos: [5]; default: 0; + * Configures efuse registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_EFUSE (BIT(5)) +#define LP_TEE_WRITE_REE0_EFUSE_M (LP_TEE_WRITE_REE0_EFUSE_V << LP_TEE_WRITE_REE0_EFUSE_S) +#define LP_TEE_WRITE_REE0_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE0_EFUSE_S 5 +/** LP_TEE_WRITE_REE1_EFUSE : R/W; bitpos: [6]; default: 0; + * Configures efuse registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_EFUSE (BIT(6)) +#define LP_TEE_WRITE_REE1_EFUSE_M (LP_TEE_WRITE_REE1_EFUSE_V << LP_TEE_WRITE_REE1_EFUSE_S) +#define LP_TEE_WRITE_REE1_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE1_EFUSE_S 6 +/** LP_TEE_WRITE_REE2_EFUSE : R/W; bitpos: [7]; default: 0; + * Configures efuse registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_EFUSE (BIT(7)) +#define LP_TEE_WRITE_REE2_EFUSE_M (LP_TEE_WRITE_REE2_EFUSE_V << LP_TEE_WRITE_REE2_EFUSE_S) +#define LP_TEE_WRITE_REE2_EFUSE_V 0x00000001U +#define LP_TEE_WRITE_REE2_EFUSE_S 7 + +/** LP_TEE_PMU_CTRL_REG register + * pmu read/write control register + */ +#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_BASE + 0x8) +/** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; + * Configures pmu registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_PMU (BIT(0)) +#define LP_TEE_READ_TEE_PMU_M (LP_TEE_READ_TEE_PMU_V << LP_TEE_READ_TEE_PMU_S) +#define LP_TEE_READ_TEE_PMU_V 0x00000001U +#define LP_TEE_READ_TEE_PMU_S 0 +/** LP_TEE_READ_REE0_PMU : R/W; bitpos: [1]; default: 0; + * Configures pmu registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_PMU (BIT(1)) +#define LP_TEE_READ_REE0_PMU_M (LP_TEE_READ_REE0_PMU_V << LP_TEE_READ_REE0_PMU_S) +#define LP_TEE_READ_REE0_PMU_V 0x00000001U +#define LP_TEE_READ_REE0_PMU_S 1 +/** LP_TEE_READ_REE1_PMU : R/W; bitpos: [2]; default: 0; + * Configures pmu registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_PMU (BIT(2)) +#define LP_TEE_READ_REE1_PMU_M (LP_TEE_READ_REE1_PMU_V << LP_TEE_READ_REE1_PMU_S) +#define LP_TEE_READ_REE1_PMU_V 0x00000001U +#define LP_TEE_READ_REE1_PMU_S 2 +/** LP_TEE_READ_REE2_PMU : R/W; bitpos: [3]; default: 0; + * Configures pmu registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_PMU (BIT(3)) +#define LP_TEE_READ_REE2_PMU_M (LP_TEE_READ_REE2_PMU_V << LP_TEE_READ_REE2_PMU_S) +#define LP_TEE_READ_REE2_PMU_V 0x00000001U +#define LP_TEE_READ_REE2_PMU_S 3 +/** LP_TEE_WRITE_TEE_PMU : R/W; bitpos: [4]; default: 1; + * Configures pmu registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_PMU (BIT(4)) +#define LP_TEE_WRITE_TEE_PMU_M (LP_TEE_WRITE_TEE_PMU_V << LP_TEE_WRITE_TEE_PMU_S) +#define LP_TEE_WRITE_TEE_PMU_V 0x00000001U +#define LP_TEE_WRITE_TEE_PMU_S 4 +/** LP_TEE_WRITE_REE0_PMU : R/W; bitpos: [5]; default: 0; + * Configures pmu registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_PMU (BIT(5)) +#define LP_TEE_WRITE_REE0_PMU_M (LP_TEE_WRITE_REE0_PMU_V << LP_TEE_WRITE_REE0_PMU_S) +#define LP_TEE_WRITE_REE0_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE0_PMU_S 5 +/** LP_TEE_WRITE_REE1_PMU : R/W; bitpos: [6]; default: 0; + * Configures pmu registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_PMU (BIT(6)) +#define LP_TEE_WRITE_REE1_PMU_M (LP_TEE_WRITE_REE1_PMU_V << LP_TEE_WRITE_REE1_PMU_S) +#define LP_TEE_WRITE_REE1_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE1_PMU_S 6 +/** LP_TEE_WRITE_REE2_PMU : R/W; bitpos: [7]; default: 0; + * Configures pmu registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_PMU (BIT(7)) +#define LP_TEE_WRITE_REE2_PMU_M (LP_TEE_WRITE_REE2_PMU_V << LP_TEE_WRITE_REE2_PMU_S) +#define LP_TEE_WRITE_REE2_PMU_V 0x00000001U +#define LP_TEE_WRITE_REE2_PMU_S 7 + +/** LP_TEE_CLKRST_CTRL_REG register + * clkrst read/write control register + */ +#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_BASE + 0xc) +/** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; + * Configures clkrst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_CLKRST (BIT(0)) +#define LP_TEE_READ_TEE_CLKRST_M (LP_TEE_READ_TEE_CLKRST_V << LP_TEE_READ_TEE_CLKRST_S) +#define LP_TEE_READ_TEE_CLKRST_V 0x00000001U +#define LP_TEE_READ_TEE_CLKRST_S 0 +/** LP_TEE_READ_REE0_CLKRST : R/W; bitpos: [1]; default: 0; + * Configures clkrst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_CLKRST (BIT(1)) +#define LP_TEE_READ_REE0_CLKRST_M (LP_TEE_READ_REE0_CLKRST_V << LP_TEE_READ_REE0_CLKRST_S) +#define LP_TEE_READ_REE0_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE0_CLKRST_S 1 +/** LP_TEE_READ_REE1_CLKRST : R/W; bitpos: [2]; default: 0; + * Configures clkrst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_CLKRST (BIT(2)) +#define LP_TEE_READ_REE1_CLKRST_M (LP_TEE_READ_REE1_CLKRST_V << LP_TEE_READ_REE1_CLKRST_S) +#define LP_TEE_READ_REE1_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE1_CLKRST_S 2 +/** LP_TEE_READ_REE2_CLKRST : R/W; bitpos: [3]; default: 0; + * Configures clkrst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_CLKRST (BIT(3)) +#define LP_TEE_READ_REE2_CLKRST_M (LP_TEE_READ_REE2_CLKRST_V << LP_TEE_READ_REE2_CLKRST_S) +#define LP_TEE_READ_REE2_CLKRST_V 0x00000001U +#define LP_TEE_READ_REE2_CLKRST_S 3 +/** LP_TEE_WRITE_TEE_CLKRST : R/W; bitpos: [4]; default: 1; + * Configures clkrst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_CLKRST (BIT(4)) +#define LP_TEE_WRITE_TEE_CLKRST_M (LP_TEE_WRITE_TEE_CLKRST_V << LP_TEE_WRITE_TEE_CLKRST_S) +#define LP_TEE_WRITE_TEE_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_TEE_CLKRST_S 4 +/** LP_TEE_WRITE_REE0_CLKRST : R/W; bitpos: [5]; default: 0; + * Configures clkrst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_CLKRST (BIT(5)) +#define LP_TEE_WRITE_REE0_CLKRST_M (LP_TEE_WRITE_REE0_CLKRST_V << LP_TEE_WRITE_REE0_CLKRST_S) +#define LP_TEE_WRITE_REE0_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE0_CLKRST_S 5 +/** LP_TEE_WRITE_REE1_CLKRST : R/W; bitpos: [6]; default: 0; + * Configures clkrst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_CLKRST (BIT(6)) +#define LP_TEE_WRITE_REE1_CLKRST_M (LP_TEE_WRITE_REE1_CLKRST_V << LP_TEE_WRITE_REE1_CLKRST_S) +#define LP_TEE_WRITE_REE1_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE1_CLKRST_S 6 +/** LP_TEE_WRITE_REE2_CLKRST : R/W; bitpos: [7]; default: 0; + * Configures clkrst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_CLKRST (BIT(7)) +#define LP_TEE_WRITE_REE2_CLKRST_M (LP_TEE_WRITE_REE2_CLKRST_V << LP_TEE_WRITE_REE2_CLKRST_S) +#define LP_TEE_WRITE_REE2_CLKRST_V 0x00000001U +#define LP_TEE_WRITE_REE2_CLKRST_S 7 + +/** LP_TEE_LP_AON_CTRL_CTRL_REG register + * lp_aon_ctrl read/write control register + */ +#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_BASE + 0x10) +/** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; + * Configures lp_aon_ctrl registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_AON_CTRL (BIT(0)) +#define LP_TEE_READ_TEE_LP_AON_CTRL_M (LP_TEE_READ_TEE_LP_AON_CTRL_V << LP_TEE_READ_TEE_LP_AON_CTRL_S) +#define LP_TEE_READ_TEE_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_TEE_LP_AON_CTRL_S 0 +/** LP_TEE_READ_REE0_LP_AON_CTRL : R/W; bitpos: [1]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_AON_CTRL (BIT(1)) +#define LP_TEE_READ_REE0_LP_AON_CTRL_M (LP_TEE_READ_REE0_LP_AON_CTRL_V << LP_TEE_READ_REE0_LP_AON_CTRL_S) +#define LP_TEE_READ_REE0_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE0_LP_AON_CTRL_S 1 +/** LP_TEE_READ_REE1_LP_AON_CTRL : R/W; bitpos: [2]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_AON_CTRL (BIT(2)) +#define LP_TEE_READ_REE1_LP_AON_CTRL_M (LP_TEE_READ_REE1_LP_AON_CTRL_V << LP_TEE_READ_REE1_LP_AON_CTRL_S) +#define LP_TEE_READ_REE1_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE1_LP_AON_CTRL_S 2 +/** LP_TEE_READ_REE2_LP_AON_CTRL : R/W; bitpos: [3]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_AON_CTRL (BIT(3)) +#define LP_TEE_READ_REE2_LP_AON_CTRL_M (LP_TEE_READ_REE2_LP_AON_CTRL_V << LP_TEE_READ_REE2_LP_AON_CTRL_S) +#define LP_TEE_READ_REE2_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_READ_REE2_LP_AON_CTRL_S 3 +/** LP_TEE_WRITE_TEE_LP_AON_CTRL : R/W; bitpos: [4]; default: 1; + * Configures lp_aon_ctrl registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_AON_CTRL (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_M (LP_TEE_WRITE_TEE_LP_AON_CTRL_V << LP_TEE_WRITE_TEE_LP_AON_CTRL_S) +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_AON_CTRL_S 4 +/** LP_TEE_WRITE_REE0_LP_AON_CTRL : R/W; bitpos: [5]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_AON_CTRL (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_M (LP_TEE_WRITE_REE0_LP_AON_CTRL_V << LP_TEE_WRITE_REE0_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_AON_CTRL_S 5 +/** LP_TEE_WRITE_REE1_LP_AON_CTRL : R/W; bitpos: [6]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_AON_CTRL (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_M (LP_TEE_WRITE_REE1_LP_AON_CTRL_V << LP_TEE_WRITE_REE1_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_AON_CTRL_S 6 +/** LP_TEE_WRITE_REE2_LP_AON_CTRL : R/W; bitpos: [7]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_AON_CTRL (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_M (LP_TEE_WRITE_REE2_LP_AON_CTRL_V << LP_TEE_WRITE_REE2_LP_AON_CTRL_S) +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7 + +/** LP_TEE_LP_TIMER_CTRL_REG register + * lp_timer read/write control register + */ +#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x14) +/** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; + * Configures lp_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_TIMER (BIT(0)) +#define LP_TEE_READ_TEE_LP_TIMER_M (LP_TEE_READ_TEE_LP_TIMER_V << LP_TEE_READ_TEE_LP_TIMER_S) +#define LP_TEE_READ_TEE_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_TEE_LP_TIMER_S 0 +/** LP_TEE_READ_REE0_LP_TIMER : R/W; bitpos: [1]; default: 0; + * Configures lp_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_TIMER (BIT(1)) +#define LP_TEE_READ_REE0_LP_TIMER_M (LP_TEE_READ_REE0_LP_TIMER_V << LP_TEE_READ_REE0_LP_TIMER_S) +#define LP_TEE_READ_REE0_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE0_LP_TIMER_S 1 +/** LP_TEE_READ_REE1_LP_TIMER : R/W; bitpos: [2]; default: 0; + * Configures lp_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_TIMER (BIT(2)) +#define LP_TEE_READ_REE1_LP_TIMER_M (LP_TEE_READ_REE1_LP_TIMER_V << LP_TEE_READ_REE1_LP_TIMER_S) +#define LP_TEE_READ_REE1_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE1_LP_TIMER_S 2 +/** LP_TEE_READ_REE2_LP_TIMER : R/W; bitpos: [3]; default: 0; + * Configures lp_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_TIMER (BIT(3)) +#define LP_TEE_READ_REE2_LP_TIMER_M (LP_TEE_READ_REE2_LP_TIMER_V << LP_TEE_READ_REE2_LP_TIMER_S) +#define LP_TEE_READ_REE2_LP_TIMER_V 0x00000001U +#define LP_TEE_READ_REE2_LP_TIMER_S 3 +/** LP_TEE_WRITE_TEE_LP_TIMER : R/W; bitpos: [4]; default: 1; + * Configures lp_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_TIMER (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_TIMER_M (LP_TEE_WRITE_TEE_LP_TIMER_V << LP_TEE_WRITE_TEE_LP_TIMER_S) +#define LP_TEE_WRITE_TEE_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_TIMER_S 4 +/** LP_TEE_WRITE_REE0_LP_TIMER : R/W; bitpos: [5]; default: 0; + * Configures lp_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_TIMER (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_TIMER_M (LP_TEE_WRITE_REE0_LP_TIMER_V << LP_TEE_WRITE_REE0_LP_TIMER_S) +#define LP_TEE_WRITE_REE0_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_TIMER_S 5 +/** LP_TEE_WRITE_REE1_LP_TIMER : R/W; bitpos: [6]; default: 0; + * Configures lp_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_TIMER (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_TIMER_M (LP_TEE_WRITE_REE1_LP_TIMER_V << LP_TEE_WRITE_REE1_LP_TIMER_S) +#define LP_TEE_WRITE_REE1_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_TIMER_S 6 +/** LP_TEE_WRITE_REE2_LP_TIMER : R/W; bitpos: [7]; default: 0; + * Configures lp_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_TIMER (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_TIMER_M (LP_TEE_WRITE_REE2_LP_TIMER_V << LP_TEE_WRITE_REE2_LP_TIMER_S) +#define LP_TEE_WRITE_REE2_LP_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_TIMER_S 7 + +/** LP_TEE_LP_WDT_CTRL_REG register + * lp_wdt read/write control register + */ +#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_BASE + 0x18) +/** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; + * Configures lp_wdt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_WDT (BIT(0)) +#define LP_TEE_READ_TEE_LP_WDT_M (LP_TEE_READ_TEE_LP_WDT_V << LP_TEE_READ_TEE_LP_WDT_S) +#define LP_TEE_READ_TEE_LP_WDT_V 0x00000001U +#define LP_TEE_READ_TEE_LP_WDT_S 0 +/** LP_TEE_READ_REE0_LP_WDT : R/W; bitpos: [1]; default: 0; + * Configures lp_wdt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_WDT (BIT(1)) +#define LP_TEE_READ_REE0_LP_WDT_M (LP_TEE_READ_REE0_LP_WDT_V << LP_TEE_READ_REE0_LP_WDT_S) +#define LP_TEE_READ_REE0_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE0_LP_WDT_S 1 +/** LP_TEE_READ_REE1_LP_WDT : R/W; bitpos: [2]; default: 0; + * Configures lp_wdt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_WDT (BIT(2)) +#define LP_TEE_READ_REE1_LP_WDT_M (LP_TEE_READ_REE1_LP_WDT_V << LP_TEE_READ_REE1_LP_WDT_S) +#define LP_TEE_READ_REE1_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE1_LP_WDT_S 2 +/** LP_TEE_READ_REE2_LP_WDT : R/W; bitpos: [3]; default: 0; + * Configures lp_wdt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_WDT (BIT(3)) +#define LP_TEE_READ_REE2_LP_WDT_M (LP_TEE_READ_REE2_LP_WDT_V << LP_TEE_READ_REE2_LP_WDT_S) +#define LP_TEE_READ_REE2_LP_WDT_V 0x00000001U +#define LP_TEE_READ_REE2_LP_WDT_S 3 +/** LP_TEE_WRITE_TEE_LP_WDT : R/W; bitpos: [4]; default: 1; + * Configures lp_wdt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_WDT (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_WDT_M (LP_TEE_WRITE_TEE_LP_WDT_V << LP_TEE_WRITE_TEE_LP_WDT_S) +#define LP_TEE_WRITE_TEE_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_WDT_S 4 +/** LP_TEE_WRITE_REE0_LP_WDT : R/W; bitpos: [5]; default: 0; + * Configures lp_wdt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_WDT (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_WDT_M (LP_TEE_WRITE_REE0_LP_WDT_V << LP_TEE_WRITE_REE0_LP_WDT_S) +#define LP_TEE_WRITE_REE0_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_WDT_S 5 +/** LP_TEE_WRITE_REE1_LP_WDT : R/W; bitpos: [6]; default: 0; + * Configures lp_wdt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_WDT (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_WDT_M (LP_TEE_WRITE_REE1_LP_WDT_V << LP_TEE_WRITE_REE1_LP_WDT_S) +#define LP_TEE_WRITE_REE1_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_WDT_S 6 +/** LP_TEE_WRITE_REE2_LP_WDT : R/W; bitpos: [7]; default: 0; + * Configures lp_wdt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_WDT (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_WDT_M (LP_TEE_WRITE_REE2_LP_WDT_V << LP_TEE_WRITE_REE2_LP_WDT_S) +#define LP_TEE_WRITE_REE2_LP_WDT_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_WDT_S 7 + +/** LP_TEE_LPPERI_CTRL_REG register + * lpperi read/write control register + */ +#define LP_TEE_LPPERI_CTRL_REG (DR_REG_LP_BASE + 0x1c) +/** LP_TEE_READ_TEE_LPPERI : R/W; bitpos: [0]; default: 1; + * Configures lpperi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LPPERI (BIT(0)) +#define LP_TEE_READ_TEE_LPPERI_M (LP_TEE_READ_TEE_LPPERI_V << LP_TEE_READ_TEE_LPPERI_S) +#define LP_TEE_READ_TEE_LPPERI_V 0x00000001U +#define LP_TEE_READ_TEE_LPPERI_S 0 +/** LP_TEE_READ_REE0_LPPERI : R/W; bitpos: [1]; default: 0; + * Configures lpperi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LPPERI (BIT(1)) +#define LP_TEE_READ_REE0_LPPERI_M (LP_TEE_READ_REE0_LPPERI_V << LP_TEE_READ_REE0_LPPERI_S) +#define LP_TEE_READ_REE0_LPPERI_V 0x00000001U +#define LP_TEE_READ_REE0_LPPERI_S 1 +/** LP_TEE_READ_REE1_LPPERI : R/W; bitpos: [2]; default: 0; + * Configures lpperi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LPPERI (BIT(2)) +#define LP_TEE_READ_REE1_LPPERI_M (LP_TEE_READ_REE1_LPPERI_V << LP_TEE_READ_REE1_LPPERI_S) +#define LP_TEE_READ_REE1_LPPERI_V 0x00000001U +#define LP_TEE_READ_REE1_LPPERI_S 2 +/** LP_TEE_READ_REE2_LPPERI : R/W; bitpos: [3]; default: 0; + * Configures lpperi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LPPERI (BIT(3)) +#define LP_TEE_READ_REE2_LPPERI_M (LP_TEE_READ_REE2_LPPERI_V << LP_TEE_READ_REE2_LPPERI_S) +#define LP_TEE_READ_REE2_LPPERI_V 0x00000001U +#define LP_TEE_READ_REE2_LPPERI_S 3 +/** LP_TEE_WRITE_TEE_LPPERI : R/W; bitpos: [4]; default: 1; + * Configures lpperi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LPPERI (BIT(4)) +#define LP_TEE_WRITE_TEE_LPPERI_M (LP_TEE_WRITE_TEE_LPPERI_V << LP_TEE_WRITE_TEE_LPPERI_S) +#define LP_TEE_WRITE_TEE_LPPERI_V 0x00000001U +#define LP_TEE_WRITE_TEE_LPPERI_S 4 +/** LP_TEE_WRITE_REE0_LPPERI : R/W; bitpos: [5]; default: 0; + * Configures lpperi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LPPERI (BIT(5)) +#define LP_TEE_WRITE_REE0_LPPERI_M (LP_TEE_WRITE_REE0_LPPERI_V << LP_TEE_WRITE_REE0_LPPERI_S) +#define LP_TEE_WRITE_REE0_LPPERI_V 0x00000001U +#define LP_TEE_WRITE_REE0_LPPERI_S 5 +/** LP_TEE_WRITE_REE1_LPPERI : R/W; bitpos: [6]; default: 0; + * Configures lpperi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LPPERI (BIT(6)) +#define LP_TEE_WRITE_REE1_LPPERI_M (LP_TEE_WRITE_REE1_LPPERI_V << LP_TEE_WRITE_REE1_LPPERI_S) +#define LP_TEE_WRITE_REE1_LPPERI_V 0x00000001U +#define LP_TEE_WRITE_REE1_LPPERI_S 6 +/** LP_TEE_WRITE_REE2_LPPERI : R/W; bitpos: [7]; default: 0; + * Configures lpperi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LPPERI (BIT(7)) +#define LP_TEE_WRITE_REE2_LPPERI_M (LP_TEE_WRITE_REE2_LPPERI_V << LP_TEE_WRITE_REE2_LPPERI_S) +#define LP_TEE_WRITE_REE2_LPPERI_V 0x00000001U +#define LP_TEE_WRITE_REE2_LPPERI_S 7 + +/** LP_TEE_LP_ANA_PERI_CTRL_REG register + * lp_ana_peri read/write control register + */ +#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_BASE + 0x20) +/** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; + * Configures lp_ana_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_ANA_PERI (BIT(0)) +#define LP_TEE_READ_TEE_LP_ANA_PERI_M (LP_TEE_READ_TEE_LP_ANA_PERI_V << LP_TEE_READ_TEE_LP_ANA_PERI_S) +#define LP_TEE_READ_TEE_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_TEE_LP_ANA_PERI_S 0 +/** LP_TEE_READ_REE0_LP_ANA_PERI : R/W; bitpos: [1]; default: 0; + * Configures lp_ana_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_ANA_PERI (BIT(1)) +#define LP_TEE_READ_REE0_LP_ANA_PERI_M (LP_TEE_READ_REE0_LP_ANA_PERI_V << LP_TEE_READ_REE0_LP_ANA_PERI_S) +#define LP_TEE_READ_REE0_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE0_LP_ANA_PERI_S 1 +/** LP_TEE_READ_REE1_LP_ANA_PERI : R/W; bitpos: [2]; default: 0; + * Configures lp_ana_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_ANA_PERI (BIT(2)) +#define LP_TEE_READ_REE1_LP_ANA_PERI_M (LP_TEE_READ_REE1_LP_ANA_PERI_V << LP_TEE_READ_REE1_LP_ANA_PERI_S) +#define LP_TEE_READ_REE1_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE1_LP_ANA_PERI_S 2 +/** LP_TEE_READ_REE2_LP_ANA_PERI : R/W; bitpos: [3]; default: 0; + * Configures lp_ana_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_ANA_PERI (BIT(3)) +#define LP_TEE_READ_REE2_LP_ANA_PERI_M (LP_TEE_READ_REE2_LP_ANA_PERI_V << LP_TEE_READ_REE2_LP_ANA_PERI_S) +#define LP_TEE_READ_REE2_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_READ_REE2_LP_ANA_PERI_S 3 +/** LP_TEE_WRITE_TEE_LP_ANA_PERI : R/W; bitpos: [4]; default: 1; + * Configures lp_ana_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_ANA_PERI (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_M (LP_TEE_WRITE_TEE_LP_ANA_PERI_V << LP_TEE_WRITE_TEE_LP_ANA_PERI_S) +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_ANA_PERI_S 4 +/** LP_TEE_WRITE_REE0_LP_ANA_PERI : R/W; bitpos: [5]; default: 0; + * Configures lp_ana_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_ANA_PERI (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_M (LP_TEE_WRITE_REE0_LP_ANA_PERI_V << LP_TEE_WRITE_REE0_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_ANA_PERI_S 5 +/** LP_TEE_WRITE_REE1_LP_ANA_PERI : R/W; bitpos: [6]; default: 0; + * Configures lp_ana_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_ANA_PERI (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_M (LP_TEE_WRITE_REE1_LP_ANA_PERI_V << LP_TEE_WRITE_REE1_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_ANA_PERI_S 6 +/** LP_TEE_WRITE_REE2_LP_ANA_PERI : R/W; bitpos: [7]; default: 0; + * Configures lp_ana_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_ANA_PERI (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_M (LP_TEE_WRITE_REE2_LP_ANA_PERI_V << LP_TEE_WRITE_REE2_LP_ANA_PERI_S) +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7 + +/** LP_TEE_LP_TOUCH_CTRL_REG register + * lp_touch read/write control register + */ +#define LP_TEE_LP_TOUCH_CTRL_REG (DR_REG_LP_BASE + 0x24) +/** LP_TEE_READ_TEE_LP_TOUCH : R/W; bitpos: [0]; default: 1; + * Configures lp_touch registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_TOUCH (BIT(0)) +#define LP_TEE_READ_TEE_LP_TOUCH_M (LP_TEE_READ_TEE_LP_TOUCH_V << LP_TEE_READ_TEE_LP_TOUCH_S) +#define LP_TEE_READ_TEE_LP_TOUCH_V 0x00000001U +#define LP_TEE_READ_TEE_LP_TOUCH_S 0 +/** LP_TEE_READ_REE0_LP_TOUCH : R/W; bitpos: [1]; default: 0; + * Configures lp_touch registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_TOUCH (BIT(1)) +#define LP_TEE_READ_REE0_LP_TOUCH_M (LP_TEE_READ_REE0_LP_TOUCH_V << LP_TEE_READ_REE0_LP_TOUCH_S) +#define LP_TEE_READ_REE0_LP_TOUCH_V 0x00000001U +#define LP_TEE_READ_REE0_LP_TOUCH_S 1 +/** LP_TEE_READ_REE1_LP_TOUCH : R/W; bitpos: [2]; default: 0; + * Configures lp_touch registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_TOUCH (BIT(2)) +#define LP_TEE_READ_REE1_LP_TOUCH_M (LP_TEE_READ_REE1_LP_TOUCH_V << LP_TEE_READ_REE1_LP_TOUCH_S) +#define LP_TEE_READ_REE1_LP_TOUCH_V 0x00000001U +#define LP_TEE_READ_REE1_LP_TOUCH_S 2 +/** LP_TEE_READ_REE2_LP_TOUCH : R/W; bitpos: [3]; default: 0; + * Configures lp_touch registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_TOUCH (BIT(3)) +#define LP_TEE_READ_REE2_LP_TOUCH_M (LP_TEE_READ_REE2_LP_TOUCH_V << LP_TEE_READ_REE2_LP_TOUCH_S) +#define LP_TEE_READ_REE2_LP_TOUCH_V 0x00000001U +#define LP_TEE_READ_REE2_LP_TOUCH_S 3 +/** LP_TEE_WRITE_TEE_LP_TOUCH : R/W; bitpos: [4]; default: 1; + * Configures lp_touch registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_TOUCH (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_TOUCH_M (LP_TEE_WRITE_TEE_LP_TOUCH_V << LP_TEE_WRITE_TEE_LP_TOUCH_S) +#define LP_TEE_WRITE_TEE_LP_TOUCH_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_TOUCH_S 4 +/** LP_TEE_WRITE_REE0_LP_TOUCH : R/W; bitpos: [5]; default: 0; + * Configures lp_touch registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_TOUCH (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_TOUCH_M (LP_TEE_WRITE_REE0_LP_TOUCH_V << LP_TEE_WRITE_REE0_LP_TOUCH_S) +#define LP_TEE_WRITE_REE0_LP_TOUCH_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_TOUCH_S 5 +/** LP_TEE_WRITE_REE1_LP_TOUCH : R/W; bitpos: [6]; default: 0; + * Configures lp_touch registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_TOUCH (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_TOUCH_M (LP_TEE_WRITE_REE1_LP_TOUCH_V << LP_TEE_WRITE_REE1_LP_TOUCH_S) +#define LP_TEE_WRITE_REE1_LP_TOUCH_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_TOUCH_S 6 +/** LP_TEE_WRITE_REE2_LP_TOUCH : R/W; bitpos: [7]; default: 0; + * Configures lp_touch registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_TOUCH (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_TOUCH_M (LP_TEE_WRITE_REE2_LP_TOUCH_V << LP_TEE_WRITE_REE2_LP_TOUCH_S) +#define LP_TEE_WRITE_REE2_LP_TOUCH_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_TOUCH_S 7 + +/** LP_TEE_TOUCH_AON_CTRL_REG register + * touch_aon read/write control register + */ +#define LP_TEE_TOUCH_AON_CTRL_REG (DR_REG_LP_BASE + 0x28) +/** LP_TEE_READ_TEE_TOUCH_AON : R/W; bitpos: [0]; default: 1; + * Configures touch_aon registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_TOUCH_AON (BIT(0)) +#define LP_TEE_READ_TEE_TOUCH_AON_M (LP_TEE_READ_TEE_TOUCH_AON_V << LP_TEE_READ_TEE_TOUCH_AON_S) +#define LP_TEE_READ_TEE_TOUCH_AON_V 0x00000001U +#define LP_TEE_READ_TEE_TOUCH_AON_S 0 +/** LP_TEE_READ_REE0_TOUCH_AON : R/W; bitpos: [1]; default: 0; + * Configures touch_aon registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_TOUCH_AON (BIT(1)) +#define LP_TEE_READ_REE0_TOUCH_AON_M (LP_TEE_READ_REE0_TOUCH_AON_V << LP_TEE_READ_REE0_TOUCH_AON_S) +#define LP_TEE_READ_REE0_TOUCH_AON_V 0x00000001U +#define LP_TEE_READ_REE0_TOUCH_AON_S 1 +/** LP_TEE_READ_REE1_TOUCH_AON : R/W; bitpos: [2]; default: 0; + * Configures touch_aon registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_TOUCH_AON (BIT(2)) +#define LP_TEE_READ_REE1_TOUCH_AON_M (LP_TEE_READ_REE1_TOUCH_AON_V << LP_TEE_READ_REE1_TOUCH_AON_S) +#define LP_TEE_READ_REE1_TOUCH_AON_V 0x00000001U +#define LP_TEE_READ_REE1_TOUCH_AON_S 2 +/** LP_TEE_READ_REE2_TOUCH_AON : R/W; bitpos: [3]; default: 0; + * Configures touch_aon registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_TOUCH_AON (BIT(3)) +#define LP_TEE_READ_REE2_TOUCH_AON_M (LP_TEE_READ_REE2_TOUCH_AON_V << LP_TEE_READ_REE2_TOUCH_AON_S) +#define LP_TEE_READ_REE2_TOUCH_AON_V 0x00000001U +#define LP_TEE_READ_REE2_TOUCH_AON_S 3 +/** LP_TEE_WRITE_TEE_TOUCH_AON : R/W; bitpos: [4]; default: 1; + * Configures touch_aon registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_TOUCH_AON (BIT(4)) +#define LP_TEE_WRITE_TEE_TOUCH_AON_M (LP_TEE_WRITE_TEE_TOUCH_AON_V << LP_TEE_WRITE_TEE_TOUCH_AON_S) +#define LP_TEE_WRITE_TEE_TOUCH_AON_V 0x00000001U +#define LP_TEE_WRITE_TEE_TOUCH_AON_S 4 +/** LP_TEE_WRITE_REE0_TOUCH_AON : R/W; bitpos: [5]; default: 0; + * Configures touch_aon registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_TOUCH_AON (BIT(5)) +#define LP_TEE_WRITE_REE0_TOUCH_AON_M (LP_TEE_WRITE_REE0_TOUCH_AON_V << LP_TEE_WRITE_REE0_TOUCH_AON_S) +#define LP_TEE_WRITE_REE0_TOUCH_AON_V 0x00000001U +#define LP_TEE_WRITE_REE0_TOUCH_AON_S 5 +/** LP_TEE_WRITE_REE1_TOUCH_AON : R/W; bitpos: [6]; default: 0; + * Configures touch_aon registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_TOUCH_AON (BIT(6)) +#define LP_TEE_WRITE_REE1_TOUCH_AON_M (LP_TEE_WRITE_REE1_TOUCH_AON_V << LP_TEE_WRITE_REE1_TOUCH_AON_S) +#define LP_TEE_WRITE_REE1_TOUCH_AON_V 0x00000001U +#define LP_TEE_WRITE_REE1_TOUCH_AON_S 6 +/** LP_TEE_WRITE_REE2_TOUCH_AON : R/W; bitpos: [7]; default: 0; + * Configures touch_aon registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_TOUCH_AON (BIT(7)) +#define LP_TEE_WRITE_REE2_TOUCH_AON_M (LP_TEE_WRITE_REE2_TOUCH_AON_V << LP_TEE_WRITE_REE2_TOUCH_AON_S) +#define LP_TEE_WRITE_REE2_TOUCH_AON_V 0x00000001U +#define LP_TEE_WRITE_REE2_TOUCH_AON_S 7 + +/** LP_TEE_LP_IO_CTRL_REG register + * lp_io read/write control register + */ +#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_BASE + 0x2c) +/** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; + * Configures lp_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_IO (BIT(0)) +#define LP_TEE_READ_TEE_LP_IO_M (LP_TEE_READ_TEE_LP_IO_V << LP_TEE_READ_TEE_LP_IO_S) +#define LP_TEE_READ_TEE_LP_IO_V 0x00000001U +#define LP_TEE_READ_TEE_LP_IO_S 0 +/** LP_TEE_READ_REE0_LP_IO : R/W; bitpos: [1]; default: 0; + * Configures lp_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_IO (BIT(1)) +#define LP_TEE_READ_REE0_LP_IO_M (LP_TEE_READ_REE0_LP_IO_V << LP_TEE_READ_REE0_LP_IO_S) +#define LP_TEE_READ_REE0_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE0_LP_IO_S 1 +/** LP_TEE_READ_REE1_LP_IO : R/W; bitpos: [2]; default: 0; + * Configures lp_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_IO (BIT(2)) +#define LP_TEE_READ_REE1_LP_IO_M (LP_TEE_READ_REE1_LP_IO_V << LP_TEE_READ_REE1_LP_IO_S) +#define LP_TEE_READ_REE1_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE1_LP_IO_S 2 +/** LP_TEE_READ_REE2_LP_IO : R/W; bitpos: [3]; default: 0; + * Configures lp_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_IO (BIT(3)) +#define LP_TEE_READ_REE2_LP_IO_M (LP_TEE_READ_REE2_LP_IO_V << LP_TEE_READ_REE2_LP_IO_S) +#define LP_TEE_READ_REE2_LP_IO_V 0x00000001U +#define LP_TEE_READ_REE2_LP_IO_S 3 +/** LP_TEE_WRITE_TEE_LP_IO : R/W; bitpos: [4]; default: 1; + * Configures lp_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_IO (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_IO_M (LP_TEE_WRITE_TEE_LP_IO_V << LP_TEE_WRITE_TEE_LP_IO_S) +#define LP_TEE_WRITE_TEE_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_IO_S 4 +/** LP_TEE_WRITE_REE0_LP_IO : R/W; bitpos: [5]; default: 0; + * Configures lp_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_IO (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_IO_M (LP_TEE_WRITE_REE0_LP_IO_V << LP_TEE_WRITE_REE0_LP_IO_S) +#define LP_TEE_WRITE_REE0_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_IO_S 5 +/** LP_TEE_WRITE_REE1_LP_IO : R/W; bitpos: [6]; default: 0; + * Configures lp_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_IO (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_IO_M (LP_TEE_WRITE_REE1_LP_IO_V << LP_TEE_WRITE_REE1_LP_IO_S) +#define LP_TEE_WRITE_REE1_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_IO_S 6 +/** LP_TEE_WRITE_REE2_LP_IO : R/W; bitpos: [7]; default: 0; + * Configures lp_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_IO (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_IO_M (LP_TEE_WRITE_REE2_LP_IO_V << LP_TEE_WRITE_REE2_LP_IO_S) +#define LP_TEE_WRITE_REE2_LP_IO_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_IO_S 7 + +/** LP_TEE_LP_BLE_TIMER_CTRL_REG register + * lp_ble_timer read/write control register + */ +#define LP_TEE_LP_BLE_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x30) +/** LP_TEE_READ_TEE_LP_BLE_TIMER : R/W; bitpos: [0]; default: 1; + * Configures lp_ble_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_BLE_TIMER (BIT(0)) +#define LP_TEE_READ_TEE_LP_BLE_TIMER_M (LP_TEE_READ_TEE_LP_BLE_TIMER_V << LP_TEE_READ_TEE_LP_BLE_TIMER_S) +#define LP_TEE_READ_TEE_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_READ_TEE_LP_BLE_TIMER_S 0 +/** LP_TEE_READ_REE0_LP_BLE_TIMER : R/W; bitpos: [1]; default: 0; + * Configures lp_ble_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_BLE_TIMER (BIT(1)) +#define LP_TEE_READ_REE0_LP_BLE_TIMER_M (LP_TEE_READ_REE0_LP_BLE_TIMER_V << LP_TEE_READ_REE0_LP_BLE_TIMER_S) +#define LP_TEE_READ_REE0_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_READ_REE0_LP_BLE_TIMER_S 1 +/** LP_TEE_READ_REE1_LP_BLE_TIMER : R/W; bitpos: [2]; default: 0; + * Configures lp_ble_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_BLE_TIMER (BIT(2)) +#define LP_TEE_READ_REE1_LP_BLE_TIMER_M (LP_TEE_READ_REE1_LP_BLE_TIMER_V << LP_TEE_READ_REE1_LP_BLE_TIMER_S) +#define LP_TEE_READ_REE1_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_READ_REE1_LP_BLE_TIMER_S 2 +/** LP_TEE_READ_REE2_LP_BLE_TIMER : R/W; bitpos: [3]; default: 0; + * Configures lp_ble_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_BLE_TIMER (BIT(3)) +#define LP_TEE_READ_REE2_LP_BLE_TIMER_M (LP_TEE_READ_REE2_LP_BLE_TIMER_V << LP_TEE_READ_REE2_LP_BLE_TIMER_S) +#define LP_TEE_READ_REE2_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_READ_REE2_LP_BLE_TIMER_S 3 +/** LP_TEE_WRITE_TEE_LP_BLE_TIMER : R/W; bitpos: [4]; default: 1; + * Configures lp_ble_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_BLE_TIMER (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_BLE_TIMER_M (LP_TEE_WRITE_TEE_LP_BLE_TIMER_V << LP_TEE_WRITE_TEE_LP_BLE_TIMER_S) +#define LP_TEE_WRITE_TEE_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_BLE_TIMER_S 4 +/** LP_TEE_WRITE_REE0_LP_BLE_TIMER : R/W; bitpos: [5]; default: 0; + * Configures lp_ble_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_BLE_TIMER (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_BLE_TIMER_M (LP_TEE_WRITE_REE0_LP_BLE_TIMER_V << LP_TEE_WRITE_REE0_LP_BLE_TIMER_S) +#define LP_TEE_WRITE_REE0_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_BLE_TIMER_S 5 +/** LP_TEE_WRITE_REE1_LP_BLE_TIMER : R/W; bitpos: [6]; default: 0; + * Configures lp_ble_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_BLE_TIMER (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_BLE_TIMER_M (LP_TEE_WRITE_REE1_LP_BLE_TIMER_V << LP_TEE_WRITE_REE1_LP_BLE_TIMER_S) +#define LP_TEE_WRITE_REE1_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_BLE_TIMER_S 6 +/** LP_TEE_WRITE_REE2_LP_BLE_TIMER : R/W; bitpos: [7]; default: 0; + * Configures lp_ble_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_BLE_TIMER (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_BLE_TIMER_M (LP_TEE_WRITE_REE2_LP_BLE_TIMER_V << LP_TEE_WRITE_REE2_LP_BLE_TIMER_S) +#define LP_TEE_WRITE_REE2_LP_BLE_TIMER_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_BLE_TIMER_S 7 + +/** LP_TEE_LP_TEE_CTRL_REG register + * lp_tee read/write control register + */ +#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_BASE + 0x34) +/** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; + * Configures lp_tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_LP_TEE (BIT(0)) +#define LP_TEE_READ_TEE_LP_TEE_M (LP_TEE_READ_TEE_LP_TEE_V << LP_TEE_READ_TEE_LP_TEE_S) +#define LP_TEE_READ_TEE_LP_TEE_V 0x00000001U +#define LP_TEE_READ_TEE_LP_TEE_S 0 +/** LP_TEE_READ_REE0_LP_TEE : HRO; bitpos: [1]; default: 0; + * Configures lp_tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_LP_TEE (BIT(1)) +#define LP_TEE_READ_REE0_LP_TEE_M (LP_TEE_READ_REE0_LP_TEE_V << LP_TEE_READ_REE0_LP_TEE_S) +#define LP_TEE_READ_REE0_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE0_LP_TEE_S 1 +/** LP_TEE_READ_REE1_LP_TEE : HRO; bitpos: [2]; default: 0; + * Configures lp_tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_LP_TEE (BIT(2)) +#define LP_TEE_READ_REE1_LP_TEE_M (LP_TEE_READ_REE1_LP_TEE_V << LP_TEE_READ_REE1_LP_TEE_S) +#define LP_TEE_READ_REE1_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE1_LP_TEE_S 2 +/** LP_TEE_READ_REE2_LP_TEE : HRO; bitpos: [3]; default: 0; + * Configures lp_tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_LP_TEE (BIT(3)) +#define LP_TEE_READ_REE2_LP_TEE_M (LP_TEE_READ_REE2_LP_TEE_V << LP_TEE_READ_REE2_LP_TEE_S) +#define LP_TEE_READ_REE2_LP_TEE_V 0x00000001U +#define LP_TEE_READ_REE2_LP_TEE_S 3 +/** LP_TEE_WRITE_TEE_LP_TEE : R/W; bitpos: [4]; default: 1; + * Configures lp_tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_LP_TEE (BIT(4)) +#define LP_TEE_WRITE_TEE_LP_TEE_M (LP_TEE_WRITE_TEE_LP_TEE_V << LP_TEE_WRITE_TEE_LP_TEE_S) +#define LP_TEE_WRITE_TEE_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_TEE_LP_TEE_S 4 +/** LP_TEE_WRITE_REE0_LP_TEE : HRO; bitpos: [5]; default: 0; + * Configures lp_tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_LP_TEE (BIT(5)) +#define LP_TEE_WRITE_REE0_LP_TEE_M (LP_TEE_WRITE_REE0_LP_TEE_V << LP_TEE_WRITE_REE0_LP_TEE_S) +#define LP_TEE_WRITE_REE0_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE0_LP_TEE_S 5 +/** LP_TEE_WRITE_REE1_LP_TEE : HRO; bitpos: [6]; default: 0; + * Configures lp_tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_LP_TEE (BIT(6)) +#define LP_TEE_WRITE_REE1_LP_TEE_M (LP_TEE_WRITE_REE1_LP_TEE_V << LP_TEE_WRITE_REE1_LP_TEE_S) +#define LP_TEE_WRITE_REE1_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE1_LP_TEE_S 6 +/** LP_TEE_WRITE_REE2_LP_TEE : HRO; bitpos: [7]; default: 0; + * Configures lp_tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_LP_TEE (BIT(7)) +#define LP_TEE_WRITE_REE2_LP_TEE_M (LP_TEE_WRITE_REE2_LP_TEE_V << LP_TEE_WRITE_REE2_LP_TEE_S) +#define LP_TEE_WRITE_REE2_LP_TEE_V 0x00000001U +#define LP_TEE_WRITE_REE2_LP_TEE_S 7 + +/** LP_TEE_HUK_CTRL_REG register + * lp_tee read/write control register + */ +#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_BASE + 0x38) +/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; + * Configures huk registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_TEE_HUK (BIT(0)) +#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S) +#define LP_TEE_READ_TEE_HUK_V 0x00000001U +#define LP_TEE_READ_TEE_HUK_S 0 +/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0; + * Configures huk registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE0_HUK (BIT(1)) +#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S) +#define LP_TEE_READ_REE0_HUK_V 0x00000001U +#define LP_TEE_READ_REE0_HUK_S 1 +/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0; + * Configures huk registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE1_HUK (BIT(2)) +#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S) +#define LP_TEE_READ_REE1_HUK_V 0x00000001U +#define LP_TEE_READ_REE1_HUK_S 2 +/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0; + * Configures huk registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define LP_TEE_READ_REE2_HUK (BIT(3)) +#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S) +#define LP_TEE_READ_REE2_HUK_V 0x00000001U +#define LP_TEE_READ_REE2_HUK_S 3 +/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1; + * Configures huk registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_TEE_HUK (BIT(4)) +#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S) +#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U +#define LP_TEE_WRITE_TEE_HUK_S 4 +/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0; + * Configures huk registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE0_HUK (BIT(5)) +#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S) +#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE0_HUK_S 5 +/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0; + * Configures huk registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE1_HUK (BIT(6)) +#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S) +#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE1_HUK_S 6 +/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0; + * Configures huk registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define LP_TEE_WRITE_REE2_HUK (BIT(7)) +#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S) +#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U +#define LP_TEE_WRITE_REE2_HUK_S 7 + +/** LP_TEE_BUS_ERR_CONF_REG register + * Clock gating register + */ +#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_BASE + 0xf0) +/** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ +#define LP_TEE_BUS_ERR_RESP_EN (BIT(0)) +#define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S) +#define LP_TEE_BUS_ERR_RESP_EN_V 0x00000001U +#define LP_TEE_BUS_ERR_RESP_EN_S 0 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xf8) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + +/** LP_TEE_DATE_REG register + * Version control register + */ +#define LP_TEE_DATE_REG (DR_REG_LP_BASE + 0xfc) +/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 37818640; + * Version control register + */ +#define LP_TEE_DATE 0x0FFFFFFFU +#define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S) +#define LP_TEE_DATE_V 0x0FFFFFFFU +#define LP_TEE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_tee_struct.h b/components/soc/esp32h4/register/soc/lp_tee_struct.h new file mode 100644 index 0000000000..519a42e2c3 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_tee_struct.h @@ -0,0 +1,968 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: read write control register */ +/** Type of tee_trng_ctrl register + * trng read/write control register + */ +typedef union { + struct { + /** tee_read_tee_trng : R/W; bitpos: [0]; default: 1; + * Configures trng registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_trng:1; + /** tee_read_ree0_trng : R/W; bitpos: [1]; default: 0; + * Configures trng registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_trng:1; + /** tee_read_ree1_trng : R/W; bitpos: [2]; default: 0; + * Configures trng registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_trng:1; + /** tee_read_ree2_trng : R/W; bitpos: [3]; default: 0; + * Configures trng registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_trng:1; + /** tee_write_tee_trng : R/W; bitpos: [4]; default: 1; + * Configures trng registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_trng:1; + /** tee_write_ree0_trng : R/W; bitpos: [5]; default: 0; + * Configures trng registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_trng:1; + /** tee_write_ree1_trng : R/W; bitpos: [6]; default: 0; + * Configures trng registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_trng:1; + /** tee_write_ree2_trng : R/W; bitpos: [7]; default: 0; + * Configures trng registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_trng:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_trng_ctrl_reg_t; + +/** Type of tee_efuse_ctrl register + * efuse read/write control register + */ +typedef union { + struct { + /** tee_read_tee_efuse : R/W; bitpos: [0]; default: 1; + * Configures efuse registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_efuse:1; + /** tee_read_ree0_efuse : R/W; bitpos: [1]; default: 0; + * Configures efuse registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_efuse:1; + /** tee_read_ree1_efuse : R/W; bitpos: [2]; default: 0; + * Configures efuse registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_efuse:1; + /** tee_read_ree2_efuse : R/W; bitpos: [3]; default: 0; + * Configures efuse registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_efuse:1; + /** tee_write_tee_efuse : R/W; bitpos: [4]; default: 1; + * Configures efuse registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_efuse:1; + /** tee_write_ree0_efuse : R/W; bitpos: [5]; default: 0; + * Configures efuse registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_efuse:1; + /** tee_write_ree1_efuse : R/W; bitpos: [6]; default: 0; + * Configures efuse registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_efuse:1; + /** tee_write_ree2_efuse : R/W; bitpos: [7]; default: 0; + * Configures efuse registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_efuse:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_efuse_ctrl_reg_t; + +/** Type of tee_pmu_ctrl register + * pmu read/write control register + */ +typedef union { + struct { + /** tee_read_tee_pmu : R/W; bitpos: [0]; default: 1; + * Configures pmu registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_pmu:1; + /** tee_read_ree0_pmu : R/W; bitpos: [1]; default: 0; + * Configures pmu registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_pmu:1; + /** tee_read_ree1_pmu : R/W; bitpos: [2]; default: 0; + * Configures pmu registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_pmu:1; + /** tee_read_ree2_pmu : R/W; bitpos: [3]; default: 0; + * Configures pmu registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_pmu:1; + /** tee_write_tee_pmu : R/W; bitpos: [4]; default: 1; + * Configures pmu registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_pmu:1; + /** tee_write_ree0_pmu : R/W; bitpos: [5]; default: 0; + * Configures pmu registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_pmu:1; + /** tee_write_ree1_pmu : R/W; bitpos: [6]; default: 0; + * Configures pmu registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_pmu:1; + /** tee_write_ree2_pmu : R/W; bitpos: [7]; default: 0; + * Configures pmu registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_pmu:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_pmu_ctrl_reg_t; + +/** Type of tee_clkrst_ctrl register + * clkrst read/write control register + */ +typedef union { + struct { + /** tee_read_tee_clkrst : R/W; bitpos: [0]; default: 1; + * Configures clkrst registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_clkrst:1; + /** tee_read_ree0_clkrst : R/W; bitpos: [1]; default: 0; + * Configures clkrst registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_clkrst:1; + /** tee_read_ree1_clkrst : R/W; bitpos: [2]; default: 0; + * Configures clkrst registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_clkrst:1; + /** tee_read_ree2_clkrst : R/W; bitpos: [3]; default: 0; + * Configures clkrst registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_clkrst:1; + /** tee_write_tee_clkrst : R/W; bitpos: [4]; default: 1; + * Configures clkrst registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_clkrst:1; + /** tee_write_ree0_clkrst : R/W; bitpos: [5]; default: 0; + * Configures clkrst registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_clkrst:1; + /** tee_write_ree1_clkrst : R/W; bitpos: [6]; default: 0; + * Configures clkrst registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_clkrst:1; + /** tee_write_ree2_clkrst : R/W; bitpos: [7]; default: 0; + * Configures clkrst registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_clkrst:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_clkrst_ctrl_reg_t; + +/** Type of tee_lp_aon_ctrl_ctrl register + * lp_aon_ctrl read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_aon_ctrl : R/W; bitpos: [0]; default: 1; + * Configures lp_aon_ctrl registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_aon_ctrl:1; + /** tee_read_ree0_lp_aon_ctrl : R/W; bitpos: [1]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_aon_ctrl:1; + /** tee_read_ree1_lp_aon_ctrl : R/W; bitpos: [2]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_aon_ctrl:1; + /** tee_read_ree2_lp_aon_ctrl : R/W; bitpos: [3]; default: 0; + * Configures lp_aon_ctrl registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_aon_ctrl:1; + /** tee_write_tee_lp_aon_ctrl : R/W; bitpos: [4]; default: 1; + * Configures lp_aon_ctrl registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_aon_ctrl:1; + /** tee_write_ree0_lp_aon_ctrl : R/W; bitpos: [5]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_aon_ctrl:1; + /** tee_write_ree1_lp_aon_ctrl : R/W; bitpos: [6]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_aon_ctrl:1; + /** tee_write_ree2_lp_aon_ctrl : R/W; bitpos: [7]; default: 0; + * Configures lp_aon_ctrl registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_aon_ctrl:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_aon_ctrl_ctrl_reg_t; + +/** Type of tee_lp_timer_ctrl register + * lp_timer read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_timer : R/W; bitpos: [0]; default: 1; + * Configures lp_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_timer:1; + /** tee_read_ree0_lp_timer : R/W; bitpos: [1]; default: 0; + * Configures lp_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_timer:1; + /** tee_read_ree1_lp_timer : R/W; bitpos: [2]; default: 0; + * Configures lp_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_timer:1; + /** tee_read_ree2_lp_timer : R/W; bitpos: [3]; default: 0; + * Configures lp_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_timer:1; + /** tee_write_tee_lp_timer : R/W; bitpos: [4]; default: 1; + * Configures lp_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_timer:1; + /** tee_write_ree0_lp_timer : R/W; bitpos: [5]; default: 0; + * Configures lp_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_timer:1; + /** tee_write_ree1_lp_timer : R/W; bitpos: [6]; default: 0; + * Configures lp_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_timer:1; + /** tee_write_ree2_lp_timer : R/W; bitpos: [7]; default: 0; + * Configures lp_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_timer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_timer_ctrl_reg_t; + +/** Type of tee_lp_wdt_ctrl register + * lp_wdt read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_wdt : R/W; bitpos: [0]; default: 1; + * Configures lp_wdt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_wdt:1; + /** tee_read_ree0_lp_wdt : R/W; bitpos: [1]; default: 0; + * Configures lp_wdt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_wdt:1; + /** tee_read_ree1_lp_wdt : R/W; bitpos: [2]; default: 0; + * Configures lp_wdt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_wdt:1; + /** tee_read_ree2_lp_wdt : R/W; bitpos: [3]; default: 0; + * Configures lp_wdt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_wdt:1; + /** tee_write_tee_lp_wdt : R/W; bitpos: [4]; default: 1; + * Configures lp_wdt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_wdt:1; + /** tee_write_ree0_lp_wdt : R/W; bitpos: [5]; default: 0; + * Configures lp_wdt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_wdt:1; + /** tee_write_ree1_lp_wdt : R/W; bitpos: [6]; default: 0; + * Configures lp_wdt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_wdt:1; + /** tee_write_ree2_lp_wdt : R/W; bitpos: [7]; default: 0; + * Configures lp_wdt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_wdt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_wdt_ctrl_reg_t; + +/** Type of tee_lpperi_ctrl register + * lpperi read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lpperi : R/W; bitpos: [0]; default: 1; + * Configures lpperi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lpperi:1; + /** tee_read_ree0_lpperi : R/W; bitpos: [1]; default: 0; + * Configures lpperi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lpperi:1; + /** tee_read_ree1_lpperi : R/W; bitpos: [2]; default: 0; + * Configures lpperi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lpperi:1; + /** tee_read_ree2_lpperi : R/W; bitpos: [3]; default: 0; + * Configures lpperi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lpperi:1; + /** tee_write_tee_lpperi : R/W; bitpos: [4]; default: 1; + * Configures lpperi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lpperi:1; + /** tee_write_ree0_lpperi : R/W; bitpos: [5]; default: 0; + * Configures lpperi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lpperi:1; + /** tee_write_ree1_lpperi : R/W; bitpos: [6]; default: 0; + * Configures lpperi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lpperi:1; + /** tee_write_ree2_lpperi : R/W; bitpos: [7]; default: 0; + * Configures lpperi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lpperi:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lpperi_ctrl_reg_t; + +/** Type of tee_lp_ana_peri_ctrl register + * lp_ana_peri read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_ana_peri : R/W; bitpos: [0]; default: 1; + * Configures lp_ana_peri registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_ana_peri:1; + /** tee_read_ree0_lp_ana_peri : R/W; bitpos: [1]; default: 0; + * Configures lp_ana_peri registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_ana_peri:1; + /** tee_read_ree1_lp_ana_peri : R/W; bitpos: [2]; default: 0; + * Configures lp_ana_peri registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_ana_peri:1; + /** tee_read_ree2_lp_ana_peri : R/W; bitpos: [3]; default: 0; + * Configures lp_ana_peri registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_ana_peri:1; + /** tee_write_tee_lp_ana_peri : R/W; bitpos: [4]; default: 1; + * Configures lp_ana_peri registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_ana_peri:1; + /** tee_write_ree0_lp_ana_peri : R/W; bitpos: [5]; default: 0; + * Configures lp_ana_peri registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_ana_peri:1; + /** tee_write_ree1_lp_ana_peri : R/W; bitpos: [6]; default: 0; + * Configures lp_ana_peri registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_ana_peri:1; + /** tee_write_ree2_lp_ana_peri : R/W; bitpos: [7]; default: 0; + * Configures lp_ana_peri registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_ana_peri:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_ana_peri_ctrl_reg_t; + +/** Type of tee_lp_touch_ctrl register + * lp_touch read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_touch : R/W; bitpos: [0]; default: 1; + * Configures lp_touch registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_touch:1; + /** tee_read_ree0_lp_touch : R/W; bitpos: [1]; default: 0; + * Configures lp_touch registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_touch:1; + /** tee_read_ree1_lp_touch : R/W; bitpos: [2]; default: 0; + * Configures lp_touch registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_touch:1; + /** tee_read_ree2_lp_touch : R/W; bitpos: [3]; default: 0; + * Configures lp_touch registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_touch:1; + /** tee_write_tee_lp_touch : R/W; bitpos: [4]; default: 1; + * Configures lp_touch registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_touch:1; + /** tee_write_ree0_lp_touch : R/W; bitpos: [5]; default: 0; + * Configures lp_touch registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_touch:1; + /** tee_write_ree1_lp_touch : R/W; bitpos: [6]; default: 0; + * Configures lp_touch registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_touch:1; + /** tee_write_ree2_lp_touch : R/W; bitpos: [7]; default: 0; + * Configures lp_touch registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_touch:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_touch_ctrl_reg_t; + +/** Type of tee_touch_aon_ctrl register + * touch_aon read/write control register + */ +typedef union { + struct { + /** tee_read_tee_touch_aon : R/W; bitpos: [0]; default: 1; + * Configures touch_aon registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_touch_aon:1; + /** tee_read_ree0_touch_aon : R/W; bitpos: [1]; default: 0; + * Configures touch_aon registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_touch_aon:1; + /** tee_read_ree1_touch_aon : R/W; bitpos: [2]; default: 0; + * Configures touch_aon registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_touch_aon:1; + /** tee_read_ree2_touch_aon : R/W; bitpos: [3]; default: 0; + * Configures touch_aon registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_touch_aon:1; + /** tee_write_tee_touch_aon : R/W; bitpos: [4]; default: 1; + * Configures touch_aon registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_touch_aon:1; + /** tee_write_ree0_touch_aon : R/W; bitpos: [5]; default: 0; + * Configures touch_aon registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_touch_aon:1; + /** tee_write_ree1_touch_aon : R/W; bitpos: [6]; default: 0; + * Configures touch_aon registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_touch_aon:1; + /** tee_write_ree2_touch_aon : R/W; bitpos: [7]; default: 0; + * Configures touch_aon registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_touch_aon:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_touch_aon_ctrl_reg_t; + +/** Type of tee_lp_io_ctrl register + * lp_io read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_io : R/W; bitpos: [0]; default: 1; + * Configures lp_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_io:1; + /** tee_read_ree0_lp_io : R/W; bitpos: [1]; default: 0; + * Configures lp_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_io:1; + /** tee_read_ree1_lp_io : R/W; bitpos: [2]; default: 0; + * Configures lp_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_io:1; + /** tee_read_ree2_lp_io : R/W; bitpos: [3]; default: 0; + * Configures lp_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_io:1; + /** tee_write_tee_lp_io : R/W; bitpos: [4]; default: 1; + * Configures lp_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_io:1; + /** tee_write_ree0_lp_io : R/W; bitpos: [5]; default: 0; + * Configures lp_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_io:1; + /** tee_write_ree1_lp_io : R/W; bitpos: [6]; default: 0; + * Configures lp_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_io:1; + /** tee_write_ree2_lp_io : R/W; bitpos: [7]; default: 0; + * Configures lp_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_io:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_io_ctrl_reg_t; + +/** Type of tee_lp_ble_timer_ctrl register + * lp_ble_timer read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_ble_timer : R/W; bitpos: [0]; default: 1; + * Configures lp_ble_timer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_ble_timer:1; + /** tee_read_ree0_lp_ble_timer : R/W; bitpos: [1]; default: 0; + * Configures lp_ble_timer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_ble_timer:1; + /** tee_read_ree1_lp_ble_timer : R/W; bitpos: [2]; default: 0; + * Configures lp_ble_timer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_ble_timer:1; + /** tee_read_ree2_lp_ble_timer : R/W; bitpos: [3]; default: 0; + * Configures lp_ble_timer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_ble_timer:1; + /** tee_write_tee_lp_ble_timer : R/W; bitpos: [4]; default: 1; + * Configures lp_ble_timer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_ble_timer:1; + /** tee_write_ree0_lp_ble_timer : R/W; bitpos: [5]; default: 0; + * Configures lp_ble_timer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_ble_timer:1; + /** tee_write_ree1_lp_ble_timer : R/W; bitpos: [6]; default: 0; + * Configures lp_ble_timer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_ble_timer:1; + /** tee_write_ree2_lp_ble_timer : R/W; bitpos: [7]; default: 0; + * Configures lp_ble_timer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_ble_timer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_ble_timer_ctrl_reg_t; + +/** Type of tee_lp_tee_ctrl register + * lp_tee read/write control register + */ +typedef union { + struct { + /** tee_read_tee_lp_tee : R/W; bitpos: [0]; default: 1; + * Configures lp_tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_lp_tee:1; + /** tee_read_ree0_lp_tee : HRO; bitpos: [1]; default: 0; + * Configures lp_tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_lp_tee:1; + /** tee_read_ree1_lp_tee : HRO; bitpos: [2]; default: 0; + * Configures lp_tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_lp_tee:1; + /** tee_read_ree2_lp_tee : HRO; bitpos: [3]; default: 0; + * Configures lp_tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_lp_tee:1; + /** tee_write_tee_lp_tee : R/W; bitpos: [4]; default: 1; + * Configures lp_tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_lp_tee:1; + /** tee_write_ree0_lp_tee : HRO; bitpos: [5]; default: 0; + * Configures lp_tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_lp_tee:1; + /** tee_write_ree1_lp_tee : HRO; bitpos: [6]; default: 0; + * Configures lp_tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_lp_tee:1; + /** tee_write_ree2_lp_tee : HRO; bitpos: [7]; default: 0; + * Configures lp_tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_lp_tee:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_lp_tee_ctrl_reg_t; + +/** Type of tee_huk_ctrl register + * lp_tee read/write control register + */ +typedef union { + struct { + /** tee_read_tee_huk : R/W; bitpos: [0]; default: 1; + * Configures huk registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_tee_huk:1; + /** tee_read_ree0_huk : R/W; bitpos: [1]; default: 0; + * Configures huk registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree0_huk:1; + /** tee_read_ree1_huk : R/W; bitpos: [2]; default: 0; + * Configures huk registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree1_huk:1; + /** tee_read_ree2_huk : R/W; bitpos: [3]; default: 0; + * Configures huk registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t tee_read_ree2_huk:1; + /** tee_write_tee_huk : R/W; bitpos: [4]; default: 1; + * Configures huk registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_tee_huk:1; + /** tee_write_ree0_huk : R/W; bitpos: [5]; default: 0; + * Configures huk registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree0_huk:1; + /** tee_write_ree1_huk : R/W; bitpos: [6]; default: 0; + * Configures huk registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree1_huk:1; + /** tee_write_ree2_huk : R/W; bitpos: [7]; default: 0; + * Configures huk registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t tee_write_ree2_huk:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_huk_ctrl_reg_t; + + +/** Group: config register */ +/** Type of tee_bus_err_conf register + * Clock gating register + */ +typedef union { + struct { + /** tee_bus_err_resp_en : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ + uint32_t tee_bus_err_resp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_bus_err_conf_reg_t; + + +/** Group: clock gating register */ +/** Type of tee_clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** tee_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t tee_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of tee_date register + * Version control register + */ +typedef union { + struct { + /** tee_date : R/W; bitpos: [27:0]; default: 37818640; + * Version control register + */ + uint32_t tee_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_tee_date_reg_t; + + +typedef struct { + volatile lp_tee_trng_ctrl_reg_t tee_trng_ctrl; + volatile lp_tee_efuse_ctrl_reg_t tee_efuse_ctrl; + volatile lp_tee_pmu_ctrl_reg_t tee_pmu_ctrl; + volatile lp_tee_clkrst_ctrl_reg_t tee_clkrst_ctrl; + volatile lp_tee_lp_aon_ctrl_ctrl_reg_t tee_lp_aon_ctrl_ctrl; + volatile lp_tee_lp_timer_ctrl_reg_t tee_lp_timer_ctrl; + volatile lp_tee_lp_wdt_ctrl_reg_t tee_lp_wdt_ctrl; + volatile lp_tee_lpperi_ctrl_reg_t tee_lpperi_ctrl; + volatile lp_tee_lp_ana_peri_ctrl_reg_t tee_lp_ana_peri_ctrl; + volatile lp_tee_lp_touch_ctrl_reg_t tee_lp_touch_ctrl; + volatile lp_tee_touch_aon_ctrl_reg_t tee_touch_aon_ctrl; + volatile lp_tee_lp_io_ctrl_reg_t tee_lp_io_ctrl; + volatile lp_tee_lp_ble_timer_ctrl_reg_t tee_lp_ble_timer_ctrl; + volatile lp_tee_lp_tee_ctrl_reg_t tee_lp_tee_ctrl; + volatile lp_tee_huk_ctrl_reg_t tee_huk_ctrl; + uint32_t reserved_03c[45]; + volatile lp_tee_bus_err_conf_reg_t tee_bus_err_conf; + uint32_t reserved_0f4; + volatile lp_tee_clock_gate_reg_t tee_clock_gate; + volatile lp_tee_date_reg_t tee_date; +} lp_tee_dev_t; + +extern lp_tee_dev_t LP_TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_timer_reg.h b/components/soc/esp32h4/register/soc/lp_timer_reg.h new file mode 100644 index 0000000000..98181a1c2e --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_timer_reg.h @@ -0,0 +1,345 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * RTC timer threshold low bits register0 + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare0. + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * RTC timer enable register0 + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare0 + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare0 alarm. + * 0: Disable + * 1: Enable + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * RTC timer threshold low bits register1 + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare1. + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * RTC timer threshold high bits register0 + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare1 + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare1 alarm. + * 0: Disable + * 1: Enable + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * RTC timer update control register + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0; + * Triggers timer by software + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 27 +/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28)) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers + * up + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when CPU enters or + * exits the stall state. + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when resetting digital + * core completes + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * RTC timer buffer0 low bits register + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer0 low bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * RTC timer buffer0 high bits register + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer0 high bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * RTC timer buffer1 low bits register + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer1 low bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * RTC timer buffer1 high bits register + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer1 high bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_INT_RAW_REG register + * RTC timer interrupt raw register + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow. + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value. + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * RTC timer interrupt status register + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * RTC timer interrupt enable register + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt.. + * 0 : Disable + * 1: Enable + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt.. + * 0 : Disable + * 1: Enable + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * RTC timer interrupt clear register + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow raw interrupt.. + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer raw interrupt.. + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * RTC timer interrupt raw register(For ULP) + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * RTC timer interrupt status register(For ULP) + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * RTC timer interrupt enable register(For ULP) + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt.. + * 0 : Disable + * 1: Enable + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt.. + * 0 : Disable + * 1: Enable + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * RTC timer interrupt clear register(For ULP) + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow clear interrupt.. + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer clear interrupt.. + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * Date register + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 36769936; + * Version data + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_timer_struct.h b/components/soc/esp32h4/register/soc/lp_timer_struct.h new file mode 100644 index 0000000000..d062f660c5 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_timer_struct.h @@ -0,0 +1,365 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of timer_tar0_low register + * RTC timer threshold low bits register0 + */ +typedef union { + struct { + /** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare0. + */ + uint32_t timer_main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of timer_tar0_high register + * RTC timer enable register0 + */ +typedef union { + struct { + /** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare0 + */ + uint32_t timer_main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare0 alarm. + * 0: Disable + * 1: Enable + */ + uint32_t timer_main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of timer_tar1_low register + * RTC timer threshold low bits register1 + */ +typedef union { + struct { + /** timer_main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare1. + */ + uint32_t timer_main_timer_tar_low1:32; + }; + uint32_t val; +} lp_timer_tar1_low_reg_t; + +/** Type of timer_tar1_high register + * RTC timer threshold high bits register0 + */ +typedef union { + struct { + /** timer_main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare1 + */ + uint32_t timer_main_timer_tar_high1:16; + uint32_t reserved_16:15; + /** timer_main_timer_tar_en1 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare1 alarm. + * 0: Disable + * 1: Enable + */ + uint32_t timer_main_timer_tar_en1:1; + }; + uint32_t val; +} lp_timer_tar1_high_reg_t; + +/** Type of timer_update register + * RTC timer update control register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** timer_main_timer_update : WT; bitpos: [27]; default: 0; + * Triggers timer by software + */ + uint32_t timer_main_timer_update:1; + /** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ + uint32_t timer_main_timer_regdma_work:1; + /** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers + * up + */ + uint32_t timer_main_timer_xtal_off:1; + /** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when CPU enters or + * exits the stall state. + */ + uint32_t timer_main_timer_sys_stall:1; + /** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when resetting digital + * core completes + */ + uint32_t timer_main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of timer_main_buf0_low register + * RTC timer buffer0 low bits register + */ +typedef union { + struct { + /** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer0 low bits register + */ + uint32_t timer_main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of timer_main_buf0_high register + * RTC timer buffer0 high bits register + */ +typedef union { + struct { + /** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer0 high bits register + */ + uint32_t timer_main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of timer_main_buf1_low register + * RTC timer buffer1 low bits register + */ +typedef union { + struct { + /** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer1 low bits register + */ + uint32_t timer_main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of timer_main_buf1_high register + * RTC timer buffer1 high bits register + */ +typedef union { + struct { + /** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer1 high bits register + */ + uint32_t timer_main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of timer_int_raw register + * RTC timer interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow. + */ + uint32_t timer_overflow_raw:1; + /** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value. + */ + uint32_t timer_soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of timer_int_st register + * RTC timer interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_st : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ + uint32_t timer_overflow_st:1; + /** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ + uint32_t timer_soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of timer_int_ena register + * RTC timer interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_ena : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt.. + * 0 : Disable + * 1: Enable + */ + uint32_t timer_overflow_ena:1; + /** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt.. + * 0 : Disable + * 1: Enable + */ + uint32_t timer_soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of timer_int_clr register + * RTC timer interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_clr : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow raw interrupt.. + */ + uint32_t timer_overflow_clr:1; + /** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer raw interrupt.. + */ + uint32_t timer_soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of timer_lp_int_raw register + * RTC timer interrupt raw register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow + */ + uint32_t timer_main_timer_overflow_lp_int_raw:1; + /** timer_main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value + */ + uint32_t timer_main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of timer_lp_int_st register + * RTC timer interrupt status register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ + uint32_t timer_main_timer_overflow_lp_int_st:1; + /** timer_main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ + uint32_t timer_main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of timer_lp_int_ena register + * RTC timer interrupt enable register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt.. + * 0 : Disable + * 1: Enable + */ + uint32_t timer_main_timer_overflow_lp_int_ena:1; + /** timer_main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt.. + * 0 : Disable + * 1: Enable + */ + uint32_t timer_main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of timer_lp_int_clr register + * RTC timer interrupt clear register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow clear interrupt.. + */ + uint32_t timer_main_timer_overflow_lp_int_clr:1; + /** timer_main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer clear interrupt.. + */ + uint32_t timer_main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of timer_date register + * Date register + */ +typedef union { + struct { + /** timer_date : R/W; bitpos: [30:0]; default: 36769936; + * Version data + */ + uint32_t timer_date:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t timer_tar0_low; + volatile lp_timer_tar0_high_reg_t timer_tar0_high; + volatile lp_timer_tar1_low_reg_t timer_tar1_low; + volatile lp_timer_tar1_high_reg_t timer_tar1_high; + volatile lp_timer_update_reg_t timer_update; + volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high; + uint32_t reserved_024; + volatile lp_timer_int_raw_reg_t timer_int_raw; + volatile lp_timer_int_st_reg_t timer_int_st; + volatile lp_timer_int_ena_reg_t timer_int_ena; + volatile lp_timer_int_clr_reg_t timer_int_clr; + volatile lp_timer_lp_int_raw_reg_t timer_lp_int_raw; + volatile lp_timer_lp_int_st_reg_t timer_lp_int_st; + volatile lp_timer_lp_int_ena_reg_t timer_lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t timer_lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t timer_date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_wdt_reg.h b/components/soc/esp32h4/register/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..d46daf3b14 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_wdt_reg.h @@ -0,0 +1,370 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * Configure the RWDT operation. + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * Configure whether or not pause RWDT when chip is in sleep mode. + * 0:Enable + * 1:Disable + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * Configure whether or not enable RWDT when chip is in SPI boot mode. + * 0:Disable + * 1:Enable + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * Configure the HP core reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * Configure the HP CPU reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * Configure the timeout action of stage3. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * Configure the timeout action of stage2. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * Configure the timeout action of stage1. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * Configure the timeout action of stage0. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable RWDT. + * 0:Disable + * 1:Enable + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * Configure the RWDT timeout of stage0 + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * Configure the timeout time for stage0. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * Configure the RWDT timeout of stage1 + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * Configure the timeout time for stage1. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * Configure the RWDT timeout of stage2 + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage2. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * Configure the RWDT timeout of stage3 + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage3. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * Configure the feed function of RWDT + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the RWDT. + * 0: Invalid + * 1: Feed RWDT + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * Configure the lock function of SWD + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock RWDT`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * Configure the SWD operation + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * Represents the SWD whether has generated the reset signal. + * 0 :No + * 1: Yes + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * Configure this bit to enable to feed SWD automatically by hardware. + * 0: Disable + * 1: Enable + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * Configure this bit to clear SWD reset flag. + * 0:Invalid + * 1: Clear the reset flag + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * Configure the SWD signal length that output to analog circuit. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * Configure this bit to disable the SWD. + * 0: Enable the SWD + * 1: Disable the SWD + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the SWD. + * 0: Invalid + * 1: Feed SWD + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * Configure the lock function of SWD + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock SWD`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * Configure whether to generate timeout interrupt + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Represents the SWD whether or not generates timeout interrupt. + * 0:No + * 1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Represents the RWDT whether or not generates timeout interrupt. + * 0:No + * 1: Yes + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * The interrupt status register of WDT + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * Represents the SWD whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * Represents the RWDT whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * The interrupt enable register of WDT + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * Configure whether or not to enable the SWD to send timeout interrupt. + * 0:Disable + * 1:Enable + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable the RWDT to send timeout interrupt. + * 0:Disable + * 1:Enable + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * The interrupt clear register of WDT + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x34) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU. + * 0: No + * 1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU. + * 0: No + * 1: Yes + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 37765456; + * Version control register + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/lp_wdt_struct.h b/components/soc/esp32h4/register/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..551cbf19e2 --- /dev/null +++ b/components/soc/esp32h4/register/soc/lp_wdt_struct.h @@ -0,0 +1,401 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of wdt_config0 register + * Configure the RWDT operation. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * Configure whether or not pause RWDT when chip is in sleep mode. + * 0:Enable + * 1:Disable + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * Configure whether or not to enable RWDT to reset CPU. + * 0:Disable + * 1:Enable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * Configure whether or not enable RWDT when chip is in SPI boot mode. + * 0:Disable + * 1:Enable + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * Configure the HP core reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * Configure the HP CPU reset time. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * Configure the timeout action of stage3. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * Configure the timeout action of stage2. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * Configure the timeout action of stage1. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * Configure the timeout action of stage0. + * 0: No operation + * 1:Generate interrupt + * 2 :Generate HP CPU reset + * 3:Generate HP core reset + * 4 :Generate system reset. + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable RWDT. + * 0:Disable + * 1:Enable + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of wdt_config1 register + * Configure the RWDT timeout of stage0 + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * Configure the timeout time for stage0. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of wdt_config2 register + * Configure the RWDT timeout of stage1 + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * Configure the timeout time for stage1. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of wdt_config3 register + * Configure the RWDT timeout of stage2 + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage2. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of wdt_config4 register + * Configure the RWDT timeout of stage3 + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage3. + * Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of wdt_config5 register + * need_des + */ +typedef union { + struct { + /** wdt_chip_reset_target : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t wdt_chip_reset_target:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; + /** wdt_chip_reset_key : R/W; bitpos: [16:9]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_key:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_wdt_config5_reg_t; + +/** Type of wdt_feed register + * Configure the feed function of RWDT + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** wdt_rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the RWDT. + * 0: Invalid + * 1: Feed RWDT + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wdt_wprotect register + * Configure the lock function of SWD + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock RWDT`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of wdt_swd_config register + * Configure the SWD operation + */ +typedef union { + struct { + /** wdt_swd_reset_flag : RO; bitpos: [0]; default: 0; + * Represents the SWD whether has generated the reset signal. + * 0 :No + * 1: Yes + */ + uint32_t wdt_swd_reset_flag:1; + uint32_t reserved_1:17; + /** wdt_swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * Configure this bit to enable to feed SWD automatically by hardware. + * 0: Disable + * 1: Enable + */ + uint32_t wdt_swd_auto_feed_en:1; + /** wdt_swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * Configure this bit to clear SWD reset flag. + * 0:Invalid + * 1: Clear the reset flag + */ + uint32_t wdt_swd_rst_flag_clr:1; + /** wdt_swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * Configure the SWD signal length that output to analog circuit. + * Measurement unit: LP\_DYN\_FAST\_CLK + */ + uint32_t wdt_swd_signal_width:10; + /** wdt_swd_disable : R/W; bitpos: [30]; default: 0; + * Configure this bit to disable the SWD. + * 0: Enable the SWD + * 1: Disable the SWD + */ + uint32_t wdt_swd_disable:1; + /** wdt_swd_feed : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the SWD. + * 0: Invalid + * 1: Feed SWD + */ + uint32_t wdt_swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of wdt_swd_wprotect register + * Configure the lock function of SWD + */ +typedef union { + struct { + /** wdt_swd_wkey : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock SWD`s configuration registers. + * 0x50D83AA1: unlock the RWDT configuration registers. + * Others value: Lock the RWDT configuration register which can`t be modified by + * software. + */ + uint32_t wdt_swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of wdt_int_raw register + * Configure whether to generate timeout interrupt + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Represents the SWD whether or not generates timeout interrupt. + * 0:No + * 1: Yes + */ + uint32_t wdt_super_wdt_int_raw:1; + /** wdt_lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Represents the RWDT whether or not generates timeout interrupt. + * 0:No + * 1: Yes + */ + uint32_t wdt_lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of wdt_int_st register + * The interrupt status register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_st : RO; bitpos: [30]; default: 0; + * Represents the SWD whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes + */ + uint32_t wdt_super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * Represents the RWDT whether or not has generated and sent timeout interrupt to CPU. + * 0:No + * 1: Yes + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of wdt_int_ena register + * The interrupt enable register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * Configure whether or not to enable the SWD to send timeout interrupt. + * 0:Disable + * 1:Enable + */ + uint32_t wdt_super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable the RWDT to send timeout interrupt. + * 0:Disable + * 1:Enable + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of wdt_int_clr register + * The interrupt clear register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU. + * 0: No + * 1: Yes + */ + uint32_t wdt_super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU. + * 0: No + * 1: Yes + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of wdt_date register + * need_des + */ +typedef union { + struct { + /** wdt_lp_wdt_date : R/W; bitpos: [30:0]; default: 37765456; + * Version control register + */ + uint32_t wdt_lp_wdt_date:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_config5_reg_t config5; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_038[241]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/rng_reg.h b/components/soc/esp32h4/register/soc/rng_reg.h new file mode 100644 index 0000000000..99c7d3c703 --- /dev/null +++ b/components/soc/esp32h4/register/soc/rng_reg.h @@ -0,0 +1,99 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RNG_DATA_REG register + * RNG result register + */ +#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x0) +/** RNG_RND_DATA : RO; bitpos: [31:0]; default: 0; + * get rng data + */ +#define RNG_RND_DATA 0xFFFFFFFFU +#define RNG_RND_DATA_M (RNG_RND_DATA_V << RNG_RND_DATA_S) +#define RNG_RND_DATA_V 0xFFFFFFFFU +#define RNG_RND_DATA_S 0 + +/** RNG_CFG_REG register + * configure rng register + */ +#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x4) +/** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define RNG_SAMPLE_ENABLE (BIT(0)) +#define RNG_SAMPLE_ENABLE_M (RNG_SAMPLE_ENABLE_V << RNG_SAMPLE_ENABLE_S) +#define RNG_SAMPLE_ENABLE_V 0x00000001U +#define RNG_SAMPLE_ENABLE_S 0 +/** RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * configure rng timer clk div + */ +#define RNG_TIMER_PSCALE 0x000000FFU +#define RNG_TIMER_PSCALE_M (RNG_TIMER_PSCALE_V << RNG_TIMER_PSCALE_S) +#define RNG_TIMER_PSCALE_V 0x000000FFU +#define RNG_TIMER_PSCALE_S 1 +/** RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * enable rng xor async rng timer + */ +#define RNG_TIMER_EN (BIT(9)) +#define RNG_TIMER_EN_M (RNG_TIMER_EN_V << RNG_TIMER_EN_S) +#define RNG_TIMER_EN_V 0x00000001U +#define RNG_TIMER_EN_S 9 +/** RNG_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * reserved + */ +#define RNG_RTC_TIMER_EN 0x00000003U +#define RNG_RTC_TIMER_EN_M (RNG_RTC_TIMER_EN_V << RNG_RTC_TIMER_EN_S) +#define RNG_RTC_TIMER_EN_V 0x00000003U +#define RNG_RTC_TIMER_EN_S 10 +/** RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * reserved + */ +#define RNG_SAMPLE_CNT 0x000000FFU +#define RNG_SAMPLE_CNT_M (RNG_SAMPLE_CNT_V << RNG_SAMPLE_CNT_S) +#define RNG_SAMPLE_CNT_V 0x000000FFU +#define RNG_SAMPLE_CNT_S 24 + +/** RNG_DATA_SYNC_REG register + * rng result sync register + */ +#define RNG_DATA_SYNC_REG (DR_REG_RNG_BASE + 0x8) +/** RNG_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * get rnd sync result + */ +#define RNG_RND_SYNC_DATA 0xFFFFFFFFU +#define RNG_RND_SYNC_DATA_M (RNG_RND_SYNC_DATA_V << RNG_RND_SYNC_DATA_S) +#define RNG_RND_SYNC_DATA_V 0xFFFFFFFFU +#define RNG_RND_SYNC_DATA_S 0 + +/** RNG_DATE_REG register + * Date register. + */ +#define RNG_DATE_REG (DR_REG_RNG_BASE + 0x3fc) +/** RNG_DATE : R/W; bitpos: [30:0]; default: 36708608; + * RNG date information/ RNG version information. + */ +#define RNG_DATE 0x7FFFFFFFU +#define RNG_DATE_M (RNG_DATE_V << RNG_DATE_S) +#define RNG_DATE_V 0x7FFFFFFFU +#define RNG_DATE_S 0 +/** RNG_CLK_EN : R/W; bitpos: [31]; default: 0; + * force on reg clk + */ +#define RNG_CLK_EN (BIT(31)) +#define RNG_CLK_EN_M (RNG_CLK_EN_V << RNG_CLK_EN_S) +#define RNG_CLK_EN_V 0x00000001U +#define RNG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/rng_struct.h b/components/soc/esp32h4/register/soc/rng_struct.h new file mode 100644 index 0000000000..1f2a6d1a31 --- /dev/null +++ b/components/soc/esp32h4/register/soc/rng_struct.h @@ -0,0 +1,106 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of data register + * RNG result register + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * get rng data + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} rng_data_reg_t; + +/** Type of cfg register + * configure rng register + */ +typedef union { + struct { + /** sample_enable : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t sample_enable:1; + /** timer_pscale : R/W; bitpos: [8:1]; default: 255; + * configure rng timer clk div + */ + uint32_t timer_pscale:8; + /** timer_en : R/W; bitpos: [9]; default: 1; + * enable rng xor async rng timer + */ + uint32_t timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * reserved + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** sample_cnt : RO; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t sample_cnt:8; + }; + uint32_t val; +} rng_cfg_reg_t; + +/** Type of data_sync register + * rng result sync register + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * get rnd sync result + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} rng_data_sync_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 36708608; + * RNG date information/ RNG version information. + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * force on reg clk + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rng_date_reg_t; + + +typedef struct { + volatile rng_data_reg_t data; + volatile rng_cfg_reg_t cfg; + volatile rng_data_sync_reg_t data_sync; + uint32_t reserved_00c[252]; + volatile rng_date_reg_t date; +} rng_dev_t; + +extern rng_dev_t TRNG; + +#ifndef __cplusplus +_Static_assert(sizeof(rng_dev_t) == 0x400, "Invalid size of rng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/sha_reg.h b/components/soc/esp32h4/register/soc/sha_reg.h new file mode 100644 index 0000000000..f40181360d --- /dev/null +++ b/components/soc/esp32h4/register/soc/sha_reg.h @@ -0,0 +1,181 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Configures SHA algorithm + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [3:0]; default: 2; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA2-224 + * 2: SHA2-256 + * 3: SHA2-384 + * 4: SHA2-512 + * 5: SHA2-512/224 + * 6: SHA2-512/256 + * 7: SHA2-512/t + * 8: SHA3-224 + * 9: SHA3-256 + * 10: SHA3-384 + * 11: SHA3-512 + * 12: SHAKE128 + * 13: SHAKE256 + * 14: SM3 + */ +#define SHA_MODE 0x0000000FU +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x0000000FU +#define SHA_MODE_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0; + * Configures the DMA-SHA block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000FFFFU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : WO; bitpos: [0]; default: 0; + * Start typical sha. + */ +#define SHA_START (BIT(0)) +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x00000001U +#define SHA_START_S 0 + +/** SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue typical sha. + */ +#define SHA_CONTINUE (BIT(0)) +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x00000001U +#define SHA_CONTINUE_S 0 + +/** SHA_BUSY_REG register + * Represents if SHA Accelerator is busy or not + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * DMA-SHA interrupt clear register + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * DMA-SHA interrupt enable register + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Version control register + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291; + * Version control register. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_DMA_RX_RESET_REG register + * DMA RX FIFO Reset Signal + */ +#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30) +/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ +#define SHA_DMA_RX_RESET (BIT(0)) +#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S) +#define SHA_DMA_RX_RESET_V 0x00000001U +#define SHA_DMA_RX_RESET_S 0 + +/** SHA_2_SM_3_H_MEM register + * SHA1, SHA2-256, SM3 H memory which contains intermediate hash or final hash. + * SHA1, SHA2-256, SM3 : 0x00~0x20 (R/W) + * SHA2-512 : 0x00~0x40 (R/W) + */ +#define SHA_2_SM_3_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_2_SM_3_H_MEM_SIZE_BYTES 64 + +/** SHA_2_SM_3_M_MEM register + * SHA1, SHA2-256, SM3 M memory which contains message. + * SHA1, SHA2-256, SM3 : 0x00~0x40 + * SHA2-512 : 0x00~0x80 + */ +#define SHA_2_SM_3_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_2_SM_3_M_MEM_SIZE_BYTES 128 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/sha_struct.h b/components/soc/esp32h4/register/soc/sha_struct.h new file mode 100644 index 0000000000..7aa6e65b1a --- /dev/null +++ b/components/soc/esp32h4/register/soc/sha_struct.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control/Configuration Registers */ +/** Type of mode register + * Configures SHA algorithm + */ +typedef union { + struct { + /** mode : R/W; bitpos: [3:0]; default: 2; + * Configures the SHA algorithm. + * 0: SHA-1 + * 1: SHA2-224 + * 2: SHA2-256 + * 3: SHA2-384 + * 4: SHA2-512 + * 5: SHA2-512/224 + * 6: SHA2-512/256 + * 7: SHA2-512/t + * 8: SHA3-224 + * 9: SHA3-256 + * 10: SHA3-384 + * 11: SHA3-512 + * 12: SHAKE128 + * 13: SHAKE256 + * 14: SM3 + */ + uint32_t mode:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of dma_block_num register + * Block number register (only effective for DMA-SHA) + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [15:0]; default: 0; + * Configures the DMA-SHA block number. + */ + uint32_t dma_block_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Starts the SHA accelerator for Typical SHA operation + */ +typedef union { + struct { + /** start : WO; bitpos: [0]; default: 0; + * Start typical sha. + */ + uint32_t start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Continues SHA operation (only effective in Typical SHA mode) + */ +typedef union { + struct { + /** continue : WO; bitpos: [0]; default: 0; + * Continue typical sha. + */ + uint32_t continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * Starts the SHA accelerator for DMA-SHA operation + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + +/** Type of dma_rx_reset register + * DMA RX FIFO Reset Signal + */ +typedef union { + struct { + /** dma_rx_reset : WO; bitpos: [0]; default: 0; + * Write 1 to reset DMA RX FIFO + */ + uint32_t dma_rx_reset:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_rx_reset_reg_t; + + +/** Group: Status Registers */ +/** Type of busy register + * Represents if SHA Accelerator is busy or not + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. + * 0: idle + * 1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of clear_irq register + * DMA-SHA interrupt clear register + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * DMA-SHA interrupt enable register + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 539232291; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct { + volatile sha_mode_reg_t mode; + uint32_t reserved_004[2]; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t continue; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + volatile sha_dma_rx_reset_reg_t dma_rx_reset; + uint32_t reserved_034[3]; + volatile uint32_t 2_sm_3_h[16]; + volatile uint32_t 2_sm_3_m[32]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/tee_reg.h b/components/soc/esp32h4/register/soc/tee_reg.h new file mode 100644 index 0000000000..537d015f50 --- /dev/null +++ b/components/soc/esp32h4/register/soc/tee_reg.h @@ -0,0 +1,4488 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M0 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 +/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M0_LOCK (BIT(2)) +#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) +#define TEE_M0_LOCK_V 0x00000001U +#define TEE_M0_LOCK_S 2 + +/** TEE_M1_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M1 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 +/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M1_LOCK (BIT(2)) +#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) +#define TEE_M1_LOCK_V 0x00000001U +#define TEE_M1_LOCK_S 2 + +/** TEE_M2_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M2 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 +/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M2_LOCK (BIT(2)) +#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) +#define TEE_M2_LOCK_V 0x00000001U +#define TEE_M2_LOCK_S 2 + +/** TEE_M3_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M3 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 +/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M3_LOCK (BIT(2)) +#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) +#define TEE_M3_LOCK_V 0x00000001U +#define TEE_M3_LOCK_S 2 + +/** TEE_M4_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M4 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 +/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M4_LOCK (BIT(2)) +#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) +#define TEE_M4_LOCK_V 0x00000001U +#define TEE_M4_LOCK_S 2 + +/** TEE_M5_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M5 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 +/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M5_LOCK (BIT(2)) +#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) +#define TEE_M5_LOCK_V 0x00000001U +#define TEE_M5_LOCK_S 2 + +/** TEE_M6_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M6 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 +/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M6_LOCK (BIT(2)) +#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) +#define TEE_M6_LOCK_V 0x00000001U +#define TEE_M6_LOCK_S 2 + +/** TEE_M7_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M7 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 +/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M7_LOCK (BIT(2)) +#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) +#define TEE_M7_LOCK_V 0x00000001U +#define TEE_M7_LOCK_S 2 + +/** TEE_M8_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M8 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 +/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M8_LOCK (BIT(2)) +#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) +#define TEE_M8_LOCK_V 0x00000001U +#define TEE_M8_LOCK_S 2 + +/** TEE_M9_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M9 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 +/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M9_LOCK (BIT(2)) +#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) +#define TEE_M9_LOCK_V 0x00000001U +#define TEE_M9_LOCK_S 2 + +/** TEE_M10_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M10 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 +/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M10_LOCK (BIT(2)) +#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) +#define TEE_M10_LOCK_V 0x00000001U +#define TEE_M10_LOCK_S 2 + +/** TEE_M11_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M11 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 +/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M11_LOCK (BIT(2)) +#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) +#define TEE_M11_LOCK_V 0x00000001U +#define TEE_M11_LOCK_S 2 + +/** TEE_M12_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M12 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 +/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M12_LOCK (BIT(2)) +#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) +#define TEE_M12_LOCK_V 0x00000001U +#define TEE_M12_LOCK_S 2 + +/** TEE_M13_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M13 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 +/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M13_LOCK (BIT(2)) +#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) +#define TEE_M13_LOCK_V 0x00000001U +#define TEE_M13_LOCK_S 2 + +/** TEE_M14_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M14 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 +/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M14_LOCK (BIT(2)) +#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) +#define TEE_M14_LOCK_V 0x00000001U +#define TEE_M14_LOCK_S 2 + +/** TEE_M15_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M15 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 +/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M15_LOCK (BIT(2)) +#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) +#define TEE_M15_LOCK_V 0x00000001U +#define TEE_M15_LOCK_S 2 + +/** TEE_M16_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M16 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 +/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M16_LOCK (BIT(2)) +#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) +#define TEE_M16_LOCK_V 0x00000001U +#define TEE_M16_LOCK_S 2 + +/** TEE_M17_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M17 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 +/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M17_LOCK (BIT(2)) +#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) +#define TEE_M17_LOCK_V 0x00000001U +#define TEE_M17_LOCK_S 2 + +/** TEE_M18_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M18 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 +/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M18_LOCK (BIT(2)) +#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) +#define TEE_M18_LOCK_V 0x00000001U +#define TEE_M18_LOCK_S 2 + +/** TEE_M19_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M19 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 +/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M19_LOCK (BIT(2)) +#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) +#define TEE_M19_LOCK_V 0x00000001U +#define TEE_M19_LOCK_S 2 + +/** TEE_M20_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M20 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 +/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M20_LOCK (BIT(2)) +#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) +#define TEE_M20_LOCK_V 0x00000001U +#define TEE_M20_LOCK_S 2 + +/** TEE_M21_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M21 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 +/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M21_LOCK (BIT(2)) +#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) +#define TEE_M21_LOCK_V 0x00000001U +#define TEE_M21_LOCK_S 2 + +/** TEE_M22_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M22 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 +/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M22_LOCK (BIT(2)) +#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) +#define TEE_M22_LOCK_V 0x00000001U +#define TEE_M22_LOCK_S 2 + +/** TEE_M23_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M23 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 +/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M23_LOCK (BIT(2)) +#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) +#define TEE_M23_LOCK_V 0x00000001U +#define TEE_M23_LOCK_S 2 + +/** TEE_M24_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M24 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 +/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M24_LOCK (BIT(2)) +#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) +#define TEE_M24_LOCK_V 0x00000001U +#define TEE_M24_LOCK_S 2 + +/** TEE_M25_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M25 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 +/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M25_LOCK (BIT(2)) +#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) +#define TEE_M25_LOCK_V 0x00000001U +#define TEE_M25_LOCK_S 2 + +/** TEE_M26_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M26 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 +/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M26_LOCK (BIT(2)) +#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) +#define TEE_M26_LOCK_V 0x00000001U +#define TEE_M26_LOCK_S 2 + +/** TEE_M27_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M27 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 +/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M27_LOCK (BIT(2)) +#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) +#define TEE_M27_LOCK_V 0x00000001U +#define TEE_M27_LOCK_S 2 + +/** TEE_M28_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M28 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 +/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M28_LOCK (BIT(2)) +#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) +#define TEE_M28_LOCK_V 0x00000001U +#define TEE_M28_LOCK_S 2 + +/** TEE_M29_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M29 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 +/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M29_LOCK (BIT(2)) +#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) +#define TEE_M29_LOCK_V 0x00000001U +#define TEE_M29_LOCK_S 2 + +/** TEE_M30_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M30 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 +/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M30_LOCK (BIT(2)) +#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) +#define TEE_M30_LOCK_V 0x00000001U +#define TEE_M30_LOCK_S 2 + +/** TEE_M31_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M31 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 +/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M31_LOCK (BIT(2)) +#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) +#define TEE_M31_LOCK_V 0x00000001U +#define TEE_M31_LOCK_S 2 + +/** TEE_GPSPI0_CTRL_REG register + * gpspi0 read/write control register + */ +#define TEE_GPSPI0_CTRL_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_READ_TEE_GPSPI0 : R/W; bitpos: [0]; default: 1; + * Configures gpspi0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GPSPI0 (BIT(0)) +#define TEE_READ_TEE_GPSPI0_M (TEE_READ_TEE_GPSPI0_V << TEE_READ_TEE_GPSPI0_S) +#define TEE_READ_TEE_GPSPI0_V 0x00000001U +#define TEE_READ_TEE_GPSPI0_S 0 +/** TEE_READ_REE0_GPSPI0 : R/W; bitpos: [1]; default: 0; + * Configures gpspi0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GPSPI0 (BIT(1)) +#define TEE_READ_REE0_GPSPI0_M (TEE_READ_REE0_GPSPI0_V << TEE_READ_REE0_GPSPI0_S) +#define TEE_READ_REE0_GPSPI0_V 0x00000001U +#define TEE_READ_REE0_GPSPI0_S 1 +/** TEE_READ_REE1_GPSPI0 : R/W; bitpos: [2]; default: 0; + * Configures gpspi0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GPSPI0 (BIT(2)) +#define TEE_READ_REE1_GPSPI0_M (TEE_READ_REE1_GPSPI0_V << TEE_READ_REE1_GPSPI0_S) +#define TEE_READ_REE1_GPSPI0_V 0x00000001U +#define TEE_READ_REE1_GPSPI0_S 2 +/** TEE_READ_REE2_GPSPI0 : R/W; bitpos: [3]; default: 0; + * Configures gpspi0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GPSPI0 (BIT(3)) +#define TEE_READ_REE2_GPSPI0_M (TEE_READ_REE2_GPSPI0_V << TEE_READ_REE2_GPSPI0_S) +#define TEE_READ_REE2_GPSPI0_V 0x00000001U +#define TEE_READ_REE2_GPSPI0_S 3 +/** TEE_WRITE_TEE_GPSPI0 : R/W; bitpos: [4]; default: 1; + * Configures gpspi0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GPSPI0 (BIT(4)) +#define TEE_WRITE_TEE_GPSPI0_M (TEE_WRITE_TEE_GPSPI0_V << TEE_WRITE_TEE_GPSPI0_S) +#define TEE_WRITE_TEE_GPSPI0_V 0x00000001U +#define TEE_WRITE_TEE_GPSPI0_S 4 +/** TEE_WRITE_REE0_GPSPI0 : R/W; bitpos: [5]; default: 0; + * Configures gpspi0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GPSPI0 (BIT(5)) +#define TEE_WRITE_REE0_GPSPI0_M (TEE_WRITE_REE0_GPSPI0_V << TEE_WRITE_REE0_GPSPI0_S) +#define TEE_WRITE_REE0_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE0_GPSPI0_S 5 +/** TEE_WRITE_REE1_GPSPI0 : R/W; bitpos: [6]; default: 0; + * Configures gpspi0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GPSPI0 (BIT(6)) +#define TEE_WRITE_REE1_GPSPI0_M (TEE_WRITE_REE1_GPSPI0_V << TEE_WRITE_REE1_GPSPI0_S) +#define TEE_WRITE_REE1_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE1_GPSPI0_S 6 +/** TEE_WRITE_REE2_GPSPI0 : R/W; bitpos: [7]; default: 0; + * Configures gpspi0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GPSPI0 (BIT(7)) +#define TEE_WRITE_REE2_GPSPI0_M (TEE_WRITE_REE2_GPSPI0_V << TEE_WRITE_REE2_GPSPI0_S) +#define TEE_WRITE_REE2_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE2_GPSPI0_S 7 + +/** TEE_GPSPI1_CTRL_REG register + * gpspi1 read/write control register + */ +#define TEE_GPSPI1_CTRL_REG (DR_REG_TEE_BASE + 0x84) +/** TEE_READ_TEE_GPSPI1 : R/W; bitpos: [0]; default: 1; + * Configures gpspi1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GPSPI1 (BIT(0)) +#define TEE_READ_TEE_GPSPI1_M (TEE_READ_TEE_GPSPI1_V << TEE_READ_TEE_GPSPI1_S) +#define TEE_READ_TEE_GPSPI1_V 0x00000001U +#define TEE_READ_TEE_GPSPI1_S 0 +/** TEE_READ_REE0_GPSPI1 : R/W; bitpos: [1]; default: 0; + * Configures gpspi1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GPSPI1 (BIT(1)) +#define TEE_READ_REE0_GPSPI1_M (TEE_READ_REE0_GPSPI1_V << TEE_READ_REE0_GPSPI1_S) +#define TEE_READ_REE0_GPSPI1_V 0x00000001U +#define TEE_READ_REE0_GPSPI1_S 1 +/** TEE_READ_REE1_GPSPI1 : R/W; bitpos: [2]; default: 0; + * Configures gpspi1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GPSPI1 (BIT(2)) +#define TEE_READ_REE1_GPSPI1_M (TEE_READ_REE1_GPSPI1_V << TEE_READ_REE1_GPSPI1_S) +#define TEE_READ_REE1_GPSPI1_V 0x00000001U +#define TEE_READ_REE1_GPSPI1_S 2 +/** TEE_READ_REE2_GPSPI1 : R/W; bitpos: [3]; default: 0; + * Configures gpspi1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GPSPI1 (BIT(3)) +#define TEE_READ_REE2_GPSPI1_M (TEE_READ_REE2_GPSPI1_V << TEE_READ_REE2_GPSPI1_S) +#define TEE_READ_REE2_GPSPI1_V 0x00000001U +#define TEE_READ_REE2_GPSPI1_S 3 +/** TEE_WRITE_TEE_GPSPI1 : R/W; bitpos: [4]; default: 1; + * Configures gpspi1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GPSPI1 (BIT(4)) +#define TEE_WRITE_TEE_GPSPI1_M (TEE_WRITE_TEE_GPSPI1_V << TEE_WRITE_TEE_GPSPI1_S) +#define TEE_WRITE_TEE_GPSPI1_V 0x00000001U +#define TEE_WRITE_TEE_GPSPI1_S 4 +/** TEE_WRITE_REE0_GPSPI1 : R/W; bitpos: [5]; default: 0; + * Configures gpspi1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GPSPI1 (BIT(5)) +#define TEE_WRITE_REE0_GPSPI1_M (TEE_WRITE_REE0_GPSPI1_V << TEE_WRITE_REE0_GPSPI1_S) +#define TEE_WRITE_REE0_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE0_GPSPI1_S 5 +/** TEE_WRITE_REE1_GPSPI1 : R/W; bitpos: [6]; default: 0; + * Configures gpspi1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GPSPI1 (BIT(6)) +#define TEE_WRITE_REE1_GPSPI1_M (TEE_WRITE_REE1_GPSPI1_V << TEE_WRITE_REE1_GPSPI1_S) +#define TEE_WRITE_REE1_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE1_GPSPI1_S 6 +/** TEE_WRITE_REE2_GPSPI1 : R/W; bitpos: [7]; default: 0; + * Configures gpspi1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GPSPI1 (BIT(7)) +#define TEE_WRITE_REE2_GPSPI1_M (TEE_WRITE_REE2_GPSPI1_V << TEE_WRITE_REE2_GPSPI1_S) +#define TEE_WRITE_REE2_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE2_GPSPI1_S 7 + +/** TEE_UART0_CTRL_REG register + * uart0 read/write control register + */ +#define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) +/** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART0 (BIT(0)) +#define TEE_READ_TEE_UART0_M (TEE_READ_TEE_UART0_V << TEE_READ_TEE_UART0_S) +#define TEE_READ_TEE_UART0_V 0x00000001U +#define TEE_READ_TEE_UART0_S 0 +/** TEE_READ_REE0_UART0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART0 (BIT(1)) +#define TEE_READ_REE0_UART0_M (TEE_READ_REE0_UART0_V << TEE_READ_REE0_UART0_S) +#define TEE_READ_REE0_UART0_V 0x00000001U +#define TEE_READ_REE0_UART0_S 1 +/** TEE_READ_REE1_UART0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART0 (BIT(2)) +#define TEE_READ_REE1_UART0_M (TEE_READ_REE1_UART0_V << TEE_READ_REE1_UART0_S) +#define TEE_READ_REE1_UART0_V 0x00000001U +#define TEE_READ_REE1_UART0_S 2 +/** TEE_READ_REE2_UART0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART0 (BIT(3)) +#define TEE_READ_REE2_UART0_M (TEE_READ_REE2_UART0_V << TEE_READ_REE2_UART0_S) +#define TEE_READ_REE2_UART0_V 0x00000001U +#define TEE_READ_REE2_UART0_S 3 +/** TEE_WRITE_TEE_UART0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART0 (BIT(4)) +#define TEE_WRITE_TEE_UART0_M (TEE_WRITE_TEE_UART0_V << TEE_WRITE_TEE_UART0_S) +#define TEE_WRITE_TEE_UART0_V 0x00000001U +#define TEE_WRITE_TEE_UART0_S 4 +/** TEE_WRITE_REE0_UART0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART0 (BIT(5)) +#define TEE_WRITE_REE0_UART0_M (TEE_WRITE_REE0_UART0_V << TEE_WRITE_REE0_UART0_S) +#define TEE_WRITE_REE0_UART0_V 0x00000001U +#define TEE_WRITE_REE0_UART0_S 5 +/** TEE_WRITE_REE1_UART0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART0 (BIT(6)) +#define TEE_WRITE_REE1_UART0_M (TEE_WRITE_REE1_UART0_V << TEE_WRITE_REE1_UART0_S) +#define TEE_WRITE_REE1_UART0_V 0x00000001U +#define TEE_WRITE_REE1_UART0_S 6 +/** TEE_WRITE_REE2_UART0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART0 (BIT(7)) +#define TEE_WRITE_REE2_UART0_M (TEE_WRITE_REE2_UART0_V << TEE_WRITE_REE2_UART0_S) +#define TEE_WRITE_REE2_UART0_V 0x00000001U +#define TEE_WRITE_REE2_UART0_S 7 + +/** TEE_UART1_CTRL_REG register + * uart1 read/write control register + */ +#define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) +/** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART1 (BIT(0)) +#define TEE_READ_TEE_UART1_M (TEE_READ_TEE_UART1_V << TEE_READ_TEE_UART1_S) +#define TEE_READ_TEE_UART1_V 0x00000001U +#define TEE_READ_TEE_UART1_S 0 +/** TEE_READ_REE0_UART1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART1 (BIT(1)) +#define TEE_READ_REE0_UART1_M (TEE_READ_REE0_UART1_V << TEE_READ_REE0_UART1_S) +#define TEE_READ_REE0_UART1_V 0x00000001U +#define TEE_READ_REE0_UART1_S 1 +/** TEE_READ_REE1_UART1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART1 (BIT(2)) +#define TEE_READ_REE1_UART1_M (TEE_READ_REE1_UART1_V << TEE_READ_REE1_UART1_S) +#define TEE_READ_REE1_UART1_V 0x00000001U +#define TEE_READ_REE1_UART1_S 2 +/** TEE_READ_REE2_UART1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART1 (BIT(3)) +#define TEE_READ_REE2_UART1_M (TEE_READ_REE2_UART1_V << TEE_READ_REE2_UART1_S) +#define TEE_READ_REE2_UART1_V 0x00000001U +#define TEE_READ_REE2_UART1_S 3 +/** TEE_WRITE_TEE_UART1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART1 (BIT(4)) +#define TEE_WRITE_TEE_UART1_M (TEE_WRITE_TEE_UART1_V << TEE_WRITE_TEE_UART1_S) +#define TEE_WRITE_TEE_UART1_V 0x00000001U +#define TEE_WRITE_TEE_UART1_S 4 +/** TEE_WRITE_REE0_UART1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART1 (BIT(5)) +#define TEE_WRITE_REE0_UART1_M (TEE_WRITE_REE0_UART1_V << TEE_WRITE_REE0_UART1_S) +#define TEE_WRITE_REE0_UART1_V 0x00000001U +#define TEE_WRITE_REE0_UART1_S 5 +/** TEE_WRITE_REE1_UART1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART1 (BIT(6)) +#define TEE_WRITE_REE1_UART1_M (TEE_WRITE_REE1_UART1_V << TEE_WRITE_REE1_UART1_S) +#define TEE_WRITE_REE1_UART1_V 0x00000001U +#define TEE_WRITE_REE1_UART1_S 6 +/** TEE_WRITE_REE2_UART1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART1 (BIT(7)) +#define TEE_WRITE_REE2_UART1_M (TEE_WRITE_REE2_UART1_V << TEE_WRITE_REE2_UART1_S) +#define TEE_WRITE_REE2_UART1_V 0x00000001U +#define TEE_WRITE_REE2_UART1_S 7 + +/** TEE_UHCI_CTRL_REG register + * uhci read/write control register + */ +#define TEE_UHCI_CTRL_REG (DR_REG_TEE_BASE + 0x90) +/** TEE_READ_TEE_UHCI : R/W; bitpos: [0]; default: 1; + * Configures uhci registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UHCI (BIT(0)) +#define TEE_READ_TEE_UHCI_M (TEE_READ_TEE_UHCI_V << TEE_READ_TEE_UHCI_S) +#define TEE_READ_TEE_UHCI_V 0x00000001U +#define TEE_READ_TEE_UHCI_S 0 +/** TEE_READ_REE0_UHCI : R/W; bitpos: [1]; default: 0; + * Configures uhci registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UHCI (BIT(1)) +#define TEE_READ_REE0_UHCI_M (TEE_READ_REE0_UHCI_V << TEE_READ_REE0_UHCI_S) +#define TEE_READ_REE0_UHCI_V 0x00000001U +#define TEE_READ_REE0_UHCI_S 1 +/** TEE_READ_REE1_UHCI : R/W; bitpos: [2]; default: 0; + * Configures uhci registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UHCI (BIT(2)) +#define TEE_READ_REE1_UHCI_M (TEE_READ_REE1_UHCI_V << TEE_READ_REE1_UHCI_S) +#define TEE_READ_REE1_UHCI_V 0x00000001U +#define TEE_READ_REE1_UHCI_S 2 +/** TEE_READ_REE2_UHCI : R/W; bitpos: [3]; default: 0; + * Configures uhci registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UHCI (BIT(3)) +#define TEE_READ_REE2_UHCI_M (TEE_READ_REE2_UHCI_V << TEE_READ_REE2_UHCI_S) +#define TEE_READ_REE2_UHCI_V 0x00000001U +#define TEE_READ_REE2_UHCI_S 3 +/** TEE_WRITE_TEE_UHCI : R/W; bitpos: [4]; default: 1; + * Configures uhci registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UHCI (BIT(4)) +#define TEE_WRITE_TEE_UHCI_M (TEE_WRITE_TEE_UHCI_V << TEE_WRITE_TEE_UHCI_S) +#define TEE_WRITE_TEE_UHCI_V 0x00000001U +#define TEE_WRITE_TEE_UHCI_S 4 +/** TEE_WRITE_REE0_UHCI : R/W; bitpos: [5]; default: 0; + * Configures uhci registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UHCI (BIT(5)) +#define TEE_WRITE_REE0_UHCI_M (TEE_WRITE_REE0_UHCI_V << TEE_WRITE_REE0_UHCI_S) +#define TEE_WRITE_REE0_UHCI_V 0x00000001U +#define TEE_WRITE_REE0_UHCI_S 5 +/** TEE_WRITE_REE1_UHCI : R/W; bitpos: [6]; default: 0; + * Configures uhci registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UHCI (BIT(6)) +#define TEE_WRITE_REE1_UHCI_M (TEE_WRITE_REE1_UHCI_V << TEE_WRITE_REE1_UHCI_S) +#define TEE_WRITE_REE1_UHCI_V 0x00000001U +#define TEE_WRITE_REE1_UHCI_S 6 +/** TEE_WRITE_REE2_UHCI : R/W; bitpos: [7]; default: 0; + * Configures uhci registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UHCI (BIT(7)) +#define TEE_WRITE_REE2_UHCI_M (TEE_WRITE_REE2_UHCI_V << TEE_WRITE_REE2_UHCI_S) +#define TEE_WRITE_REE2_UHCI_V 0x00000001U +#define TEE_WRITE_REE2_UHCI_S 7 + +/** TEE_I2C0_CTRL_REG register + * i2c0 read/write control register + */ +#define TEE_I2C0_CTRL_REG (DR_REG_TEE_BASE + 0x94) +/** TEE_READ_TEE_I2C0 : R/W; bitpos: [0]; default: 1; + * Configures i2c0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2C0 (BIT(0)) +#define TEE_READ_TEE_I2C0_M (TEE_READ_TEE_I2C0_V << TEE_READ_TEE_I2C0_S) +#define TEE_READ_TEE_I2C0_V 0x00000001U +#define TEE_READ_TEE_I2C0_S 0 +/** TEE_READ_REE0_I2C0 : R/W; bitpos: [1]; default: 0; + * Configures i2c0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2C0 (BIT(1)) +#define TEE_READ_REE0_I2C0_M (TEE_READ_REE0_I2C0_V << TEE_READ_REE0_I2C0_S) +#define TEE_READ_REE0_I2C0_V 0x00000001U +#define TEE_READ_REE0_I2C0_S 1 +/** TEE_READ_REE1_I2C0 : R/W; bitpos: [2]; default: 0; + * Configures i2c0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2C0 (BIT(2)) +#define TEE_READ_REE1_I2C0_M (TEE_READ_REE1_I2C0_V << TEE_READ_REE1_I2C0_S) +#define TEE_READ_REE1_I2C0_V 0x00000001U +#define TEE_READ_REE1_I2C0_S 2 +/** TEE_READ_REE2_I2C0 : R/W; bitpos: [3]; default: 0; + * Configures i2c0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2C0 (BIT(3)) +#define TEE_READ_REE2_I2C0_M (TEE_READ_REE2_I2C0_V << TEE_READ_REE2_I2C0_S) +#define TEE_READ_REE2_I2C0_V 0x00000001U +#define TEE_READ_REE2_I2C0_S 3 +/** TEE_WRITE_TEE_I2C0 : R/W; bitpos: [4]; default: 1; + * Configures i2c0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2C0 (BIT(4)) +#define TEE_WRITE_TEE_I2C0_M (TEE_WRITE_TEE_I2C0_V << TEE_WRITE_TEE_I2C0_S) +#define TEE_WRITE_TEE_I2C0_V 0x00000001U +#define TEE_WRITE_TEE_I2C0_S 4 +/** TEE_WRITE_REE0_I2C0 : R/W; bitpos: [5]; default: 0; + * Configures i2c0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2C0 (BIT(5)) +#define TEE_WRITE_REE0_I2C0_M (TEE_WRITE_REE0_I2C0_V << TEE_WRITE_REE0_I2C0_S) +#define TEE_WRITE_REE0_I2C0_V 0x00000001U +#define TEE_WRITE_REE0_I2C0_S 5 +/** TEE_WRITE_REE1_I2C0 : R/W; bitpos: [6]; default: 0; + * Configures i2c0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2C0 (BIT(6)) +#define TEE_WRITE_REE1_I2C0_M (TEE_WRITE_REE1_I2C0_V << TEE_WRITE_REE1_I2C0_S) +#define TEE_WRITE_REE1_I2C0_V 0x00000001U +#define TEE_WRITE_REE1_I2C0_S 6 +/** TEE_WRITE_REE2_I2C0 : R/W; bitpos: [7]; default: 0; + * Configures i2c0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2C0 (BIT(7)) +#define TEE_WRITE_REE2_I2C0_M (TEE_WRITE_REE2_I2C0_V << TEE_WRITE_REE2_I2C0_S) +#define TEE_WRITE_REE2_I2C0_V 0x00000001U +#define TEE_WRITE_REE2_I2C0_S 7 + +/** TEE_I2C1_CTRL_REG register + * i2c1 read/write control register + */ +#define TEE_I2C1_CTRL_REG (DR_REG_TEE_BASE + 0x98) +/** TEE_READ_TEE_I2C1 : R/W; bitpos: [0]; default: 1; + * Configures i2c1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2C1 (BIT(0)) +#define TEE_READ_TEE_I2C1_M (TEE_READ_TEE_I2C1_V << TEE_READ_TEE_I2C1_S) +#define TEE_READ_TEE_I2C1_V 0x00000001U +#define TEE_READ_TEE_I2C1_S 0 +/** TEE_READ_REE0_I2C1 : R/W; bitpos: [1]; default: 0; + * Configures i2c1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2C1 (BIT(1)) +#define TEE_READ_REE0_I2C1_M (TEE_READ_REE0_I2C1_V << TEE_READ_REE0_I2C1_S) +#define TEE_READ_REE0_I2C1_V 0x00000001U +#define TEE_READ_REE0_I2C1_S 1 +/** TEE_READ_REE1_I2C1 : R/W; bitpos: [2]; default: 0; + * Configures i2c1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2C1 (BIT(2)) +#define TEE_READ_REE1_I2C1_M (TEE_READ_REE1_I2C1_V << TEE_READ_REE1_I2C1_S) +#define TEE_READ_REE1_I2C1_V 0x00000001U +#define TEE_READ_REE1_I2C1_S 2 +/** TEE_READ_REE2_I2C1 : R/W; bitpos: [3]; default: 0; + * Configures i2c1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2C1 (BIT(3)) +#define TEE_READ_REE2_I2C1_M (TEE_READ_REE2_I2C1_V << TEE_READ_REE2_I2C1_S) +#define TEE_READ_REE2_I2C1_V 0x00000001U +#define TEE_READ_REE2_I2C1_S 3 +/** TEE_WRITE_TEE_I2C1 : R/W; bitpos: [4]; default: 1; + * Configures i2c1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2C1 (BIT(4)) +#define TEE_WRITE_TEE_I2C1_M (TEE_WRITE_TEE_I2C1_V << TEE_WRITE_TEE_I2C1_S) +#define TEE_WRITE_TEE_I2C1_V 0x00000001U +#define TEE_WRITE_TEE_I2C1_S 4 +/** TEE_WRITE_REE0_I2C1 : R/W; bitpos: [5]; default: 0; + * Configures i2c1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2C1 (BIT(5)) +#define TEE_WRITE_REE0_I2C1_M (TEE_WRITE_REE0_I2C1_V << TEE_WRITE_REE0_I2C1_S) +#define TEE_WRITE_REE0_I2C1_V 0x00000001U +#define TEE_WRITE_REE0_I2C1_S 5 +/** TEE_WRITE_REE1_I2C1 : R/W; bitpos: [6]; default: 0; + * Configures i2c1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2C1 (BIT(6)) +#define TEE_WRITE_REE1_I2C1_M (TEE_WRITE_REE1_I2C1_V << TEE_WRITE_REE1_I2C1_S) +#define TEE_WRITE_REE1_I2C1_V 0x00000001U +#define TEE_WRITE_REE1_I2C1_S 6 +/** TEE_WRITE_REE2_I2C1 : R/W; bitpos: [7]; default: 0; + * Configures i2c1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2C1 (BIT(7)) +#define TEE_WRITE_REE2_I2C1_M (TEE_WRITE_REE2_I2C1_V << TEE_WRITE_REE2_I2C1_S) +#define TEE_WRITE_REE2_I2C1_V 0x00000001U +#define TEE_WRITE_REE2_I2C1_S 7 + +/** TEE_I2S_CTRL_REG register + * i2s read/write control register + */ +#define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) +/** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2S (BIT(0)) +#define TEE_READ_TEE_I2S_M (TEE_READ_TEE_I2S_V << TEE_READ_TEE_I2S_S) +#define TEE_READ_TEE_I2S_V 0x00000001U +#define TEE_READ_TEE_I2S_S 0 +/** TEE_READ_REE0_I2S : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2S (BIT(1)) +#define TEE_READ_REE0_I2S_M (TEE_READ_REE0_I2S_V << TEE_READ_REE0_I2S_S) +#define TEE_READ_REE0_I2S_V 0x00000001U +#define TEE_READ_REE0_I2S_S 1 +/** TEE_READ_REE1_I2S : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2S (BIT(2)) +#define TEE_READ_REE1_I2S_M (TEE_READ_REE1_I2S_V << TEE_READ_REE1_I2S_S) +#define TEE_READ_REE1_I2S_V 0x00000001U +#define TEE_READ_REE1_I2S_S 2 +/** TEE_READ_REE2_I2S : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2S (BIT(3)) +#define TEE_READ_REE2_I2S_M (TEE_READ_REE2_I2S_V << TEE_READ_REE2_I2S_S) +#define TEE_READ_REE2_I2S_V 0x00000001U +#define TEE_READ_REE2_I2S_S 3 +/** TEE_WRITE_TEE_I2S : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2S (BIT(4)) +#define TEE_WRITE_TEE_I2S_M (TEE_WRITE_TEE_I2S_V << TEE_WRITE_TEE_I2S_S) +#define TEE_WRITE_TEE_I2S_V 0x00000001U +#define TEE_WRITE_TEE_I2S_S 4 +/** TEE_WRITE_REE0_I2S : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2S (BIT(5)) +#define TEE_WRITE_REE0_I2S_M (TEE_WRITE_REE0_I2S_V << TEE_WRITE_REE0_I2S_S) +#define TEE_WRITE_REE0_I2S_V 0x00000001U +#define TEE_WRITE_REE0_I2S_S 5 +/** TEE_WRITE_REE1_I2S : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2S (BIT(6)) +#define TEE_WRITE_REE1_I2S_M (TEE_WRITE_REE1_I2S_V << TEE_WRITE_REE1_I2S_S) +#define TEE_WRITE_REE1_I2S_V 0x00000001U +#define TEE_WRITE_REE1_I2S_S 6 +/** TEE_WRITE_REE2_I2S : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2S (BIT(7)) +#define TEE_WRITE_REE2_I2S_M (TEE_WRITE_REE2_I2S_V << TEE_WRITE_REE2_I2S_S) +#define TEE_WRITE_REE2_I2S_V 0x00000001U +#define TEE_WRITE_REE2_I2S_S 7 + +/** TEE_PARL_IO_CTRL_REG register + * parl_io read/write control register + */ +#define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) +/** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PARL_IO (BIT(0)) +#define TEE_READ_TEE_PARL_IO_M (TEE_READ_TEE_PARL_IO_V << TEE_READ_TEE_PARL_IO_S) +#define TEE_READ_TEE_PARL_IO_V 0x00000001U +#define TEE_READ_TEE_PARL_IO_S 0 +/** TEE_READ_REE0_PARL_IO : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PARL_IO (BIT(1)) +#define TEE_READ_REE0_PARL_IO_M (TEE_READ_REE0_PARL_IO_V << TEE_READ_REE0_PARL_IO_S) +#define TEE_READ_REE0_PARL_IO_V 0x00000001U +#define TEE_READ_REE0_PARL_IO_S 1 +/** TEE_READ_REE1_PARL_IO : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PARL_IO (BIT(2)) +#define TEE_READ_REE1_PARL_IO_M (TEE_READ_REE1_PARL_IO_V << TEE_READ_REE1_PARL_IO_S) +#define TEE_READ_REE1_PARL_IO_V 0x00000001U +#define TEE_READ_REE1_PARL_IO_S 2 +/** TEE_READ_REE2_PARL_IO : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PARL_IO (BIT(3)) +#define TEE_READ_REE2_PARL_IO_M (TEE_READ_REE2_PARL_IO_V << TEE_READ_REE2_PARL_IO_S) +#define TEE_READ_REE2_PARL_IO_V 0x00000001U +#define TEE_READ_REE2_PARL_IO_S 3 +/** TEE_WRITE_TEE_PARL_IO : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PARL_IO (BIT(4)) +#define TEE_WRITE_TEE_PARL_IO_M (TEE_WRITE_TEE_PARL_IO_V << TEE_WRITE_TEE_PARL_IO_S) +#define TEE_WRITE_TEE_PARL_IO_V 0x00000001U +#define TEE_WRITE_TEE_PARL_IO_S 4 +/** TEE_WRITE_REE0_PARL_IO : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PARL_IO (BIT(5)) +#define TEE_WRITE_REE0_PARL_IO_M (TEE_WRITE_REE0_PARL_IO_V << TEE_WRITE_REE0_PARL_IO_S) +#define TEE_WRITE_REE0_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE0_PARL_IO_S 5 +/** TEE_WRITE_REE1_PARL_IO : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PARL_IO (BIT(6)) +#define TEE_WRITE_REE1_PARL_IO_M (TEE_WRITE_REE1_PARL_IO_V << TEE_WRITE_REE1_PARL_IO_S) +#define TEE_WRITE_REE1_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE1_PARL_IO_S 6 +/** TEE_WRITE_REE2_PARL_IO : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PARL_IO (BIT(7)) +#define TEE_WRITE_REE2_PARL_IO_M (TEE_WRITE_REE2_PARL_IO_V << TEE_WRITE_REE2_PARL_IO_S) +#define TEE_WRITE_REE2_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE2_PARL_IO_S 7 + +/** TEE_PWM0_CTRL_REG register + * pwm0 read/write control register + */ +#define TEE_PWM0_CTRL_REG (DR_REG_TEE_BASE + 0xa4) +/** TEE_READ_TEE_PWM0 : R/W; bitpos: [0]; default: 1; + * Configures pwm0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PWM0 (BIT(0)) +#define TEE_READ_TEE_PWM0_M (TEE_READ_TEE_PWM0_V << TEE_READ_TEE_PWM0_S) +#define TEE_READ_TEE_PWM0_V 0x00000001U +#define TEE_READ_TEE_PWM0_S 0 +/** TEE_READ_REE0_PWM0 : R/W; bitpos: [1]; default: 0; + * Configures pwm0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PWM0 (BIT(1)) +#define TEE_READ_REE0_PWM0_M (TEE_READ_REE0_PWM0_V << TEE_READ_REE0_PWM0_S) +#define TEE_READ_REE0_PWM0_V 0x00000001U +#define TEE_READ_REE0_PWM0_S 1 +/** TEE_READ_REE1_PWM0 : R/W; bitpos: [2]; default: 0; + * Configures pwm0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PWM0 (BIT(2)) +#define TEE_READ_REE1_PWM0_M (TEE_READ_REE1_PWM0_V << TEE_READ_REE1_PWM0_S) +#define TEE_READ_REE1_PWM0_V 0x00000001U +#define TEE_READ_REE1_PWM0_S 2 +/** TEE_READ_REE2_PWM0 : R/W; bitpos: [3]; default: 0; + * Configures pwm0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PWM0 (BIT(3)) +#define TEE_READ_REE2_PWM0_M (TEE_READ_REE2_PWM0_V << TEE_READ_REE2_PWM0_S) +#define TEE_READ_REE2_PWM0_V 0x00000001U +#define TEE_READ_REE2_PWM0_S 3 +/** TEE_WRITE_TEE_PWM0 : R/W; bitpos: [4]; default: 1; + * Configures pwm0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PWM0 (BIT(4)) +#define TEE_WRITE_TEE_PWM0_M (TEE_WRITE_TEE_PWM0_V << TEE_WRITE_TEE_PWM0_S) +#define TEE_WRITE_TEE_PWM0_V 0x00000001U +#define TEE_WRITE_TEE_PWM0_S 4 +/** TEE_WRITE_REE0_PWM0 : R/W; bitpos: [5]; default: 0; + * Configures pwm0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PWM0 (BIT(5)) +#define TEE_WRITE_REE0_PWM0_M (TEE_WRITE_REE0_PWM0_V << TEE_WRITE_REE0_PWM0_S) +#define TEE_WRITE_REE0_PWM0_V 0x00000001U +#define TEE_WRITE_REE0_PWM0_S 5 +/** TEE_WRITE_REE1_PWM0 : R/W; bitpos: [6]; default: 0; + * Configures pwm0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PWM0 (BIT(6)) +#define TEE_WRITE_REE1_PWM0_M (TEE_WRITE_REE1_PWM0_V << TEE_WRITE_REE1_PWM0_S) +#define TEE_WRITE_REE1_PWM0_V 0x00000001U +#define TEE_WRITE_REE1_PWM0_S 6 +/** TEE_WRITE_REE2_PWM0 : R/W; bitpos: [7]; default: 0; + * Configures pwm0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PWM0 (BIT(7)) +#define TEE_WRITE_REE2_PWM0_M (TEE_WRITE_REE2_PWM0_V << TEE_WRITE_REE2_PWM0_S) +#define TEE_WRITE_REE2_PWM0_V 0x00000001U +#define TEE_WRITE_REE2_PWM0_S 7 + +/** TEE_PWM1_CTRL_REG register + * pwm1 read/write control register + */ +#define TEE_PWM1_CTRL_REG (DR_REG_TEE_BASE + 0xa8) +/** TEE_READ_TEE_PWM1 : R/W; bitpos: [0]; default: 1; + * Configures pwm1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PWM1 (BIT(0)) +#define TEE_READ_TEE_PWM1_M (TEE_READ_TEE_PWM1_V << TEE_READ_TEE_PWM1_S) +#define TEE_READ_TEE_PWM1_V 0x00000001U +#define TEE_READ_TEE_PWM1_S 0 +/** TEE_READ_REE0_PWM1 : R/W; bitpos: [1]; default: 0; + * Configures pwm1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PWM1 (BIT(1)) +#define TEE_READ_REE0_PWM1_M (TEE_READ_REE0_PWM1_V << TEE_READ_REE0_PWM1_S) +#define TEE_READ_REE0_PWM1_V 0x00000001U +#define TEE_READ_REE0_PWM1_S 1 +/** TEE_READ_REE1_PWM1 : R/W; bitpos: [2]; default: 0; + * Configures pwm1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PWM1 (BIT(2)) +#define TEE_READ_REE1_PWM1_M (TEE_READ_REE1_PWM1_V << TEE_READ_REE1_PWM1_S) +#define TEE_READ_REE1_PWM1_V 0x00000001U +#define TEE_READ_REE1_PWM1_S 2 +/** TEE_READ_REE2_PWM1 : R/W; bitpos: [3]; default: 0; + * Configures pwm1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PWM1 (BIT(3)) +#define TEE_READ_REE2_PWM1_M (TEE_READ_REE2_PWM1_V << TEE_READ_REE2_PWM1_S) +#define TEE_READ_REE2_PWM1_V 0x00000001U +#define TEE_READ_REE2_PWM1_S 3 +/** TEE_WRITE_TEE_PWM1 : R/W; bitpos: [4]; default: 1; + * Configures pwm1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PWM1 (BIT(4)) +#define TEE_WRITE_TEE_PWM1_M (TEE_WRITE_TEE_PWM1_V << TEE_WRITE_TEE_PWM1_S) +#define TEE_WRITE_TEE_PWM1_V 0x00000001U +#define TEE_WRITE_TEE_PWM1_S 4 +/** TEE_WRITE_REE0_PWM1 : R/W; bitpos: [5]; default: 0; + * Configures pwm1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PWM1 (BIT(5)) +#define TEE_WRITE_REE0_PWM1_M (TEE_WRITE_REE0_PWM1_V << TEE_WRITE_REE0_PWM1_S) +#define TEE_WRITE_REE0_PWM1_V 0x00000001U +#define TEE_WRITE_REE0_PWM1_S 5 +/** TEE_WRITE_REE1_PWM1 : R/W; bitpos: [6]; default: 0; + * Configures pwm1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PWM1 (BIT(6)) +#define TEE_WRITE_REE1_PWM1_M (TEE_WRITE_REE1_PWM1_V << TEE_WRITE_REE1_PWM1_S) +#define TEE_WRITE_REE1_PWM1_V 0x00000001U +#define TEE_WRITE_REE1_PWM1_S 6 +/** TEE_WRITE_REE2_PWM1 : R/W; bitpos: [7]; default: 0; + * Configures pwm1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PWM1 (BIT(7)) +#define TEE_WRITE_REE2_PWM1_M (TEE_WRITE_REE2_PWM1_V << TEE_WRITE_REE2_PWM1_S) +#define TEE_WRITE_REE2_PWM1_V 0x00000001U +#define TEE_WRITE_REE2_PWM1_S 7 + +/** TEE_LEDC_CTRL_REG register + * ledc read/write control register + */ +#define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) +/** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_LEDC (BIT(0)) +#define TEE_READ_TEE_LEDC_M (TEE_READ_TEE_LEDC_V << TEE_READ_TEE_LEDC_S) +#define TEE_READ_TEE_LEDC_V 0x00000001U +#define TEE_READ_TEE_LEDC_S 0 +/** TEE_READ_REE0_LEDC : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_LEDC (BIT(1)) +#define TEE_READ_REE0_LEDC_M (TEE_READ_REE0_LEDC_V << TEE_READ_REE0_LEDC_S) +#define TEE_READ_REE0_LEDC_V 0x00000001U +#define TEE_READ_REE0_LEDC_S 1 +/** TEE_READ_REE1_LEDC : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_LEDC (BIT(2)) +#define TEE_READ_REE1_LEDC_M (TEE_READ_REE1_LEDC_V << TEE_READ_REE1_LEDC_S) +#define TEE_READ_REE1_LEDC_V 0x00000001U +#define TEE_READ_REE1_LEDC_S 2 +/** TEE_READ_REE2_LEDC : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_LEDC (BIT(3)) +#define TEE_READ_REE2_LEDC_M (TEE_READ_REE2_LEDC_V << TEE_READ_REE2_LEDC_S) +#define TEE_READ_REE2_LEDC_V 0x00000001U +#define TEE_READ_REE2_LEDC_S 3 +/** TEE_WRITE_TEE_LEDC : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_LEDC (BIT(4)) +#define TEE_WRITE_TEE_LEDC_M (TEE_WRITE_TEE_LEDC_V << TEE_WRITE_TEE_LEDC_S) +#define TEE_WRITE_TEE_LEDC_V 0x00000001U +#define TEE_WRITE_TEE_LEDC_S 4 +/** TEE_WRITE_REE0_LEDC : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_LEDC (BIT(5)) +#define TEE_WRITE_REE0_LEDC_M (TEE_WRITE_REE0_LEDC_V << TEE_WRITE_REE0_LEDC_S) +#define TEE_WRITE_REE0_LEDC_V 0x00000001U +#define TEE_WRITE_REE0_LEDC_S 5 +/** TEE_WRITE_REE1_LEDC : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_LEDC (BIT(6)) +#define TEE_WRITE_REE1_LEDC_M (TEE_WRITE_REE1_LEDC_V << TEE_WRITE_REE1_LEDC_S) +#define TEE_WRITE_REE1_LEDC_V 0x00000001U +#define TEE_WRITE_REE1_LEDC_S 6 +/** TEE_WRITE_REE2_LEDC : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_LEDC (BIT(7)) +#define TEE_WRITE_REE2_LEDC_M (TEE_WRITE_REE2_LEDC_V << TEE_WRITE_REE2_LEDC_S) +#define TEE_WRITE_REE2_LEDC_V 0x00000001U +#define TEE_WRITE_REE2_LEDC_S 7 + +/** TEE_CAN_CTRL_REG register + * can read/write control register + */ +#define TEE_CAN_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_CAN : R/W; bitpos: [0]; default: 1; + * Configures can registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CAN (BIT(0)) +#define TEE_READ_TEE_CAN_M (TEE_READ_TEE_CAN_V << TEE_READ_TEE_CAN_S) +#define TEE_READ_TEE_CAN_V 0x00000001U +#define TEE_READ_TEE_CAN_S 0 +/** TEE_READ_REE0_CAN : R/W; bitpos: [1]; default: 0; + * Configures can registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CAN (BIT(1)) +#define TEE_READ_REE0_CAN_M (TEE_READ_REE0_CAN_V << TEE_READ_REE0_CAN_S) +#define TEE_READ_REE0_CAN_V 0x00000001U +#define TEE_READ_REE0_CAN_S 1 +/** TEE_READ_REE1_CAN : R/W; bitpos: [2]; default: 0; + * Configures can registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CAN (BIT(2)) +#define TEE_READ_REE1_CAN_M (TEE_READ_REE1_CAN_V << TEE_READ_REE1_CAN_S) +#define TEE_READ_REE1_CAN_V 0x00000001U +#define TEE_READ_REE1_CAN_S 2 +/** TEE_READ_REE2_CAN : R/W; bitpos: [3]; default: 0; + * Configures can registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CAN (BIT(3)) +#define TEE_READ_REE2_CAN_M (TEE_READ_REE2_CAN_V << TEE_READ_REE2_CAN_S) +#define TEE_READ_REE2_CAN_V 0x00000001U +#define TEE_READ_REE2_CAN_S 3 +/** TEE_WRITE_TEE_CAN : R/W; bitpos: [4]; default: 1; + * Configures can registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CAN (BIT(4)) +#define TEE_WRITE_TEE_CAN_M (TEE_WRITE_TEE_CAN_V << TEE_WRITE_TEE_CAN_S) +#define TEE_WRITE_TEE_CAN_V 0x00000001U +#define TEE_WRITE_TEE_CAN_S 4 +/** TEE_WRITE_REE0_CAN : R/W; bitpos: [5]; default: 0; + * Configures can registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CAN (BIT(5)) +#define TEE_WRITE_REE0_CAN_M (TEE_WRITE_REE0_CAN_V << TEE_WRITE_REE0_CAN_S) +#define TEE_WRITE_REE0_CAN_V 0x00000001U +#define TEE_WRITE_REE0_CAN_S 5 +/** TEE_WRITE_REE1_CAN : R/W; bitpos: [6]; default: 0; + * Configures can registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CAN (BIT(6)) +#define TEE_WRITE_REE1_CAN_M (TEE_WRITE_REE1_CAN_V << TEE_WRITE_REE1_CAN_S) +#define TEE_WRITE_REE1_CAN_V 0x00000001U +#define TEE_WRITE_REE1_CAN_S 6 +/** TEE_WRITE_REE2_CAN : R/W; bitpos: [7]; default: 0; + * Configures can registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CAN (BIT(7)) +#define TEE_WRITE_REE2_CAN_M (TEE_WRITE_REE2_CAN_V << TEE_WRITE_REE2_CAN_S) +#define TEE_WRITE_REE2_CAN_V 0x00000001U +#define TEE_WRITE_REE2_CAN_S 7 + +/** TEE_USB_SERIAL_JTAG_CTRL_REG register + * usb_serial_jtag read/write control register + */ +#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1; + * Configures usb_serial_jtag registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_SERIAL_JTAG (BIT(0)) +#define TEE_READ_TEE_USB_SERIAL_JTAG_M (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S) +#define TEE_READ_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_TEE_USB_SERIAL_JTAG_S 0 +/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0; + * Configures usb_serial_jtag registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_SERIAL_JTAG (BIT(1)) +#define TEE_READ_REE0_USB_SERIAL_JTAG_M (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S) +#define TEE_READ_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE0_USB_SERIAL_JTAG_S 1 +/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0; + * Configures usb_serial_jtag registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_SERIAL_JTAG (BIT(2)) +#define TEE_READ_REE1_USB_SERIAL_JTAG_M (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S) +#define TEE_READ_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE1_USB_SERIAL_JTAG_S 2 +/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0; + * Configures usb_serial_jtag registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_SERIAL_JTAG (BIT(3)) +#define TEE_READ_REE2_USB_SERIAL_JTAG_M (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S) +#define TEE_READ_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE2_USB_SERIAL_JTAG_S 3 +/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1; + * Configures usb_serial_jtag registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_SERIAL_JTAG (BIT(4)) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S 4 +/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0; + * Configures usb_serial_jtag registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_SERIAL_JTAG (BIT(5)) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S 5 +/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0; + * Configures usb_serial_jtag registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_SERIAL_JTAG (BIT(6)) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S 6 +/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0; + * Configures usb_serial_jtag registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_SERIAL_JTAG (BIT(7)) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S 7 + +/** TEE_RMT_CTRL_REG register + * rmt read/write control register + */ +#define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) +/** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_RMT (BIT(0)) +#define TEE_READ_TEE_RMT_M (TEE_READ_TEE_RMT_V << TEE_READ_TEE_RMT_S) +#define TEE_READ_TEE_RMT_V 0x00000001U +#define TEE_READ_TEE_RMT_S 0 +/** TEE_READ_REE0_RMT : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_RMT (BIT(1)) +#define TEE_READ_REE0_RMT_M (TEE_READ_REE0_RMT_V << TEE_READ_REE0_RMT_S) +#define TEE_READ_REE0_RMT_V 0x00000001U +#define TEE_READ_REE0_RMT_S 1 +/** TEE_READ_REE1_RMT : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_RMT (BIT(2)) +#define TEE_READ_REE1_RMT_M (TEE_READ_REE1_RMT_V << TEE_READ_REE1_RMT_S) +#define TEE_READ_REE1_RMT_V 0x00000001U +#define TEE_READ_REE1_RMT_S 2 +/** TEE_READ_REE2_RMT : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_RMT (BIT(3)) +#define TEE_READ_REE2_RMT_M (TEE_READ_REE2_RMT_V << TEE_READ_REE2_RMT_S) +#define TEE_READ_REE2_RMT_V 0x00000001U +#define TEE_READ_REE2_RMT_S 3 +/** TEE_WRITE_TEE_RMT : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_RMT (BIT(4)) +#define TEE_WRITE_TEE_RMT_M (TEE_WRITE_TEE_RMT_V << TEE_WRITE_TEE_RMT_S) +#define TEE_WRITE_TEE_RMT_V 0x00000001U +#define TEE_WRITE_TEE_RMT_S 4 +/** TEE_WRITE_REE0_RMT : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_RMT (BIT(5)) +#define TEE_WRITE_REE0_RMT_M (TEE_WRITE_REE0_RMT_V << TEE_WRITE_REE0_RMT_S) +#define TEE_WRITE_REE0_RMT_V 0x00000001U +#define TEE_WRITE_REE0_RMT_S 5 +/** TEE_WRITE_REE1_RMT : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_RMT (BIT(6)) +#define TEE_WRITE_REE1_RMT_M (TEE_WRITE_REE1_RMT_V << TEE_WRITE_REE1_RMT_S) +#define TEE_WRITE_REE1_RMT_V 0x00000001U +#define TEE_WRITE_REE1_RMT_S 6 +/** TEE_WRITE_REE2_RMT : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_RMT (BIT(7)) +#define TEE_WRITE_REE2_RMT_M (TEE_WRITE_REE2_RMT_V << TEE_WRITE_REE2_RMT_S) +#define TEE_WRITE_REE2_RMT_V 0x00000001U +#define TEE_WRITE_REE2_RMT_S 7 + +/** TEE_GDMA_CTRL_REG register + * gdma read/write control register + */ +#define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) +/** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GDMA (BIT(0)) +#define TEE_READ_TEE_GDMA_M (TEE_READ_TEE_GDMA_V << TEE_READ_TEE_GDMA_S) +#define TEE_READ_TEE_GDMA_V 0x00000001U +#define TEE_READ_TEE_GDMA_S 0 +/** TEE_READ_REE0_GDMA : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GDMA (BIT(1)) +#define TEE_READ_REE0_GDMA_M (TEE_READ_REE0_GDMA_V << TEE_READ_REE0_GDMA_S) +#define TEE_READ_REE0_GDMA_V 0x00000001U +#define TEE_READ_REE0_GDMA_S 1 +/** TEE_READ_REE1_GDMA : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GDMA (BIT(2)) +#define TEE_READ_REE1_GDMA_M (TEE_READ_REE1_GDMA_V << TEE_READ_REE1_GDMA_S) +#define TEE_READ_REE1_GDMA_V 0x00000001U +#define TEE_READ_REE1_GDMA_S 2 +/** TEE_READ_REE2_GDMA : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GDMA (BIT(3)) +#define TEE_READ_REE2_GDMA_M (TEE_READ_REE2_GDMA_V << TEE_READ_REE2_GDMA_S) +#define TEE_READ_REE2_GDMA_V 0x00000001U +#define TEE_READ_REE2_GDMA_S 3 +/** TEE_WRITE_TEE_GDMA : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GDMA (BIT(4)) +#define TEE_WRITE_TEE_GDMA_M (TEE_WRITE_TEE_GDMA_V << TEE_WRITE_TEE_GDMA_S) +#define TEE_WRITE_TEE_GDMA_V 0x00000001U +#define TEE_WRITE_TEE_GDMA_S 4 +/** TEE_WRITE_REE0_GDMA : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GDMA (BIT(5)) +#define TEE_WRITE_REE0_GDMA_M (TEE_WRITE_REE0_GDMA_V << TEE_WRITE_REE0_GDMA_S) +#define TEE_WRITE_REE0_GDMA_V 0x00000001U +#define TEE_WRITE_REE0_GDMA_S 5 +/** TEE_WRITE_REE1_GDMA : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GDMA (BIT(6)) +#define TEE_WRITE_REE1_GDMA_M (TEE_WRITE_REE1_GDMA_V << TEE_WRITE_REE1_GDMA_S) +#define TEE_WRITE_REE1_GDMA_V 0x00000001U +#define TEE_WRITE_REE1_GDMA_S 6 +/** TEE_WRITE_REE2_GDMA : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GDMA (BIT(7)) +#define TEE_WRITE_REE2_GDMA_M (TEE_WRITE_REE2_GDMA_V << TEE_WRITE_REE2_GDMA_S) +#define TEE_WRITE_REE2_GDMA_V 0x00000001U +#define TEE_WRITE_REE2_GDMA_S 7 + +/** TEE_REGDMA_CTRL_REG register + * regdma read/write control register + */ +#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) +/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_REGDMA (BIT(0)) +#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) +#define TEE_READ_TEE_REGDMA_V 0x00000001U +#define TEE_READ_TEE_REGDMA_S 0 +/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_REGDMA (BIT(1)) +#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) +#define TEE_READ_REE0_REGDMA_V 0x00000001U +#define TEE_READ_REE0_REGDMA_S 1 +/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_REGDMA (BIT(2)) +#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) +#define TEE_READ_REE1_REGDMA_V 0x00000001U +#define TEE_READ_REE1_REGDMA_S 2 +/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_REGDMA (BIT(3)) +#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) +#define TEE_READ_REE2_REGDMA_V 0x00000001U +#define TEE_READ_REE2_REGDMA_S 3 +/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_REGDMA (BIT(4)) +#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) +#define TEE_WRITE_TEE_REGDMA_V 0x00000001U +#define TEE_WRITE_TEE_REGDMA_S 4 +/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_REGDMA (BIT(5)) +#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) +#define TEE_WRITE_REE0_REGDMA_V 0x00000001U +#define TEE_WRITE_REE0_REGDMA_S 5 +/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_REGDMA (BIT(6)) +#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) +#define TEE_WRITE_REE1_REGDMA_V 0x00000001U +#define TEE_WRITE_REE1_REGDMA_S 6 +/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_REGDMA (BIT(7)) +#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) +#define TEE_WRITE_REE2_REGDMA_V 0x00000001U +#define TEE_WRITE_REE2_REGDMA_S 7 + +/** TEE_ETM_CTRL_REG register + * etm read/write control register + */ +#define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) +/** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_ETM (BIT(0)) +#define TEE_READ_TEE_ETM_M (TEE_READ_TEE_ETM_V << TEE_READ_TEE_ETM_S) +#define TEE_READ_TEE_ETM_V 0x00000001U +#define TEE_READ_TEE_ETM_S 0 +/** TEE_READ_REE0_ETM : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_ETM (BIT(1)) +#define TEE_READ_REE0_ETM_M (TEE_READ_REE0_ETM_V << TEE_READ_REE0_ETM_S) +#define TEE_READ_REE0_ETM_V 0x00000001U +#define TEE_READ_REE0_ETM_S 1 +/** TEE_READ_REE1_ETM : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_ETM (BIT(2)) +#define TEE_READ_REE1_ETM_M (TEE_READ_REE1_ETM_V << TEE_READ_REE1_ETM_S) +#define TEE_READ_REE1_ETM_V 0x00000001U +#define TEE_READ_REE1_ETM_S 2 +/** TEE_READ_REE2_ETM : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_ETM (BIT(3)) +#define TEE_READ_REE2_ETM_M (TEE_READ_REE2_ETM_V << TEE_READ_REE2_ETM_S) +#define TEE_READ_REE2_ETM_V 0x00000001U +#define TEE_READ_REE2_ETM_S 3 +/** TEE_WRITE_TEE_ETM : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_ETM (BIT(4)) +#define TEE_WRITE_TEE_ETM_M (TEE_WRITE_TEE_ETM_V << TEE_WRITE_TEE_ETM_S) +#define TEE_WRITE_TEE_ETM_V 0x00000001U +#define TEE_WRITE_TEE_ETM_S 4 +/** TEE_WRITE_REE0_ETM : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_ETM (BIT(5)) +#define TEE_WRITE_REE0_ETM_M (TEE_WRITE_REE0_ETM_V << TEE_WRITE_REE0_ETM_S) +#define TEE_WRITE_REE0_ETM_V 0x00000001U +#define TEE_WRITE_REE0_ETM_S 5 +/** TEE_WRITE_REE1_ETM : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_ETM (BIT(6)) +#define TEE_WRITE_REE1_ETM_M (TEE_WRITE_REE1_ETM_V << TEE_WRITE_REE1_ETM_S) +#define TEE_WRITE_REE1_ETM_V 0x00000001U +#define TEE_WRITE_REE1_ETM_S 6 +/** TEE_WRITE_REE2_ETM : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_ETM (BIT(7)) +#define TEE_WRITE_REE2_ETM_M (TEE_WRITE_REE2_ETM_V << TEE_WRITE_REE2_ETM_S) +#define TEE_WRITE_REE2_ETM_V 0x00000001U +#define TEE_WRITE_REE2_ETM_S 7 + +/** TEE_INTMTX_CORE0_CTRL_REG register + * intmtx_core0 read/write control register + */ +#define TEE_INTMTX_CORE0_CTRL_REG (DR_REG_TEE_BASE + 0xc8) +/** TEE_READ_TEE_INTMTX_CORE0 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTMTX_CORE0 (BIT(0)) +#define TEE_READ_TEE_INTMTX_CORE0_M (TEE_READ_TEE_INTMTX_CORE0_V << TEE_READ_TEE_INTMTX_CORE0_S) +#define TEE_READ_TEE_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_TEE_INTMTX_CORE0_S 0 +/** TEE_READ_REE0_INTMTX_CORE0 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTMTX_CORE0 (BIT(1)) +#define TEE_READ_REE0_INTMTX_CORE0_M (TEE_READ_REE0_INTMTX_CORE0_V << TEE_READ_REE0_INTMTX_CORE0_S) +#define TEE_READ_REE0_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE0_INTMTX_CORE0_S 1 +/** TEE_READ_REE1_INTMTX_CORE0 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTMTX_CORE0 (BIT(2)) +#define TEE_READ_REE1_INTMTX_CORE0_M (TEE_READ_REE1_INTMTX_CORE0_V << TEE_READ_REE1_INTMTX_CORE0_S) +#define TEE_READ_REE1_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE1_INTMTX_CORE0_S 2 +/** TEE_READ_REE2_INTMTX_CORE0 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTMTX_CORE0 (BIT(3)) +#define TEE_READ_REE2_INTMTX_CORE0_M (TEE_READ_REE2_INTMTX_CORE0_V << TEE_READ_REE2_INTMTX_CORE0_S) +#define TEE_READ_REE2_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE2_INTMTX_CORE0_S 3 +/** TEE_WRITE_TEE_INTMTX_CORE0 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTMTX_CORE0 (BIT(4)) +#define TEE_WRITE_TEE_INTMTX_CORE0_M (TEE_WRITE_TEE_INTMTX_CORE0_V << TEE_WRITE_TEE_INTMTX_CORE0_S) +#define TEE_WRITE_TEE_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_TEE_INTMTX_CORE0_S 4 +/** TEE_WRITE_REE0_INTMTX_CORE0 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTMTX_CORE0 (BIT(5)) +#define TEE_WRITE_REE0_INTMTX_CORE0_M (TEE_WRITE_REE0_INTMTX_CORE0_V << TEE_WRITE_REE0_INTMTX_CORE0_S) +#define TEE_WRITE_REE0_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE0_INTMTX_CORE0_S 5 +/** TEE_WRITE_REE1_INTMTX_CORE0 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTMTX_CORE0 (BIT(6)) +#define TEE_WRITE_REE1_INTMTX_CORE0_M (TEE_WRITE_REE1_INTMTX_CORE0_V << TEE_WRITE_REE1_INTMTX_CORE0_S) +#define TEE_WRITE_REE1_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE1_INTMTX_CORE0_S 6 +/** TEE_WRITE_REE2_INTMTX_CORE0 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTMTX_CORE0 (BIT(7)) +#define TEE_WRITE_REE2_INTMTX_CORE0_M (TEE_WRITE_REE2_INTMTX_CORE0_V << TEE_WRITE_REE2_INTMTX_CORE0_S) +#define TEE_WRITE_REE2_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE2_INTMTX_CORE0_S 7 + +/** TEE_INTMTX_CORE1_CTRL_REG register + * intmtx_core1 read/write control register + */ +#define TEE_INTMTX_CORE1_CTRL_REG (DR_REG_TEE_BASE + 0xcc) +/** TEE_READ_TEE_INTMTX_CORE1 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTMTX_CORE1 (BIT(0)) +#define TEE_READ_TEE_INTMTX_CORE1_M (TEE_READ_TEE_INTMTX_CORE1_V << TEE_READ_TEE_INTMTX_CORE1_S) +#define TEE_READ_TEE_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_TEE_INTMTX_CORE1_S 0 +/** TEE_READ_REE0_INTMTX_CORE1 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTMTX_CORE1 (BIT(1)) +#define TEE_READ_REE0_INTMTX_CORE1_M (TEE_READ_REE0_INTMTX_CORE1_V << TEE_READ_REE0_INTMTX_CORE1_S) +#define TEE_READ_REE0_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE0_INTMTX_CORE1_S 1 +/** TEE_READ_REE1_INTMTX_CORE1 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTMTX_CORE1 (BIT(2)) +#define TEE_READ_REE1_INTMTX_CORE1_M (TEE_READ_REE1_INTMTX_CORE1_V << TEE_READ_REE1_INTMTX_CORE1_S) +#define TEE_READ_REE1_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE1_INTMTX_CORE1_S 2 +/** TEE_READ_REE2_INTMTX_CORE1 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTMTX_CORE1 (BIT(3)) +#define TEE_READ_REE2_INTMTX_CORE1_M (TEE_READ_REE2_INTMTX_CORE1_V << TEE_READ_REE2_INTMTX_CORE1_S) +#define TEE_READ_REE2_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE2_INTMTX_CORE1_S 3 +/** TEE_WRITE_TEE_INTMTX_CORE1 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTMTX_CORE1 (BIT(4)) +#define TEE_WRITE_TEE_INTMTX_CORE1_M (TEE_WRITE_TEE_INTMTX_CORE1_V << TEE_WRITE_TEE_INTMTX_CORE1_S) +#define TEE_WRITE_TEE_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_TEE_INTMTX_CORE1_S 4 +/** TEE_WRITE_REE0_INTMTX_CORE1 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTMTX_CORE1 (BIT(5)) +#define TEE_WRITE_REE0_INTMTX_CORE1_M (TEE_WRITE_REE0_INTMTX_CORE1_V << TEE_WRITE_REE0_INTMTX_CORE1_S) +#define TEE_WRITE_REE0_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE0_INTMTX_CORE1_S 5 +/** TEE_WRITE_REE1_INTMTX_CORE1 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTMTX_CORE1 (BIT(6)) +#define TEE_WRITE_REE1_INTMTX_CORE1_M (TEE_WRITE_REE1_INTMTX_CORE1_V << TEE_WRITE_REE1_INTMTX_CORE1_S) +#define TEE_WRITE_REE1_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE1_INTMTX_CORE1_S 6 +/** TEE_WRITE_REE2_INTMTX_CORE1 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTMTX_CORE1 (BIT(7)) +#define TEE_WRITE_REE2_INTMTX_CORE1_M (TEE_WRITE_REE2_INTMTX_CORE1_V << TEE_WRITE_REE2_INTMTX_CORE1_S) +#define TEE_WRITE_REE2_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE2_INTMTX_CORE1_S 7 + +/** TEE_APB_ADC_CTRL_REG register + * apb_adc read/write control register + */ +#define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) +/** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_APB_ADC (BIT(0)) +#define TEE_READ_TEE_APB_ADC_M (TEE_READ_TEE_APB_ADC_V << TEE_READ_TEE_APB_ADC_S) +#define TEE_READ_TEE_APB_ADC_V 0x00000001U +#define TEE_READ_TEE_APB_ADC_S 0 +/** TEE_READ_REE0_APB_ADC : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_APB_ADC (BIT(1)) +#define TEE_READ_REE0_APB_ADC_M (TEE_READ_REE0_APB_ADC_V << TEE_READ_REE0_APB_ADC_S) +#define TEE_READ_REE0_APB_ADC_V 0x00000001U +#define TEE_READ_REE0_APB_ADC_S 1 +/** TEE_READ_REE1_APB_ADC : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_APB_ADC (BIT(2)) +#define TEE_READ_REE1_APB_ADC_M (TEE_READ_REE1_APB_ADC_V << TEE_READ_REE1_APB_ADC_S) +#define TEE_READ_REE1_APB_ADC_V 0x00000001U +#define TEE_READ_REE1_APB_ADC_S 2 +/** TEE_READ_REE2_APB_ADC : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_APB_ADC (BIT(3)) +#define TEE_READ_REE2_APB_ADC_M (TEE_READ_REE2_APB_ADC_V << TEE_READ_REE2_APB_ADC_S) +#define TEE_READ_REE2_APB_ADC_V 0x00000001U +#define TEE_READ_REE2_APB_ADC_S 3 +/** TEE_WRITE_TEE_APB_ADC : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_APB_ADC (BIT(4)) +#define TEE_WRITE_TEE_APB_ADC_M (TEE_WRITE_TEE_APB_ADC_V << TEE_WRITE_TEE_APB_ADC_S) +#define TEE_WRITE_TEE_APB_ADC_V 0x00000001U +#define TEE_WRITE_TEE_APB_ADC_S 4 +/** TEE_WRITE_REE0_APB_ADC : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_APB_ADC (BIT(5)) +#define TEE_WRITE_REE0_APB_ADC_M (TEE_WRITE_REE0_APB_ADC_V << TEE_WRITE_REE0_APB_ADC_S) +#define TEE_WRITE_REE0_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE0_APB_ADC_S 5 +/** TEE_WRITE_REE1_APB_ADC : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_APB_ADC (BIT(6)) +#define TEE_WRITE_REE1_APB_ADC_M (TEE_WRITE_REE1_APB_ADC_V << TEE_WRITE_REE1_APB_ADC_S) +#define TEE_WRITE_REE1_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE1_APB_ADC_S 6 +/** TEE_WRITE_REE2_APB_ADC : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_APB_ADC (BIT(7)) +#define TEE_WRITE_REE2_APB_ADC_M (TEE_WRITE_REE2_APB_ADC_V << TEE_WRITE_REE2_APB_ADC_S) +#define TEE_WRITE_REE2_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE2_APB_ADC_S 7 + +/** TEE_TIMERGROUP0_CTRL_REG register + * timergroup0 read/write control register + */ +#define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) +/** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP0 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP0_M (TEE_READ_TEE_TIMERGROUP0_V << TEE_READ_TEE_TIMERGROUP0_S) +#define TEE_READ_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP0_S 0 +/** TEE_READ_REE0_TIMERGROUP0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP0 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP0_M (TEE_READ_REE0_TIMERGROUP0_V << TEE_READ_REE0_TIMERGROUP0_S) +#define TEE_READ_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP0_S 1 +/** TEE_READ_REE1_TIMERGROUP0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP0 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP0_M (TEE_READ_REE1_TIMERGROUP0_V << TEE_READ_REE1_TIMERGROUP0_S) +#define TEE_READ_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP0_S 2 +/** TEE_READ_REE2_TIMERGROUP0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP0 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP0_M (TEE_READ_REE2_TIMERGROUP0_V << TEE_READ_REE2_TIMERGROUP0_S) +#define TEE_READ_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP0_S 3 +/** TEE_WRITE_TEE_TIMERGROUP0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP0 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP0_M (TEE_WRITE_TEE_TIMERGROUP0_V << TEE_WRITE_TEE_TIMERGROUP0_S) +#define TEE_WRITE_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP0_S 4 +/** TEE_WRITE_REE0_TIMERGROUP0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP0 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP0_M (TEE_WRITE_REE0_TIMERGROUP0_V << TEE_WRITE_REE0_TIMERGROUP0_S) +#define TEE_WRITE_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP0_S 5 +/** TEE_WRITE_REE1_TIMERGROUP0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP0 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP0_M (TEE_WRITE_REE1_TIMERGROUP0_V << TEE_WRITE_REE1_TIMERGROUP0_S) +#define TEE_WRITE_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP0_S 6 +/** TEE_WRITE_REE2_TIMERGROUP0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP0 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP0_M (TEE_WRITE_REE2_TIMERGROUP0_V << TEE_WRITE_REE2_TIMERGROUP0_S) +#define TEE_WRITE_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP0_S 7 + +/** TEE_TIMERGROUP1_CTRL_REG register + * timergroup1 read/write control register + */ +#define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) +/** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP1 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP1_M (TEE_READ_TEE_TIMERGROUP1_V << TEE_READ_TEE_TIMERGROUP1_S) +#define TEE_READ_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP1_S 0 +/** TEE_READ_REE0_TIMERGROUP1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP1 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP1_M (TEE_READ_REE0_TIMERGROUP1_V << TEE_READ_REE0_TIMERGROUP1_S) +#define TEE_READ_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP1_S 1 +/** TEE_READ_REE1_TIMERGROUP1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP1 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP1_M (TEE_READ_REE1_TIMERGROUP1_V << TEE_READ_REE1_TIMERGROUP1_S) +#define TEE_READ_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP1_S 2 +/** TEE_READ_REE2_TIMERGROUP1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP1 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP1_M (TEE_READ_REE2_TIMERGROUP1_V << TEE_READ_REE2_TIMERGROUP1_S) +#define TEE_READ_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP1_S 3 +/** TEE_WRITE_TEE_TIMERGROUP1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP1 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP1_M (TEE_WRITE_TEE_TIMERGROUP1_V << TEE_WRITE_TEE_TIMERGROUP1_S) +#define TEE_WRITE_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP1_S 4 +/** TEE_WRITE_REE0_TIMERGROUP1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP1 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP1_M (TEE_WRITE_REE0_TIMERGROUP1_V << TEE_WRITE_REE0_TIMERGROUP1_S) +#define TEE_WRITE_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP1_S 5 +/** TEE_WRITE_REE1_TIMERGROUP1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP1 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP1_M (TEE_WRITE_REE1_TIMERGROUP1_V << TEE_WRITE_REE1_TIMERGROUP1_S) +#define TEE_WRITE_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP1_S 6 +/** TEE_WRITE_REE2_TIMERGROUP1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP1 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP1_M (TEE_WRITE_REE2_TIMERGROUP1_V << TEE_WRITE_REE2_TIMERGROUP1_S) +#define TEE_WRITE_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP1_S 7 + +/** TEE_SYSTIMER_CTRL_REG register + * systimer read/write control register + */ +#define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) +/** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SYSTIMER (BIT(0)) +#define TEE_READ_TEE_SYSTIMER_M (TEE_READ_TEE_SYSTIMER_V << TEE_READ_TEE_SYSTIMER_S) +#define TEE_READ_TEE_SYSTIMER_V 0x00000001U +#define TEE_READ_TEE_SYSTIMER_S 0 +/** TEE_READ_REE0_SYSTIMER : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SYSTIMER (BIT(1)) +#define TEE_READ_REE0_SYSTIMER_M (TEE_READ_REE0_SYSTIMER_V << TEE_READ_REE0_SYSTIMER_S) +#define TEE_READ_REE0_SYSTIMER_V 0x00000001U +#define TEE_READ_REE0_SYSTIMER_S 1 +/** TEE_READ_REE1_SYSTIMER : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SYSTIMER (BIT(2)) +#define TEE_READ_REE1_SYSTIMER_M (TEE_READ_REE1_SYSTIMER_V << TEE_READ_REE1_SYSTIMER_S) +#define TEE_READ_REE1_SYSTIMER_V 0x00000001U +#define TEE_READ_REE1_SYSTIMER_S 2 +/** TEE_READ_REE2_SYSTIMER : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SYSTIMER (BIT(3)) +#define TEE_READ_REE2_SYSTIMER_M (TEE_READ_REE2_SYSTIMER_V << TEE_READ_REE2_SYSTIMER_S) +#define TEE_READ_REE2_SYSTIMER_V 0x00000001U +#define TEE_READ_REE2_SYSTIMER_S 3 +/** TEE_WRITE_TEE_SYSTIMER : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SYSTIMER (BIT(4)) +#define TEE_WRITE_TEE_SYSTIMER_M (TEE_WRITE_TEE_SYSTIMER_V << TEE_WRITE_TEE_SYSTIMER_S) +#define TEE_WRITE_TEE_SYSTIMER_V 0x00000001U +#define TEE_WRITE_TEE_SYSTIMER_S 4 +/** TEE_WRITE_REE0_SYSTIMER : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SYSTIMER (BIT(5)) +#define TEE_WRITE_REE0_SYSTIMER_M (TEE_WRITE_REE0_SYSTIMER_V << TEE_WRITE_REE0_SYSTIMER_S) +#define TEE_WRITE_REE0_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE0_SYSTIMER_S 5 +/** TEE_WRITE_REE1_SYSTIMER : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SYSTIMER (BIT(6)) +#define TEE_WRITE_REE1_SYSTIMER_M (TEE_WRITE_REE1_SYSTIMER_V << TEE_WRITE_REE1_SYSTIMER_S) +#define TEE_WRITE_REE1_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE1_SYSTIMER_S 6 +/** TEE_WRITE_REE2_SYSTIMER : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SYSTIMER (BIT(7)) +#define TEE_WRITE_REE2_SYSTIMER_M (TEE_WRITE_REE2_SYSTIMER_V << TEE_WRITE_REE2_SYSTIMER_S) +#define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE2_SYSTIMER_S 7 + +/** TEE_MISC_CTRL_REG register + * misc read/write control register + */ +#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) +/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MISC (BIT(0)) +#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) +#define TEE_READ_TEE_MISC_V 0x00000001U +#define TEE_READ_TEE_MISC_S 0 +/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MISC (BIT(1)) +#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) +#define TEE_READ_REE0_MISC_V 0x00000001U +#define TEE_READ_REE0_MISC_S 1 +/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MISC (BIT(2)) +#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) +#define TEE_READ_REE1_MISC_V 0x00000001U +#define TEE_READ_REE1_MISC_S 2 +/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MISC (BIT(3)) +#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) +#define TEE_READ_REE2_MISC_V 0x00000001U +#define TEE_READ_REE2_MISC_S 3 +/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MISC (BIT(4)) +#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) +#define TEE_WRITE_TEE_MISC_V 0x00000001U +#define TEE_WRITE_TEE_MISC_S 4 +/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MISC (BIT(5)) +#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) +#define TEE_WRITE_REE0_MISC_V 0x00000001U +#define TEE_WRITE_REE0_MISC_S 5 +/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MISC (BIT(6)) +#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) +#define TEE_WRITE_REE1_MISC_V 0x00000001U +#define TEE_WRITE_REE1_MISC_S 6 +/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MISC (BIT(7)) +#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) +#define TEE_WRITE_REE2_MISC_V 0x00000001U +#define TEE_WRITE_REE2_MISC_S 7 + +/** TEE_SRC_CTRL_REG register + * src read/write control register + */ +#define TEE_SRC_CTRL_REG (DR_REG_TEE_BASE + 0xe4) +/** TEE_READ_TEE_SRC : R/W; bitpos: [0]; default: 1; + * Configures src registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SRC (BIT(0)) +#define TEE_READ_TEE_SRC_M (TEE_READ_TEE_SRC_V << TEE_READ_TEE_SRC_S) +#define TEE_READ_TEE_SRC_V 0x00000001U +#define TEE_READ_TEE_SRC_S 0 +/** TEE_READ_REE0_SRC : R/W; bitpos: [1]; default: 0; + * Configures src registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SRC (BIT(1)) +#define TEE_READ_REE0_SRC_M (TEE_READ_REE0_SRC_V << TEE_READ_REE0_SRC_S) +#define TEE_READ_REE0_SRC_V 0x00000001U +#define TEE_READ_REE0_SRC_S 1 +/** TEE_READ_REE1_SRC : R/W; bitpos: [2]; default: 0; + * Configures src registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SRC (BIT(2)) +#define TEE_READ_REE1_SRC_M (TEE_READ_REE1_SRC_V << TEE_READ_REE1_SRC_S) +#define TEE_READ_REE1_SRC_V 0x00000001U +#define TEE_READ_REE1_SRC_S 2 +/** TEE_READ_REE2_SRC : R/W; bitpos: [3]; default: 0; + * Configures src registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SRC (BIT(3)) +#define TEE_READ_REE2_SRC_M (TEE_READ_REE2_SRC_V << TEE_READ_REE2_SRC_S) +#define TEE_READ_REE2_SRC_V 0x00000001U +#define TEE_READ_REE2_SRC_S 3 +/** TEE_WRITE_TEE_SRC : R/W; bitpos: [4]; default: 1; + * Configures src registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SRC (BIT(4)) +#define TEE_WRITE_TEE_SRC_M (TEE_WRITE_TEE_SRC_V << TEE_WRITE_TEE_SRC_S) +#define TEE_WRITE_TEE_SRC_V 0x00000001U +#define TEE_WRITE_TEE_SRC_S 4 +/** TEE_WRITE_REE0_SRC : R/W; bitpos: [5]; default: 0; + * Configures src registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SRC (BIT(5)) +#define TEE_WRITE_REE0_SRC_M (TEE_WRITE_REE0_SRC_V << TEE_WRITE_REE0_SRC_S) +#define TEE_WRITE_REE0_SRC_V 0x00000001U +#define TEE_WRITE_REE0_SRC_S 5 +/** TEE_WRITE_REE1_SRC : R/W; bitpos: [6]; default: 0; + * Configures src registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SRC (BIT(6)) +#define TEE_WRITE_REE1_SRC_M (TEE_WRITE_REE1_SRC_V << TEE_WRITE_REE1_SRC_S) +#define TEE_WRITE_REE1_SRC_V 0x00000001U +#define TEE_WRITE_REE1_SRC_S 6 +/** TEE_WRITE_REE2_SRC : R/W; bitpos: [7]; default: 0; + * Configures src registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SRC (BIT(7)) +#define TEE_WRITE_REE2_SRC_M (TEE_WRITE_REE2_SRC_V << TEE_WRITE_REE2_SRC_S) +#define TEE_WRITE_REE2_SRC_V 0x00000001U +#define TEE_WRITE_REE2_SRC_S 7 + +/** TEE_USB_OTG_FS_CORE_CTRL_REG register + * usb_otg_fs_core read/write control register + */ +#define TEE_USB_OTG_FS_CORE_CTRL_REG (DR_REG_TEE_BASE + 0xe8) +/** TEE_READ_TEE_USB_OTG_FS_CORE : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_core registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_OTG_FS_CORE (BIT(0)) +#define TEE_READ_TEE_USB_OTG_FS_CORE_M (TEE_READ_TEE_USB_OTG_FS_CORE_V << TEE_READ_TEE_USB_OTG_FS_CORE_S) +#define TEE_READ_TEE_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_TEE_USB_OTG_FS_CORE_S 0 +/** TEE_READ_REE0_USB_OTG_FS_CORE : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_OTG_FS_CORE (BIT(1)) +#define TEE_READ_REE0_USB_OTG_FS_CORE_M (TEE_READ_REE0_USB_OTG_FS_CORE_V << TEE_READ_REE0_USB_OTG_FS_CORE_S) +#define TEE_READ_REE0_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE0_USB_OTG_FS_CORE_S 1 +/** TEE_READ_REE1_USB_OTG_FS_CORE : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_OTG_FS_CORE (BIT(2)) +#define TEE_READ_REE1_USB_OTG_FS_CORE_M (TEE_READ_REE1_USB_OTG_FS_CORE_V << TEE_READ_REE1_USB_OTG_FS_CORE_S) +#define TEE_READ_REE1_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE1_USB_OTG_FS_CORE_S 2 +/** TEE_READ_REE2_USB_OTG_FS_CORE : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_OTG_FS_CORE (BIT(3)) +#define TEE_READ_REE2_USB_OTG_FS_CORE_M (TEE_READ_REE2_USB_OTG_FS_CORE_V << TEE_READ_REE2_USB_OTG_FS_CORE_S) +#define TEE_READ_REE2_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE2_USB_OTG_FS_CORE_S 3 +/** TEE_WRITE_TEE_USB_OTG_FS_CORE : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_core registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_OTG_FS_CORE (BIT(4)) +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_M (TEE_WRITE_TEE_USB_OTG_FS_CORE_V << TEE_WRITE_TEE_USB_OTG_FS_CORE_S) +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_S 4 +/** TEE_WRITE_REE0_USB_OTG_FS_CORE : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_OTG_FS_CORE (BIT(5)) +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_M (TEE_WRITE_REE0_USB_OTG_FS_CORE_V << TEE_WRITE_REE0_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_S 5 +/** TEE_WRITE_REE1_USB_OTG_FS_CORE : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_OTG_FS_CORE (BIT(6)) +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_M (TEE_WRITE_REE1_USB_OTG_FS_CORE_V << TEE_WRITE_REE1_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_S 6 +/** TEE_WRITE_REE2_USB_OTG_FS_CORE : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_OTG_FS_CORE (BIT(7)) +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_M (TEE_WRITE_REE2_USB_OTG_FS_CORE_V << TEE_WRITE_REE2_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_S 7 + +/** TEE_USB_OTG_FS_PHY_CTRL_REG register + * usb_otg_fs_phy read/write control register + */ +#define TEE_USB_OTG_FS_PHY_CTRL_REG (DR_REG_TEE_BASE + 0xec) +/** TEE_READ_TEE_USB_OTG_FS_PHY : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_phy registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_OTG_FS_PHY (BIT(0)) +#define TEE_READ_TEE_USB_OTG_FS_PHY_M (TEE_READ_TEE_USB_OTG_FS_PHY_V << TEE_READ_TEE_USB_OTG_FS_PHY_S) +#define TEE_READ_TEE_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_TEE_USB_OTG_FS_PHY_S 0 +/** TEE_READ_REE0_USB_OTG_FS_PHY : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_OTG_FS_PHY (BIT(1)) +#define TEE_READ_REE0_USB_OTG_FS_PHY_M (TEE_READ_REE0_USB_OTG_FS_PHY_V << TEE_READ_REE0_USB_OTG_FS_PHY_S) +#define TEE_READ_REE0_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE0_USB_OTG_FS_PHY_S 1 +/** TEE_READ_REE1_USB_OTG_FS_PHY : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_OTG_FS_PHY (BIT(2)) +#define TEE_READ_REE1_USB_OTG_FS_PHY_M (TEE_READ_REE1_USB_OTG_FS_PHY_V << TEE_READ_REE1_USB_OTG_FS_PHY_S) +#define TEE_READ_REE1_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE1_USB_OTG_FS_PHY_S 2 +/** TEE_READ_REE2_USB_OTG_FS_PHY : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_OTG_FS_PHY (BIT(3)) +#define TEE_READ_REE2_USB_OTG_FS_PHY_M (TEE_READ_REE2_USB_OTG_FS_PHY_V << TEE_READ_REE2_USB_OTG_FS_PHY_S) +#define TEE_READ_REE2_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE2_USB_OTG_FS_PHY_S 3 +/** TEE_WRITE_TEE_USB_OTG_FS_PHY : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_phy registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_OTG_FS_PHY (BIT(4)) +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_M (TEE_WRITE_TEE_USB_OTG_FS_PHY_V << TEE_WRITE_TEE_USB_OTG_FS_PHY_S) +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_S 4 +/** TEE_WRITE_REE0_USB_OTG_FS_PHY : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_OTG_FS_PHY (BIT(5)) +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_M (TEE_WRITE_REE0_USB_OTG_FS_PHY_V << TEE_WRITE_REE0_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_S 5 +/** TEE_WRITE_REE1_USB_OTG_FS_PHY : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_OTG_FS_PHY (BIT(6)) +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_M (TEE_WRITE_REE1_USB_OTG_FS_PHY_V << TEE_WRITE_REE1_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_S 6 +/** TEE_WRITE_REE2_USB_OTG_FS_PHY : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_OTG_FS_PHY (BIT(7)) +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_M (TEE_WRITE_REE2_USB_OTG_FS_PHY_V << TEE_WRITE_REE2_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_S 7 + +/** TEE_PVT_MONITOR_CTRL_REG register + * pvt_monitor read/write control register + */ +#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) +/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) +#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) +#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PVT_MONITOR_S 0 +/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) +#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) +#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PVT_MONITOR_S 1 +/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) +#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) +#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PVT_MONITOR_S 2 +/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) +#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) +#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PVT_MONITOR_S 3 +/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) +#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PVT_MONITOR_S 4 +/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) +#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PVT_MONITOR_S 5 +/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) +#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PVT_MONITOR_S 6 +/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) +#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PVT_MONITOR_S 7 + +/** TEE_PCNT_CTRL_REG register + * pcnt read/write control register + */ +#define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) +/** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCNT (BIT(0)) +#define TEE_READ_TEE_PCNT_M (TEE_READ_TEE_PCNT_V << TEE_READ_TEE_PCNT_S) +#define TEE_READ_TEE_PCNT_V 0x00000001U +#define TEE_READ_TEE_PCNT_S 0 +/** TEE_READ_REE0_PCNT : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCNT (BIT(1)) +#define TEE_READ_REE0_PCNT_M (TEE_READ_REE0_PCNT_V << TEE_READ_REE0_PCNT_S) +#define TEE_READ_REE0_PCNT_V 0x00000001U +#define TEE_READ_REE0_PCNT_S 1 +/** TEE_READ_REE1_PCNT : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCNT (BIT(2)) +#define TEE_READ_REE1_PCNT_M (TEE_READ_REE1_PCNT_V << TEE_READ_REE1_PCNT_S) +#define TEE_READ_REE1_PCNT_V 0x00000001U +#define TEE_READ_REE1_PCNT_S 2 +/** TEE_READ_REE2_PCNT : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCNT (BIT(3)) +#define TEE_READ_REE2_PCNT_M (TEE_READ_REE2_PCNT_V << TEE_READ_REE2_PCNT_S) +#define TEE_READ_REE2_PCNT_V 0x00000001U +#define TEE_READ_REE2_PCNT_S 3 +/** TEE_WRITE_TEE_PCNT : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCNT (BIT(4)) +#define TEE_WRITE_TEE_PCNT_M (TEE_WRITE_TEE_PCNT_V << TEE_WRITE_TEE_PCNT_S) +#define TEE_WRITE_TEE_PCNT_V 0x00000001U +#define TEE_WRITE_TEE_PCNT_S 4 +/** TEE_WRITE_REE0_PCNT : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCNT (BIT(5)) +#define TEE_WRITE_REE0_PCNT_M (TEE_WRITE_REE0_PCNT_V << TEE_WRITE_REE0_PCNT_S) +#define TEE_WRITE_REE0_PCNT_V 0x00000001U +#define TEE_WRITE_REE0_PCNT_S 5 +/** TEE_WRITE_REE1_PCNT : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCNT (BIT(6)) +#define TEE_WRITE_REE1_PCNT_M (TEE_WRITE_REE1_PCNT_V << TEE_WRITE_REE1_PCNT_S) +#define TEE_WRITE_REE1_PCNT_V 0x00000001U +#define TEE_WRITE_REE1_PCNT_S 6 +/** TEE_WRITE_REE2_PCNT : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCNT (BIT(7)) +#define TEE_WRITE_REE2_PCNT_M (TEE_WRITE_REE2_PCNT_V << TEE_WRITE_REE2_PCNT_S) +#define TEE_WRITE_REE2_PCNT_V 0x00000001U +#define TEE_WRITE_REE2_PCNT_S 7 + +/** TEE_IOMUX_CTRL_REG register + * iomux read/write control register + */ +#define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) +/** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_IOMUX (BIT(0)) +#define TEE_READ_TEE_IOMUX_M (TEE_READ_TEE_IOMUX_V << TEE_READ_TEE_IOMUX_S) +#define TEE_READ_TEE_IOMUX_V 0x00000001U +#define TEE_READ_TEE_IOMUX_S 0 +/** TEE_READ_REE0_IOMUX : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_IOMUX (BIT(1)) +#define TEE_READ_REE0_IOMUX_M (TEE_READ_REE0_IOMUX_V << TEE_READ_REE0_IOMUX_S) +#define TEE_READ_REE0_IOMUX_V 0x00000001U +#define TEE_READ_REE0_IOMUX_S 1 +/** TEE_READ_REE1_IOMUX : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_IOMUX (BIT(2)) +#define TEE_READ_REE1_IOMUX_M (TEE_READ_REE1_IOMUX_V << TEE_READ_REE1_IOMUX_S) +#define TEE_READ_REE1_IOMUX_V 0x00000001U +#define TEE_READ_REE1_IOMUX_S 2 +/** TEE_READ_REE2_IOMUX : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_IOMUX (BIT(3)) +#define TEE_READ_REE2_IOMUX_M (TEE_READ_REE2_IOMUX_V << TEE_READ_REE2_IOMUX_S) +#define TEE_READ_REE2_IOMUX_V 0x00000001U +#define TEE_READ_REE2_IOMUX_S 3 +/** TEE_WRITE_TEE_IOMUX : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_IOMUX (BIT(4)) +#define TEE_WRITE_TEE_IOMUX_M (TEE_WRITE_TEE_IOMUX_V << TEE_WRITE_TEE_IOMUX_S) +#define TEE_WRITE_TEE_IOMUX_V 0x00000001U +#define TEE_WRITE_TEE_IOMUX_S 4 +/** TEE_WRITE_REE0_IOMUX : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_IOMUX (BIT(5)) +#define TEE_WRITE_REE0_IOMUX_M (TEE_WRITE_REE0_IOMUX_V << TEE_WRITE_REE0_IOMUX_S) +#define TEE_WRITE_REE0_IOMUX_V 0x00000001U +#define TEE_WRITE_REE0_IOMUX_S 5 +/** TEE_WRITE_REE1_IOMUX : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_IOMUX (BIT(6)) +#define TEE_WRITE_REE1_IOMUX_M (TEE_WRITE_REE1_IOMUX_V << TEE_WRITE_REE1_IOMUX_S) +#define TEE_WRITE_REE1_IOMUX_V 0x00000001U +#define TEE_WRITE_REE1_IOMUX_S 6 +/** TEE_WRITE_REE2_IOMUX : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_IOMUX (BIT(7)) +#define TEE_WRITE_REE2_IOMUX_M (TEE_WRITE_REE2_IOMUX_V << TEE_WRITE_REE2_IOMUX_S) +#define TEE_WRITE_REE2_IOMUX_V 0x00000001U +#define TEE_WRITE_REE2_IOMUX_S 7 + +/** TEE_PSRAM_MEM_MONITOR_CTRL_REG register + * psram_mem_monitor read/write control register + */ +#define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) +/** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PSRAM_MEM_MONITOR (BIT(0)) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_M (TEE_READ_TEE_PSRAM_MEM_MONITOR_V << TEE_READ_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_S 0 +/** TEE_READ_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PSRAM_MEM_MONITOR (BIT(1)) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_M (TEE_READ_REE0_PSRAM_MEM_MONITOR_V << TEE_READ_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_S 1 +/** TEE_READ_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PSRAM_MEM_MONITOR (BIT(2)) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_M (TEE_READ_REE1_PSRAM_MEM_MONITOR_V << TEE_READ_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_S 2 +/** TEE_READ_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PSRAM_MEM_MONITOR (BIT(3)) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_M (TEE_READ_REE2_PSRAM_MEM_MONITOR_V << TEE_READ_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_S 3 +/** TEE_WRITE_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_M (TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V << TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S 4 +/** TEE_WRITE_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S 5 +/** TEE_WRITE_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S 6 +/** TEE_WRITE_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 + +/** TEE_MEM_ACS_MONITOR_CTRL_REG register + * mem_acs_monitor read/write control register + */ +#define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) +/** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MEM_ACS_MONITOR (BIT(0)) +#define TEE_READ_TEE_MEM_ACS_MONITOR_M (TEE_READ_TEE_MEM_ACS_MONITOR_V << TEE_READ_TEE_MEM_ACS_MONITOR_S) +#define TEE_READ_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_MEM_ACS_MONITOR_S 0 +/** TEE_READ_REE0_MEM_ACS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MEM_ACS_MONITOR (BIT(1)) +#define TEE_READ_REE0_MEM_ACS_MONITOR_M (TEE_READ_REE0_MEM_ACS_MONITOR_V << TEE_READ_REE0_MEM_ACS_MONITOR_S) +#define TEE_READ_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_MEM_ACS_MONITOR_S 1 +/** TEE_READ_REE1_MEM_ACS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MEM_ACS_MONITOR (BIT(2)) +#define TEE_READ_REE1_MEM_ACS_MONITOR_M (TEE_READ_REE1_MEM_ACS_MONITOR_V << TEE_READ_REE1_MEM_ACS_MONITOR_S) +#define TEE_READ_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_MEM_ACS_MONITOR_S 2 +/** TEE_READ_REE2_MEM_ACS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MEM_ACS_MONITOR (BIT(3)) +#define TEE_READ_REE2_MEM_ACS_MONITOR_M (TEE_READ_REE2_MEM_ACS_MONITOR_V << TEE_READ_REE2_MEM_ACS_MONITOR_S) +#define TEE_READ_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_MEM_ACS_MONITOR_S 3 +/** TEE_WRITE_TEE_MEM_ACS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MEM_ACS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_M (TEE_WRITE_TEE_MEM_ACS_MONITOR_V << TEE_WRITE_TEE_MEM_ACS_MONITOR_S) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_S 4 +/** TEE_WRITE_REE0_MEM_ACS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MEM_ACS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_M (TEE_WRITE_REE0_MEM_ACS_MONITOR_V << TEE_WRITE_REE0_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_S 5 +/** TEE_WRITE_REE1_MEM_ACS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MEM_ACS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_M (TEE_WRITE_REE1_MEM_ACS_MONITOR_V << TEE_WRITE_REE1_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_S 6 +/** TEE_WRITE_REE2_MEM_ACS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MEM_ACS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_M (TEE_WRITE_REE2_MEM_ACS_MONITOR_V << TEE_WRITE_REE2_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 + +/** TEE_HP_SYSTEM_REG_CTRL_REG register + * hp_system_reg read/write control register + */ +#define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) +/** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_SYSTEM_REG (BIT(0)) +#define TEE_READ_TEE_HP_SYSTEM_REG_M (TEE_READ_TEE_HP_SYSTEM_REG_V << TEE_READ_TEE_HP_SYSTEM_REG_S) +#define TEE_READ_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_TEE_HP_SYSTEM_REG_S 0 +/** TEE_READ_REE0_HP_SYSTEM_REG : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_SYSTEM_REG (BIT(1)) +#define TEE_READ_REE0_HP_SYSTEM_REG_M (TEE_READ_REE0_HP_SYSTEM_REG_V << TEE_READ_REE0_HP_SYSTEM_REG_S) +#define TEE_READ_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE0_HP_SYSTEM_REG_S 1 +/** TEE_READ_REE1_HP_SYSTEM_REG : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_SYSTEM_REG (BIT(2)) +#define TEE_READ_REE1_HP_SYSTEM_REG_M (TEE_READ_REE1_HP_SYSTEM_REG_V << TEE_READ_REE1_HP_SYSTEM_REG_S) +#define TEE_READ_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE1_HP_SYSTEM_REG_S 2 +/** TEE_READ_REE2_HP_SYSTEM_REG : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_SYSTEM_REG (BIT(3)) +#define TEE_READ_REE2_HP_SYSTEM_REG_M (TEE_READ_REE2_HP_SYSTEM_REG_V << TEE_READ_REE2_HP_SYSTEM_REG_S) +#define TEE_READ_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE2_HP_SYSTEM_REG_S 3 +/** TEE_WRITE_TEE_HP_SYSTEM_REG : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_SYSTEM_REG (BIT(4)) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_M (TEE_WRITE_TEE_HP_SYSTEM_REG_V << TEE_WRITE_TEE_HP_SYSTEM_REG_S) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_TEE_HP_SYSTEM_REG_S 4 +/** TEE_WRITE_REE0_HP_SYSTEM_REG : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_SYSTEM_REG (BIT(5)) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_M (TEE_WRITE_REE0_HP_SYSTEM_REG_V << TEE_WRITE_REE0_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE0_HP_SYSTEM_REG_S 5 +/** TEE_WRITE_REE1_HP_SYSTEM_REG : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_SYSTEM_REG (BIT(6)) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_M (TEE_WRITE_REE1_HP_SYSTEM_REG_V << TEE_WRITE_REE1_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE1_HP_SYSTEM_REG_S 6 +/** TEE_WRITE_REE2_HP_SYSTEM_REG : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_SYSTEM_REG (BIT(7)) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_M (TEE_WRITE_REE2_HP_SYSTEM_REG_V << TEE_WRITE_REE2_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 + +/** TEE_PCR_REG_CTRL_REG register + * pcr_reg read/write control register + */ +#define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) +/** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCR_REG (BIT(0)) +#define TEE_READ_TEE_PCR_REG_M (TEE_READ_TEE_PCR_REG_V << TEE_READ_TEE_PCR_REG_S) +#define TEE_READ_TEE_PCR_REG_V 0x00000001U +#define TEE_READ_TEE_PCR_REG_S 0 +/** TEE_READ_REE0_PCR_REG : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCR_REG (BIT(1)) +#define TEE_READ_REE0_PCR_REG_M (TEE_READ_REE0_PCR_REG_V << TEE_READ_REE0_PCR_REG_S) +#define TEE_READ_REE0_PCR_REG_V 0x00000001U +#define TEE_READ_REE0_PCR_REG_S 1 +/** TEE_READ_REE1_PCR_REG : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCR_REG (BIT(2)) +#define TEE_READ_REE1_PCR_REG_M (TEE_READ_REE1_PCR_REG_V << TEE_READ_REE1_PCR_REG_S) +#define TEE_READ_REE1_PCR_REG_V 0x00000001U +#define TEE_READ_REE1_PCR_REG_S 2 +/** TEE_READ_REE2_PCR_REG : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCR_REG (BIT(3)) +#define TEE_READ_REE2_PCR_REG_M (TEE_READ_REE2_PCR_REG_V << TEE_READ_REE2_PCR_REG_S) +#define TEE_READ_REE2_PCR_REG_V 0x00000001U +#define TEE_READ_REE2_PCR_REG_S 3 +/** TEE_WRITE_TEE_PCR_REG : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCR_REG (BIT(4)) +#define TEE_WRITE_TEE_PCR_REG_M (TEE_WRITE_TEE_PCR_REG_V << TEE_WRITE_TEE_PCR_REG_S) +#define TEE_WRITE_TEE_PCR_REG_V 0x00000001U +#define TEE_WRITE_TEE_PCR_REG_S 4 +/** TEE_WRITE_REE0_PCR_REG : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCR_REG (BIT(5)) +#define TEE_WRITE_REE0_PCR_REG_M (TEE_WRITE_REE0_PCR_REG_V << TEE_WRITE_REE0_PCR_REG_S) +#define TEE_WRITE_REE0_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE0_PCR_REG_S 5 +/** TEE_WRITE_REE1_PCR_REG : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCR_REG (BIT(6)) +#define TEE_WRITE_REE1_PCR_REG_M (TEE_WRITE_REE1_PCR_REG_V << TEE_WRITE_REE1_PCR_REG_S) +#define TEE_WRITE_REE1_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE1_PCR_REG_S 6 +/** TEE_WRITE_REE2_PCR_REG : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCR_REG (BIT(7)) +#define TEE_WRITE_REE2_PCR_REG_M (TEE_WRITE_REE2_PCR_REG_V << TEE_WRITE_REE2_PCR_REG_S) +#define TEE_WRITE_REE2_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE2_PCR_REG_S 7 + +/** TEE_MSPI_CTRL_REG register + * mspi read/write control register + */ +#define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) +/** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MSPI (BIT(0)) +#define TEE_READ_TEE_MSPI_M (TEE_READ_TEE_MSPI_V << TEE_READ_TEE_MSPI_S) +#define TEE_READ_TEE_MSPI_V 0x00000001U +#define TEE_READ_TEE_MSPI_S 0 +/** TEE_READ_REE0_MSPI : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MSPI (BIT(1)) +#define TEE_READ_REE0_MSPI_M (TEE_READ_REE0_MSPI_V << TEE_READ_REE0_MSPI_S) +#define TEE_READ_REE0_MSPI_V 0x00000001U +#define TEE_READ_REE0_MSPI_S 1 +/** TEE_READ_REE1_MSPI : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MSPI (BIT(2)) +#define TEE_READ_REE1_MSPI_M (TEE_READ_REE1_MSPI_V << TEE_READ_REE1_MSPI_S) +#define TEE_READ_REE1_MSPI_V 0x00000001U +#define TEE_READ_REE1_MSPI_S 2 +/** TEE_READ_REE2_MSPI : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MSPI (BIT(3)) +#define TEE_READ_REE2_MSPI_M (TEE_READ_REE2_MSPI_V << TEE_READ_REE2_MSPI_S) +#define TEE_READ_REE2_MSPI_V 0x00000001U +#define TEE_READ_REE2_MSPI_S 3 +/** TEE_WRITE_TEE_MSPI : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MSPI (BIT(4)) +#define TEE_WRITE_TEE_MSPI_M (TEE_WRITE_TEE_MSPI_V << TEE_WRITE_TEE_MSPI_S) +#define TEE_WRITE_TEE_MSPI_V 0x00000001U +#define TEE_WRITE_TEE_MSPI_S 4 +/** TEE_WRITE_REE0_MSPI : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MSPI (BIT(5)) +#define TEE_WRITE_REE0_MSPI_M (TEE_WRITE_REE0_MSPI_V << TEE_WRITE_REE0_MSPI_S) +#define TEE_WRITE_REE0_MSPI_V 0x00000001U +#define TEE_WRITE_REE0_MSPI_S 5 +/** TEE_WRITE_REE1_MSPI : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MSPI (BIT(6)) +#define TEE_WRITE_REE1_MSPI_M (TEE_WRITE_REE1_MSPI_V << TEE_WRITE_REE1_MSPI_S) +#define TEE_WRITE_REE1_MSPI_V 0x00000001U +#define TEE_WRITE_REE1_MSPI_S 6 +/** TEE_WRITE_REE2_MSPI : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MSPI (BIT(7)) +#define TEE_WRITE_REE2_MSPI_M (TEE_WRITE_REE2_MSPI_V << TEE_WRITE_REE2_MSPI_S) +#define TEE_WRITE_REE2_MSPI_V 0x00000001U +#define TEE_WRITE_REE2_MSPI_S 7 + +/** TEE_HP_APM_CTRL_REG register + * hp_apm read/write control register + */ +#define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) +/** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_APM (BIT(0)) +#define TEE_READ_TEE_HP_APM_M (TEE_READ_TEE_HP_APM_V << TEE_READ_TEE_HP_APM_S) +#define TEE_READ_TEE_HP_APM_V 0x00000001U +#define TEE_READ_TEE_HP_APM_S 0 +/** TEE_READ_REE0_HP_APM : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_APM (BIT(1)) +#define TEE_READ_REE0_HP_APM_M (TEE_READ_REE0_HP_APM_V << TEE_READ_REE0_HP_APM_S) +#define TEE_READ_REE0_HP_APM_V 0x00000001U +#define TEE_READ_REE0_HP_APM_S 1 +/** TEE_READ_REE1_HP_APM : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_APM (BIT(2)) +#define TEE_READ_REE1_HP_APM_M (TEE_READ_REE1_HP_APM_V << TEE_READ_REE1_HP_APM_S) +#define TEE_READ_REE1_HP_APM_V 0x00000001U +#define TEE_READ_REE1_HP_APM_S 2 +/** TEE_READ_REE2_HP_APM : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_APM (BIT(3)) +#define TEE_READ_REE2_HP_APM_M (TEE_READ_REE2_HP_APM_V << TEE_READ_REE2_HP_APM_S) +#define TEE_READ_REE2_HP_APM_V 0x00000001U +#define TEE_READ_REE2_HP_APM_S 3 +/** TEE_WRITE_TEE_HP_APM : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_APM (BIT(4)) +#define TEE_WRITE_TEE_HP_APM_M (TEE_WRITE_TEE_HP_APM_V << TEE_WRITE_TEE_HP_APM_S) +#define TEE_WRITE_TEE_HP_APM_V 0x00000001U +#define TEE_WRITE_TEE_HP_APM_S 4 +/** TEE_WRITE_REE0_HP_APM : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_APM (BIT(5)) +#define TEE_WRITE_REE0_HP_APM_M (TEE_WRITE_REE0_HP_APM_V << TEE_WRITE_REE0_HP_APM_S) +#define TEE_WRITE_REE0_HP_APM_V 0x00000001U +#define TEE_WRITE_REE0_HP_APM_S 5 +/** TEE_WRITE_REE1_HP_APM : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_APM (BIT(6)) +#define TEE_WRITE_REE1_HP_APM_M (TEE_WRITE_REE1_HP_APM_V << TEE_WRITE_REE1_HP_APM_S) +#define TEE_WRITE_REE1_HP_APM_V 0x00000001U +#define TEE_WRITE_REE1_HP_APM_S 6 +/** TEE_WRITE_REE2_HP_APM : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_APM (BIT(7)) +#define TEE_WRITE_REE2_HP_APM_M (TEE_WRITE_REE2_HP_APM_V << TEE_WRITE_REE2_HP_APM_S) +#define TEE_WRITE_REE2_HP_APM_V 0x00000001U +#define TEE_WRITE_REE2_HP_APM_S 7 + +/** TEE_CPU_APM_CTRL_REG register + * cpu_apm read/write control register + */ +#define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) +/** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_APM (BIT(0)) +#define TEE_READ_TEE_CPU_APM_M (TEE_READ_TEE_CPU_APM_V << TEE_READ_TEE_CPU_APM_S) +#define TEE_READ_TEE_CPU_APM_V 0x00000001U +#define TEE_READ_TEE_CPU_APM_S 0 +/** TEE_READ_REE0_CPU_APM : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_APM (BIT(1)) +#define TEE_READ_REE0_CPU_APM_M (TEE_READ_REE0_CPU_APM_V << TEE_READ_REE0_CPU_APM_S) +#define TEE_READ_REE0_CPU_APM_V 0x00000001U +#define TEE_READ_REE0_CPU_APM_S 1 +/** TEE_READ_REE1_CPU_APM : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_APM (BIT(2)) +#define TEE_READ_REE1_CPU_APM_M (TEE_READ_REE1_CPU_APM_V << TEE_READ_REE1_CPU_APM_S) +#define TEE_READ_REE1_CPU_APM_V 0x00000001U +#define TEE_READ_REE1_CPU_APM_S 2 +/** TEE_READ_REE2_CPU_APM : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_APM (BIT(3)) +#define TEE_READ_REE2_CPU_APM_M (TEE_READ_REE2_CPU_APM_V << TEE_READ_REE2_CPU_APM_S) +#define TEE_READ_REE2_CPU_APM_V 0x00000001U +#define TEE_READ_REE2_CPU_APM_S 3 +/** TEE_WRITE_TEE_CPU_APM : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_APM (BIT(4)) +#define TEE_WRITE_TEE_CPU_APM_M (TEE_WRITE_TEE_CPU_APM_V << TEE_WRITE_TEE_CPU_APM_S) +#define TEE_WRITE_TEE_CPU_APM_V 0x00000001U +#define TEE_WRITE_TEE_CPU_APM_S 4 +/** TEE_WRITE_REE0_CPU_APM : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_APM (BIT(5)) +#define TEE_WRITE_REE0_CPU_APM_M (TEE_WRITE_REE0_CPU_APM_V << TEE_WRITE_REE0_CPU_APM_S) +#define TEE_WRITE_REE0_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE0_CPU_APM_S 5 +/** TEE_WRITE_REE1_CPU_APM : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_APM (BIT(6)) +#define TEE_WRITE_REE1_CPU_APM_M (TEE_WRITE_REE1_CPU_APM_V << TEE_WRITE_REE1_CPU_APM_S) +#define TEE_WRITE_REE1_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE1_CPU_APM_S 6 +/** TEE_WRITE_REE2_CPU_APM : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_APM (BIT(7)) +#define TEE_WRITE_REE2_CPU_APM_M (TEE_WRITE_REE2_CPU_APM_V << TEE_WRITE_REE2_CPU_APM_S) +#define TEE_WRITE_REE2_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE2_CPU_APM_S 7 + +/** TEE_TEE_CTRL_REG register + * tee read/write control register + */ +#define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118) +/** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TEE (BIT(0)) +#define TEE_READ_TEE_TEE_M (TEE_READ_TEE_TEE_V << TEE_READ_TEE_TEE_S) +#define TEE_READ_TEE_TEE_V 0x00000001U +#define TEE_READ_TEE_TEE_S 0 +/** TEE_READ_REE0_TEE : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TEE (BIT(1)) +#define TEE_READ_REE0_TEE_M (TEE_READ_REE0_TEE_V << TEE_READ_REE0_TEE_S) +#define TEE_READ_REE0_TEE_V 0x00000001U +#define TEE_READ_REE0_TEE_S 1 +/** TEE_READ_REE1_TEE : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TEE (BIT(2)) +#define TEE_READ_REE1_TEE_M (TEE_READ_REE1_TEE_V << TEE_READ_REE1_TEE_S) +#define TEE_READ_REE1_TEE_V 0x00000001U +#define TEE_READ_REE1_TEE_S 2 +/** TEE_READ_REE2_TEE : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TEE (BIT(3)) +#define TEE_READ_REE2_TEE_M (TEE_READ_REE2_TEE_V << TEE_READ_REE2_TEE_S) +#define TEE_READ_REE2_TEE_V 0x00000001U +#define TEE_READ_REE2_TEE_S 3 +/** TEE_WRITE_TEE_TEE : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TEE (BIT(4)) +#define TEE_WRITE_TEE_TEE_M (TEE_WRITE_TEE_TEE_V << TEE_WRITE_TEE_TEE_S) +#define TEE_WRITE_TEE_TEE_V 0x00000001U +#define TEE_WRITE_TEE_TEE_S 4 +/** TEE_WRITE_REE0_TEE : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TEE (BIT(5)) +#define TEE_WRITE_REE0_TEE_M (TEE_WRITE_REE0_TEE_V << TEE_WRITE_REE0_TEE_S) +#define TEE_WRITE_REE0_TEE_V 0x00000001U +#define TEE_WRITE_REE0_TEE_S 5 +/** TEE_WRITE_REE1_TEE : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TEE (BIT(6)) +#define TEE_WRITE_REE1_TEE_M (TEE_WRITE_REE1_TEE_V << TEE_WRITE_REE1_TEE_S) +#define TEE_WRITE_REE1_TEE_V 0x00000001U +#define TEE_WRITE_REE1_TEE_S 6 +/** TEE_WRITE_REE2_TEE : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TEE (BIT(7)) +#define TEE_WRITE_REE2_TEE_M (TEE_WRITE_REE2_TEE_V << TEE_WRITE_REE2_TEE_S) +#define TEE_WRITE_REE2_TEE_V 0x00000001U +#define TEE_WRITE_REE2_TEE_S 7 + +/** TEE_KM_CTRL_REG register + * crypt read/write control register + */ +#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x11c) +/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_KM (BIT(0)) +#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) +#define TEE_READ_TEE_KM_V 0x00000001U +#define TEE_READ_TEE_KM_S 0 +/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_KM (BIT(1)) +#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) +#define TEE_READ_REE0_KM_V 0x00000001U +#define TEE_READ_REE0_KM_S 1 +/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_KM (BIT(2)) +#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) +#define TEE_READ_REE1_KM_V 0x00000001U +#define TEE_READ_REE1_KM_S 2 +/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_KM (BIT(3)) +#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) +#define TEE_READ_REE2_KM_V 0x00000001U +#define TEE_READ_REE2_KM_S 3 +/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_KM (BIT(4)) +#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) +#define TEE_WRITE_TEE_KM_V 0x00000001U +#define TEE_WRITE_TEE_KM_S 4 +/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_KM (BIT(5)) +#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) +#define TEE_WRITE_REE0_KM_V 0x00000001U +#define TEE_WRITE_REE0_KM_S 5 +/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_KM (BIT(6)) +#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) +#define TEE_WRITE_REE1_KM_V 0x00000001U +#define TEE_WRITE_REE1_KM_S 6 +/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_KM (BIT(7)) +#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) +#define TEE_WRITE_REE2_KM_V 0x00000001U +#define TEE_WRITE_REE2_KM_S 7 + +/** TEE_CRYPT_CTRL_REG register + * crypt read/write control register + */ +#define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x120) +/** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CRYPT (BIT(0)) +#define TEE_READ_TEE_CRYPT_M (TEE_READ_TEE_CRYPT_V << TEE_READ_TEE_CRYPT_S) +#define TEE_READ_TEE_CRYPT_V 0x00000001U +#define TEE_READ_TEE_CRYPT_S 0 +/** TEE_READ_REE0_CRYPT : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CRYPT (BIT(1)) +#define TEE_READ_REE0_CRYPT_M (TEE_READ_REE0_CRYPT_V << TEE_READ_REE0_CRYPT_S) +#define TEE_READ_REE0_CRYPT_V 0x00000001U +#define TEE_READ_REE0_CRYPT_S 1 +/** TEE_READ_REE1_CRYPT : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CRYPT (BIT(2)) +#define TEE_READ_REE1_CRYPT_M (TEE_READ_REE1_CRYPT_V << TEE_READ_REE1_CRYPT_S) +#define TEE_READ_REE1_CRYPT_V 0x00000001U +#define TEE_READ_REE1_CRYPT_S 2 +/** TEE_READ_REE2_CRYPT : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CRYPT (BIT(3)) +#define TEE_READ_REE2_CRYPT_M (TEE_READ_REE2_CRYPT_V << TEE_READ_REE2_CRYPT_S) +#define TEE_READ_REE2_CRYPT_V 0x00000001U +#define TEE_READ_REE2_CRYPT_S 3 +/** TEE_WRITE_TEE_CRYPT : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CRYPT (BIT(4)) +#define TEE_WRITE_TEE_CRYPT_M (TEE_WRITE_TEE_CRYPT_V << TEE_WRITE_TEE_CRYPT_S) +#define TEE_WRITE_TEE_CRYPT_V 0x00000001U +#define TEE_WRITE_TEE_CRYPT_S 4 +/** TEE_WRITE_REE0_CRYPT : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CRYPT (BIT(5)) +#define TEE_WRITE_REE0_CRYPT_M (TEE_WRITE_REE0_CRYPT_V << TEE_WRITE_REE0_CRYPT_S) +#define TEE_WRITE_REE0_CRYPT_V 0x00000001U +#define TEE_WRITE_REE0_CRYPT_S 5 +/** TEE_WRITE_REE1_CRYPT : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CRYPT (BIT(6)) +#define TEE_WRITE_REE1_CRYPT_M (TEE_WRITE_REE1_CRYPT_V << TEE_WRITE_REE1_CRYPT_S) +#define TEE_WRITE_REE1_CRYPT_V 0x00000001U +#define TEE_WRITE_REE1_CRYPT_S 6 +/** TEE_WRITE_REE2_CRYPT : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CRYPT (BIT(7)) +#define TEE_WRITE_REE2_CRYPT_M (TEE_WRITE_REE2_CRYPT_V << TEE_WRITE_REE2_CRYPT_S) +#define TEE_WRITE_REE2_CRYPT_V 0x00000001U +#define TEE_WRITE_REE2_CRYPT_S 7 + +/** TEE_CORE0_TRACE_CTRL_REG register + * core0_trace read/write control register + */ +#define TEE_CORE0_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x124) +/** TEE_READ_TEE_CORE0_TRACE : R/W; bitpos: [0]; default: 1; + * Configures core0_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CORE0_TRACE (BIT(0)) +#define TEE_READ_TEE_CORE0_TRACE_M (TEE_READ_TEE_CORE0_TRACE_V << TEE_READ_TEE_CORE0_TRACE_S) +#define TEE_READ_TEE_CORE0_TRACE_V 0x00000001U +#define TEE_READ_TEE_CORE0_TRACE_S 0 +/** TEE_READ_REE0_CORE0_TRACE : R/W; bitpos: [1]; default: 0; + * Configures core0_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CORE0_TRACE (BIT(1)) +#define TEE_READ_REE0_CORE0_TRACE_M (TEE_READ_REE0_CORE0_TRACE_V << TEE_READ_REE0_CORE0_TRACE_S) +#define TEE_READ_REE0_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE0_CORE0_TRACE_S 1 +/** TEE_READ_REE1_CORE0_TRACE : R/W; bitpos: [2]; default: 0; + * Configures core0_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CORE0_TRACE (BIT(2)) +#define TEE_READ_REE1_CORE0_TRACE_M (TEE_READ_REE1_CORE0_TRACE_V << TEE_READ_REE1_CORE0_TRACE_S) +#define TEE_READ_REE1_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE1_CORE0_TRACE_S 2 +/** TEE_READ_REE2_CORE0_TRACE : R/W; bitpos: [3]; default: 0; + * Configures core0_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CORE0_TRACE (BIT(3)) +#define TEE_READ_REE2_CORE0_TRACE_M (TEE_READ_REE2_CORE0_TRACE_V << TEE_READ_REE2_CORE0_TRACE_S) +#define TEE_READ_REE2_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE2_CORE0_TRACE_S 3 +/** TEE_WRITE_TEE_CORE0_TRACE : R/W; bitpos: [4]; default: 1; + * Configures core0_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CORE0_TRACE (BIT(4)) +#define TEE_WRITE_TEE_CORE0_TRACE_M (TEE_WRITE_TEE_CORE0_TRACE_V << TEE_WRITE_TEE_CORE0_TRACE_S) +#define TEE_WRITE_TEE_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_TEE_CORE0_TRACE_S 4 +/** TEE_WRITE_REE0_CORE0_TRACE : R/W; bitpos: [5]; default: 0; + * Configures core0_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CORE0_TRACE (BIT(5)) +#define TEE_WRITE_REE0_CORE0_TRACE_M (TEE_WRITE_REE0_CORE0_TRACE_V << TEE_WRITE_REE0_CORE0_TRACE_S) +#define TEE_WRITE_REE0_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE0_CORE0_TRACE_S 5 +/** TEE_WRITE_REE1_CORE0_TRACE : R/W; bitpos: [6]; default: 0; + * Configures core0_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CORE0_TRACE (BIT(6)) +#define TEE_WRITE_REE1_CORE0_TRACE_M (TEE_WRITE_REE1_CORE0_TRACE_V << TEE_WRITE_REE1_CORE0_TRACE_S) +#define TEE_WRITE_REE1_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE1_CORE0_TRACE_S 6 +/** TEE_WRITE_REE2_CORE0_TRACE : R/W; bitpos: [7]; default: 0; + * Configures core0_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CORE0_TRACE (BIT(7)) +#define TEE_WRITE_REE2_CORE0_TRACE_M (TEE_WRITE_REE2_CORE0_TRACE_V << TEE_WRITE_REE2_CORE0_TRACE_S) +#define TEE_WRITE_REE2_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE2_CORE0_TRACE_S 7 + +/** TEE_CORE1_TRACE_CTRL_REG register + * core1_trace read/write control register + */ +#define TEE_CORE1_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x128) +/** TEE_READ_TEE_CORE1_TRACE : R/W; bitpos: [0]; default: 1; + * Configures core1_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CORE1_TRACE (BIT(0)) +#define TEE_READ_TEE_CORE1_TRACE_M (TEE_READ_TEE_CORE1_TRACE_V << TEE_READ_TEE_CORE1_TRACE_S) +#define TEE_READ_TEE_CORE1_TRACE_V 0x00000001U +#define TEE_READ_TEE_CORE1_TRACE_S 0 +/** TEE_READ_REE0_CORE1_TRACE : R/W; bitpos: [1]; default: 0; + * Configures core1_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CORE1_TRACE (BIT(1)) +#define TEE_READ_REE0_CORE1_TRACE_M (TEE_READ_REE0_CORE1_TRACE_V << TEE_READ_REE0_CORE1_TRACE_S) +#define TEE_READ_REE0_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE0_CORE1_TRACE_S 1 +/** TEE_READ_REE1_CORE1_TRACE : R/W; bitpos: [2]; default: 0; + * Configures core1_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CORE1_TRACE (BIT(2)) +#define TEE_READ_REE1_CORE1_TRACE_M (TEE_READ_REE1_CORE1_TRACE_V << TEE_READ_REE1_CORE1_TRACE_S) +#define TEE_READ_REE1_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE1_CORE1_TRACE_S 2 +/** TEE_READ_REE2_CORE1_TRACE : R/W; bitpos: [3]; default: 0; + * Configures core1_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CORE1_TRACE (BIT(3)) +#define TEE_READ_REE2_CORE1_TRACE_M (TEE_READ_REE2_CORE1_TRACE_V << TEE_READ_REE2_CORE1_TRACE_S) +#define TEE_READ_REE2_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE2_CORE1_TRACE_S 3 +/** TEE_WRITE_TEE_CORE1_TRACE : R/W; bitpos: [4]; default: 1; + * Configures core1_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CORE1_TRACE (BIT(4)) +#define TEE_WRITE_TEE_CORE1_TRACE_M (TEE_WRITE_TEE_CORE1_TRACE_V << TEE_WRITE_TEE_CORE1_TRACE_S) +#define TEE_WRITE_TEE_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_TEE_CORE1_TRACE_S 4 +/** TEE_WRITE_REE0_CORE1_TRACE : R/W; bitpos: [5]; default: 0; + * Configures core1_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CORE1_TRACE (BIT(5)) +#define TEE_WRITE_REE0_CORE1_TRACE_M (TEE_WRITE_REE0_CORE1_TRACE_V << TEE_WRITE_REE0_CORE1_TRACE_S) +#define TEE_WRITE_REE0_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE0_CORE1_TRACE_S 5 +/** TEE_WRITE_REE1_CORE1_TRACE : R/W; bitpos: [6]; default: 0; + * Configures core1_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CORE1_TRACE (BIT(6)) +#define TEE_WRITE_REE1_CORE1_TRACE_M (TEE_WRITE_REE1_CORE1_TRACE_V << TEE_WRITE_REE1_CORE1_TRACE_S) +#define TEE_WRITE_REE1_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE1_CORE1_TRACE_S 6 +/** TEE_WRITE_REE2_CORE1_TRACE : R/W; bitpos: [7]; default: 0; + * Configures core1_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CORE1_TRACE (BIT(7)) +#define TEE_WRITE_REE2_CORE1_TRACE_M (TEE_WRITE_REE2_CORE1_TRACE_V << TEE_WRITE_REE2_CORE1_TRACE_S) +#define TEE_WRITE_REE2_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE2_CORE1_TRACE_S 7 + +/** TEE_CPU_BUS_MONITOR_CTRL_REG register + * cpu_bus_monitor read/write control register + */ +#define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x12c) +/** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_BUS_MONITOR (BIT(0)) +#define TEE_READ_TEE_CPU_BUS_MONITOR_M (TEE_READ_TEE_CPU_BUS_MONITOR_V << TEE_READ_TEE_CPU_BUS_MONITOR_S) +#define TEE_READ_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_CPU_BUS_MONITOR_S 0 +/** TEE_READ_REE0_CPU_BUS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_BUS_MONITOR (BIT(1)) +#define TEE_READ_REE0_CPU_BUS_MONITOR_M (TEE_READ_REE0_CPU_BUS_MONITOR_V << TEE_READ_REE0_CPU_BUS_MONITOR_S) +#define TEE_READ_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_CPU_BUS_MONITOR_S 1 +/** TEE_READ_REE1_CPU_BUS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_BUS_MONITOR (BIT(2)) +#define TEE_READ_REE1_CPU_BUS_MONITOR_M (TEE_READ_REE1_CPU_BUS_MONITOR_V << TEE_READ_REE1_CPU_BUS_MONITOR_S) +#define TEE_READ_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_CPU_BUS_MONITOR_S 2 +/** TEE_READ_REE2_CPU_BUS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_BUS_MONITOR (BIT(3)) +#define TEE_READ_REE2_CPU_BUS_MONITOR_M (TEE_READ_REE2_CPU_BUS_MONITOR_V << TEE_READ_REE2_CPU_BUS_MONITOR_S) +#define TEE_READ_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_CPU_BUS_MONITOR_S 3 +/** TEE_WRITE_TEE_CPU_BUS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_BUS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_M (TEE_WRITE_TEE_CPU_BUS_MONITOR_V << TEE_WRITE_TEE_CPU_BUS_MONITOR_S) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_S 4 +/** TEE_WRITE_REE0_CPU_BUS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_BUS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_M (TEE_WRITE_REE0_CPU_BUS_MONITOR_V << TEE_WRITE_REE0_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_S 5 +/** TEE_WRITE_REE1_CPU_BUS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_BUS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_M (TEE_WRITE_REE1_CPU_BUS_MONITOR_V << TEE_WRITE_REE1_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_S 6 +/** TEE_WRITE_REE2_CPU_BUS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_BUS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_M (TEE_WRITE_REE2_CPU_BUS_MONITOR_V << TEE_WRITE_REE2_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 + +/** TEE_INTPRI_REG_CTRL_REG register + * intpri_reg read/write control register + */ +#define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x130) +/** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTPRI_REG (BIT(0)) +#define TEE_READ_TEE_INTPRI_REG_M (TEE_READ_TEE_INTPRI_REG_V << TEE_READ_TEE_INTPRI_REG_S) +#define TEE_READ_TEE_INTPRI_REG_V 0x00000001U +#define TEE_READ_TEE_INTPRI_REG_S 0 +/** TEE_READ_REE0_INTPRI_REG : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTPRI_REG (BIT(1)) +#define TEE_READ_REE0_INTPRI_REG_M (TEE_READ_REE0_INTPRI_REG_V << TEE_READ_REE0_INTPRI_REG_S) +#define TEE_READ_REE0_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE0_INTPRI_REG_S 1 +/** TEE_READ_REE1_INTPRI_REG : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTPRI_REG (BIT(2)) +#define TEE_READ_REE1_INTPRI_REG_M (TEE_READ_REE1_INTPRI_REG_V << TEE_READ_REE1_INTPRI_REG_S) +#define TEE_READ_REE1_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE1_INTPRI_REG_S 2 +/** TEE_READ_REE2_INTPRI_REG : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTPRI_REG (BIT(3)) +#define TEE_READ_REE2_INTPRI_REG_M (TEE_READ_REE2_INTPRI_REG_V << TEE_READ_REE2_INTPRI_REG_S) +#define TEE_READ_REE2_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE2_INTPRI_REG_S 3 +/** TEE_WRITE_TEE_INTPRI_REG : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTPRI_REG (BIT(4)) +#define TEE_WRITE_TEE_INTPRI_REG_M (TEE_WRITE_TEE_INTPRI_REG_V << TEE_WRITE_TEE_INTPRI_REG_S) +#define TEE_WRITE_TEE_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_TEE_INTPRI_REG_S 4 +/** TEE_WRITE_REE0_INTPRI_REG : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTPRI_REG (BIT(5)) +#define TEE_WRITE_REE0_INTPRI_REG_M (TEE_WRITE_REE0_INTPRI_REG_V << TEE_WRITE_REE0_INTPRI_REG_S) +#define TEE_WRITE_REE0_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE0_INTPRI_REG_S 5 +/** TEE_WRITE_REE1_INTPRI_REG : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTPRI_REG (BIT(6)) +#define TEE_WRITE_REE1_INTPRI_REG_M (TEE_WRITE_REE1_INTPRI_REG_V << TEE_WRITE_REE1_INTPRI_REG_S) +#define TEE_WRITE_REE1_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE1_INTPRI_REG_S 6 +/** TEE_WRITE_REE2_INTPRI_REG : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTPRI_REG (BIT(7)) +#define TEE_WRITE_REE2_INTPRI_REG_M (TEE_WRITE_REE2_INTPRI_REG_V << TEE_WRITE_REE2_INTPRI_REG_S) +#define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE2_INTPRI_REG_S 7 + +/** TEE_CACHE_CFG_CTRL_REG register + * cache_cfg read/write control register + */ +#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x134) +/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CACHE_CFG (BIT(0)) +#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) +#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U +#define TEE_READ_TEE_CACHE_CFG_S 0 +/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CACHE_CFG (BIT(1)) +#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) +#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE0_CACHE_CFG_S 1 +/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CACHE_CFG (BIT(2)) +#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) +#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE1_CACHE_CFG_S 2 +/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CACHE_CFG (BIT(3)) +#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) +#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE2_CACHE_CFG_S 3 +/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) +#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) +#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_TEE_CACHE_CFG_S 4 +/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) +#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) +#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE0_CACHE_CFG_S 5 +/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) +#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) +#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE1_CACHE_CFG_S 6 +/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) +#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) +#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE2_CACHE_CFG_S 7 + +/** TEE_MODEM_CTRL_REG register + * modem read/write control register + */ +#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MODEM (BIT(0)) +#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) +#define TEE_READ_TEE_MODEM_V 0x00000001U +#define TEE_READ_TEE_MODEM_S 0 +/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MODEM (BIT(1)) +#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) +#define TEE_READ_REE0_MODEM_V 0x00000001U +#define TEE_READ_REE0_MODEM_S 1 +/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MODEM (BIT(2)) +#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) +#define TEE_READ_REE1_MODEM_V 0x00000001U +#define TEE_READ_REE1_MODEM_S 2 +/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MODEM (BIT(3)) +#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) +#define TEE_READ_REE2_MODEM_V 0x00000001U +#define TEE_READ_REE2_MODEM_S 3 +/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MODEM (BIT(4)) +#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) +#define TEE_WRITE_TEE_MODEM_V 0x00000001U +#define TEE_WRITE_TEE_MODEM_S 4 +/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MODEM (BIT(5)) +#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) +#define TEE_WRITE_REE0_MODEM_V 0x00000001U +#define TEE_WRITE_REE0_MODEM_S 5 +/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MODEM (BIT(6)) +#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) +#define TEE_WRITE_REE1_MODEM_V 0x00000001U +#define TEE_WRITE_REE1_MODEM_S 6 +/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MODEM (BIT(7)) +#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) +#define TEE_WRITE_REE2_MODEM_V 0x00000001U +#define TEE_WRITE_REE2_MODEM_S 7 + +/** TEE_ZERO_DET_CTRL_REG register + * zero_det read/write control register + */ +#define TEE_ZERO_DET_CTRL_REG (DR_REG_TEE_BASE + 0x13c) +/** TEE_READ_TEE_ZERO_DET : R/W; bitpos: [0]; default: 1; + * Configures zero_det registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_ZERO_DET (BIT(0)) +#define TEE_READ_TEE_ZERO_DET_M (TEE_READ_TEE_ZERO_DET_V << TEE_READ_TEE_ZERO_DET_S) +#define TEE_READ_TEE_ZERO_DET_V 0x00000001U +#define TEE_READ_TEE_ZERO_DET_S 0 +/** TEE_READ_REE0_ZERO_DET : R/W; bitpos: [1]; default: 0; + * Configures zero_det registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_ZERO_DET (BIT(1)) +#define TEE_READ_REE0_ZERO_DET_M (TEE_READ_REE0_ZERO_DET_V << TEE_READ_REE0_ZERO_DET_S) +#define TEE_READ_REE0_ZERO_DET_V 0x00000001U +#define TEE_READ_REE0_ZERO_DET_S 1 +/** TEE_READ_REE1_ZERO_DET : R/W; bitpos: [2]; default: 0; + * Configures zero_det registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_ZERO_DET (BIT(2)) +#define TEE_READ_REE1_ZERO_DET_M (TEE_READ_REE1_ZERO_DET_V << TEE_READ_REE1_ZERO_DET_S) +#define TEE_READ_REE1_ZERO_DET_V 0x00000001U +#define TEE_READ_REE1_ZERO_DET_S 2 +/** TEE_READ_REE2_ZERO_DET : R/W; bitpos: [3]; default: 0; + * Configures zero_det registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_ZERO_DET (BIT(3)) +#define TEE_READ_REE2_ZERO_DET_M (TEE_READ_REE2_ZERO_DET_V << TEE_READ_REE2_ZERO_DET_S) +#define TEE_READ_REE2_ZERO_DET_V 0x00000001U +#define TEE_READ_REE2_ZERO_DET_S 3 +/** TEE_WRITE_TEE_ZERO_DET : R/W; bitpos: [4]; default: 1; + * Configures zero_det registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_ZERO_DET (BIT(4)) +#define TEE_WRITE_TEE_ZERO_DET_M (TEE_WRITE_TEE_ZERO_DET_V << TEE_WRITE_TEE_ZERO_DET_S) +#define TEE_WRITE_TEE_ZERO_DET_V 0x00000001U +#define TEE_WRITE_TEE_ZERO_DET_S 4 +/** TEE_WRITE_REE0_ZERO_DET : R/W; bitpos: [5]; default: 0; + * Configures zero_det registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_ZERO_DET (BIT(5)) +#define TEE_WRITE_REE0_ZERO_DET_M (TEE_WRITE_REE0_ZERO_DET_V << TEE_WRITE_REE0_ZERO_DET_S) +#define TEE_WRITE_REE0_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE0_ZERO_DET_S 5 +/** TEE_WRITE_REE1_ZERO_DET : R/W; bitpos: [6]; default: 0; + * Configures zero_det registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_ZERO_DET (BIT(6)) +#define TEE_WRITE_REE1_ZERO_DET_M (TEE_WRITE_REE1_ZERO_DET_V << TEE_WRITE_REE1_ZERO_DET_S) +#define TEE_WRITE_REE1_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE1_ZERO_DET_S 6 +/** TEE_WRITE_REE2_ZERO_DET : R/W; bitpos: [7]; default: 0; + * Configures zero_det registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_ZERO_DET (BIT(7)) +#define TEE_WRITE_REE2_ZERO_DET_M (TEE_WRITE_REE2_ZERO_DET_V << TEE_WRITE_REE2_ZERO_DET_S) +#define TEE_WRITE_REE2_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE2_ZERO_DET_S 7 + +/** TEE_BUS_ERR_CONF_REG register + * Clock gating register + */ +#define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) +/** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ +#define TEE_BUS_ERR_RESP_EN (BIT(0)) +#define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) +#define TEE_BUS_ERR_RESP_EN_V 0x00000001U +#define TEE_BUS_ERR_RESP_EN_S 0 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version control register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE : R/W; bitpos: [27:0]; default: 37818480; + * Version control register + */ +#define TEE_DATE 0x0FFFFFFFU +#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) +#define TEE_DATE_V 0x0FFFFFFFU +#define TEE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/tee_struct.h b/components/soc/esp32h4/register/soc/tee_struct.h new file mode 100644 index 0000000000..77f79af053 --- /dev/null +++ b/components/soc/esp32h4/register/soc/tee_struct.h @@ -0,0 +1,2940 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of mn_mode_ctrl register + * TEE mode control register + */ +typedef union { + struct { + /** mn_mode : R/W; bitpos: [1:0]; default: 0; + * Configures Mn security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ + uint32_t mn_mode:2; + /** mn_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t mn_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_mn_mode_ctrl_reg_t; + + +/** Group: read write control register */ +/** Type of gpspi0_ctrl register + * gpspi0 read/write control register + */ +typedef union { + struct { + /** read_tee_gpspi0 : R/W; bitpos: [0]; default: 1; + * Configures gpspi0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gpspi0:1; + /** read_ree0_gpspi0 : R/W; bitpos: [1]; default: 0; + * Configures gpspi0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gpspi0:1; + /** read_ree1_gpspi0 : R/W; bitpos: [2]; default: 0; + * Configures gpspi0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gpspi0:1; + /** read_ree2_gpspi0 : R/W; bitpos: [3]; default: 0; + * Configures gpspi0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gpspi0:1; + /** write_tee_gpspi0 : R/W; bitpos: [4]; default: 1; + * Configures gpspi0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gpspi0:1; + /** write_ree0_gpspi0 : R/W; bitpos: [5]; default: 0; + * Configures gpspi0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gpspi0:1; + /** write_ree1_gpspi0 : R/W; bitpos: [6]; default: 0; + * Configures gpspi0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gpspi0:1; + /** write_ree2_gpspi0 : R/W; bitpos: [7]; default: 0; + * Configures gpspi0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gpspi0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gpspi0_ctrl_reg_t; + +/** Type of gpspi1_ctrl register + * gpspi1 read/write control register + */ +typedef union { + struct { + /** read_tee_gpspi1 : R/W; bitpos: [0]; default: 1; + * Configures gpspi1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gpspi1:1; + /** read_ree0_gpspi1 : R/W; bitpos: [1]; default: 0; + * Configures gpspi1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gpspi1:1; + /** read_ree1_gpspi1 : R/W; bitpos: [2]; default: 0; + * Configures gpspi1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gpspi1:1; + /** read_ree2_gpspi1 : R/W; bitpos: [3]; default: 0; + * Configures gpspi1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gpspi1:1; + /** write_tee_gpspi1 : R/W; bitpos: [4]; default: 1; + * Configures gpspi1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gpspi1:1; + /** write_ree0_gpspi1 : R/W; bitpos: [5]; default: 0; + * Configures gpspi1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gpspi1:1; + /** write_ree1_gpspi1 : R/W; bitpos: [6]; default: 0; + * Configures gpspi1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gpspi1:1; + /** write_ree2_gpspi1 : R/W; bitpos: [7]; default: 0; + * Configures gpspi1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gpspi1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gpspi1_ctrl_reg_t; + +/** Type of uart0_ctrl register + * uart0 read/write control register + */ +typedef union { + struct { + /** read_tee_uart0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart0:1; + /** read_ree0_uart0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart0:1; + /** read_ree1_uart0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart0:1; + /** read_ree2_uart0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart0:1; + /** write_tee_uart0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart0:1; + /** write_ree0_uart0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart0:1; + /** write_ree1_uart0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart0:1; + /** write_ree2_uart0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart0_ctrl_reg_t; + +/** Type of uart1_ctrl register + * uart1 read/write control register + */ +typedef union { + struct { + /** read_tee_uart1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart1:1; + /** read_ree0_uart1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart1:1; + /** read_ree1_uart1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart1:1; + /** read_ree2_uart1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart1:1; + /** write_tee_uart1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart1:1; + /** write_ree0_uart1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart1:1; + /** write_ree1_uart1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart1:1; + /** write_ree2_uart1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart1_ctrl_reg_t; + +/** Type of uhci_ctrl register + * uhci read/write control register + */ +typedef union { + struct { + /** read_tee_uhci : R/W; bitpos: [0]; default: 1; + * Configures uhci registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uhci:1; + /** read_ree0_uhci : R/W; bitpos: [1]; default: 0; + * Configures uhci registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uhci:1; + /** read_ree1_uhci : R/W; bitpos: [2]; default: 0; + * Configures uhci registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uhci:1; + /** read_ree2_uhci : R/W; bitpos: [3]; default: 0; + * Configures uhci registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uhci:1; + /** write_tee_uhci : R/W; bitpos: [4]; default: 1; + * Configures uhci registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uhci:1; + /** write_ree0_uhci : R/W; bitpos: [5]; default: 0; + * Configures uhci registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uhci:1; + /** write_ree1_uhci : R/W; bitpos: [6]; default: 0; + * Configures uhci registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uhci:1; + /** write_ree2_uhci : R/W; bitpos: [7]; default: 0; + * Configures uhci registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uhci:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uhci_ctrl_reg_t; + +/** Type of i2c0_ctrl register + * i2c0 read/write control register + */ +typedef union { + struct { + /** read_tee_i2c0 : R/W; bitpos: [0]; default: 1; + * Configures i2c0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c0:1; + /** read_ree0_i2c0 : R/W; bitpos: [1]; default: 0; + * Configures i2c0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c0:1; + /** read_ree1_i2c0 : R/W; bitpos: [2]; default: 0; + * Configures i2c0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c0:1; + /** read_ree2_i2c0 : R/W; bitpos: [3]; default: 0; + * Configures i2c0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c0:1; + /** write_tee_i2c0 : R/W; bitpos: [4]; default: 1; + * Configures i2c0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c0:1; + /** write_ree0_i2c0 : R/W; bitpos: [5]; default: 0; + * Configures i2c0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c0:1; + /** write_ree1_i2c0 : R/W; bitpos: [6]; default: 0; + * Configures i2c0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c0:1; + /** write_ree2_i2c0 : R/W; bitpos: [7]; default: 0; + * Configures i2c0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2c0_ctrl_reg_t; + +/** Type of i2c1_ctrl register + * i2c1 read/write control register + */ +typedef union { + struct { + /** read_tee_i2c1 : R/W; bitpos: [0]; default: 1; + * Configures i2c1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c1:1; + /** read_ree0_i2c1 : R/W; bitpos: [1]; default: 0; + * Configures i2c1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c1:1; + /** read_ree1_i2c1 : R/W; bitpos: [2]; default: 0; + * Configures i2c1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c1:1; + /** read_ree2_i2c1 : R/W; bitpos: [3]; default: 0; + * Configures i2c1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c1:1; + /** write_tee_i2c1 : R/W; bitpos: [4]; default: 1; + * Configures i2c1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c1:1; + /** write_ree0_i2c1 : R/W; bitpos: [5]; default: 0; + * Configures i2c1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c1:1; + /** write_ree1_i2c1 : R/W; bitpos: [6]; default: 0; + * Configures i2c1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c1:1; + /** write_ree2_i2c1 : R/W; bitpos: [7]; default: 0; + * Configures i2c1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2c1_ctrl_reg_t; + +/** Type of i2s_ctrl register + * i2s read/write control register + */ +typedef union { + struct { + /** read_tee_i2s : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2s:1; + /** read_ree0_i2s : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2s:1; + /** read_ree1_i2s : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2s:1; + /** read_ree2_i2s : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2s:1; + /** write_tee_i2s : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2s:1; + /** write_ree0_i2s : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2s:1; + /** write_ree1_i2s : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2s:1; + /** write_ree2_i2s : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2s:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2s_ctrl_reg_t; + +/** Type of parl_io_ctrl register + * parl_io read/write control register + */ +typedef union { + struct { + /** read_tee_parl_io : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_parl_io:1; + /** read_ree0_parl_io : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_parl_io:1; + /** read_ree1_parl_io : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_parl_io:1; + /** read_ree2_parl_io : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_parl_io:1; + /** write_tee_parl_io : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_parl_io:1; + /** write_ree0_parl_io : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_parl_io:1; + /** write_ree1_parl_io : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_parl_io:1; + /** write_ree2_parl_io : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_parl_io:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_parl_io_ctrl_reg_t; + +/** Type of pwm0_ctrl register + * pwm0 read/write control register + */ +typedef union { + struct { + /** read_tee_pwm0 : R/W; bitpos: [0]; default: 1; + * Configures pwm0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pwm0:1; + /** read_ree0_pwm0 : R/W; bitpos: [1]; default: 0; + * Configures pwm0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pwm0:1; + /** read_ree1_pwm0 : R/W; bitpos: [2]; default: 0; + * Configures pwm0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pwm0:1; + /** read_ree2_pwm0 : R/W; bitpos: [3]; default: 0; + * Configures pwm0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pwm0:1; + /** write_tee_pwm0 : R/W; bitpos: [4]; default: 1; + * Configures pwm0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pwm0:1; + /** write_ree0_pwm0 : R/W; bitpos: [5]; default: 0; + * Configures pwm0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pwm0:1; + /** write_ree1_pwm0 : R/W; bitpos: [6]; default: 0; + * Configures pwm0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pwm0:1; + /** write_ree2_pwm0 : R/W; bitpos: [7]; default: 0; + * Configures pwm0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pwm0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pwm0_ctrl_reg_t; + +/** Type of pwm1_ctrl register + * pwm1 read/write control register + */ +typedef union { + struct { + /** read_tee_pwm1 : R/W; bitpos: [0]; default: 1; + * Configures pwm1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pwm1:1; + /** read_ree0_pwm1 : R/W; bitpos: [1]; default: 0; + * Configures pwm1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pwm1:1; + /** read_ree1_pwm1 : R/W; bitpos: [2]; default: 0; + * Configures pwm1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pwm1:1; + /** read_ree2_pwm1 : R/W; bitpos: [3]; default: 0; + * Configures pwm1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pwm1:1; + /** write_tee_pwm1 : R/W; bitpos: [4]; default: 1; + * Configures pwm1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pwm1:1; + /** write_ree0_pwm1 : R/W; bitpos: [5]; default: 0; + * Configures pwm1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pwm1:1; + /** write_ree1_pwm1 : R/W; bitpos: [6]; default: 0; + * Configures pwm1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pwm1:1; + /** write_ree2_pwm1 : R/W; bitpos: [7]; default: 0; + * Configures pwm1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pwm1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pwm1_ctrl_reg_t; + +/** Type of ledc_ctrl register + * ledc read/write control register + */ +typedef union { + struct { + /** read_tee_ledc : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_ledc:1; + /** read_ree0_ledc : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_ledc:1; + /** read_ree1_ledc : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_ledc:1; + /** read_ree2_ledc : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_ledc:1; + /** write_tee_ledc : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_ledc:1; + /** write_ree0_ledc : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_ledc:1; + /** write_ree1_ledc : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_ledc:1; + /** write_ree2_ledc : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_ledc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_ledc_ctrl_reg_t; + +/** Type of can_ctrl register + * can read/write control register + */ +typedef union { + struct { + /** read_tee_can : R/W; bitpos: [0]; default: 1; + * Configures can registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_can:1; + /** read_ree0_can : R/W; bitpos: [1]; default: 0; + * Configures can registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_can:1; + /** read_ree1_can : R/W; bitpos: [2]; default: 0; + * Configures can registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_can:1; + /** read_ree2_can : R/W; bitpos: [3]; default: 0; + * Configures can registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_can:1; + /** write_tee_can : R/W; bitpos: [4]; default: 1; + * Configures can registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_can:1; + /** write_ree0_can : R/W; bitpos: [5]; default: 0; + * Configures can registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_can:1; + /** write_ree1_can : R/W; bitpos: [6]; default: 0; + * Configures can registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_can:1; + /** write_ree2_can : R/W; bitpos: [7]; default: 0; + * Configures can registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_can:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_can_ctrl_reg_t; + +/** Type of usb_serial_jtag_ctrl register + * usb_serial_jtag read/write control register + */ +typedef union { + struct { + /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1; + * Configures usb_serial_jtag registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_serial_jtag:1; + /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0; + * Configures usb_serial_jtag registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_serial_jtag:1; + /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0; + * Configures usb_serial_jtag registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_serial_jtag:1; + /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0; + * Configures usb_serial_jtag registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_serial_jtag:1; + /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1; + * Configures usb_serial_jtag registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_serial_jtag:1; + /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0; + * Configures usb_serial_jtag registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_serial_jtag:1; + /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0; + * Configures usb_serial_jtag registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_serial_jtag:1; + /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0; + * Configures usb_serial_jtag registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_serial_jtag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_serial_jtag_ctrl_reg_t; + +/** Type of rmt_ctrl register + * rmt read/write control register + */ +typedef union { + struct { + /** read_tee_rmt : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_rmt:1; + /** read_ree0_rmt : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_rmt:1; + /** read_ree1_rmt : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_rmt:1; + /** read_ree2_rmt : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_rmt:1; + /** write_tee_rmt : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_rmt:1; + /** write_ree0_rmt : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_rmt:1; + /** write_ree1_rmt : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_rmt:1; + /** write_ree2_rmt : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_rmt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_rmt_ctrl_reg_t; + +/** Type of gdma_ctrl register + * gdma read/write control register + */ +typedef union { + struct { + /** read_tee_gdma : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gdma:1; + /** read_ree0_gdma : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gdma:1; + /** read_ree1_gdma : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gdma:1; + /** read_ree2_gdma : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gdma:1; + /** write_tee_gdma : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gdma:1; + /** write_ree0_gdma : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gdma:1; + /** write_ree1_gdma : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gdma:1; + /** write_ree2_gdma : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gdma_ctrl_reg_t; + +/** Type of regdma_ctrl register + * regdma read/write control register + */ +typedef union { + struct { + /** read_tee_regdma : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_regdma:1; + /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_regdma:1; + /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_regdma:1; + /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_regdma:1; + /** write_tee_regdma : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_regdma:1; + /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_regdma:1; + /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_regdma:1; + /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_regdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_regdma_ctrl_reg_t; + +/** Type of etm_ctrl register + * etm read/write control register + */ +typedef union { + struct { + /** read_tee_etm : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_etm:1; + /** read_ree0_etm : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_etm:1; + /** read_ree1_etm : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_etm:1; + /** read_ree2_etm : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_etm:1; + /** write_tee_etm : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_etm:1; + /** write_ree0_etm : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_etm:1; + /** write_ree1_etm : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_etm:1; + /** write_ree2_etm : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_etm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_etm_ctrl_reg_t; + +/** Type of intmtx_core0_ctrl register + * intmtx_core0 read/write control register + */ +typedef union { + struct { + /** read_tee_intmtx_core0 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intmtx_core0:1; + /** read_ree0_intmtx_core0 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intmtx_core0:1; + /** read_ree1_intmtx_core0 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intmtx_core0:1; + /** read_ree2_intmtx_core0 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intmtx_core0:1; + /** write_tee_intmtx_core0 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intmtx_core0:1; + /** write_ree0_intmtx_core0 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intmtx_core0:1; + /** write_ree1_intmtx_core0 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intmtx_core0:1; + /** write_ree2_intmtx_core0 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intmtx_core0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intmtx_core0_ctrl_reg_t; + +/** Type of intmtx_core1_ctrl register + * intmtx_core1 read/write control register + */ +typedef union { + struct { + /** read_tee_intmtx_core1 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intmtx_core1:1; + /** read_ree0_intmtx_core1 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intmtx_core1:1; + /** read_ree1_intmtx_core1 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intmtx_core1:1; + /** read_ree2_intmtx_core1 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intmtx_core1:1; + /** write_tee_intmtx_core1 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intmtx_core1:1; + /** write_ree0_intmtx_core1 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intmtx_core1:1; + /** write_ree1_intmtx_core1 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intmtx_core1:1; + /** write_ree2_intmtx_core1 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intmtx_core1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intmtx_core1_ctrl_reg_t; + +/** Type of apb_adc_ctrl register + * apb_adc read/write control register + */ +typedef union { + struct { + /** read_tee_apb_adc : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_apb_adc:1; + /** read_ree0_apb_adc : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_apb_adc:1; + /** read_ree1_apb_adc : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_apb_adc:1; + /** read_ree2_apb_adc : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_apb_adc:1; + /** write_tee_apb_adc : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_apb_adc:1; + /** write_ree0_apb_adc : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_apb_adc:1; + /** write_ree1_apb_adc : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_apb_adc:1; + /** write_ree2_apb_adc : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_apb_adc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_apb_adc_ctrl_reg_t; + +/** Type of timergroup0_ctrl register + * timergroup0 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup0:1; + /** read_ree0_timergroup0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup0:1; + /** read_ree1_timergroup0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup0:1; + /** read_ree2_timergroup0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup0:1; + /** write_tee_timergroup0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup0:1; + /** write_ree0_timergroup0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup0:1; + /** write_ree1_timergroup0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup0:1; + /** write_ree2_timergroup0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup0_ctrl_reg_t; + +/** Type of timergroup1_ctrl register + * timergroup1 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup1:1; + /** read_ree0_timergroup1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup1:1; + /** read_ree1_timergroup1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup1:1; + /** read_ree2_timergroup1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup1:1; + /** write_tee_timergroup1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup1:1; + /** write_ree0_timergroup1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup1:1; + /** write_ree1_timergroup1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup1:1; + /** write_ree2_timergroup1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup1_ctrl_reg_t; + +/** Type of systimer_ctrl register + * systimer read/write control register + */ +typedef union { + struct { + /** read_tee_systimer : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_systimer:1; + /** read_ree0_systimer : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_systimer:1; + /** read_ree1_systimer : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_systimer:1; + /** read_ree2_systimer : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_systimer:1; + /** write_tee_systimer : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_systimer:1; + /** write_ree0_systimer : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_systimer:1; + /** write_ree1_systimer : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_systimer:1; + /** write_ree2_systimer : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_systimer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_systimer_ctrl_reg_t; + +/** Type of misc_ctrl register + * misc read/write control register + */ +typedef union { + struct { + /** read_tee_misc : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_misc:1; + /** read_ree0_misc : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_misc:1; + /** read_ree1_misc : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_misc:1; + /** read_ree2_misc : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_misc:1; + /** write_tee_misc : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_misc:1; + /** write_ree0_misc : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_misc:1; + /** write_ree1_misc : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_misc:1; + /** write_ree2_misc : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_misc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_misc_ctrl_reg_t; + +/** Type of src_ctrl register + * src read/write control register + */ +typedef union { + struct { + /** read_tee_src : R/W; bitpos: [0]; default: 1; + * Configures src registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_src:1; + /** read_ree0_src : R/W; bitpos: [1]; default: 0; + * Configures src registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_src:1; + /** read_ree1_src : R/W; bitpos: [2]; default: 0; + * Configures src registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_src:1; + /** read_ree2_src : R/W; bitpos: [3]; default: 0; + * Configures src registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_src:1; + /** write_tee_src : R/W; bitpos: [4]; default: 1; + * Configures src registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_src:1; + /** write_ree0_src : R/W; bitpos: [5]; default: 0; + * Configures src registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_src:1; + /** write_ree1_src : R/W; bitpos: [6]; default: 0; + * Configures src registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_src:1; + /** write_ree2_src : R/W; bitpos: [7]; default: 0; + * Configures src registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_src:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_src_ctrl_reg_t; + +/** Type of usb_otg_fs_core_ctrl register + * usb_otg_fs_core read/write control register + */ +typedef union { + struct { + /** read_tee_usb_otg_fs_core : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_core registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_otg_fs_core:1; + /** read_ree0_usb_otg_fs_core : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_otg_fs_core:1; + /** read_ree1_usb_otg_fs_core : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_otg_fs_core:1; + /** read_ree2_usb_otg_fs_core : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_otg_fs_core:1; + /** write_tee_usb_otg_fs_core : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_core registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_otg_fs_core:1; + /** write_ree0_usb_otg_fs_core : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_otg_fs_core:1; + /** write_ree1_usb_otg_fs_core : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_otg_fs_core:1; + /** write_ree2_usb_otg_fs_core : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_otg_fs_core:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_otg_fs_core_ctrl_reg_t; + +/** Type of usb_otg_fs_phy_ctrl register + * usb_otg_fs_phy read/write control register + */ +typedef union { + struct { + /** read_tee_usb_otg_fs_phy : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_phy registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_otg_fs_phy:1; + /** read_ree0_usb_otg_fs_phy : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_otg_fs_phy:1; + /** read_ree1_usb_otg_fs_phy : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_otg_fs_phy:1; + /** read_ree2_usb_otg_fs_phy : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_otg_fs_phy:1; + /** write_tee_usb_otg_fs_phy : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_phy registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_otg_fs_phy:1; + /** write_ree0_usb_otg_fs_phy : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_otg_fs_phy:1; + /** write_ree1_usb_otg_fs_phy : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_otg_fs_phy:1; + /** write_ree2_usb_otg_fs_phy : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_otg_fs_phy:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_otg_fs_phy_ctrl_reg_t; + +/** Type of pvt_monitor_ctrl register + * pvt_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pvt_monitor:1; + /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pvt_monitor:1; + /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pvt_monitor:1; + /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pvt_monitor:1; + /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pvt_monitor:1; + /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pvt_monitor:1; + /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pvt_monitor:1; + /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pvt_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pvt_monitor_ctrl_reg_t; + +/** Type of pcnt_ctrl register + * pcnt read/write control register + */ +typedef union { + struct { + /** read_tee_pcnt : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcnt:1; + /** read_ree0_pcnt : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcnt:1; + /** read_ree1_pcnt : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcnt:1; + /** read_ree2_pcnt : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcnt:1; + /** write_tee_pcnt : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcnt:1; + /** write_ree0_pcnt : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcnt:1; + /** write_ree1_pcnt : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcnt:1; + /** write_ree2_pcnt : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcnt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcnt_ctrl_reg_t; + +/** Type of iomux_ctrl register + * iomux read/write control register + */ +typedef union { + struct { + /** read_tee_iomux : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_iomux:1; + /** read_ree0_iomux : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_iomux:1; + /** read_ree1_iomux : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_iomux:1; + /** read_ree2_iomux : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_iomux:1; + /** write_tee_iomux : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_iomux:1; + /** write_ree0_iomux : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_iomux:1; + /** write_ree1_iomux : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_iomux:1; + /** write_ree2_iomux : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_iomux:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_iomux_ctrl_reg_t; + +/** Type of psram_mem_monitor_ctrl register + * psram_mem_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_psram_mem_monitor : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_psram_mem_monitor:1; + /** read_ree0_psram_mem_monitor : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_psram_mem_monitor:1; + /** read_ree1_psram_mem_monitor : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_psram_mem_monitor:1; + /** read_ree2_psram_mem_monitor : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_psram_mem_monitor:1; + /** write_tee_psram_mem_monitor : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_psram_mem_monitor:1; + /** write_ree0_psram_mem_monitor : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_psram_mem_monitor:1; + /** write_ree1_psram_mem_monitor : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_psram_mem_monitor:1; + /** write_ree2_psram_mem_monitor : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_psram_mem_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_psram_mem_monitor_ctrl_reg_t; + +/** Type of mem_acs_monitor_ctrl register + * mem_acs_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_mem_acs_monitor : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mem_acs_monitor:1; + /** read_ree0_mem_acs_monitor : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mem_acs_monitor:1; + /** read_ree1_mem_acs_monitor : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mem_acs_monitor:1; + /** read_ree2_mem_acs_monitor : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mem_acs_monitor:1; + /** write_tee_mem_acs_monitor : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mem_acs_monitor:1; + /** write_ree0_mem_acs_monitor : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mem_acs_monitor:1; + /** write_ree1_mem_acs_monitor : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mem_acs_monitor:1; + /** write_ree2_mem_acs_monitor : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mem_acs_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mem_acs_monitor_ctrl_reg_t; + +/** Type of hp_system_reg_ctrl register + * hp_system_reg read/write control register + */ +typedef union { + struct { + /** read_tee_hp_system_reg : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_system_reg:1; + /** read_ree0_hp_system_reg : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_system_reg:1; + /** read_ree1_hp_system_reg : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_system_reg:1; + /** read_ree2_hp_system_reg : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_system_reg:1; + /** write_tee_hp_system_reg : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_system_reg:1; + /** write_ree0_hp_system_reg : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_system_reg:1; + /** write_ree1_hp_system_reg : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_system_reg:1; + /** write_ree2_hp_system_reg : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_system_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_system_reg_ctrl_reg_t; + +/** Type of pcr_reg_ctrl register + * pcr_reg read/write control register + */ +typedef union { + struct { + /** read_tee_pcr_reg : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcr_reg:1; + /** read_ree0_pcr_reg : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcr_reg:1; + /** read_ree1_pcr_reg : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcr_reg:1; + /** read_ree2_pcr_reg : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcr_reg:1; + /** write_tee_pcr_reg : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcr_reg:1; + /** write_ree0_pcr_reg : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcr_reg:1; + /** write_ree1_pcr_reg : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcr_reg:1; + /** write_ree2_pcr_reg : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcr_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcr_reg_ctrl_reg_t; + +/** Type of mspi_ctrl register + * mspi read/write control register + */ +typedef union { + struct { + /** read_tee_mspi : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mspi:1; + /** read_ree0_mspi : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mspi:1; + /** read_ree1_mspi : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mspi:1; + /** read_ree2_mspi : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mspi:1; + /** write_tee_mspi : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mspi:1; + /** write_ree0_mspi : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mspi:1; + /** write_ree1_mspi : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mspi:1; + /** write_ree2_mspi : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mspi:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mspi_ctrl_reg_t; + +/** Type of hp_apm_ctrl register + * hp_apm read/write control register + */ +typedef union { + struct { + /** read_tee_hp_apm : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_apm:1; + /** read_ree0_hp_apm : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_apm:1; + /** read_ree1_hp_apm : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_apm:1; + /** read_ree2_hp_apm : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_apm:1; + /** write_tee_hp_apm : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_apm:1; + /** write_ree0_hp_apm : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_apm:1; + /** write_ree1_hp_apm : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_apm:1; + /** write_ree2_hp_apm : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_apm_ctrl_reg_t; + +/** Type of cpu_apm_ctrl register + * cpu_apm read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_apm : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_apm:1; + /** read_ree0_cpu_apm : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_apm:1; + /** read_ree1_cpu_apm : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_apm:1; + /** read_ree2_cpu_apm : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_apm:1; + /** write_tee_cpu_apm : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_apm:1; + /** write_ree0_cpu_apm : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_apm:1; + /** write_ree1_cpu_apm : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_apm:1; + /** write_ree2_cpu_apm : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_apm_ctrl_reg_t; + +/** Type of tee_ctrl register + * tee read/write control register + */ +typedef union { + struct { + /** read_tee_tee : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_tee:1; + /** read_ree0_tee : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_tee:1; + /** read_ree1_tee : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_tee:1; + /** read_ree2_tee : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_tee:1; + /** write_tee_tee : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_tee:1; + /** write_ree0_tee : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_tee:1; + /** write_ree1_tee : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_tee:1; + /** write_ree2_tee : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_tee:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_tee_ctrl_reg_t; + +/** Type of km_ctrl register + * crypt read/write control register + */ +typedef union { + struct { + /** read_tee_km : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_km:1; + /** read_ree0_km : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_km:1; + /** read_ree1_km : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_km:1; + /** read_ree2_km : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_km:1; + /** write_tee_km : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_km:1; + /** write_ree0_km : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_km:1; + /** write_ree1_km : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_km:1; + /** write_ree2_km : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_km:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_km_ctrl_reg_t; + +/** Type of crypt_ctrl register + * crypt read/write control register + */ +typedef union { + struct { + /** read_tee_crypt : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_crypt:1; + /** read_ree0_crypt : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_crypt:1; + /** read_ree1_crypt : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_crypt:1; + /** read_ree2_crypt : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_crypt:1; + /** write_tee_crypt : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_crypt:1; + /** write_ree0_crypt : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_crypt:1; + /** write_ree1_crypt : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_crypt:1; + /** write_ree2_crypt : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_crypt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_crypt_ctrl_reg_t; + +/** Type of core0_trace_ctrl register + * core0_trace read/write control register + */ +typedef union { + struct { + /** read_tee_core0_trace : R/W; bitpos: [0]; default: 1; + * Configures core0_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_core0_trace:1; + /** read_ree0_core0_trace : R/W; bitpos: [1]; default: 0; + * Configures core0_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_core0_trace:1; + /** read_ree1_core0_trace : R/W; bitpos: [2]; default: 0; + * Configures core0_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_core0_trace:1; + /** read_ree2_core0_trace : R/W; bitpos: [3]; default: 0; + * Configures core0_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_core0_trace:1; + /** write_tee_core0_trace : R/W; bitpos: [4]; default: 1; + * Configures core0_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_core0_trace:1; + /** write_ree0_core0_trace : R/W; bitpos: [5]; default: 0; + * Configures core0_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_core0_trace:1; + /** write_ree1_core0_trace : R/W; bitpos: [6]; default: 0; + * Configures core0_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_core0_trace:1; + /** write_ree2_core0_trace : R/W; bitpos: [7]; default: 0; + * Configures core0_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_core0_trace:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_core0_trace_ctrl_reg_t; + +/** Type of core1_trace_ctrl register + * core1_trace read/write control register + */ +typedef union { + struct { + /** read_tee_core1_trace : R/W; bitpos: [0]; default: 1; + * Configures core1_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_core1_trace:1; + /** read_ree0_core1_trace : R/W; bitpos: [1]; default: 0; + * Configures core1_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_core1_trace:1; + /** read_ree1_core1_trace : R/W; bitpos: [2]; default: 0; + * Configures core1_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_core1_trace:1; + /** read_ree2_core1_trace : R/W; bitpos: [3]; default: 0; + * Configures core1_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_core1_trace:1; + /** write_tee_core1_trace : R/W; bitpos: [4]; default: 1; + * Configures core1_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_core1_trace:1; + /** write_ree0_core1_trace : R/W; bitpos: [5]; default: 0; + * Configures core1_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_core1_trace:1; + /** write_ree1_core1_trace : R/W; bitpos: [6]; default: 0; + * Configures core1_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_core1_trace:1; + /** write_ree2_core1_trace : R/W; bitpos: [7]; default: 0; + * Configures core1_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_core1_trace:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_core1_trace_ctrl_reg_t; + +/** Type of cpu_bus_monitor_ctrl register + * cpu_bus_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_bus_monitor : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_bus_monitor:1; + /** read_ree0_cpu_bus_monitor : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_bus_monitor:1; + /** read_ree1_cpu_bus_monitor : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_bus_monitor:1; + /** read_ree2_cpu_bus_monitor : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_bus_monitor:1; + /** write_tee_cpu_bus_monitor : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_bus_monitor:1; + /** write_ree0_cpu_bus_monitor : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_bus_monitor:1; + /** write_ree1_cpu_bus_monitor : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_bus_monitor:1; + /** write_ree2_cpu_bus_monitor : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_bus_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_bus_monitor_ctrl_reg_t; + +/** Type of intpri_reg_ctrl register + * intpri_reg read/write control register + */ +typedef union { + struct { + /** read_tee_intpri_reg : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intpri_reg:1; + /** read_ree0_intpri_reg : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intpri_reg:1; + /** read_ree1_intpri_reg : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intpri_reg:1; + /** read_ree2_intpri_reg : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intpri_reg:1; + /** write_tee_intpri_reg : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intpri_reg:1; + /** write_ree0_intpri_reg : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intpri_reg:1; + /** write_ree1_intpri_reg : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intpri_reg:1; + /** write_ree2_intpri_reg : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intpri_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intpri_reg_ctrl_reg_t; + +/** Type of cache_cfg_ctrl register + * cache_cfg read/write control register + */ +typedef union { + struct { + /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cache_cfg:1; + /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cache_cfg:1; + /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cache_cfg:1; + /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cache_cfg:1; + /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cache_cfg:1; + /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cache_cfg:1; + /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cache_cfg:1; + /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cache_cfg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cache_cfg_ctrl_reg_t; + +/** Type of modem_ctrl register + * modem read/write control register + */ +typedef union { + struct { + /** read_tee_modem : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_modem:1; + /** read_ree0_modem : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_modem:1; + /** read_ree1_modem : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_modem:1; + /** read_ree2_modem : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_modem:1; + /** write_tee_modem : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_modem:1; + /** write_ree0_modem : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_modem:1; + /** write_ree1_modem : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_modem:1; + /** write_ree2_modem : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_modem:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_modem_ctrl_reg_t; + +/** Type of zero_det_ctrl register + * zero_det read/write control register + */ +typedef union { + struct { + /** read_tee_zero_det : R/W; bitpos: [0]; default: 1; + * Configures zero_det registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_zero_det:1; + /** read_ree0_zero_det : R/W; bitpos: [1]; default: 0; + * Configures zero_det registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_zero_det:1; + /** read_ree1_zero_det : R/W; bitpos: [2]; default: 0; + * Configures zero_det registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_zero_det:1; + /** read_ree2_zero_det : R/W; bitpos: [3]; default: 0; + * Configures zero_det registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_zero_det:1; + /** write_tee_zero_det : R/W; bitpos: [4]; default: 1; + * Configures zero_det registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_zero_det:1; + /** write_ree0_zero_det : R/W; bitpos: [5]; default: 0; + * Configures zero_det registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_zero_det:1; + /** write_ree1_zero_det : R/W; bitpos: [6]; default: 0; + * Configures zero_det registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_zero_det:1; + /** write_ree2_zero_det : R/W; bitpos: [7]; default: 0; + * Configures zero_det registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_zero_det:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_zero_det_ctrl_reg_t; + + +/** Group: config register */ +/** Type of bus_err_conf register + * Clock gating register + */ +typedef union { + struct { + /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ + uint32_t bus_err_resp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_bus_err_conf_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37818480; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct { + volatile tee_mn_mode_ctrl_reg_t mn_mode_ctrl[32]; + volatile tee_gpspi0_ctrl_reg_t gpspi0_ctrl; + volatile tee_gpspi1_ctrl_reg_t gpspi1_ctrl; + volatile tee_uart0_ctrl_reg_t uart0_ctrl; + volatile tee_uart1_ctrl_reg_t uart1_ctrl; + volatile tee_uhci_ctrl_reg_t uhci_ctrl; + volatile tee_i2c0_ctrl_reg_t i2c0_ctrl; + volatile tee_i2c1_ctrl_reg_t i2c1_ctrl; + volatile tee_i2s_ctrl_reg_t i2s_ctrl; + volatile tee_parl_io_ctrl_reg_t parl_io_ctrl; + volatile tee_pwm0_ctrl_reg_t pwm0_ctrl; + volatile tee_pwm1_ctrl_reg_t pwm1_ctrl; + volatile tee_ledc_ctrl_reg_t ledc_ctrl; + volatile tee_can_ctrl_reg_t can_ctrl; + volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl; + volatile tee_rmt_ctrl_reg_t rmt_ctrl; + volatile tee_gdma_ctrl_reg_t gdma_ctrl; + volatile tee_regdma_ctrl_reg_t regdma_ctrl; + volatile tee_etm_ctrl_reg_t etm_ctrl; + volatile tee_intmtx_core0_ctrl_reg_t intmtx_core0_ctrl; + volatile tee_intmtx_core1_ctrl_reg_t intmtx_core1_ctrl; + volatile tee_apb_adc_ctrl_reg_t apb_adc_ctrl; + volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; + volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; + volatile tee_systimer_ctrl_reg_t systimer_ctrl; + volatile tee_misc_ctrl_reg_t misc_ctrl; + volatile tee_src_ctrl_reg_t src_ctrl; + volatile tee_usb_otg_fs_core_ctrl_reg_t usb_otg_fs_core_ctrl; + volatile tee_usb_otg_fs_phy_ctrl_reg_t usb_otg_fs_phy_ctrl; + volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; + volatile tee_iomux_ctrl_reg_t iomux_ctrl; + volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; + volatile tee_mem_acs_monitor_ctrl_reg_t mem_acs_monitor_ctrl; + volatile tee_hp_system_reg_ctrl_reg_t hp_system_reg_ctrl; + volatile tee_pcr_reg_ctrl_reg_t pcr_reg_ctrl; + volatile tee_mspi_ctrl_reg_t mspi_ctrl; + volatile tee_hp_apm_ctrl_reg_t hp_apm_ctrl; + volatile tee_cpu_apm_ctrl_reg_t cpu_apm_ctrl; + volatile tee_tee_ctrl_reg_t tee_ctrl; + volatile tee_km_ctrl_reg_t km_ctrl; + volatile tee_crypt_ctrl_reg_t crypt_ctrl; + volatile tee_core0_trace_ctrl_reg_t core0_trace_ctrl; + volatile tee_core1_trace_ctrl_reg_t core1_trace_ctrl; + volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; + volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; + volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; + volatile tee_modem_ctrl_reg_t modem_ctrl; + volatile tee_zero_det_ctrl_reg_t zero_det_ctrl; + uint32_t reserved_140[940]; + volatile tee_bus_err_conf_reg_t bus_err_conf; + uint32_t reserved_ff4; + volatile tee_clock_gate_reg_t clock_gate; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/usb_otgfs_core_ctrl_reg.h b/components/soc/esp32h4/register/soc/usb_otgfs_core_ctrl_reg.h new file mode 100644 index 0000000000..081211d013 --- /dev/null +++ b/components/soc/esp32h4/register/soc/usb_otgfs_core_ctrl_reg.h @@ -0,0 +1,16130 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_OTGFS_GOTGCTL_REG register + * OTG Control and Status Register The OTG Control and Status register controls the + * behavior and reflects the status of the OTG function of the controller. + */ +#define USB_OTGFS_GOTGCTL_REG(i) (DR_REG_USB_BASE(i) + 0x0) +/** USB_OTGFS_GOTGCTL_SESREQSCS : RO; bitpos: [0]; default: 0; + * Mode: Device only + * Session Request Success (SesReqScs) + * The core sets this bit when a session request initiation is successful. + * - 1'b0: Session request failure + * - 1'b1: Session request success + */ +#define USB_OTGFS_GOTGCTL_SESREQSCS (BIT(0)) +#define USB_OTGFS_GOTGCTL_SESREQSCS_M (USB_OTGFS_GOTGCTL_SESREQSCS_V << USB_OTGFS_GOTGCTL_SESREQSCS_S) +#define USB_OTGFS_GOTGCTL_SESREQSCS_V 0x00000001U +#define USB_OTGFS_GOTGCTL_SESREQSCS_S 0 +/** USB_OTGFS_GOTGCTL_SESREQ : R/W; bitpos: [1]; default: 0; + * Mode: Device only + * Session Request (SesReq) + * The application sets this bit to initiate a session request on the USB. The + * application can clear this bit by writing a 0 when the Host Negotiation Success + * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. + * The core clears this bit when the HstNegSucStsChng bit is cleared. + * If you use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the + * session request, the application must wait until the VBUS discharges to 0.2 V, + * after the B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This + * discharge time varies between different PHYs and can be obtained from the PHY + * vendor. + * - 1'b0: No session request + * - 1'b1: Session request + */ +#define USB_OTGFS_GOTGCTL_SESREQ (BIT(1)) +#define USB_OTGFS_GOTGCTL_SESREQ_M (USB_OTGFS_GOTGCTL_SESREQ_V << USB_OTGFS_GOTGCTL_SESREQ_S) +#define USB_OTGFS_GOTGCTL_SESREQ_V 0x00000001U +#define USB_OTGFS_GOTGCTL_SESREQ_S 1 +/** USB_OTGFS_GOTGCTL_VBVALIDOVEN : R/W; bitpos: [2]; default: 0; + * Mode: Host only + * VBUS Valid Override Enable (VbvalidOvEn) + * This bit is used to enable/disable the software to override the Bvalid signal using + * the GOTGCTL.VbvalidOvVal. + * - 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL.VbvalidOvVal. + * - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the controller. + */ +#define USB_OTGFS_GOTGCTL_VBVALIDOVEN (BIT(2)) +#define USB_OTGFS_GOTGCTL_VBVALIDOVEN_M (USB_OTGFS_GOTGCTL_VBVALIDOVEN_V << USB_OTGFS_GOTGCTL_VBVALIDOVEN_S) +#define USB_OTGFS_GOTGCTL_VBVALIDOVEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_VBVALIDOVEN_S 2 +/** USB_OTGFS_GOTGCTL_VBVALIDOVVAL : R/W; bitpos: [3]; default: 0; + * Mode: Host only + * VBUS Valid OverrideValue (VbvalidOvVal) + * This bit is used to set Override value for vbusvalid signal when + * GOTGCTL.VbvalidOvEn is set. + * - 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1 + * - 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1 + */ +#define USB_OTGFS_GOTGCTL_VBVALIDOVVAL (BIT(3)) +#define USB_OTGFS_GOTGCTL_VBVALIDOVVAL_M (USB_OTGFS_GOTGCTL_VBVALIDOVVAL_V << USB_OTGFS_GOTGCTL_VBVALIDOVVAL_S) +#define USB_OTGFS_GOTGCTL_VBVALIDOVVAL_V 0x00000001U +#define USB_OTGFS_GOTGCTL_VBVALIDOVVAL_S 3 +/** USB_OTGFS_GOTGCTL_AVALIDOVEN : R/W; bitpos: [4]; default: 0; + * Mode: Host only + * A-Peripheral Session Valid Override Enable (AvalidOvEn) + * This bit is used to enable/disable the software to override the Avalid signal using + * the GOTGCTL.AvalidOvVal. + * - 1'b1: Internally Avalid received from the PHY is overridden with + * GOTGCTL.AvalidOvVal. + * - 1'b0: Override is disabled and avalid signal from the respective PHY selected is + * used internally by the core + */ +#define USB_OTGFS_GOTGCTL_AVALIDOVEN (BIT(4)) +#define USB_OTGFS_GOTGCTL_AVALIDOVEN_M (USB_OTGFS_GOTGCTL_AVALIDOVEN_V << USB_OTGFS_GOTGCTL_AVALIDOVEN_S) +#define USB_OTGFS_GOTGCTL_AVALIDOVEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_AVALIDOVEN_S 4 +/** USB_OTGFS_GOTGCTL_AVALIDOVVAL : R/W; bitpos: [5]; default: 0; + * Mode: Host only + * A-Peripheral Session Valid OverrideValue (AvalidOvVal) + * This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is + * set. + * - 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + * - 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + */ +#define USB_OTGFS_GOTGCTL_AVALIDOVVAL (BIT(5)) +#define USB_OTGFS_GOTGCTL_AVALIDOVVAL_M (USB_OTGFS_GOTGCTL_AVALIDOVVAL_V << USB_OTGFS_GOTGCTL_AVALIDOVVAL_S) +#define USB_OTGFS_GOTGCTL_AVALIDOVVAL_V 0x00000001U +#define USB_OTGFS_GOTGCTL_AVALIDOVVAL_S 5 +/** USB_OTGFS_GOTGCTL_BVALIDOVEN : R/W; bitpos: [6]; default: 0; + * Mode: Device only + * B-Peripheral Session Valid Override Value (BvalidOvEn) + * This bit is used to enable/disable the software to override the Bvalid signal using + * the GOTGCTL.BvalidOvVal. + * - 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL.BvalidOvVal. + * - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the force + */ +#define USB_OTGFS_GOTGCTL_BVALIDOVEN (BIT(6)) +#define USB_OTGFS_GOTGCTL_BVALIDOVEN_M (USB_OTGFS_GOTGCTL_BVALIDOVEN_V << USB_OTGFS_GOTGCTL_BVALIDOVEN_S) +#define USB_OTGFS_GOTGCTL_BVALIDOVEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_BVALIDOVEN_S 6 +/** USB_OTGFS_GOTGCTL_BVALIDOVVAL : R/W; bitpos: [7]; default: 0; + * Mode: Device only + * B-Peripheral Session Valid OverrideValue (BvalidOvVal) + * This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is + * set. + * - 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1 + * - 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1 + */ +#define USB_OTGFS_GOTGCTL_BVALIDOVVAL (BIT(7)) +#define USB_OTGFS_GOTGCTL_BVALIDOVVAL_M (USB_OTGFS_GOTGCTL_BVALIDOVVAL_V << USB_OTGFS_GOTGCTL_BVALIDOVVAL_S) +#define USB_OTGFS_GOTGCTL_BVALIDOVVAL_V 0x00000001U +#define USB_OTGFS_GOTGCTL_BVALIDOVVAL_S 7 +/** USB_OTGFS_GOTGCTL_HSTNEGSCS : RO; bitpos: [8]; default: 0; + * Mode: HNP-capable Device + * Host Negotiation Success (HstNegScs) + * The controller sets this bit when host negotiation is successful. The controller + * clears this bit when the HNP Request (HNPReq) bit in this register is set. + * - 1'b0: Host negotiation failure + * - 1'b1: Host negotiation success + */ +#define USB_OTGFS_GOTGCTL_HSTNEGSCS (BIT(8)) +#define USB_OTGFS_GOTGCTL_HSTNEGSCS_M (USB_OTGFS_GOTGCTL_HSTNEGSCS_V << USB_OTGFS_GOTGCTL_HSTNEGSCS_S) +#define USB_OTGFS_GOTGCTL_HSTNEGSCS_V 0x00000001U +#define USB_OTGFS_GOTGCTL_HSTNEGSCS_S 8 +/** USB_OTGFS_GOTGCTL_HNPREQ : R/W; bitpos: [9]; default: 0; + * Mode: HNP Capable OTG Device + * HNP Request (HNPReq) + * The application sets this bit to initiate an HNP request to the connected USB host. + * The application can clear this bit by writing a 0 when the Host Negotiation Success + * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. + * The controller clears this bit when the HstNegSucStsChng bit is cleared. + * - 1'b0: No HNP request + * - 1'b1: HNP request + */ +#define USB_OTGFS_GOTGCTL_HNPREQ (BIT(9)) +#define USB_OTGFS_GOTGCTL_HNPREQ_M (USB_OTGFS_GOTGCTL_HNPREQ_V << USB_OTGFS_GOTGCTL_HNPREQ_S) +#define USB_OTGFS_GOTGCTL_HNPREQ_V 0x00000001U +#define USB_OTGFS_GOTGCTL_HNPREQ_S 9 +/** USB_OTGFS_GOTGCTL_HSTSETHNPEN : R/W; bitpos: [10]; default: 0; + * Mode: HNP Capable OTG Host + * Host Set HNP Enable (HstSetHNPEn) + * The application sets this bit when it has successfully enabled HNP (using the + * SetFeature.SetHNPEnable command) on the connected device. + * - 1'b0: Host Set HNP is not enabled + * - 1'b1: Host Set HNP is enabled + */ +#define USB_OTGFS_GOTGCTL_HSTSETHNPEN (BIT(10)) +#define USB_OTGFS_GOTGCTL_HSTSETHNPEN_M (USB_OTGFS_GOTGCTL_HSTSETHNPEN_V << USB_OTGFS_GOTGCTL_HSTSETHNPEN_S) +#define USB_OTGFS_GOTGCTL_HSTSETHNPEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_HSTSETHNPEN_S 10 +/** USB_OTGFS_GOTGCTL_DEVHNPEN : R/W; bitpos: [11]; default: 0; + * Mode: HNP Capable OTG Device + * Device HNP Enabled (DevHNPEn) + * The application sets this bit when it successfully receives a + * SetFeature.SetHNPEnable command from the connected USB host. + * - 1'b0: HNP is not enabled in the application + * - 1'b1: HNP is enabled in the application + */ +#define USB_OTGFS_GOTGCTL_DEVHNPEN (BIT(11)) +#define USB_OTGFS_GOTGCTL_DEVHNPEN_M (USB_OTGFS_GOTGCTL_DEVHNPEN_V << USB_OTGFS_GOTGCTL_DEVHNPEN_S) +#define USB_OTGFS_GOTGCTL_DEVHNPEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_DEVHNPEN_S 11 +/** USB_OTGFS_GOTGCTL_EHEN : R/W; bitpos: [12]; default: 0; + * Mode: SRP Capable Host + * Embedded Host Enable + * It is used to select between OTG A Device state Machine and Embedded Host state + * machine. + * - 1'b0: OTG A Device state machine is selected + * - 1'b1: Embedded Host State Machine is selected + * Note: + * This field is valid only in SRP-Capable OTG Mode (OTG_MODE=0,1). + */ +#define USB_OTGFS_GOTGCTL_EHEN (BIT(12)) +#define USB_OTGFS_GOTGCTL_EHEN_M (USB_OTGFS_GOTGCTL_EHEN_V << USB_OTGFS_GOTGCTL_EHEN_S) +#define USB_OTGFS_GOTGCTL_EHEN_V 0x00000001U +#define USB_OTGFS_GOTGCTL_EHEN_S 12 +/** USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS : R/W; bitpos: [15]; default: 0; + * Mode: Host and Device + * Debounce Filter Bypass + * Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when + * enabled. + * - 1'b0: Disabled + * - 1'b1: Enabled + * + * + * Note: This register bit is valid only when debounce filters are present in core. + */ +#define USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS (BIT(15)) +#define USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS_M (USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS_V << USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS_S) +#define USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS_V 0x00000001U +#define USB_OTGFS_GOTGCTL_DBNCEFLTRBYPASS_S 15 +/** USB_OTGFS_GOTGCTL_CONIDSTS : RO; bitpos: [16]; default: 1; + * Mode: Host and Device + * Connector ID Status (ConIDSts) + * Indicates the connector ID status on a connect event. + * - 1'b0: The core is in A-Device mode. + * - 1'b1: The core is in B-Device mode. + * + * Note: + * The reset value of this register field can be read only after the PHY clock is + * stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read + * the correct reset value which ever event is later. + * Reset: + * - 1'b0: in host only mode (OTG_MODE = 5 or 6) + * - 1'b1: in all other configurations + */ +#define USB_OTGFS_GOTGCTL_CONIDSTS (BIT(16)) +#define USB_OTGFS_GOTGCTL_CONIDSTS_M (USB_OTGFS_GOTGCTL_CONIDSTS_V << USB_OTGFS_GOTGCTL_CONIDSTS_S) +#define USB_OTGFS_GOTGCTL_CONIDSTS_V 0x00000001U +#define USB_OTGFS_GOTGCTL_CONIDSTS_S 16 +/** USB_OTGFS_GOTGCTL_DBNCTIME : RO; bitpos: [17]; default: 0; + * Mode: Host only + * Long/Short Debounce Time (DbncTime) + * Indicates the debounce time of a detected connection. + * - 1'b0: Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + * - 1'b1: Short debounce time, used for soft connections (2.5 micro-sec) + */ +#define USB_OTGFS_GOTGCTL_DBNCTIME (BIT(17)) +#define USB_OTGFS_GOTGCTL_DBNCTIME_M (USB_OTGFS_GOTGCTL_DBNCTIME_V << USB_OTGFS_GOTGCTL_DBNCTIME_S) +#define USB_OTGFS_GOTGCTL_DBNCTIME_V 0x00000001U +#define USB_OTGFS_GOTGCTL_DBNCTIME_S 17 +/** USB_OTGFS_GOTGCTL_ASESVLD : RO; bitpos: [18]; default: 0; + * Mode: Host only + * A-Session Valid (ASesVld) + * Indicates the Host mode transceiver status. + * - 1'b0: A-session is not valid + * - 1'b1: A-session is valid + * Note: If you do not enabled OTG features (such as SRP and HNP), the read reset + * value will be 1. The vbus assigns the values internally for non-SRP or non-HNP + * configurations. + * In case of OTG_MODE=0, the reset value of this bit is 1'b0. + */ +#define USB_OTGFS_GOTGCTL_ASESVLD (BIT(18)) +#define USB_OTGFS_GOTGCTL_ASESVLD_M (USB_OTGFS_GOTGCTL_ASESVLD_V << USB_OTGFS_GOTGCTL_ASESVLD_S) +#define USB_OTGFS_GOTGCTL_ASESVLD_V 0x00000001U +#define USB_OTGFS_GOTGCTL_ASESVLD_S 18 +/** USB_OTGFS_GOTGCTL_BSESVLD : RO; bitpos: [19]; default: 0; + * Mode: Device only + * B-Session Valid (BSesVld) + * Indicates the Device mode transceiver status. + * - 1'b0: B-session is not valid. + * - 1'b1: B-session is valid. + * In OTG mode, you can use this bit to determine if the device is connected or + * disconnected. + * + * Note: + * - If you do not enable OTG features (such as SRP and HNP), the read reset value + * will be 1.The vbus assigns the values internally for non- SRP or non-HNP + * configurations. + * - In case of OTG_MODE=0, the reset value of this bit is 1'b0. + * - The reset value of this register field can be read only after the PHY clock is + * stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read + * the correct reset value which ever event is later. + */ +#define USB_OTGFS_GOTGCTL_BSESVLD (BIT(19)) +#define USB_OTGFS_GOTGCTL_BSESVLD_M (USB_OTGFS_GOTGCTL_BSESVLD_V << USB_OTGFS_GOTGCTL_BSESVLD_S) +#define USB_OTGFS_GOTGCTL_BSESVLD_V 0x00000001U +#define USB_OTGFS_GOTGCTL_BSESVLD_S 19 +/** USB_OTGFS_GOTGCTL_OTGVER : R/W; bitpos: [20]; default: 0; + * OTG Version (OTGVer) + * Indicates the OTG revision. + * - 1'b0: OTG Version 1.3. In this version the core supports Data line pulsing and + * VBus pulsing for SRP. + * - 1'b1: OTG Version 2.0. In this version the core supports only Data line pulsing + * for SRP. + */ +#define USB_OTGFS_GOTGCTL_OTGVER (BIT(20)) +#define USB_OTGFS_GOTGCTL_OTGVER_M (USB_OTGFS_GOTGCTL_OTGVER_V << USB_OTGFS_GOTGCTL_OTGVER_S) +#define USB_OTGFS_GOTGCTL_OTGVER_V 0x00000001U +#define USB_OTGFS_GOTGCTL_OTGVER_S 20 +/** USB_OTGFS_GOTGCTL_CURMOD : RO; bitpos: [21]; default: 0; + * Current Mode of Operation (CurMod) + * Mode: Host and Device + * Indicates the current mode. + * - 1'b0: Device mode + * - 1'b1: Host mode + * Reset: + * - 1'b1 in Host-only mode (OTG_MODE=5 or 6) + * - 1'b0 in all other configurations + * Note: The reset value of this register field can be read only after the PHY clock + * is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to + * read the correct reset value which ever event is later. + */ +#define USB_OTGFS_GOTGCTL_CURMOD (BIT(21)) +#define USB_OTGFS_GOTGCTL_CURMOD_M (USB_OTGFS_GOTGCTL_CURMOD_V << USB_OTGFS_GOTGCTL_CURMOD_S) +#define USB_OTGFS_GOTGCTL_CURMOD_V 0x00000001U +#define USB_OTGFS_GOTGCTL_CURMOD_S 21 + +/** USB_OTGFS_GOTGINT_REG register + * OTG Interrupt Register The application reads this register whenever there is an OTG + * interrupt and clears the bits in this register to clear the OTG interrupt. + */ +#define USB_OTGFS_GOTGINT_REG(i) (DR_REG_USB_BASE(i) + 0x4) +/** USB_OTGFS_GOTGINT_SESENDDET : R/W; bitpos: [2]; default: 0; + * Mode: Host and Device + * Session End Detected (SesEndDet) + * The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit + * can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_SESENDDET (BIT(2)) +#define USB_OTGFS_GOTGINT_SESENDDET_M (USB_OTGFS_GOTGINT_SESENDDET_V << USB_OTGFS_GOTGINT_SESENDDET_S) +#define USB_OTGFS_GOTGINT_SESENDDET_V 0x00000001U +#define USB_OTGFS_GOTGINT_SESENDDET_S 2 +/** USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG : R/W; bitpos: [8]; default: 0; + * Mode: Host and Device + * Session Request Success Status Change (SesReqSucStsChng) + * The core sets this bit on the success or failure of a session request. The + * application must read the Session Request Success bit in the OTG Control and Status + * register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set + * only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG (BIT(8)) +#define USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG_M (USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG_V << USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG_S) +#define USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG_V 0x00000001U +#define USB_OTGFS_GOTGINT_SESREQSUCSTSCHNG_S 8 +/** USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG : R/W; bitpos: [9]; default: 0; + * Mode: Host and Device + * Host Negotiation Success Status Change (HstNegSucStsChng) + * The core sets this bit on the success or failure of a USB host negotiation request. + * The application must read the Host Negotiation Success bit of the OTG Control and + * Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can + * be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG (BIT(9)) +#define USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG_M (USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG_V << USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG_S) +#define USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG_V 0x00000001U +#define USB_OTGFS_GOTGINT_HSTNEGSUCSTSCHNG_S 9 +/** USB_OTGFS_GOTGINT_HSTNEGDET : R/W; bitpos: [17]; default: 0; + * Mode:Host and Device + * Host Negotiation Detected (HstNegDet) + * The core sets this bit when it detects a host negotiation request on the USB. This + * bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_HSTNEGDET (BIT(17)) +#define USB_OTGFS_GOTGINT_HSTNEGDET_M (USB_OTGFS_GOTGINT_HSTNEGDET_V << USB_OTGFS_GOTGINT_HSTNEGDET_S) +#define USB_OTGFS_GOTGINT_HSTNEGDET_V 0x00000001U +#define USB_OTGFS_GOTGINT_HSTNEGDET_S 17 +/** USB_OTGFS_GOTGINT_ADEVTOUTCHG : R/W; bitpos: [18]; default: 0; + * Mode: Host and Device + * A-Device Timeout Change (ADevTOUTChg) + * The core sets this bit to indicate that the A-device has timed out while waiting + * for the B-device to connect.This bit can be set only by the core and the + * application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_ADEVTOUTCHG (BIT(18)) +#define USB_OTGFS_GOTGINT_ADEVTOUTCHG_M (USB_OTGFS_GOTGINT_ADEVTOUTCHG_V << USB_OTGFS_GOTGINT_ADEVTOUTCHG_S) +#define USB_OTGFS_GOTGINT_ADEVTOUTCHG_V 0x00000001U +#define USB_OTGFS_GOTGINT_ADEVTOUTCHG_S 18 +/** USB_OTGFS_GOTGINT_DBNCEDONE : R/W; bitpos: [19]; default: 0; + * Mode: Host only + * Debounce Done (DbnceDone) + * The core sets this bit when the debounce is completed after the device connect. The + * application can start driving USB reset after seeing this interrupt. This bit is + * only valid when the HNP Capable or SRP Capable bit is SET in the Core USB + * Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit + * can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GOTGINT_DBNCEDONE (BIT(19)) +#define USB_OTGFS_GOTGINT_DBNCEDONE_M (USB_OTGFS_GOTGINT_DBNCEDONE_V << USB_OTGFS_GOTGINT_DBNCEDONE_S) +#define USB_OTGFS_GOTGINT_DBNCEDONE_V 0x00000001U +#define USB_OTGFS_GOTGINT_DBNCEDONE_S 19 + +/** USB_OTGFS_GAHBCFG_REG register + * AHB Configuration Register This register can be used to configure the core after + * power-on or a change in mode. This register mainly contains AHB system-related + * configuration parameters. Do not change this register after the initial + * programming. The application must program this register before starting any + * transactions on either the AHB or the USB. + */ +#define USB_OTGFS_GAHBCFG_REG(i) (DR_REG_USB_BASE(i) + 0x8) +/** USB_OTGFS_GAHBCFG_GLBLINTRMSK : R/W; bitpos: [0]; default: 0; + * Mode: Host and device + * Global Interrupt Mask (GlblIntrMsk) + * The application uses this bit to mask or unmask the interrupt line assertion to + * itself. Irrespective of this bit's setting, the interrupt status registers are + * updated by the controller. + * - 1'b0: Mask the interrupt assertion to the application. + * - 1'b1: Unmask the interrupt assertion to the application. + */ +#define USB_OTGFS_GAHBCFG_GLBLINTRMSK (BIT(0)) +#define USB_OTGFS_GAHBCFG_GLBLINTRMSK_M (USB_OTGFS_GAHBCFG_GLBLINTRMSK_V << USB_OTGFS_GAHBCFG_GLBLINTRMSK_S) +#define USB_OTGFS_GAHBCFG_GLBLINTRMSK_V 0x00000001U +#define USB_OTGFS_GAHBCFG_GLBLINTRMSK_S 0 +/** USB_OTGFS_GAHBCFG_HBSTLEN : R/W; bitpos: [4:1]; default: 0; + * Mode: Host and device + * Burst Length/Type (HBstLen) + * This field is used in both External and Internal DMA modes. In External DMA mode, + * these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper + * to interface the External DMA Controller interface to Synopsis DW_ahb_dmac or ARM + * PrimeCell. + * External DMA Mode defines the DMA burst length in terms of 32-bit words: + * - 4'b0000: 1 word + * - 4'b0001: 4 words + * - 4'b0010: 8 words + * - 4'b0011: 16 words + * - 4'b0100: 32 words + * - 4'b0101: 64 words + * - 4'b0110: 128 words + * - 4'b0111: 256 words + * - Others: Reserved + * Internal DMA Mode AHB Master burst type: + * - 4'b0000 Single + * - 4'b0001 INCR + * - 4'b0011 INCR4 + * - 4'b0101 INCR8 + * - 4'b0111 INCR16 + * - Others: Reserved + */ +#define USB_OTGFS_GAHBCFG_HBSTLEN 0x0000000FU +#define USB_OTGFS_GAHBCFG_HBSTLEN_M (USB_OTGFS_GAHBCFG_HBSTLEN_V << USB_OTGFS_GAHBCFG_HBSTLEN_S) +#define USB_OTGFS_GAHBCFG_HBSTLEN_V 0x0000000FU +#define USB_OTGFS_GAHBCFG_HBSTLEN_S 1 +/** USB_OTGFS_GAHBCFG_DMAEN : R/W; bitpos: [5]; default: 0; + * Mode: Host and device + * DMA Enable (DMAEn) + * + * This bit is always 0 when Slave-Only mode has been selected. + * + * Reset: 1'b0 + */ +#define USB_OTGFS_GAHBCFG_DMAEN (BIT(5)) +#define USB_OTGFS_GAHBCFG_DMAEN_M (USB_OTGFS_GAHBCFG_DMAEN_V << USB_OTGFS_GAHBCFG_DMAEN_S) +#define USB_OTGFS_GAHBCFG_DMAEN_V 0x00000001U +#define USB_OTGFS_GAHBCFG_DMAEN_S 5 +/** USB_OTGFS_GAHBCFG_NPTXFEMPLVL : R/W; bitpos: [7]; default: 0; + * Mode: Host and device + * Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + * This bit is used only in Slave mode. In host mode and with Shared FIFO with device + * mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the + * Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. + * With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit + * FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. + * Host mode and with Shared FIFO with device mode: + * - 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half + * empty + * - 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is + * completely empty + * Dedicated FIFO in device mode: + * - 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half + * empty + * - 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is + * completely empty + */ +#define USB_OTGFS_GAHBCFG_NPTXFEMPLVL (BIT(7)) +#define USB_OTGFS_GAHBCFG_NPTXFEMPLVL_M (USB_OTGFS_GAHBCFG_NPTXFEMPLVL_V << USB_OTGFS_GAHBCFG_NPTXFEMPLVL_S) +#define USB_OTGFS_GAHBCFG_NPTXFEMPLVL_V 0x00000001U +#define USB_OTGFS_GAHBCFG_NPTXFEMPLVL_S 7 +/** USB_OTGFS_GAHBCFG_PTXFEMPLVL : R/W; bitpos: [8]; default: 0; + * Mode: Host only + * Periodic TxFIFO Empty Level (PTxFEmpLvl) + * Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt + * register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode. + * - 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty + * - 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely + * empty + */ +#define USB_OTGFS_GAHBCFG_PTXFEMPLVL (BIT(8)) +#define USB_OTGFS_GAHBCFG_PTXFEMPLVL_M (USB_OTGFS_GAHBCFG_PTXFEMPLVL_V << USB_OTGFS_GAHBCFG_PTXFEMPLVL_S) +#define USB_OTGFS_GAHBCFG_PTXFEMPLVL_V 0x00000001U +#define USB_OTGFS_GAHBCFG_PTXFEMPLVL_S 8 +/** USB_OTGFS_GAHBCFG_REMMEMSUPP : R/W; bitpos: [21]; default: 0; + * Mode: Host and Device + * Remote Memory Support (RemMemSupp) + * This bit is programmed to enable the functionality to wait for the system DMA Done + * Signal for the DMA Write Transfers. + * - GAHBCFG.RemMemSupp=1 + * The int_dma_req output signal is asserted when the DMA starts write transfer to the + * external memory. When the core is done with the Transfers it asserts int_dma_done + * signal to flag the completion of DMA writes from the controller. The core then + * waits for sys_dma_done signal from the system to proceed further and complete the + * Data Transfer corresponding to a particular Channel/Endpoint. + * - GAHBCFG.RemMemSupp=0 + * The int_dma_req and int_dma_done signals are not asserted and the core proceeds + * with the assertion of the XferComp interrupt as soon as the DMA write transfer is + * done at the Core Boundary and it does not wait for the sys_dma_done signal to + * complete the DATA transfers. + */ +#define USB_OTGFS_GAHBCFG_REMMEMSUPP (BIT(21)) +#define USB_OTGFS_GAHBCFG_REMMEMSUPP_M (USB_OTGFS_GAHBCFG_REMMEMSUPP_V << USB_OTGFS_GAHBCFG_REMMEMSUPP_S) +#define USB_OTGFS_GAHBCFG_REMMEMSUPP_V 0x00000001U +#define USB_OTGFS_GAHBCFG_REMMEMSUPP_S 21 +/** USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT : R/W; bitpos: [22]; default: 0; + * Mode: Host and Device + * Notify All DMA Write Transactions (NotiAllDmaWrit) + * This bit is programmed to enable the System DMA Done functionality for all the DMA + * write Transactions corresponding to the Channel/Endpoint. This bit is valid only + * when GAHBCFG.RemMemSupp is set to 1. + * - GAHBCFG.NotiAllDmaWrit = 1 + * The core asserts int_dma_req for all the DMA write transactions on the AHB + * interface along with int_dma_done, chep_last_transact and chep_number signal + * information. The core waits for sys_dma_done signal for all the DMA write + * transactions in order to complete the transfer of a particular Channel/Endpoint. + * - GAHBCFG.NotiAllDmaWrit = 0 + * The core asserts int_dma_req signal only for the last transaction of DMA write + * transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits + * for sys_dma_done signal only for that transaction of DMA write to complete the + * transfer of a particular Channel/Endpoint. + */ +#define USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT (BIT(22)) +#define USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT_M (USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT_V << USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT_S) +#define USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT_V 0x00000001U +#define USB_OTGFS_GAHBCFG_NOTIALLDMAWRIT_S 22 +/** USB_OTGFS_GAHBCFG_AHBSINGLE : R/W; bitpos: [23]; default: 0; + * Mode: Host and Device + * AHB Single Support (AHBSingle) + * This bit when programmed supports Single transfers for the remaining data in a + * transfer when the core is operating in DMA mode. + * - 1'b0: The remaining data in the transfer is sent using INCR burst size. + * - 1'b1: The remaining data in the transfer is sent using Single burst size. + * Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR + * burst type. Enable this feature when the AHB Slave connected to the core does not + * support INCR burst (and when Split, and Retry transactions are not being used in + * the bus). + */ +#define USB_OTGFS_GAHBCFG_AHBSINGLE (BIT(23)) +#define USB_OTGFS_GAHBCFG_AHBSINGLE_M (USB_OTGFS_GAHBCFG_AHBSINGLE_V << USB_OTGFS_GAHBCFG_AHBSINGLE_S) +#define USB_OTGFS_GAHBCFG_AHBSINGLE_V 0x00000001U +#define USB_OTGFS_GAHBCFG_AHBSINGLE_S 23 +/** USB_OTGFS_GAHBCFG_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0; + * Mode: Host and Device + * Invert Descriptor Endianness (InvDescEndianess) + * - 1'b0: Descriptor Endianness is same as AHB Master Endianness. + * - 1'b1: + * -- If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little + * Endian. + * -- If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big + * Endian. + */ +#define USB_OTGFS_GAHBCFG_INVDESCENDIANESS (BIT(24)) +#define USB_OTGFS_GAHBCFG_INVDESCENDIANESS_M (USB_OTGFS_GAHBCFG_INVDESCENDIANESS_V << USB_OTGFS_GAHBCFG_INVDESCENDIANESS_S) +#define USB_OTGFS_GAHBCFG_INVDESCENDIANESS_V 0x00000001U +#define USB_OTGFS_GAHBCFG_INVDESCENDIANESS_S 24 + +/** USB_OTGFS_GUSBCFG_REG register + * USB Configuration Register This register can be used to configure the core after + * power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY + * related configuration parameters. The application must program this register before + * starting any transactions on either the AHB or the USB. Do not make changes to this + * register after the initial programming. + */ +#define USB_OTGFS_GUSBCFG_REG(i) (DR_REG_USB_BASE(i) + 0xc) +/** USB_OTGFS_GUSBCFG_TOUTCAL : R/W; bitpos: [2:0]; default: 0; + * Mode: Host and Device + * HS/FS Timeout Calibration (TOutCal) + * + * The number of PHY clocks that the application programs in this field is added to + * the high-speed/full-speed interpacket timeout duration in the core to account for + * any additional delays introduced by the PHY. This can be required, because the + * delay introduced by the PHY in generating the linestate condition can vary from one + * PHY to another. + * + * The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) + * bit times. The USB standard timeout value for full-speed operation is 16 to 18 + * (inclusive) bit times. The application must program this field based on the speed + * of enumeration. The number of bit times added per PHY clock are as follows: + * + * High-speed operation: + * - One 30-MHz PHY clock = 16 bit times + * - One 60-MHz PHY clock = 8 bit times + * Full-speed operation: + * - One 30-MHz PHY clock = 0.4 bit times + * - One 60-MHz PHY clock = 0.2 bit times + * - One 48-MHz PHY clock = 0.25 bit times + */ +#define USB_OTGFS_GUSBCFG_TOUTCAL 0x00000007U +#define USB_OTGFS_GUSBCFG_TOUTCAL_M (USB_OTGFS_GUSBCFG_TOUTCAL_V << USB_OTGFS_GUSBCFG_TOUTCAL_S) +#define USB_OTGFS_GUSBCFG_TOUTCAL_V 0x00000007U +#define USB_OTGFS_GUSBCFG_TOUTCAL_S 0 +/** USB_OTGFS_GUSBCFG_PHYIF : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * PHY Interface (PHYIf) + * The application uses this bit to configure the core to support a UTMI+ PHY with an + * 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode. + * - 1'b0: 8 bits + * - 1'b1: 16 bits + * This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit + * returns the value for the power-on interface selected during configuration. + */ +#define USB_OTGFS_GUSBCFG_PHYIF (BIT(3)) +#define USB_OTGFS_GUSBCFG_PHYIF_M (USB_OTGFS_GUSBCFG_PHYIF_V << USB_OTGFS_GUSBCFG_PHYIF_S) +#define USB_OTGFS_GUSBCFG_PHYIF_V 0x00000001U +#define USB_OTGFS_GUSBCFG_PHYIF_S 3 +/** USB_OTGFS_GUSBCFG_FSINTF : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * Full-Speed Serial Interface Select (FSIntf) + * + * The application uses this bit to select either a unidirectional or bidirectional + * USB 1.1 full-speed serial transceiver interface. + * - 1'b0: 6-pin unidirectional full-speed serial interface + * - 1'b1: 3-pin bidirectional full-speed serial interface + * If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is + * always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the + * application can Set this bit to select between the 3- and 6-pin interfaces, and + * access is Read and Write. + * + * Note: For supporting the new 4-pin bi-directional interface, you need to select + * 6-pin unidirectional FS serial mode, and add an external control to convert it to a + * 4-pin interface. + */ +#define USB_OTGFS_GUSBCFG_FSINTF (BIT(5)) +#define USB_OTGFS_GUSBCFG_FSINTF_M (USB_OTGFS_GUSBCFG_FSINTF_V << USB_OTGFS_GUSBCFG_FSINTF_S) +#define USB_OTGFS_GUSBCFG_FSINTF_V 0x00000001U +#define USB_OTGFS_GUSBCFG_FSINTF_S 5 +/** USB_OTGFS_GUSBCFG_PHYSEL : RO; bitpos: [6]; default: 1; + * PHYSel + * + * Mode: Host and Device + * + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel) + * The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a + * full-speed transceiver. + * - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY + * - 1'b1: USB 1.1 full-speed serial transceiver + * If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit + * is always 0, with Write Only access. + * If a high-speed PHY interface was not selected in, this bit is always 1, with Write + * Only access. + * If both interface types were selected (parameters have non-zero values), the + * application uses this bit to select which interface is active, and access is Read + * and Write. + */ +#define USB_OTGFS_GUSBCFG_PHYSEL (BIT(6)) +#define USB_OTGFS_GUSBCFG_PHYSEL_M (USB_OTGFS_GUSBCFG_PHYSEL_V << USB_OTGFS_GUSBCFG_PHYSEL_S) +#define USB_OTGFS_GUSBCFG_PHYSEL_V 0x00000001U +#define USB_OTGFS_GUSBCFG_PHYSEL_S 6 +/** USB_OTGFS_GUSBCFG_SRPCAP : R/W; bitpos: [8]; default: 0; + * Mode: Host and Device + * SRP-Capable (SRPCap) + * The application uses this bit to control the controller's SRP capabilities. If the + * core operates as a non-SRP-capable B-device, it cannot request the connected + * A-device (host) to + * activate VBUS and start a session. + * - 1'b0: SRP capability is not enabled. + * - 1'b1: SRP capability is enabled. + * If SRP functionality is disabled by the software, the OTG signals on the PHY domain + * must be tied to the appropriate values. + */ +#define USB_OTGFS_GUSBCFG_SRPCAP (BIT(8)) +#define USB_OTGFS_GUSBCFG_SRPCAP_M (USB_OTGFS_GUSBCFG_SRPCAP_V << USB_OTGFS_GUSBCFG_SRPCAP_S) +#define USB_OTGFS_GUSBCFG_SRPCAP_V 0x00000001U +#define USB_OTGFS_GUSBCFG_SRPCAP_S 8 +/** USB_OTGFS_GUSBCFG_HNPCAP : R/W; bitpos: [9]; default: 0; + * Mode: Host and Device + * HNP-Capable (HNPCap) + * The application uses this bit to control the controller's HNP capabilities. + * - 1'b0: HNP capability is not enabled. + * - 1'b1: HNP capability is enabled. + * If HNP functionality is disabled by the software, the OTG signals on the PHY domain + * must be tied to the appropriate values. + */ +#define USB_OTGFS_GUSBCFG_HNPCAP (BIT(9)) +#define USB_OTGFS_GUSBCFG_HNPCAP_M (USB_OTGFS_GUSBCFG_HNPCAP_V << USB_OTGFS_GUSBCFG_HNPCAP_S) +#define USB_OTGFS_GUSBCFG_HNPCAP_V 0x00000001U +#define USB_OTGFS_GUSBCFG_HNPCAP_S 9 +/** USB_OTGFS_GUSBCFG_USBTRDTIM : R/W; bitpos: [13:10]; default: 5; + * Mode: Device only + * USB Turnaround Time (USBTrdTim) + * Sets the turnaround time in PHY clocks. Specifies the response time for a MAC + * request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). + * This must be programmed to + * - 4'h5: When the MAC interface is 16-bit UTMI+ . + * - 4'h9: When the MAC interface is 8-bit UTMI+ . + * Note: The previous values are calculated for the minimum AHB frequency of 30 MHz. + * USB turnaround time is critical for certification where long cables and 5-Hubs are + * used. If you need the AHB to run at less than 30 MHz, and if USB turnaround time is + * not critical, these bits can be programmed to a larger value. + */ +#define USB_OTGFS_GUSBCFG_USBTRDTIM 0x0000000FU +#define USB_OTGFS_GUSBCFG_USBTRDTIM_M (USB_OTGFS_GUSBCFG_USBTRDTIM_V << USB_OTGFS_GUSBCFG_USBTRDTIM_S) +#define USB_OTGFS_GUSBCFG_USBTRDTIM_V 0x0000000FU +#define USB_OTGFS_GUSBCFG_USBTRDTIM_S 10 +/** USB_OTGFS_GUSBCFG_TERMSELDLPULSE : RO; bitpos: [22]; default: 0; + * Mode: Device only + * TermSel DLine Pulsing Selection (TermSelDLPulse) + * This bit selects utmi_termselect to drive data line pulse during SRP. + * - 1'b0: Data line pulsing using utmi_txvalid (Default). + * - 1'b1: Data line pulsing using utmi_termsel. + */ +#define USB_OTGFS_GUSBCFG_TERMSELDLPULSE (BIT(22)) +#define USB_OTGFS_GUSBCFG_TERMSELDLPULSE_M (USB_OTGFS_GUSBCFG_TERMSELDLPULSE_V << USB_OTGFS_GUSBCFG_TERMSELDLPULSE_S) +#define USB_OTGFS_GUSBCFG_TERMSELDLPULSE_V 0x00000001U +#define USB_OTGFS_GUSBCFG_TERMSELDLPULSE_S 22 +/** USB_OTGFS_GUSBCFG_IC_USBCAP : RO; bitpos: [26]; default: 0; + * Mode: Host and Device + * IC_USB-Capable (IC_USBCap) + * The application uses this bit to control the core's IC_USB capabilities. + * - 1'b0: IC_USB PHY Interface is not selected. + * - 1'b1: IC_USB PHY Interface is selected. + * This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0. + * The reset value depends on the configuration parameter OTG_SELECT_IC_USB when + * OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is + * read only. + */ +#define USB_OTGFS_GUSBCFG_IC_USBCAP (BIT(26)) +#define USB_OTGFS_GUSBCFG_IC_USBCAP_M (USB_OTGFS_GUSBCFG_IC_USBCAP_V << USB_OTGFS_GUSBCFG_IC_USBCAP_S) +#define USB_OTGFS_GUSBCFG_IC_USBCAP_V 0x00000001U +#define USB_OTGFS_GUSBCFG_IC_USBCAP_S 26 +/** USB_OTGFS_GUSBCFG_TXENDDELAY : R/W; bitpos: [28]; default: 0; + * Mode: Device only + * Tx End Delay (TxEndDelay) + * Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as + * per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup. + * - 1'b0 : Normal Mode. + * - 1'b1 : Tx End delay. + */ +#define USB_OTGFS_GUSBCFG_TXENDDELAY (BIT(28)) +#define USB_OTGFS_GUSBCFG_TXENDDELAY_M (USB_OTGFS_GUSBCFG_TXENDDELAY_V << USB_OTGFS_GUSBCFG_TXENDDELAY_S) +#define USB_OTGFS_GUSBCFG_TXENDDELAY_V 0x00000001U +#define USB_OTGFS_GUSBCFG_TXENDDELAY_S 28 +/** USB_OTGFS_GUSBCFG_FORCEHSTMODE : R/W; bitpos: [29]; default: 0; + * Mode: Host and device + * Force Host Mode (ForceHstMode) + * Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig + * input pin. + * - 1'b0 : Normal Mode. + * - 1'b1 : Force Host Mode. + * After setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for 500 + * micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all + * other cases, this bit reads 0. + */ +#define USB_OTGFS_GUSBCFG_FORCEHSTMODE (BIT(29)) +#define USB_OTGFS_GUSBCFG_FORCEHSTMODE_M (USB_OTGFS_GUSBCFG_FORCEHSTMODE_V << USB_OTGFS_GUSBCFG_FORCEHSTMODE_S) +#define USB_OTGFS_GUSBCFG_FORCEHSTMODE_V 0x00000001U +#define USB_OTGFS_GUSBCFG_FORCEHSTMODE_S 29 +/** USB_OTGFS_GUSBCFG_FORCEDEVMODE : R/W; bitpos: [30]; default: 0; + * Mode:Host and device + * Force Device Mode (ForceDevMode) + * Writing a 1 to this bit forces the controller to device mode irrespective of + * utmiotg_iddig input pin. + * - 1'b0 : Normal Mode. + * - 1'b1 : Force Device Mode. + * After setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for 500 + * micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all + * other cases, this bit reads 0. + */ +#define USB_OTGFS_GUSBCFG_FORCEDEVMODE (BIT(30)) +#define USB_OTGFS_GUSBCFG_FORCEDEVMODE_M (USB_OTGFS_GUSBCFG_FORCEDEVMODE_V << USB_OTGFS_GUSBCFG_FORCEDEVMODE_S) +#define USB_OTGFS_GUSBCFG_FORCEDEVMODE_V 0x00000001U +#define USB_OTGFS_GUSBCFG_FORCEDEVMODE_S 30 +/** USB_OTGFS_GUSBCFG_CORRUPTTXPKT : R/W; bitpos: [31]; default: 0; + * Mode: Host and device + * Corrupt Tx packet (CorruptTxPkt) + * This bit is for debug purposes only. Never Set this bit to 1. The application + * should always write 1'b0 to this bit. + */ +#define USB_OTGFS_GUSBCFG_CORRUPTTXPKT (BIT(31)) +#define USB_OTGFS_GUSBCFG_CORRUPTTXPKT_M (USB_OTGFS_GUSBCFG_CORRUPTTXPKT_V << USB_OTGFS_GUSBCFG_CORRUPTTXPKT_S) +#define USB_OTGFS_GUSBCFG_CORRUPTTXPKT_V 0x00000001U +#define USB_OTGFS_GUSBCFG_CORRUPTTXPKT_S 31 + +/** USB_OTGFS_GRSTCTL_REG register + * Reset Register The application uses this register to reset various hardware + * features inside the controller. + */ +#define USB_OTGFS_GRSTCTL_REG(i) (DR_REG_USB_BASE(i) + 0x10) +/** USB_OTGFS_GRSTCTL_CSFTRST : R/W; bitpos: [0]; default: 0; + * Mode: Host and Device + * Core Soft Reset (CSftRst) + * Resets the hclk and phy_clock domains as follows: + * - Clears the interrupts and all the CSR registers except the following register + * bits: + * -- PCGCCTL.RstPdwnModule + * -- PCGCCTL.GateHclk + * -- PCGCCTL.PwrClmp + * -- PCGCCTL.StopPPhyLPwrClkSelclk + * -- GUSBCFG.ForceDevMode + * -- GUSBCFG.ForceHstMode + * -- GUSBCFG.PhyLPwrClkSel + * -- GUSBCFG.DDRSel + * -- GUSBCFG.PHYSel + * -- GUSBCFG.FSIntf + * -- GUSBCFG.ULPI_UTMI_Sel + * -- GUSBCFG.TxEndDelay + * -- GUSBCFG.TermSelDLPulse + * -- GUSBCFG.ULPIClkSusM + * -- GUSBCFG.ULPIAutoRes + * -- GUSBCFG.ULPIFsLs + * -- GGPIO + * -- GPWRDN + * -- GADPCTL + * -- HCFG.FSLSPclkSel + * -- DCFG.DevSpd + * -- DCTL.SftDiscon + * - All module state machines + * - All module state machines (except the AHB Slave Unit) are reset to the IDLE + * state, and all the transmit FIFOs and the receive FIFO are flushed. + * - Any transactions on the AHB Master are terminated as soon as possible, after + * gracefully completing the last data phase of an AHB transfer. Any transactions on + * the USB are terminated immediately. + * - When Hibernation or ADP feature is enabled, the PMU module is not reset by the + * Core Soft Reset. + * The application can write to this bit any time it wants to reset the core. This is + * a self-clearing bit and the core clears this bit after + * all the necessary logic is reset in the core, which can take several clocks, + * depending on the current state of the core. Once this bit is cleared software must + * wait at least 3 PHY clocks before doing any access to the PHY domain + * (synchronization delay). Software must also must check that bit 31 of this register + * is 1 (AHB Master is IDLE) before starting any operation. + * + * Typically software reset is used during software development and also when you + * dynamically change the PHY selection bits in the USB configuration registers listed + * above. When you change the PHY, the corresponding clock for the PHY is selected and + * used in the PHY domain. Once a new clock is selected, the PHY domain has to be + * reset for proper operation. + */ +#define USB_OTGFS_GRSTCTL_CSFTRST (BIT(0)) +#define USB_OTGFS_GRSTCTL_CSFTRST_M (USB_OTGFS_GRSTCTL_CSFTRST_V << USB_OTGFS_GRSTCTL_CSFTRST_S) +#define USB_OTGFS_GRSTCTL_CSFTRST_V 0x00000001U +#define USB_OTGFS_GRSTCTL_CSFTRST_S 0 +/** USB_OTGFS_GRSTCTL_PIUFSSFTRST : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + * + * Resets the PIU FS Dedicated Controller + * All module state machines in FS Dedicated Controller of PIU are reset to the IDLE + * state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors + * like Loss of activity or Babble Error resulting in the PHY remaining in RX state + * for more than one frame boundary. + * This is a self clearing bit and core clears this bit after all the necessary logic + * is reset in the core. + */ +#define USB_OTGFS_GRSTCTL_PIUFSSFTRST (BIT(1)) +#define USB_OTGFS_GRSTCTL_PIUFSSFTRST_M (USB_OTGFS_GRSTCTL_PIUFSSFTRST_V << USB_OTGFS_GRSTCTL_PIUFSSFTRST_S) +#define USB_OTGFS_GRSTCTL_PIUFSSFTRST_V 0x00000001U +#define USB_OTGFS_GRSTCTL_PIUFSSFTRST_S 1 +/** USB_OTGFS_GRSTCTL_FRMCNTRRST : R/W; bitpos: [2]; default: 0; + * Mode: Host only + * Host Frame Counter Reset (FrmCntrRst) + * The application writes this bit to reset the (micro)Frame number counter inside the + * core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the + * core has a (micro)Frame number of 0. + * When application writes 1 to the bit, it might not be able to read back the value + * as it will get cleared by the core in a few clock cycles. + */ +#define USB_OTGFS_GRSTCTL_FRMCNTRRST (BIT(2)) +#define USB_OTGFS_GRSTCTL_FRMCNTRRST_M (USB_OTGFS_GRSTCTL_FRMCNTRRST_V << USB_OTGFS_GRSTCTL_FRMCNTRRST_S) +#define USB_OTGFS_GRSTCTL_FRMCNTRRST_V 0x00000001U +#define USB_OTGFS_GRSTCTL_FRMCNTRRST_S 2 +/** USB_OTGFS_GRSTCTL_RXFFLSH : R/W; bitpos: [4]; default: 0; + * Mode: Host and Device + * RxFIFO Flush (RxFFlsh) + * The application can flush the entire RxFIFO using this bit, but must first ensure + * that the core is not in the middle of a transaction. + * The application must only write to this bit after checking that the controller is + * neither reading from the RxFIFO nor writing to the RxFIFO. + * + * The application must wait until the bit is cleared before performing any other + * operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear. + */ +#define USB_OTGFS_GRSTCTL_RXFFLSH (BIT(4)) +#define USB_OTGFS_GRSTCTL_RXFFLSH_M (USB_OTGFS_GRSTCTL_RXFFLSH_V << USB_OTGFS_GRSTCTL_RXFFLSH_S) +#define USB_OTGFS_GRSTCTL_RXFFLSH_V 0x00000001U +#define USB_OTGFS_GRSTCTL_RXFFLSH_S 4 +/** USB_OTGFS_GRSTCTL_TXFFLSH : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * TxFIFO Flush (TxFFlsh) + * This bit selectively flushes a single or all transmit FIFOs, but cannot do so If + * the core is in the midst of a transaction. + * The application must write this bit only after checking that the core is neither + * writing to the TxFIFO nor reading from the TxFIFO. + * Verify using these registers: + * - ReadNAK Effective Interrupt ensures the core is not reading from the FIFO + * - WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO. + * Flushing is normally recommended when FIFOs are reconfigured or when switching + * between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also + * recommended during device endpoint disable. The application must wait until the + * core clears this bit before performing any operations. This bit takes eight clocks + * to clear, using the slower clock of phy_clk or hclk. + */ +#define USB_OTGFS_GRSTCTL_TXFFLSH (BIT(5)) +#define USB_OTGFS_GRSTCTL_TXFFLSH_M (USB_OTGFS_GRSTCTL_TXFFLSH_V << USB_OTGFS_GRSTCTL_TXFFLSH_S) +#define USB_OTGFS_GRSTCTL_TXFFLSH_V 0x00000001U +#define USB_OTGFS_GRSTCTL_TXFFLSH_S 5 +/** USB_OTGFS_GRSTCTL_TXFNUM : R/W; bitpos: [10:6]; default: 0; + * Mode: Host and Device + * TxFIFO Number (TxFNum) + * This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field + * must not be changed until the core clears the TxFIFO Flush bit. + * - 5'h0: + * -- Non-periodic TxFIFO flush in Host mode + * -- Non-periodic TxFIFO flush in device mode when in shared FIFO operation + * -- Tx FIFO 0 flush in device mode when in dedicated FIFO mode + * - 5'h1: + * -- Periodic TxFIFO flush in Host mode + * -- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation + * -- TXFIFO 1 flush in device mode when in dedicated FIFO mode + * - 5'h2: + * -- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation + * -- TXFIFO 2 flush in device mode when in dedicated FIFO mode + * ... + * - 5'hF + * -- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation + * -- TXFIFO 15 flush in device mode when in dedicated FIFO mode + * - 5'h10: Flush all the transmit FIFOs in device or host mode + */ +#define USB_OTGFS_GRSTCTL_TXFNUM 0x0000001FU +#define USB_OTGFS_GRSTCTL_TXFNUM_M (USB_OTGFS_GRSTCTL_TXFNUM_V << USB_OTGFS_GRSTCTL_TXFNUM_S) +#define USB_OTGFS_GRSTCTL_TXFNUM_V 0x0000001FU +#define USB_OTGFS_GRSTCTL_TXFNUM_S 6 +/** USB_OTGFS_GRSTCTL_DMAREQ : RO; bitpos: [30]; default: 0; + * Mode: Host and Device + * DMA Request Signal (DMAReq) + * Indicates that the DMA request is in progress. Used for debug. + */ +#define USB_OTGFS_GRSTCTL_DMAREQ (BIT(30)) +#define USB_OTGFS_GRSTCTL_DMAREQ_M (USB_OTGFS_GRSTCTL_DMAREQ_V << USB_OTGFS_GRSTCTL_DMAREQ_S) +#define USB_OTGFS_GRSTCTL_DMAREQ_V 0x00000001U +#define USB_OTGFS_GRSTCTL_DMAREQ_S 30 +/** USB_OTGFS_GRSTCTL_AHBIDLE : RO; bitpos: [31]; default: 1; + * Mode: Host and Device + * AHB Master Idle (AHBIdle) + * Indicates that the AHB Master State Machine is in the IDLE condition. + */ +#define USB_OTGFS_GRSTCTL_AHBIDLE (BIT(31)) +#define USB_OTGFS_GRSTCTL_AHBIDLE_M (USB_OTGFS_GRSTCTL_AHBIDLE_V << USB_OTGFS_GRSTCTL_AHBIDLE_S) +#define USB_OTGFS_GRSTCTL_AHBIDLE_V 0x00000001U +#define USB_OTGFS_GRSTCTL_AHBIDLE_S 31 + +/** USB_OTGFS_GINTSTS_REG register + * Interrupt Register This register interrupts the application for system-level + * events in the current mode (Device mode or Host mode). Some of the bits in this + * register are valid only in Host mode, while others are valid in Device mode only. + * This register also indicates the current mode. To clear the interrupt status bits + * of type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status + * interrupts are read only; once software reads from or writes to the FIFO while + * servicing these interrupts, FIFO interrupt conditions are cleared automatically. + * The application must clear the GINTSTS register at initialization before unmasking + * the interrupt bit to avoid any interrupts generated prior to initialization. Note: + * Read the reset value of GINTSTS.CurMod only after the following conditions: - If + * IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER + * is enabled, read only after the filter timer expires. + */ +#define USB_OTGFS_GINTSTS_REG(i) (DR_REG_USB_BASE(i) + 0x14) +/** USB_OTGFS_GINTSTS_CURMOD : RO; bitpos: [0]; default: 0; + * Mode: Host and Device + * Current Mode of Operation (CurMod) + * Indicates the current mode. + * - 1'b0: Device mode + * - 1'b1: Host mode + * + * + * Note: The reset value of this register field can be read only after the PHY clock + * is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to + * read the correct reset value which ever event is later. + */ +#define USB_OTGFS_GINTSTS_CURMOD (BIT(0)) +#define USB_OTGFS_GINTSTS_CURMOD_M (USB_OTGFS_GINTSTS_CURMOD_V << USB_OTGFS_GINTSTS_CURMOD_S) +#define USB_OTGFS_GINTSTS_CURMOD_V 0x00000001U +#define USB_OTGFS_GINTSTS_CURMOD_S 0 +/** USB_OTGFS_GINTSTS_MODEMIS : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * Mode Mismatch Interrupt (ModeMis) + * The core sets this bit when the application is trying to access: + * - A Host mode register, when the controller is operating in Device mode + * - A Device mode register, when the controller is operating in Host mode + * The register access is completed on the AHB with an OKAY response, but is ignored + * by the controller internally and does not affect the operation of the controller. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_GINTSTS_MODEMIS (BIT(1)) +#define USB_OTGFS_GINTSTS_MODEMIS_M (USB_OTGFS_GINTSTS_MODEMIS_V << USB_OTGFS_GINTSTS_MODEMIS_S) +#define USB_OTGFS_GINTSTS_MODEMIS_V 0x00000001U +#define USB_OTGFS_GINTSTS_MODEMIS_S 1 +/** USB_OTGFS_GINTSTS_OTGINT : RO; bitpos: [2]; default: 0; + * Mode: Host and Device + * OTG Interrupt (OTGInt) + * The controller sets this bit to indicate an OTG protocol event. The application + * must read the OTG Interrupt Status (GOTGINT) register to determine the exact event + * that caused this interrupt. The application must clear the appropriate status bit + * in the GOTGINT register to clear this bit. + */ +#define USB_OTGFS_GINTSTS_OTGINT (BIT(2)) +#define USB_OTGFS_GINTSTS_OTGINT_M (USB_OTGFS_GINTSTS_OTGINT_V << USB_OTGFS_GINTSTS_OTGINT_S) +#define USB_OTGFS_GINTSTS_OTGINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_OTGINT_S 2 +/** USB_OTGFS_GINTSTS_SOF : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * Start of (micro)Frame (Sof) + * + * In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), + * or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to + * this bit to clear the interrupt. + * + * In Device mode, the controller sets this bit to indicate that an SOF token has been + * received on the USB. The application can read the Device Status register to get the + * current (micro)Frame number. This interrupt is seen only when the core is operating + * at either HS or FS. This bit can be set only by the core and the application must + * write 1 to clear it. + * + * Note: This register may return 1'b1 if read immediately after power-on reset. + * If the register bit reads 1'b1 immediately after power-on reset, it does not + * indicate that an SOF has been sent (in case of host mode) or SOF has been received + * (in case of device mode). + * The read value of this interrupt is valid only after a valid connection between + * host and device is established. If the bit is set after power on reset the + * application can clear the bit. + */ +#define USB_OTGFS_GINTSTS_SOF (BIT(3)) +#define USB_OTGFS_GINTSTS_SOF_M (USB_OTGFS_GINTSTS_SOF_V << USB_OTGFS_GINTSTS_SOF_S) +#define USB_OTGFS_GINTSTS_SOF_V 0x00000001U +#define USB_OTGFS_GINTSTS_SOF_S 3 +/** USB_OTGFS_GINTSTS_RXFLVL : RO; bitpos: [4]; default: 0; + * Mode: Host and Device + * RxFIFO Non-Empty (RxFLvl) + * + * Indicates that there is at least one packet pending to be read from the RxFIFO. + */ +#define USB_OTGFS_GINTSTS_RXFLVL (BIT(4)) +#define USB_OTGFS_GINTSTS_RXFLVL_M (USB_OTGFS_GINTSTS_RXFLVL_V << USB_OTGFS_GINTSTS_RXFLVL_S) +#define USB_OTGFS_GINTSTS_RXFLVL_V 0x00000001U +#define USB_OTGFS_GINTSTS_RXFLVL_S 4 +/** USB_OTGFS_GINTSTS_NPTXFEMP : RO; bitpos: [5]; default: 1; + * Mode: Host and Device + * Non-periodic TxFIFO Empty (NPTxFEmp) + * This interrupt is asserted when the Non-periodic TxFIFO is either half or + * completely empty, and there is space for at least one Entry to be written to the + * Non-periodic Transmit Request Queue. The half or completely empty status is + * determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration + * register (GAHBCFG.NPTxFEmpLvl). + * In host mode, the application can use GINTSTS.NPTxFEmp with the OTG_EN_DED_TX_FIFO + * parameter set to either 1 or 0. + * In device mode, the application uses GINTSTS.NPTxFEmp when OTG_EN_DED_TX_FIFO=0. + * When OTG_EN_DED_TX_FIFO=1, the application uses DIEPINTn.TxFEmp. + */ +#define USB_OTGFS_GINTSTS_NPTXFEMP (BIT(5)) +#define USB_OTGFS_GINTSTS_NPTXFEMP_M (USB_OTGFS_GINTSTS_NPTXFEMP_V << USB_OTGFS_GINTSTS_NPTXFEMP_S) +#define USB_OTGFS_GINTSTS_NPTXFEMP_V 0x00000001U +#define USB_OTGFS_GINTSTS_NPTXFEMP_S 5 +/** USB_OTGFS_GINTSTS_GINNAKEFF : RO; bitpos: [6]; default: 0; + * Mode: Device only + * Global IN Non-periodic NAK Effective (GINNakEff) + * Indicates that the Set Global Non-periodic IN NAK bit in the Device Control + * register (DCTL.SGNPInNak) set by the application, has taken effect in the core. + * That is, the core has sampled the Global IN NAK bit Set by the application. This + * bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the + * Device Control register (DCTL.CGNPInNak). This interrupt does not necessarily mean + * that a NAK handshake + * is sent out on the USB. The STALL bit takes precedence over the NAK bit. + */ +#define USB_OTGFS_GINTSTS_GINNAKEFF (BIT(6)) +#define USB_OTGFS_GINTSTS_GINNAKEFF_M (USB_OTGFS_GINTSTS_GINNAKEFF_V << USB_OTGFS_GINTSTS_GINNAKEFF_S) +#define USB_OTGFS_GINTSTS_GINNAKEFF_V 0x00000001U +#define USB_OTGFS_GINTSTS_GINNAKEFF_S 6 +/** USB_OTGFS_GINTSTS_GOUTNAKEFF : RO; bitpos: [7]; default: 0; + * Mode: Device only + * Global OUT NAK Effective (GOUTNakEff) + * Indicates that the Set Global OUT NAK bit in the Device Control register + * (DCTL.SGOUTNak), Set by the application, has taken effect in the core. This bit can + * be cleared by writing the Clear Global OUT NAK bit in the Device Control register + * (DCTL.CGOUTNak). + */ +#define USB_OTGFS_GINTSTS_GOUTNAKEFF (BIT(7)) +#define USB_OTGFS_GINTSTS_GOUTNAKEFF_M (USB_OTGFS_GINTSTS_GOUTNAKEFF_V << USB_OTGFS_GINTSTS_GOUTNAKEFF_S) +#define USB_OTGFS_GINTSTS_GOUTNAKEFF_V 0x00000001U +#define USB_OTGFS_GINTSTS_GOUTNAKEFF_S 7 +/** USB_OTGFS_GINTSTS_ERLYSUSP : R/W; bitpos: [10]; default: 0; + * Mode: Device only + * Early Suspend (ErlySusp) + * The controller sets this bit to indicate that an Idle state has been detected on + * the USB for 3 ms. + */ +#define USB_OTGFS_GINTSTS_ERLYSUSP (BIT(10)) +#define USB_OTGFS_GINTSTS_ERLYSUSP_M (USB_OTGFS_GINTSTS_ERLYSUSP_V << USB_OTGFS_GINTSTS_ERLYSUSP_S) +#define USB_OTGFS_GINTSTS_ERLYSUSP_V 0x00000001U +#define USB_OTGFS_GINTSTS_ERLYSUSP_S 10 +/** USB_OTGFS_GINTSTS_USBSUSP : R/W; bitpos: [11]; default: 0; + * Mode: Device only + * USB Suspend (USBSusp) + * The controller sets this bit to indicate that a suspend was detected on the USB. + * The controller enters the Suspended state when there is no activity on the + * linestate signal for an extended period of time. + */ +#define USB_OTGFS_GINTSTS_USBSUSP (BIT(11)) +#define USB_OTGFS_GINTSTS_USBSUSP_M (USB_OTGFS_GINTSTS_USBSUSP_V << USB_OTGFS_GINTSTS_USBSUSP_S) +#define USB_OTGFS_GINTSTS_USBSUSP_V 0x00000001U +#define USB_OTGFS_GINTSTS_USBSUSP_S 11 +/** USB_OTGFS_GINTSTS_USBRST : R/W; bitpos: [12]; default: 0; + * Mode: Device only + * USB Reset (USBRst) + * The controller sets this bit to indicate that a reset is detected on the USB. + */ +#define USB_OTGFS_GINTSTS_USBRST (BIT(12)) +#define USB_OTGFS_GINTSTS_USBRST_M (USB_OTGFS_GINTSTS_USBRST_V << USB_OTGFS_GINTSTS_USBRST_S) +#define USB_OTGFS_GINTSTS_USBRST_V 0x00000001U +#define USB_OTGFS_GINTSTS_USBRST_S 12 +/** USB_OTGFS_GINTSTS_ENUMDONE : R/W; bitpos: [13]; default: 0; + * Mode: Device only + * Enumeration Done (EnumDone) + * The core sets this bit to indicate that speed enumeration is complete. The + * application must read the Device Status (DSTS) register to obtain the enumerated + * speed. + */ +#define USB_OTGFS_GINTSTS_ENUMDONE (BIT(13)) +#define USB_OTGFS_GINTSTS_ENUMDONE_M (USB_OTGFS_GINTSTS_ENUMDONE_V << USB_OTGFS_GINTSTS_ENUMDONE_S) +#define USB_OTGFS_GINTSTS_ENUMDONE_V 0x00000001U +#define USB_OTGFS_GINTSTS_ENUMDONE_S 13 +/** USB_OTGFS_GINTSTS_ISOOUTDROP : R/W; bitpos: [14]; default: 0; + * Mode: Device only + * Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + * The controller sets this bit when it fails to write an isochronous OUT packet into + * the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum + * packet size packet for the isochronous OUT endpoint. + */ +#define USB_OTGFS_GINTSTS_ISOOUTDROP (BIT(14)) +#define USB_OTGFS_GINTSTS_ISOOUTDROP_M (USB_OTGFS_GINTSTS_ISOOUTDROP_V << USB_OTGFS_GINTSTS_ISOOUTDROP_S) +#define USB_OTGFS_GINTSTS_ISOOUTDROP_V 0x00000001U +#define USB_OTGFS_GINTSTS_ISOOUTDROP_S 14 +/** USB_OTGFS_GINTSTS_EOPF : R/W; bitpos: [15]; default: 0; + * Mode: Device only + * End of Periodic Frame Interrupt (EOPF) + * Indicates that the period specified in the Periodic Frame Interval field of the + * Device Configuration register (DCFG.PerFrInt) has been reached in the current + * microframe. + */ +#define USB_OTGFS_GINTSTS_EOPF (BIT(15)) +#define USB_OTGFS_GINTSTS_EOPF_M (USB_OTGFS_GINTSTS_EOPF_V << USB_OTGFS_GINTSTS_EOPF_S) +#define USB_OTGFS_GINTSTS_EOPF_V 0x00000001U +#define USB_OTGFS_GINTSTS_EOPF_S 15 +/** USB_OTGFS_GINTSTS_EPMIS : R/W; bitpos: [17]; default: 0; + * Mode: Device only + * Endpoint Mismatch Interrupt (EPMis) + * Note: This interrupt is valid only in shared FIFO operation. + * Indicates that an IN token has been received for a non-periodic endpoint, but the + * data for another endpoint is present in the top of the Non-periodic Transmit FIFO + * and the IN endpoint mismatch count programmed by the application has expired. + */ +#define USB_OTGFS_GINTSTS_EPMIS (BIT(17)) +#define USB_OTGFS_GINTSTS_EPMIS_M (USB_OTGFS_GINTSTS_EPMIS_V << USB_OTGFS_GINTSTS_EPMIS_S) +#define USB_OTGFS_GINTSTS_EPMIS_V 0x00000001U +#define USB_OTGFS_GINTSTS_EPMIS_S 17 +/** USB_OTGFS_GINTSTS_IEPINT : RO; bitpos: [18]; default: 0; + * Mode: Device only + * IN Endpoints Interrupt (IEPInt) + * The core sets this bit to indicate that an interrupt is pending on one of the IN + * endpoints of the core (in Device mode). The application must read the Device All + * Endpoints Interrupt (DAINT) register to determine the exact number of the IN + * endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the + * exact cause of the interrupt. The application must clear the appropriate status bit + * in the corresponding DIEPINTn register to + * clear this bit. + */ +#define USB_OTGFS_GINTSTS_IEPINT (BIT(18)) +#define USB_OTGFS_GINTSTS_IEPINT_M (USB_OTGFS_GINTSTS_IEPINT_V << USB_OTGFS_GINTSTS_IEPINT_S) +#define USB_OTGFS_GINTSTS_IEPINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_IEPINT_S 18 +/** USB_OTGFS_GINTSTS_OEPINT : RO; bitpos: [19]; default: 0; + * Mode: Device only + * OUT Endpoints Interrupt (OEPInt) + * The controller sets this bit to indicate that an interrupt is pending on one of the + * OUT endpoints of the core (in Device mode). The application must read the Device + * All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT + * endpoint on which the interrupt occurred, and then read the corresponding Device + * OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the + * interrupt. The application must + * clear the appropriate status bit in the corresponding DOEPINTn register to clear + * this bit. + */ +#define USB_OTGFS_GINTSTS_OEPINT (BIT(19)) +#define USB_OTGFS_GINTSTS_OEPINT_M (USB_OTGFS_GINTSTS_OEPINT_V << USB_OTGFS_GINTSTS_OEPINT_S) +#define USB_OTGFS_GINTSTS_OEPINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_OEPINT_S 19 +/** USB_OTGFS_GINTSTS_INCOMPISOIN : R/W; bitpos: [20]; default: 0; + * Mode: Device only + * Incomplete Isochronous IN Transfer (incompISOIN) + * The core sets this interrupt to indicate that there is at least one isochronous IN + * endpoint on which the transfer is not completed in the current microframe. This + * interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in + * this register. + * Note: This interrupt is not asserted in Scatter/Gather DMA mode. + */ +#define USB_OTGFS_GINTSTS_INCOMPISOIN (BIT(20)) +#define USB_OTGFS_GINTSTS_INCOMPISOIN_M (USB_OTGFS_GINTSTS_INCOMPISOIN_V << USB_OTGFS_GINTSTS_INCOMPISOIN_S) +#define USB_OTGFS_GINTSTS_INCOMPISOIN_V 0x00000001U +#define USB_OTGFS_GINTSTS_INCOMPISOIN_S 20 +/** USB_OTGFS_GINTSTS_INCOMPLP : R/W; bitpos: [21]; default: 0; + * Incomplete Periodic Transfer (incomplP) + * Mode: Host only + * In Host mode, the core sets this interrupt bit when there are incomplete periodic + * transactions still pending which are scheduled for the current microframe. + * Incomplete Isochronous OUT Transfer (incompISOOUT) + * Mode: Device only + * The Device mode, the core sets this interrupt to indicate that there is at least + * one isochronous OUT endpoint on which the transfer is not completed in the current + * microframe. This interrupt is asserted along with the End of Periodic Frame + * Interrupt (EOPF) bit in this register. + */ +#define USB_OTGFS_GINTSTS_INCOMPLP (BIT(21)) +#define USB_OTGFS_GINTSTS_INCOMPLP_M (USB_OTGFS_GINTSTS_INCOMPLP_V << USB_OTGFS_GINTSTS_INCOMPLP_S) +#define USB_OTGFS_GINTSTS_INCOMPLP_V 0x00000001U +#define USB_OTGFS_GINTSTS_INCOMPLP_S 21 +/** USB_OTGFS_GINTSTS_FETSUSP : R/W; bitpos: [22]; default: 0; + * Mode: Device only + * Data Fetch Suspended (FetSusp) + * This interrupt is valid only in DMA mode. This interrupt indicates that the core + * has stopped fetching data. For IN endpoints due to the unavailability of TxFIFO + * space or Request Queue space. This interrupt is used by the application for an + * endpoint mismatch algorithm. + * + * For example, after detecting an endpoint mismatch, the application: + * - Sets a Global non-periodic IN NAK handshake + * - Disables IN endpoints + * - Flushes the FIFO + * - Determines the token sequence from the IN Token Sequence Learning Queue + * - Re-enables the endpoints + * - Clears the Global non-periodic IN NAK handshake + * If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for + * the IN endpoint, and the IN token is received. The core generates an 'IN token + * received when FIFO empty' interrupt. The DWC_otg then sends the host a NAK + * response. To avoid this scenario, the application can check the GINTSTS.FetSusp + * interrupt, which ensures that the FIFO is full before clearing a Global NAK + * handshake. + * + * Alternatively, the application can mask the IN token received when FIFO empty + * interrupt when clearing a Global IN NAK handshake. + */ +#define USB_OTGFS_GINTSTS_FETSUSP (BIT(22)) +#define USB_OTGFS_GINTSTS_FETSUSP_M (USB_OTGFS_GINTSTS_FETSUSP_V << USB_OTGFS_GINTSTS_FETSUSP_S) +#define USB_OTGFS_GINTSTS_FETSUSP_V 0x00000001U +#define USB_OTGFS_GINTSTS_FETSUSP_S 22 +/** USB_OTGFS_GINTSTS_RESETDET : R/W; bitpos: [23]; default: 0; + * Mode: Device only + * Reset detected Interrupt (ResetDet) + * In Device mode, this interrupt is asserted when a reset is detected on the USB in + * partial power-down mode when the device is in Suspend. + * + * In Host mode, this interrupt is not asserted. + */ +#define USB_OTGFS_GINTSTS_RESETDET (BIT(23)) +#define USB_OTGFS_GINTSTS_RESETDET_M (USB_OTGFS_GINTSTS_RESETDET_V << USB_OTGFS_GINTSTS_RESETDET_S) +#define USB_OTGFS_GINTSTS_RESETDET_V 0x00000001U +#define USB_OTGFS_GINTSTS_RESETDET_S 23 +/** USB_OTGFS_GINTSTS_PRTINT : RO; bitpos: [24]; default: 0; + * Mode: Host only + * Host Port Interrupt (PrtInt) + * The core sets this bit to indicate a change in port status of one of the controller + * ports in Host mode. The application must read the Host Port Control and Status + * (HPRT) register to determine the exact event that caused this interrupt. The + * application must clear the appropriate status bit in the Host Port + * Control and Status register to clear this bit. + */ +#define USB_OTGFS_GINTSTS_PRTINT (BIT(24)) +#define USB_OTGFS_GINTSTS_PRTINT_M (USB_OTGFS_GINTSTS_PRTINT_V << USB_OTGFS_GINTSTS_PRTINT_S) +#define USB_OTGFS_GINTSTS_PRTINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_PRTINT_S 24 +/** USB_OTGFS_GINTSTS_HCHINT : RO; bitpos: [25]; default: 0; + * Mode: Host only + * Host Channels Interrupt (HChInt) + * The core sets this bit to indicate that an interrupt is pending on one of the + * channels of the core (in Host mode). The application must read the Host All + * Channels Interrupt (HAINT) register to determine the exact number of the channel on + * which the interrupt occurred, and Then read the corresponding Host + * Channel-n Interrupt (HCINTn) register to determine the exact cause of the + * interrupt. The application must clear the appropriate status bit in the HCINTn + * register to clear this bit. + */ +#define USB_OTGFS_GINTSTS_HCHINT (BIT(25)) +#define USB_OTGFS_GINTSTS_HCHINT_M (USB_OTGFS_GINTSTS_HCHINT_V << USB_OTGFS_GINTSTS_HCHINT_S) +#define USB_OTGFS_GINTSTS_HCHINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_HCHINT_S 25 +/** USB_OTGFS_GINTSTS_PTXFEMP : RO; bitpos: [26]; default: 1; + * Mode: Host only + * Periodic TxFIFO Empty (PTxFEmp) + * This interrupt is asserted when the Periodic Transmit FIFO is either half or + * completely empty and there is space for at least one entry to be written in the + * Periodic Request Queue. The half or completely empty status is determined by the + * Periodic TxFIFO Empty Level bit in the Core AHB Configuration register + * (GAHBCFG.PTxFEmpLvl). + */ +#define USB_OTGFS_GINTSTS_PTXFEMP (BIT(26)) +#define USB_OTGFS_GINTSTS_PTXFEMP_M (USB_OTGFS_GINTSTS_PTXFEMP_V << USB_OTGFS_GINTSTS_PTXFEMP_S) +#define USB_OTGFS_GINTSTS_PTXFEMP_V 0x00000001U +#define USB_OTGFS_GINTSTS_PTXFEMP_S 26 +/** USB_OTGFS_GINTSTS_CONIDSTSCHNG : R/W; bitpos: [28]; default: 0; + * Mode: Host and Device + * Connector ID Status Change (ConIDStsChng) + * The core sets this bit when there is a change in connector ID status. + */ +#define USB_OTGFS_GINTSTS_CONIDSTSCHNG (BIT(28)) +#define USB_OTGFS_GINTSTS_CONIDSTSCHNG_M (USB_OTGFS_GINTSTS_CONIDSTSCHNG_V << USB_OTGFS_GINTSTS_CONIDSTSCHNG_S) +#define USB_OTGFS_GINTSTS_CONIDSTSCHNG_V 0x00000001U +#define USB_OTGFS_GINTSTS_CONIDSTSCHNG_S 28 +/** USB_OTGFS_GINTSTS_DISCONNINT : R/W; bitpos: [29]; default: 0; + * Mode: Host only + * Disconnect Detected Interrupt (DisconnInt) + * Asserted when a device disconnect is detected. + */ +#define USB_OTGFS_GINTSTS_DISCONNINT (BIT(29)) +#define USB_OTGFS_GINTSTS_DISCONNINT_M (USB_OTGFS_GINTSTS_DISCONNINT_V << USB_OTGFS_GINTSTS_DISCONNINT_S) +#define USB_OTGFS_GINTSTS_DISCONNINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_DISCONNINT_S 29 +/** USB_OTGFS_GINTSTS_SESSREQINT : R/W; bitpos: [30]; default: 0; + * Mode: Host and Device + * Session Request/New Session Detected Interrupt (SessReqInt) + * In Host mode, this interrupt is asserted when a session request is detected from + * the device. In Host mode, this interrupt is asserted when a session request is + * detected from the device. + * In Device mode, this interrupt is asserted when the utmisrp_bvalid signal goes high. + * For more information on how to use this interrupt, see 'Partial Power-Down and + * Clock Gating Programming Model' in the Programming Guide. + */ +#define USB_OTGFS_GINTSTS_SESSREQINT (BIT(30)) +#define USB_OTGFS_GINTSTS_SESSREQINT_M (USB_OTGFS_GINTSTS_SESSREQINT_V << USB_OTGFS_GINTSTS_SESSREQINT_S) +#define USB_OTGFS_GINTSTS_SESSREQINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_SESSREQINT_S 30 +/** USB_OTGFS_GINTSTS_WKUPINT : R/W; bitpos: [31]; default: 0; + * Mode: Host and Device + * Resume/Remote Wakeup Detected Interrupt (WkUpInt) + * Wakeup Interrupt during Suspend(L2) or LPM(L1) state. + * - During Suspend(L2): + * -- Device Mode: This interrupt is asserted only when Host Initiated Resume is + * detected on USB. + * -- Host Mode: This interrupt is asserted only when Device Initiated Remote Wakeup + * is detected on USB. + * For more information, see 'Partial Power-Down and Clock Gating Programming Model' + * in the Programming Guide. + * - During LPM(L1): + * -- Device Mode: This interrupt is asserted for either Host Initiated Resume or + * Device Initiated Remote Wakeup on USB. + * -- Host Mode: This interrupt is asserted for either Host Initiated Resume or Device + * Initiated Remote Wakeup on USB. + * For more information, see 'LPM Entry and Exit Programming Model' in the Programming + * Guide. + */ +#define USB_OTGFS_GINTSTS_WKUPINT (BIT(31)) +#define USB_OTGFS_GINTSTS_WKUPINT_M (USB_OTGFS_GINTSTS_WKUPINT_V << USB_OTGFS_GINTSTS_WKUPINT_S) +#define USB_OTGFS_GINTSTS_WKUPINT_V 0x00000001U +#define USB_OTGFS_GINTSTS_WKUPINT_S 31 + +/** USB_OTGFS_GINTMSK_REG register + * Interrupt Mask Register This register works with the Interrupt Register (GINTSTS) + * to interrupt the application. When an interrupt bit is masked, the interrupt + * associated with that bit is not generated. However, the GINTSTS register bit + * corresponding to that interrupt is still set. Note: The fields of this register + * change depending on host or device mode. + */ +#define USB_OTGFS_GINTMSK_REG(i) (DR_REG_USB_BASE(i) + 0x18) +/** USB_OTGFS_GINTMSK_MODEMISMSK : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * Mode Mismatch Interrupt Mask (ModeMisMsk) + */ +#define USB_OTGFS_GINTMSK_MODEMISMSK (BIT(1)) +#define USB_OTGFS_GINTMSK_MODEMISMSK_M (USB_OTGFS_GINTMSK_MODEMISMSK_V << USB_OTGFS_GINTMSK_MODEMISMSK_S) +#define USB_OTGFS_GINTMSK_MODEMISMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_MODEMISMSK_S 1 +/** USB_OTGFS_GINTMSK_OTGINTMSK : R/W; bitpos: [2]; default: 0; + * Mode: Host and Device + * OTG Interrupt Mask (OTGIntMsk) + */ +#define USB_OTGFS_GINTMSK_OTGINTMSK (BIT(2)) +#define USB_OTGFS_GINTMSK_OTGINTMSK_M (USB_OTGFS_GINTMSK_OTGINTMSK_V << USB_OTGFS_GINTMSK_OTGINTMSK_S) +#define USB_OTGFS_GINTMSK_OTGINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_OTGINTMSK_S 2 +/** USB_OTGFS_GINTMSK_SOFMSK : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * Start of (micro)Frame Mask (SofMsk) + */ +#define USB_OTGFS_GINTMSK_SOFMSK (BIT(3)) +#define USB_OTGFS_GINTMSK_SOFMSK_M (USB_OTGFS_GINTMSK_SOFMSK_V << USB_OTGFS_GINTMSK_SOFMSK_S) +#define USB_OTGFS_GINTMSK_SOFMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_SOFMSK_S 3 +/** USB_OTGFS_GINTMSK_RXFLVLMSK : R/W; bitpos: [4]; default: 0; + * Mode: Host and Device + * Receive FIFO Non-Empty Mask (RxFLvlMsk) + */ +#define USB_OTGFS_GINTMSK_RXFLVLMSK (BIT(4)) +#define USB_OTGFS_GINTMSK_RXFLVLMSK_M (USB_OTGFS_GINTMSK_RXFLVLMSK_V << USB_OTGFS_GINTMSK_RXFLVLMSK_S) +#define USB_OTGFS_GINTMSK_RXFLVLMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_RXFLVLMSK_S 4 +/** USB_OTGFS_GINTMSK_NPTXFEMPMSK : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + */ +#define USB_OTGFS_GINTMSK_NPTXFEMPMSK (BIT(5)) +#define USB_OTGFS_GINTMSK_NPTXFEMPMSK_M (USB_OTGFS_GINTMSK_NPTXFEMPMSK_V << USB_OTGFS_GINTMSK_NPTXFEMPMSK_S) +#define USB_OTGFS_GINTMSK_NPTXFEMPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_NPTXFEMPMSK_S 5 +/** USB_OTGFS_GINTMSK_GINNAKEFFMSK : R/W; bitpos: [6]; default: 0; + * Mode: Device only, + * Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + */ +#define USB_OTGFS_GINTMSK_GINNAKEFFMSK (BIT(6)) +#define USB_OTGFS_GINTMSK_GINNAKEFFMSK_M (USB_OTGFS_GINTMSK_GINNAKEFFMSK_V << USB_OTGFS_GINTMSK_GINNAKEFFMSK_S) +#define USB_OTGFS_GINTMSK_GINNAKEFFMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_GINNAKEFFMSK_S 6 +/** USB_OTGFS_GINTMSK_GOUTNAKEFFMSK : R/W; bitpos: [7]; default: 0; + * Mode: Device only + * Global OUT NAK Effective Mask (GOUTNakEffMsk) + */ +#define USB_OTGFS_GINTMSK_GOUTNAKEFFMSK (BIT(7)) +#define USB_OTGFS_GINTMSK_GOUTNAKEFFMSK_M (USB_OTGFS_GINTMSK_GOUTNAKEFFMSK_V << USB_OTGFS_GINTMSK_GOUTNAKEFFMSK_S) +#define USB_OTGFS_GINTMSK_GOUTNAKEFFMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_GOUTNAKEFFMSK_S 7 +/** USB_OTGFS_GINTMSK_ERLYSUSPMSK : R/W; bitpos: [10]; default: 0; + * Mode: Device only + * Early Suspend Mask (ErlySuspMsk) + */ +#define USB_OTGFS_GINTMSK_ERLYSUSPMSK (BIT(10)) +#define USB_OTGFS_GINTMSK_ERLYSUSPMSK_M (USB_OTGFS_GINTMSK_ERLYSUSPMSK_V << USB_OTGFS_GINTMSK_ERLYSUSPMSK_S) +#define USB_OTGFS_GINTMSK_ERLYSUSPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_ERLYSUSPMSK_S 10 +/** USB_OTGFS_GINTMSK_USBSUSPMSK : R/W; bitpos: [11]; default: 0; + * Mode: Device only + * USB Suspend Mask (USBSuspMsk) + */ +#define USB_OTGFS_GINTMSK_USBSUSPMSK (BIT(11)) +#define USB_OTGFS_GINTMSK_USBSUSPMSK_M (USB_OTGFS_GINTMSK_USBSUSPMSK_V << USB_OTGFS_GINTMSK_USBSUSPMSK_S) +#define USB_OTGFS_GINTMSK_USBSUSPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_USBSUSPMSK_S 11 +/** USB_OTGFS_GINTMSK_USBRSTMSK : R/W; bitpos: [12]; default: 0; + * Mode: Device only + * USB Reset Mask (USBRstMsk) + */ +#define USB_OTGFS_GINTMSK_USBRSTMSK (BIT(12)) +#define USB_OTGFS_GINTMSK_USBRSTMSK_M (USB_OTGFS_GINTMSK_USBRSTMSK_V << USB_OTGFS_GINTMSK_USBRSTMSK_S) +#define USB_OTGFS_GINTMSK_USBRSTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_USBRSTMSK_S 12 +/** USB_OTGFS_GINTMSK_ENUMDONEMSK : R/W; bitpos: [13]; default: 0; + * Mode: Device only + * Enumeration Done Mask (EnumDoneMsk) + */ +#define USB_OTGFS_GINTMSK_ENUMDONEMSK (BIT(13)) +#define USB_OTGFS_GINTMSK_ENUMDONEMSK_M (USB_OTGFS_GINTMSK_ENUMDONEMSK_V << USB_OTGFS_GINTMSK_ENUMDONEMSK_S) +#define USB_OTGFS_GINTMSK_ENUMDONEMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_ENUMDONEMSK_S 13 +/** USB_OTGFS_GINTMSK_ISOOUTDROPMSK : R/W; bitpos: [14]; default: 0; + * Mode: Device only + * Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + */ +#define USB_OTGFS_GINTMSK_ISOOUTDROPMSK (BIT(14)) +#define USB_OTGFS_GINTMSK_ISOOUTDROPMSK_M (USB_OTGFS_GINTMSK_ISOOUTDROPMSK_V << USB_OTGFS_GINTMSK_ISOOUTDROPMSK_S) +#define USB_OTGFS_GINTMSK_ISOOUTDROPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_ISOOUTDROPMSK_S 14 +/** USB_OTGFS_GINTMSK_EOPFMSK : R/W; bitpos: [15]; default: 0; + * Mode: Device only + * End of Periodic Frame Interrupt Mask (EOPFMsk) + */ +#define USB_OTGFS_GINTMSK_EOPFMSK (BIT(15)) +#define USB_OTGFS_GINTMSK_EOPFMSK_M (USB_OTGFS_GINTMSK_EOPFMSK_V << USB_OTGFS_GINTMSK_EOPFMSK_S) +#define USB_OTGFS_GINTMSK_EOPFMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_EOPFMSK_S 15 +/** USB_OTGFS_GINTMSK_EPMISMSK : R/W; bitpos: [17]; default: 0; + * Mode: Device only + * Endpoint Mismatch Interrupt Mask (EPMisMsk) + */ +#define USB_OTGFS_GINTMSK_EPMISMSK (BIT(17)) +#define USB_OTGFS_GINTMSK_EPMISMSK_M (USB_OTGFS_GINTMSK_EPMISMSK_V << USB_OTGFS_GINTMSK_EPMISMSK_S) +#define USB_OTGFS_GINTMSK_EPMISMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_EPMISMSK_S 17 +/** USB_OTGFS_GINTMSK_IEPINTMSK : R/W; bitpos: [18]; default: 0; + * Mode: Device only + * IN Endpoints Interrupt Mask (IEPIntMsk) + */ +#define USB_OTGFS_GINTMSK_IEPINTMSK (BIT(18)) +#define USB_OTGFS_GINTMSK_IEPINTMSK_M (USB_OTGFS_GINTMSK_IEPINTMSK_V << USB_OTGFS_GINTMSK_IEPINTMSK_S) +#define USB_OTGFS_GINTMSK_IEPINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_IEPINTMSK_S 18 +/** USB_OTGFS_GINTMSK_OEPINTMSK : R/W; bitpos: [19]; default: 0; + * Mode: Device only + * OUT Endpoints Interrupt Mask (OEPIntMsk) + */ +#define USB_OTGFS_GINTMSK_OEPINTMSK (BIT(19)) +#define USB_OTGFS_GINTMSK_OEPINTMSK_M (USB_OTGFS_GINTMSK_OEPINTMSK_V << USB_OTGFS_GINTMSK_OEPINTMSK_S) +#define USB_OTGFS_GINTMSK_OEPINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_OEPINTMSK_S 19 +/** USB_OTGFS_GINTMSK_INCOMPLPMSK : R/W; bitpos: [21]; default: 0; + * Incomplete Periodic Transfer Mask (incomplPMsk) + * Mode: Host only + * Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk) + * Mode: Device only + */ +#define USB_OTGFS_GINTMSK_INCOMPLPMSK (BIT(21)) +#define USB_OTGFS_GINTMSK_INCOMPLPMSK_M (USB_OTGFS_GINTMSK_INCOMPLPMSK_V << USB_OTGFS_GINTMSK_INCOMPLPMSK_S) +#define USB_OTGFS_GINTMSK_INCOMPLPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_INCOMPLPMSK_S 21 +/** USB_OTGFS_GINTMSK_FETSUSPMSK : R/W; bitpos: [22]; default: 0; + * Mode: Device only + * Data Fetch Suspended Mask (FetSuspMsk) + */ +#define USB_OTGFS_GINTMSK_FETSUSPMSK (BIT(22)) +#define USB_OTGFS_GINTMSK_FETSUSPMSK_M (USB_OTGFS_GINTMSK_FETSUSPMSK_V << USB_OTGFS_GINTMSK_FETSUSPMSK_S) +#define USB_OTGFS_GINTMSK_FETSUSPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_FETSUSPMSK_S 22 +/** USB_OTGFS_GINTMSK_RESETDETMSK : R/W; bitpos: [23]; default: 0; + * Mode: Device only + * Reset detected Interrupt Mask (ResetDetMsk) + */ +#define USB_OTGFS_GINTMSK_RESETDETMSK (BIT(23)) +#define USB_OTGFS_GINTMSK_RESETDETMSK_M (USB_OTGFS_GINTMSK_RESETDETMSK_V << USB_OTGFS_GINTMSK_RESETDETMSK_S) +#define USB_OTGFS_GINTMSK_RESETDETMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_RESETDETMSK_S 23 +/** USB_OTGFS_GINTMSK_PRTINTMSK : R/W; bitpos: [24]; default: 0; + * Mode: Host only + * Host Port Interrupt Mask (PrtIntMsk) + */ +#define USB_OTGFS_GINTMSK_PRTINTMSK (BIT(24)) +#define USB_OTGFS_GINTMSK_PRTINTMSK_M (USB_OTGFS_GINTMSK_PRTINTMSK_V << USB_OTGFS_GINTMSK_PRTINTMSK_S) +#define USB_OTGFS_GINTMSK_PRTINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_PRTINTMSK_S 24 +/** USB_OTGFS_GINTMSK_HCHINTMSK : R/W; bitpos: [25]; default: 0; + * Mode: Host only + * Host Channels Interrupt Mask (HChIntMsk) + */ +#define USB_OTGFS_GINTMSK_HCHINTMSK (BIT(25)) +#define USB_OTGFS_GINTMSK_HCHINTMSK_M (USB_OTGFS_GINTMSK_HCHINTMSK_V << USB_OTGFS_GINTMSK_HCHINTMSK_S) +#define USB_OTGFS_GINTMSK_HCHINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_HCHINTMSK_S 25 +/** USB_OTGFS_GINTMSK_PTXFEMPMSK : R/W; bitpos: [26]; default: 0; + * Mode: Host only + * Periodic TxFIFO Empty Mask (PTxFEmpMsk) + */ +#define USB_OTGFS_GINTMSK_PTXFEMPMSK (BIT(26)) +#define USB_OTGFS_GINTMSK_PTXFEMPMSK_M (USB_OTGFS_GINTMSK_PTXFEMPMSK_V << USB_OTGFS_GINTMSK_PTXFEMPMSK_S) +#define USB_OTGFS_GINTMSK_PTXFEMPMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_PTXFEMPMSK_S 26 +/** USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK : R/W; bitpos: [28]; default: 0; + * Mode: Host and Device + * Connector ID Status Change Mask (ConIDStsChngMsk) + */ +#define USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK (BIT(28)) +#define USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK_M (USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK_V << USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK_S) +#define USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_CONIDSTSCHNGMSK_S 28 +/** USB_OTGFS_GINTMSK_DISCONNINTMSK : R/W; bitpos: [29]; default: 0; + * Mode: Host and Device + * Disconnect Detected Interrupt Mask (DisconnIntMsk) + */ +#define USB_OTGFS_GINTMSK_DISCONNINTMSK (BIT(29)) +#define USB_OTGFS_GINTMSK_DISCONNINTMSK_M (USB_OTGFS_GINTMSK_DISCONNINTMSK_V << USB_OTGFS_GINTMSK_DISCONNINTMSK_S) +#define USB_OTGFS_GINTMSK_DISCONNINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_DISCONNINTMSK_S 29 +/** USB_OTGFS_GINTMSK_SESSREQINTMSK : R/W; bitpos: [30]; default: 0; + * Mode: Host and Device + * Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + */ +#define USB_OTGFS_GINTMSK_SESSREQINTMSK (BIT(30)) +#define USB_OTGFS_GINTMSK_SESSREQINTMSK_M (USB_OTGFS_GINTMSK_SESSREQINTMSK_V << USB_OTGFS_GINTMSK_SESSREQINTMSK_S) +#define USB_OTGFS_GINTMSK_SESSREQINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_SESSREQINTMSK_S 30 +/** USB_OTGFS_GINTMSK_WKUPINTMSK : R/W; bitpos: [31]; default: 0; + * Mode: Host and Device + * Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + * The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in + * suspend state. + */ +#define USB_OTGFS_GINTMSK_WKUPINTMSK (BIT(31)) +#define USB_OTGFS_GINTMSK_WKUPINTMSK_M (USB_OTGFS_GINTMSK_WKUPINTMSK_V << USB_OTGFS_GINTMSK_WKUPINTMSK_S) +#define USB_OTGFS_GINTMSK_WKUPINTMSK_V 0x00000001U +#define USB_OTGFS_GINTMSK_WKUPINTMSK_S 31 + +/** USB_OTGFS_GRXSTSR_REG register + * Receive Status Debug Read Register A read to the Receive Status Debug Read register + * returns the contents of the top of the Receive FIFO. The receive status contents + * must be interpreted differently in Host and Device modes. The core ignores the + * receive status read when the receive FIFO is empty and returns a value of + * 32'h0000_0000. Note: - Use of these fields vary based on whether the core is + * functioning as a host or a device. - Do not read this register's reset value + * before configuring the core because the read value is 'X' in the simulation. + */ +#define USB_OTGFS_GRXSTSR_REG(i) (DR_REG_USB_BASE(i) + 0x1c) +/** USB_OTGFS_GRXSTSR_CHNUM : RO; bitpos: [3:0]; default: 0; + * Channel Number (ChNum) + * Mode: Host only + * Indicates the channel number to which the current received packet belongs. + * Endpoint Number (EPNum) + * Mode: Device only + * Indicates the endpoint number to which the current received packet belongs. + */ +#define USB_OTGFS_GRXSTSR_CHNUM 0x0000000FU +#define USB_OTGFS_GRXSTSR_CHNUM_M (USB_OTGFS_GRXSTSR_CHNUM_V << USB_OTGFS_GRXSTSR_CHNUM_S) +#define USB_OTGFS_GRXSTSR_CHNUM_V 0x0000000FU +#define USB_OTGFS_GRXSTSR_CHNUM_S 0 +/** USB_OTGFS_GRXSTSR_BCNT : RO; bitpos: [14:4]; default: 0; + * Byte Count (BCnt) + * + * In host mode, indicates the byte count of the received IN data packet. + * + * In device mode, indicates the byte count of the received data packet. + */ +#define USB_OTGFS_GRXSTSR_BCNT 0x000007FFU +#define USB_OTGFS_GRXSTSR_BCNT_M (USB_OTGFS_GRXSTSR_BCNT_V << USB_OTGFS_GRXSTSR_BCNT_S) +#define USB_OTGFS_GRXSTSR_BCNT_V 0x000007FFU +#define USB_OTGFS_GRXSTSR_BCNT_S 4 +/** USB_OTGFS_GRXSTSR_DPID : RO; bitpos: [16:15]; default: 0; + * Data PID (DPID) + * + * In host mode, indicates the Data PID of the received packet. In device mode, + * indicates the Data PID of the received OUT data packet. + * - 2'b00: DATA0 + * - 2'b10: DATA1 + * - 2'b01: DATA2 + * - 2'b11: MDATA + * Reset: 2'h0 + */ +#define USB_OTGFS_GRXSTSR_DPID 0x00000003U +#define USB_OTGFS_GRXSTSR_DPID_M (USB_OTGFS_GRXSTSR_DPID_V << USB_OTGFS_GRXSTSR_DPID_S) +#define USB_OTGFS_GRXSTSR_DPID_V 0x00000003U +#define USB_OTGFS_GRXSTSR_DPID_S 15 +/** USB_OTGFS_GRXSTSR_PKTSTS : RO; bitpos: [20:17]; default: 0; + * Packet Status (PktSts) indicates the status of the received packet. + * In host mode, + * - 4'b0010: IN data packet received + * - 4'b0011: IN transfer completed (triggers an interrupt) + * - 4'b0101: Data toggle error (triggers an interrupt) + * - 4'b0111: Channel halted (triggers an interrupt) + * - Others: Reserved + * Reset:4'b0 + * + * In device mode, + * - 4'b0001: Global OUT NAK (triggers an interrupt) + * - 4'b0010: OUT data packet received + * - 4'b0011: OUT transfer completed (triggers an interrupt) + * - 4'b0100: SETUP transaction completed (triggers an interrupt) + * - 4'b0110: SETUP data packet received + * - Others: Reserved + * Reset:4'h0 + */ +#define USB_OTGFS_GRXSTSR_PKTSTS 0x0000000FU +#define USB_OTGFS_GRXSTSR_PKTSTS_M (USB_OTGFS_GRXSTSR_PKTSTS_V << USB_OTGFS_GRXSTSR_PKTSTS_S) +#define USB_OTGFS_GRXSTSR_PKTSTS_V 0x0000000FU +#define USB_OTGFS_GRXSTSR_PKTSTS_S 17 +/** USB_OTGFS_GRXSTSR_FN : RO; bitpos: [24:21]; default: 0; + * Mode: Device only + * Frame Number (FN) + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported. + */ +#define USB_OTGFS_GRXSTSR_FN 0x0000000FU +#define USB_OTGFS_GRXSTSR_FN_M (USB_OTGFS_GRXSTSR_FN_V << USB_OTGFS_GRXSTSR_FN_S) +#define USB_OTGFS_GRXSTSR_FN_V 0x0000000FU +#define USB_OTGFS_GRXSTSR_FN_S 21 + +/** USB_OTGFS_GRXSTSP_REG register + * Receive Status Read/Pop Register A read to the Receive Status Read and Pop register + * returns the contents of the top of the Receive FIFO and additionally pops the top + * data entry out of the RxFIFO. The receive status contents must be interpreted + * differently in Host and Device modes. The core ignores the receive status pop/read + * when the receive FIFO is empty and returns a value of 32'h0000_0000. The + * application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty + * bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Note: - Use of + * these fields vary based on whether the core is functioning as a host or a device. + * - Do not read this register's reset value before configuring the core because the + * read value is 'X' in the simulation. + */ +#define USB_OTGFS_GRXSTSP_REG(i) (DR_REG_USB_BASE(i) + 0x20) +/** USB_OTGFS_GRXSTSP_CHNUM : RO; bitpos: [3:0]; default: 0; + * Channel Number (ChNum) + * Mode: Host only + * Indicates the channel number to which the current received packet belongs. + * Endpoint Number (EPNum) + * Mode: Device only + * Indicates the endpoint number to which the current received packet belongs. + */ +#define USB_OTGFS_GRXSTSP_CHNUM 0x0000000FU +#define USB_OTGFS_GRXSTSP_CHNUM_M (USB_OTGFS_GRXSTSP_CHNUM_V << USB_OTGFS_GRXSTSP_CHNUM_S) +#define USB_OTGFS_GRXSTSP_CHNUM_V 0x0000000FU +#define USB_OTGFS_GRXSTSP_CHNUM_S 0 +/** USB_OTGFS_GRXSTSP_BCNT : RO; bitpos: [14:4]; default: 0; + * Byte Count (BCnt) + * + * In host mode, indicates the byte count of the received IN data packet. + * + * In device mode, indicates the byte count of the received data packet. + */ +#define USB_OTGFS_GRXSTSP_BCNT 0x000007FFU +#define USB_OTGFS_GRXSTSP_BCNT_M (USB_OTGFS_GRXSTSP_BCNT_V << USB_OTGFS_GRXSTSP_BCNT_S) +#define USB_OTGFS_GRXSTSP_BCNT_V 0x000007FFU +#define USB_OTGFS_GRXSTSP_BCNT_S 4 +/** USB_OTGFS_GRXSTSP_DPID : RO; bitpos: [16:15]; default: 0; + * Data PID (DPID) + * + * In host mode, indicates the Data PID of the received packet. In device mode, + * indicates the Data PID of the received OUT data packet. + * - 2'b00: DATA0 + * - 2'b10: DATA1 + * - 2'b01: DATA2 + * - 2'b11: MDATA + * Reset: 2'h0 + */ +#define USB_OTGFS_GRXSTSP_DPID 0x00000003U +#define USB_OTGFS_GRXSTSP_DPID_M (USB_OTGFS_GRXSTSP_DPID_V << USB_OTGFS_GRXSTSP_DPID_S) +#define USB_OTGFS_GRXSTSP_DPID_V 0x00000003U +#define USB_OTGFS_GRXSTSP_DPID_S 15 +/** USB_OTGFS_GRXSTSP_PKTSTS : RO; bitpos: [20:17]; default: 0; + * Packet Status (PktSts) indicates the status of the received packet. + * In host mode, + * - 4'b0010: IN data packet received + * - 4'b0011: IN transfer completed (triggers an interrupt) + * - 4'b0101: Data toggle error (triggers an interrupt) + * - 4'b0111: Channel halted (triggers an interrupt) + * - Others: Reserved + * Reset:4'b0 + * + * In device mode, + * - 4'b0001: Global OUT NAK (triggers an interrupt) + * - 4'b0010: OUT data packet received + * - 4'b0011: OUT transfer completed (triggers an interrupt) + * - 4'b0100: SETUP transaction completed (triggers an interrupt) + * - 4'b0110: SETUP data packet received + * - Others: Reserved + * Reset:4'h0 + */ +#define USB_OTGFS_GRXSTSP_PKTSTS 0x0000000FU +#define USB_OTGFS_GRXSTSP_PKTSTS_M (USB_OTGFS_GRXSTSP_PKTSTS_V << USB_OTGFS_GRXSTSP_PKTSTS_S) +#define USB_OTGFS_GRXSTSP_PKTSTS_V 0x0000000FU +#define USB_OTGFS_GRXSTSP_PKTSTS_S 17 +/** USB_OTGFS_GRXSTSP_FN : RO; bitpos: [24:21]; default: 0; + * Mode: Device only + * Frame Number (FN) + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported. + */ +#define USB_OTGFS_GRXSTSP_FN 0x0000000FU +#define USB_OTGFS_GRXSTSP_FN_M (USB_OTGFS_GRXSTSP_FN_V << USB_OTGFS_GRXSTSP_FN_S) +#define USB_OTGFS_GRXSTSP_FN_V 0x0000000FU +#define USB_OTGFS_GRXSTSP_FN_S 21 + +/** USB_OTGFS_GRXFSIZ_REG register + * Receive FIFO Size Register The application can program the RAM size that must be + * allocated to the RxFIFO. + */ +#define USB_OTGFS_GRXFSIZ_REG(i) (DR_REG_USB_BASE(i) + 0x24) +/** USB_OTGFS_GRXFSIZ_RXFDEP : R/W; bitpos: [8:0]; default: 256; + * Mode: Host and Device + * RxFIFO Depth (RxFDep) + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * The power-on reset value of this register is specified as the Largest Rx Data FIFO + * Depth during configuration. + * If Enable Dynamic FIFO Sizing is selected in coreConsultant, these flops are + * optimized, and reads return the power-on value. + * If Enable Dynamic FIFO Sizing is selected in coreConsultant, you can write a new + * value in this field. Programmed values must not exceed the power-on value. + */ +#define USB_OTGFS_GRXFSIZ_RXFDEP 0x000001FFU +#define USB_OTGFS_GRXFSIZ_RXFDEP_M (USB_OTGFS_GRXFSIZ_RXFDEP_V << USB_OTGFS_GRXFSIZ_RXFDEP_S) +#define USB_OTGFS_GRXFSIZ_RXFDEP_V 0x000001FFU +#define USB_OTGFS_GRXFSIZ_RXFDEP_S 0 + +/** USB_OTGFS_GNPTXFSIZ_REG register + * Non-periodic Transmit FIFO Size Register The application can program the RAM size + * and the memory start address for the Non-periodic TxFIFO Note: The fields of this + * register change depending on host or device mode. + */ +#define USB_OTGFS_GNPTXFSIZ_REG(i) (DR_REG_USB_BASE(i) + 0x28) +/** USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR : R/W; bitpos: [8:0]; default: 256; + * Non-periodic Transmit RAM Start Address (NPTxFStAddr) + * For host mode, this field is always valid. + * This field contains the memory start address for Non-periodic Transmit FIFO RAM. + * - This field is determined during coreConsultant configuration by Enable Dynamic + * FIFO Sizing? (OTG_DFIFO_DYNAMIC):OTG_DFIFO_DYNAMIC = 0 + * These flops are optimized, and reads return the power-on value. + * - OTG_DFIFO_DYNAMIC = 1 The application can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + * Programmed values must not exceed the power-on value set in coreConsultant. + * The power-on reset value of this field is specified during coreConsultant + * configuration by Largest Rx Data FIFO Depth (parameter OTG_RX_DFIFO_DEPTH). + */ +#define USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR 0x000001FFU +#define USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR_M (USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR_V << USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR_S) +#define USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR_V 0x000001FFU +#define USB_OTGFS_GNPTXFSIZ_NPTXFSTADDR_S 0 +/** USB_OTGFS_GNPTXFSIZ_NPTXFDEP : R/W; bitpos: [24:16]; default: 256; + * Mode: Host only + * Non-periodic TxFIFO Depth (NPTxFDep) + * For host mode, this field is always valid. + * For device mode, this field is valid only when OTG_EN_DED_TX_FIFO=0. + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * This attribute of field is determined during coreConsultant configuration by Enable + * Dynamic FIFO Sizing? (OTG_DFIFO_DYNAMIC): + * - OTG_DFIFO_DYNAMIC = 0: These flops are optimized, and reads return the power-on + * value. + * - OTG_DFIFO_DYNAMIC = 1: The application can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + * The power-on reset value of this field is specified during coreConsultant + * configuration as Largest IN Endpoint FIFO 0 Depth (parameter + * OTG_TX_DINEP_DFIFO_DEPTH_0). + */ +#define USB_OTGFS_GNPTXFSIZ_NPTXFDEP 0x000001FFU +#define USB_OTGFS_GNPTXFSIZ_NPTXFDEP_M (USB_OTGFS_GNPTXFSIZ_NPTXFDEP_V << USB_OTGFS_GNPTXFSIZ_NPTXFDEP_S) +#define USB_OTGFS_GNPTXFSIZ_NPTXFDEP_V 0x000001FFU +#define USB_OTGFS_GNPTXFSIZ_NPTXFDEP_S 16 + +/** USB_OTGFS_GNPTXSTS_REG register + * Non-periodic Transmit FIFO/Queue Status Register In Device mode, this register is + * valid only in Shared FIFO operation. This read-only register contains the free + * space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request + * Queue. + */ +#define USB_OTGFS_GNPTXSTS_REG(i) (DR_REG_USB_BASE(i) + 0x2c) +/** USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL : RO; bitpos: [15:0]; default: 256; + * Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + * Indicates the amount of free space available in the Non-periodic TxFIFO. + * Values are in terms of 32-bit words. + * - 16'h0: Non-periodic TxFIFO is full + * - 16'h1: 1 word available + * - 16'h2: 2 words available + * - 16'hn: n words available (where 0 <= n <= 32,768) + * - 16'h8000: 32,768 words available + * - Others: Reserved + * Reset: Configurable + */ +#define USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL 0x0000FFFFU +#define USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL_M (USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL_V << USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL_S) +#define USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL_V 0x0000FFFFU +#define USB_OTGFS_GNPTXSTS_NPTXFSPCAVAIL_S 0 +/** USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL : RO; bitpos: [23:16]; default: 4; + * Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + * Indicates the amount of free space available in the Non-periodic Transmit Request + * Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only + * IN requests. + * - 8'h0: Non-periodic Transmit Request Queue is full + * - 8'h1: 1 location available + * - 8'h2: 2 locations available + * - n: n locations available (0 <= n <= 8) + * - Others: Reserved + * Reset: Configurable + */ +#define USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL 0x000000FFU +#define USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL_M (USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL_V << USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL_S) +#define USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL_V 0x000000FFU +#define USB_OTGFS_GNPTXSTS_NPTXQSPCAVAIL_S 16 +/** USB_OTGFS_GNPTXSTS_NPTXQTOP : RO; bitpos: [30:24]; default: 0; + * Top of the Non-periodic Transmit Request Queue (NPTxQTop) + * Entry in the Non-periodic Tx Request Queue that is currently being processed by the + * MAC. + * + * - Bits [30:27]: Channel/endpoint number + * - Bits [26:25]: + * - 2'b00: IN/OUT token + * -- 2'b01: Zero-length transmit packet (device IN/host OUT) + * -- 2'b10: PING/CSPLIT token + * -- 2'b11: Channel halt command + * - Bit [24]: Terminate (last Entry for selected channel/endpoint) + * Reset: 7'h0 + */ +#define USB_OTGFS_GNPTXSTS_NPTXQTOP 0x0000007FU +#define USB_OTGFS_GNPTXSTS_NPTXQTOP_M (USB_OTGFS_GNPTXSTS_NPTXQTOP_V << USB_OTGFS_GNPTXSTS_NPTXQTOP_S) +#define USB_OTGFS_GNPTXSTS_NPTXQTOP_V 0x0000007FU +#define USB_OTGFS_GNPTXSTS_NPTXQTOP_S 24 + +/** USB_OTGFS_GSNPSID_REG register + * Synopsis ID Register This read-only register contains the release number of the + * core being used. + */ +#define USB_OTGFS_GSNPSID_REG(i) (DR_REG_USB_BASE(i) + 0x40) +/** USB_OTGFS_GSNPSID_SYNOPSYSID : RO; bitpos: [31:0]; default: 1330921482; + * Release number of the controller being used currently. + */ +#define USB_OTGFS_GSNPSID_SYNOPSYSID 0xFFFFFFFFU +#define USB_OTGFS_GSNPSID_SYNOPSYSID_M (USB_OTGFS_GSNPSID_SYNOPSYSID_V << USB_OTGFS_GSNPSID_SYNOPSYSID_S) +#define USB_OTGFS_GSNPSID_SYNOPSYSID_V 0xFFFFFFFFU +#define USB_OTGFS_GSNPSID_SYNOPSYSID_S 0 + +/** USB_OTGFS_GHWCFG1_REG register + * User Hardware Configuration 1 Register This register contains the logical endpoint + * direction(s) selected using coreConsultant. + */ +#define USB_OTGFS_GHWCFG1_REG(i) (DR_REG_USB_BASE(i) + 0x44) +/** USB_OTGFS_GHWCFG1_EPDIR : RO; bitpos: [31:0]; default: 0; + * This 32-bit field uses two bits per + * endpoint to determine the endpoint direction. + * + * Endpoint + * - Bits [31:30]: Endpoint 15 direction + * - Bits [29:28]: Endpoint 14 direction + * ... + * - Bits [3:2]: Endpoint 1 direction + * - Bits[1:0]: Endpoint 0 direction (always BIDIR) + * Direction + * - 2'b00: BIDIR (IN and OUT) endpoint + * - 2'b01: IN endpoint + * - 2'b10: OUT endpoint + * - 2'b11: Reserved + * Note: This field is configured using the OTG_EP_DIR_1(n) parameter. + */ +#define USB_OTGFS_GHWCFG1_EPDIR 0xFFFFFFFFU +#define USB_OTGFS_GHWCFG1_EPDIR_M (USB_OTGFS_GHWCFG1_EPDIR_V << USB_OTGFS_GHWCFG1_EPDIR_S) +#define USB_OTGFS_GHWCFG1_EPDIR_V 0xFFFFFFFFU +#define USB_OTGFS_GHWCFG1_EPDIR_S 0 + +/** USB_OTGFS_GHWCFG2_REG register + * User Hardware Configuration 2 Register This register contains configuration + * options selected using coreConsultant. + */ +#define USB_OTGFS_GHWCFG2_REG(i) (DR_REG_USB_BASE(i) + 0x48) +/** USB_OTGFS_GHWCFG2_OTGMODE : RO; bitpos: [2:0]; default: 0; + * Mode of Operation (OtgMode) + * - 3'b000: HNP- and SRP-Capable OTG (Host & Device) + * - 3'b001: SRP-Capable OTG (Host & Device) + * - 3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device) + * - 3'b011: SRP-Capable Device + * - 3'b100: Non-OTG Device + * - 3'b101: SRP-Capable Host + * - 3'b110: Non-OTG Host + * - Others: Reserved + * Note: This field is configured using the OTG_MODE parameter. + */ +#define USB_OTGFS_GHWCFG2_OTGMODE 0x00000007U +#define USB_OTGFS_GHWCFG2_OTGMODE_M (USB_OTGFS_GHWCFG2_OTGMODE_V << USB_OTGFS_GHWCFG2_OTGMODE_S) +#define USB_OTGFS_GHWCFG2_OTGMODE_V 0x00000007U +#define USB_OTGFS_GHWCFG2_OTGMODE_S 0 +/** USB_OTGFS_GHWCFG2_OTGARCH : RO; bitpos: [4:3]; default: 2; + * Architecture (OtgArch) + * - 2'b00: Slave-Only + * - 2'b01: External DMA + * - 2'b10: Internal DMA + * - Others: Reserved + * Note: This field is configured using the OTG_ARCHITECTURE parameter. + */ +#define USB_OTGFS_GHWCFG2_OTGARCH 0x00000003U +#define USB_OTGFS_GHWCFG2_OTGARCH_M (USB_OTGFS_GHWCFG2_OTGARCH_V << USB_OTGFS_GHWCFG2_OTGARCH_S) +#define USB_OTGFS_GHWCFG2_OTGARCH_V 0x00000003U +#define USB_OTGFS_GHWCFG2_OTGARCH_S 3 +/** USB_OTGFS_GHWCFG2_SINGPNT : RO; bitpos: [5]; default: 1; + * Point-to-Point (SingPnt) + * - 1'b0: Multi-point application (hub and split support) + * - 1'b1: Single-point application (no hub and split support) + * Note: This field is configured using the OTG_SINGLE_POINT parameter. + */ +#define USB_OTGFS_GHWCFG2_SINGPNT (BIT(5)) +#define USB_OTGFS_GHWCFG2_SINGPNT_M (USB_OTGFS_GHWCFG2_SINGPNT_V << USB_OTGFS_GHWCFG2_SINGPNT_S) +#define USB_OTGFS_GHWCFG2_SINGPNT_V 0x00000001U +#define USB_OTGFS_GHWCFG2_SINGPNT_S 5 +/** USB_OTGFS_GHWCFG2_HSPHYTYPE : RO; bitpos: [7:6]; default: 0; + * High-Speed PHY Interface Type (HSPhyType) + * - 2'b00: High-Speed interface not supported + * - 2'b01: UTMI+ + * - 2'b10: ULPI + * - 2'b11: UTMI+ and ULPI + * Note: This field is configured using the OTG_HSPHY_INTERFACE parameter. + */ +#define USB_OTGFS_GHWCFG2_HSPHYTYPE 0x00000003U +#define USB_OTGFS_GHWCFG2_HSPHYTYPE_M (USB_OTGFS_GHWCFG2_HSPHYTYPE_V << USB_OTGFS_GHWCFG2_HSPHYTYPE_S) +#define USB_OTGFS_GHWCFG2_HSPHYTYPE_V 0x00000003U +#define USB_OTGFS_GHWCFG2_HSPHYTYPE_S 6 +/** USB_OTGFS_GHWCFG2_FSPHYTYPE : RO; bitpos: [9:8]; default: 1; + * Full-Speed PHY Interface Type (FSPhyType) + * - 2'b00: Full-speed interface not supported + * - 2'b01: Dedicated full-speed interface + * - 2'b10: FS pins shared with UTMI+ pins + * - 2'b11: FS pins shared with ULPI pins + * Note: This field is configured using the OTG_FSPHY_INTERFACE parameter. + */ +#define USB_OTGFS_GHWCFG2_FSPHYTYPE 0x00000003U +#define USB_OTGFS_GHWCFG2_FSPHYTYPE_M (USB_OTGFS_GHWCFG2_FSPHYTYPE_V << USB_OTGFS_GHWCFG2_FSPHYTYPE_S) +#define USB_OTGFS_GHWCFG2_FSPHYTYPE_V 0x00000003U +#define USB_OTGFS_GHWCFG2_FSPHYTYPE_S 8 +/** USB_OTGFS_GHWCFG2_NUMDEVEPS : RO; bitpos: [13:10]; default: 6; + * Number of Device Endpoints (NumDevEps) + * + * Indicates the number of device endpoints supported by the core in Device mode. + * + * The range of this field is 0-15. + * + * Note: This field is configured using the OTG_NUM_EPS parameter. + */ +#define USB_OTGFS_GHWCFG2_NUMDEVEPS 0x0000000FU +#define USB_OTGFS_GHWCFG2_NUMDEVEPS_M (USB_OTGFS_GHWCFG2_NUMDEVEPS_V << USB_OTGFS_GHWCFG2_NUMDEVEPS_S) +#define USB_OTGFS_GHWCFG2_NUMDEVEPS_V 0x0000000FU +#define USB_OTGFS_GHWCFG2_NUMDEVEPS_S 10 +/** USB_OTGFS_GHWCFG2_NUMHSTCHNL : RO; bitpos: [17:14]; default: 7; + * Number of Host Channels (NumHstChnl) + * Indicates the number of host channels supported by the core in Host mode. The range + * of this field is 0-15: 0 specifies 1 channel, 15 specifies 16 channels. + * + * Note: This field is configured using the OTG_NUM_HOST_CHAN parameter. + */ +#define USB_OTGFS_GHWCFG2_NUMHSTCHNL 0x0000000FU +#define USB_OTGFS_GHWCFG2_NUMHSTCHNL_M (USB_OTGFS_GHWCFG2_NUMHSTCHNL_V << USB_OTGFS_GHWCFG2_NUMHSTCHNL_S) +#define USB_OTGFS_GHWCFG2_NUMHSTCHNL_V 0x0000000FU +#define USB_OTGFS_GHWCFG2_NUMHSTCHNL_S 14 +/** USB_OTGFS_GHWCFG2_PERIOSUPPORT : RO; bitpos: [18]; default: 1; + * Periodic OUT Channels Supported in Host Mode (PerioSupport) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_EN_PERIO_HOST parameter. + */ +#define USB_OTGFS_GHWCFG2_PERIOSUPPORT (BIT(18)) +#define USB_OTGFS_GHWCFG2_PERIOSUPPORT_M (USB_OTGFS_GHWCFG2_PERIOSUPPORT_V << USB_OTGFS_GHWCFG2_PERIOSUPPORT_S) +#define USB_OTGFS_GHWCFG2_PERIOSUPPORT_V 0x00000001U +#define USB_OTGFS_GHWCFG2_PERIOSUPPORT_S 18 +/** USB_OTGFS_GHWCFG2_DYNFIFOSIZING : RO; bitpos: [19]; default: 1; + * Dynamic FIFO Sizing Enabled (DynFifoSizing) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_DFIFO_DYNAMIC parameter. + */ +#define USB_OTGFS_GHWCFG2_DYNFIFOSIZING (BIT(19)) +#define USB_OTGFS_GHWCFG2_DYNFIFOSIZING_M (USB_OTGFS_GHWCFG2_DYNFIFOSIZING_V << USB_OTGFS_GHWCFG2_DYNFIFOSIZING_S) +#define USB_OTGFS_GHWCFG2_DYNFIFOSIZING_V 0x00000001U +#define USB_OTGFS_GHWCFG2_DYNFIFOSIZING_S 19 +/** USB_OTGFS_GHWCFG2_MULTIPROCINTRPT : RO; bitpos: [20]; default: 0; + * Multi Processor Interrupt Enabled (MultiProcIntrpt) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_MULTI_PROC_INTRPT parameter. + */ +#define USB_OTGFS_GHWCFG2_MULTIPROCINTRPT (BIT(20)) +#define USB_OTGFS_GHWCFG2_MULTIPROCINTRPT_M (USB_OTGFS_GHWCFG2_MULTIPROCINTRPT_V << USB_OTGFS_GHWCFG2_MULTIPROCINTRPT_S) +#define USB_OTGFS_GHWCFG2_MULTIPROCINTRPT_V 0x00000001U +#define USB_OTGFS_GHWCFG2_MULTIPROCINTRPT_S 20 +/** USB_OTGFS_GHWCFG2_NPTXQDEPTH : RO; bitpos: [23:22]; default: 1; + * Non-periodic Request Queue Depth (NPTxQDepth) + * - 2'b00: 2 + * - 2'b01: 4 + * - 2'b10: 8 + * - Others: Reserved + * Note: This field is configured using the OTG_NPERIO_TX_QUEUE_DEPTH parameter. + */ +#define USB_OTGFS_GHWCFG2_NPTXQDEPTH 0x00000003U +#define USB_OTGFS_GHWCFG2_NPTXQDEPTH_M (USB_OTGFS_GHWCFG2_NPTXQDEPTH_V << USB_OTGFS_GHWCFG2_NPTXQDEPTH_S) +#define USB_OTGFS_GHWCFG2_NPTXQDEPTH_V 0x00000003U +#define USB_OTGFS_GHWCFG2_NPTXQDEPTH_S 22 +/** USB_OTGFS_GHWCFG2_PTXQDEPTH : RO; bitpos: [25:24]; default: 2; + * Host Mode Periodic Request Queue Depth (PTxQDepth) + * - 2'b00: 2 + * - 2'b01: 4 + * - 2'b10: 8 + * - 2'b11:16 + * Note: This field is configured using the OTG_PERIO_TX_QUEUE_DEPTH parameter. + */ +#define USB_OTGFS_GHWCFG2_PTXQDEPTH 0x00000003U +#define USB_OTGFS_GHWCFG2_PTXQDEPTH_M (USB_OTGFS_GHWCFG2_PTXQDEPTH_V << USB_OTGFS_GHWCFG2_PTXQDEPTH_S) +#define USB_OTGFS_GHWCFG2_PTXQDEPTH_V 0x00000003U +#define USB_OTGFS_GHWCFG2_PTXQDEPTH_S 24 +/** USB_OTGFS_GHWCFG2_TKNQDEPTH : RO; bitpos: [30:26]; default: 8; + * Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + * Range: 0-30 + * + * Note: This field is configured using the OTG_TOKEN_QUEUE_DEPTH parameter. + */ +#define USB_OTGFS_GHWCFG2_TKNQDEPTH 0x0000001FU +#define USB_OTGFS_GHWCFG2_TKNQDEPTH_M (USB_OTGFS_GHWCFG2_TKNQDEPTH_V << USB_OTGFS_GHWCFG2_TKNQDEPTH_S) +#define USB_OTGFS_GHWCFG2_TKNQDEPTH_V 0x0000001FU +#define USB_OTGFS_GHWCFG2_TKNQDEPTH_S 26 + +/** USB_OTGFS_GHWCFG3_REG register + * User Hardware Configuration 3 Register + */ +#define USB_OTGFS_GHWCFG3_REG(i) (DR_REG_USB_BASE(i) + 0x4c) +/** USB_OTGFS_GHWCFG3_XFERSIZEWIDTH : RO; bitpos: [3:0]; default: 5; + * Width of Transfer Size Counters (XferSizeWidth) + * - 4'b0000: 11 bits + * - 4'b0001: 12 bits + * ... + * - 4'b1000: 19 bits + * - Others: Reserved + * Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter. + */ +#define USB_OTGFS_GHWCFG3_XFERSIZEWIDTH 0x0000000FU +#define USB_OTGFS_GHWCFG3_XFERSIZEWIDTH_M (USB_OTGFS_GHWCFG3_XFERSIZEWIDTH_V << USB_OTGFS_GHWCFG3_XFERSIZEWIDTH_S) +#define USB_OTGFS_GHWCFG3_XFERSIZEWIDTH_V 0x0000000FU +#define USB_OTGFS_GHWCFG3_XFERSIZEWIDTH_S 0 +/** USB_OTGFS_GHWCFG3_PKTSIZEWIDTH : RO; bitpos: [6:4]; default: 3; + * Width of Packet Size Counters (PktSizeWidth) + * - 3'b000: 4 bits + * - 3'b001: 5 bits + * - 3'b010: 6 bits + * - 3'b011: 7 bits + * - 3'b100: 8 bits + * - 3'b101: 9 bits + * - 3'b110: 10 bits + * - Others: Reserved + * Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter. + */ +#define USB_OTGFS_GHWCFG3_PKTSIZEWIDTH 0x00000007U +#define USB_OTGFS_GHWCFG3_PKTSIZEWIDTH_M (USB_OTGFS_GHWCFG3_PKTSIZEWIDTH_V << USB_OTGFS_GHWCFG3_PKTSIZEWIDTH_S) +#define USB_OTGFS_GHWCFG3_PKTSIZEWIDTH_V 0x00000007U +#define USB_OTGFS_GHWCFG3_PKTSIZEWIDTH_S 4 +/** USB_OTGFS_GHWCFG3_OTGEN : RO; bitpos: [7]; default: 1; + * OTG Function Enabled (OtgEn) + * + * The application uses this bit to indicate the OTG capabilities of the controller . + * - 1'b0: Not OTG capable + * - 1'b1: OTG Capable + * Note: This field is configured using the OTG_MODE parameter. + */ +#define USB_OTGFS_GHWCFG3_OTGEN (BIT(7)) +#define USB_OTGFS_GHWCFG3_OTGEN_M (USB_OTGFS_GHWCFG3_OTGEN_V << USB_OTGFS_GHWCFG3_OTGEN_S) +#define USB_OTGFS_GHWCFG3_OTGEN_V 0x00000001U +#define USB_OTGFS_GHWCFG3_OTGEN_S 7 +/** USB_OTGFS_GHWCFG3_I2CINTSEL : RO; bitpos: [8]; default: 0; + * I2C Selection (I2CIntSel) + * - 1'b0: I2C Interface is not available on the controller. + * - 1'b1: I2C Interface is available on the controller. + * Note: This field is configured using the OTG_I2C_INTERFACE parameter. + */ +#define USB_OTGFS_GHWCFG3_I2CINTSEL (BIT(8)) +#define USB_OTGFS_GHWCFG3_I2CINTSEL_M (USB_OTGFS_GHWCFG3_I2CINTSEL_V << USB_OTGFS_GHWCFG3_I2CINTSEL_S) +#define USB_OTGFS_GHWCFG3_I2CINTSEL_V 0x00000001U +#define USB_OTGFS_GHWCFG3_I2CINTSEL_S 8 +/** USB_OTGFS_GHWCFG3_VNDCTLSUPT : RO; bitpos: [9]; default: 0; + * Vendor Control Interface Support (VndctlSupt) + * + * - 1'b0: Vendor Control Interface is not available on the core. + * - 1'b1: Vendor Control Interface is available. + * Note: This field is configured using the OTG_VENDOR_CTL_INTERFACE parameter. + */ +#define USB_OTGFS_GHWCFG3_VNDCTLSUPT (BIT(9)) +#define USB_OTGFS_GHWCFG3_VNDCTLSUPT_M (USB_OTGFS_GHWCFG3_VNDCTLSUPT_V << USB_OTGFS_GHWCFG3_VNDCTLSUPT_S) +#define USB_OTGFS_GHWCFG3_VNDCTLSUPT_V 0x00000001U +#define USB_OTGFS_GHWCFG3_VNDCTLSUPT_S 9 +/** USB_OTGFS_GHWCFG3_OPTFEATURE : RO; bitpos: [10]; default: 1; + * Optional Features Removed (OptFeature) + * Indicates whether the User ID register, GPIO interface ports, and SOF toggle and + * counter ports were removed for gate count optimization by enabling Remove Optional + * Features. + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_RM_OPT_FEATURES parameter. + */ +#define USB_OTGFS_GHWCFG3_OPTFEATURE (BIT(10)) +#define USB_OTGFS_GHWCFG3_OPTFEATURE_M (USB_OTGFS_GHWCFG3_OPTFEATURE_V << USB_OTGFS_GHWCFG3_OPTFEATURE_S) +#define USB_OTGFS_GHWCFG3_OPTFEATURE_V 0x00000001U +#define USB_OTGFS_GHWCFG3_OPTFEATURE_S 10 +/** USB_OTGFS_GHWCFG3_RSTTYPE : RO; bitpos: [11]; default: 0; + * Reset Style for Clocked always Blocks in RTL (RstType) + * - 1'b0: Asynchronous reset is used in the controller + * - 1'b1: Synchronous reset is used in the controller + * Note: This field is configured using the OTG_SYNC_RESET_TYPE parameter. + */ +#define USB_OTGFS_GHWCFG3_RSTTYPE (BIT(11)) +#define USB_OTGFS_GHWCFG3_RSTTYPE_M (USB_OTGFS_GHWCFG3_RSTTYPE_V << USB_OTGFS_GHWCFG3_RSTTYPE_S) +#define USB_OTGFS_GHWCFG3_RSTTYPE_V 0x00000001U +#define USB_OTGFS_GHWCFG3_RSTTYPE_S 11 +/** USB_OTGFS_GHWCFG3_ADPSUPPORT : RO; bitpos: [12]; default: 0; + * This bit indicates whether ADP logic is present within or external to the controller + * - 0: No ADP logic present with the controller + * - 1: ADP logic is present along with the controller. + */ +#define USB_OTGFS_GHWCFG3_ADPSUPPORT (BIT(12)) +#define USB_OTGFS_GHWCFG3_ADPSUPPORT_M (USB_OTGFS_GHWCFG3_ADPSUPPORT_V << USB_OTGFS_GHWCFG3_ADPSUPPORT_S) +#define USB_OTGFS_GHWCFG3_ADPSUPPORT_V 0x00000001U +#define USB_OTGFS_GHWCFG3_ADPSUPPORT_S 12 +/** USB_OTGFS_GHWCFG3_HSICMODE : RO; bitpos: [13]; default: 0; + * HSIC mode specified for Mode of Operation + * Value Range: 0 - 1 + * - 1: HSIC-capable with shared UTMI PHY interface + * - 0: Non-HSIC-capable + */ +#define USB_OTGFS_GHWCFG3_HSICMODE (BIT(13)) +#define USB_OTGFS_GHWCFG3_HSICMODE_M (USB_OTGFS_GHWCFG3_HSICMODE_V << USB_OTGFS_GHWCFG3_HSICMODE_S) +#define USB_OTGFS_GHWCFG3_HSICMODE_V 0x00000001U +#define USB_OTGFS_GHWCFG3_HSICMODE_S 13 +/** USB_OTGFS_GHWCFG3_BCSUPPORT : RO; bitpos: [14]; default: 0; + * This bit indicates the controller support for Battery Charger. + * - 0 - No Battery Charger Support + * - 1 - Battery Charger support present + */ +#define USB_OTGFS_GHWCFG3_BCSUPPORT (BIT(14)) +#define USB_OTGFS_GHWCFG3_BCSUPPORT_M (USB_OTGFS_GHWCFG3_BCSUPPORT_V << USB_OTGFS_GHWCFG3_BCSUPPORT_S) +#define USB_OTGFS_GHWCFG3_BCSUPPORT_V 0x00000001U +#define USB_OTGFS_GHWCFG3_BCSUPPORT_S 14 +/** USB_OTGFS_GHWCFG3_LPMMODE : RO; bitpos: [15]; default: 0; + * LPM mode specified for Mode of Operation. + */ +#define USB_OTGFS_GHWCFG3_LPMMODE (BIT(15)) +#define USB_OTGFS_GHWCFG3_LPMMODE_M (USB_OTGFS_GHWCFG3_LPMMODE_V << USB_OTGFS_GHWCFG3_LPMMODE_S) +#define USB_OTGFS_GHWCFG3_LPMMODE_V 0x00000001U +#define USB_OTGFS_GHWCFG3_LPMMODE_S 15 +/** USB_OTGFS_GHWCFG3_DFIFODEPTH : RO; bitpos: [31:16]; default: 200; + * DFIFO Depth (DfifoDepth - EP_LOC_CNT) + * + * This value is in terms of 32-bit words. + * - Minimum value is 32 + * - Maximum value is 32,768 + * Note: This field is configured using the OTG_DFIFO_DEPTH parameter. For more + * information on EP_LOC_CNT, see the Endpoint Information Controller (EPINFO_CTL) + * section. + */ +#define USB_OTGFS_GHWCFG3_DFIFODEPTH 0x0000FFFFU +#define USB_OTGFS_GHWCFG3_DFIFODEPTH_M (USB_OTGFS_GHWCFG3_DFIFODEPTH_V << USB_OTGFS_GHWCFG3_DFIFODEPTH_S) +#define USB_OTGFS_GHWCFG3_DFIFODEPTH_V 0x0000FFFFU +#define USB_OTGFS_GHWCFG3_DFIFODEPTH_S 16 + +/** USB_OTGFS_GHWCFG4_REG register + * User Hardware Configuration 4 Register Note Bit [31] is available only when + * Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this + * field is reserved. + */ +#define USB_OTGFS_GHWCFG4_REG(i) (DR_REG_USB_BASE(i) + 0x50) +/** USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS : RO; bitpos: [3:0]; default: 0; + * Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + * + * Range: 0-15 + */ +#define USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS 0x0000000FU +#define USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS_M (USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS_V << USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS_S) +#define USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS_V 0x0000000FU +#define USB_OTGFS_GHWCFG4_NUMDEVPERIOEPS_S 0 +/** USB_OTGFS_GHWCFG4_PARTIALPWRDN : RO; bitpos: [4]; default: 1; + * Enable Partial Power Down (PartialPwrDn) + * - 1'b0: Partial Power Down Not Enabled + * - 1'b1: Partial Power Down Enabled + */ +#define USB_OTGFS_GHWCFG4_PARTIALPWRDN (BIT(4)) +#define USB_OTGFS_GHWCFG4_PARTIALPWRDN_M (USB_OTGFS_GHWCFG4_PARTIALPWRDN_V << USB_OTGFS_GHWCFG4_PARTIALPWRDN_S) +#define USB_OTGFS_GHWCFG4_PARTIALPWRDN_V 0x00000001U +#define USB_OTGFS_GHWCFG4_PARTIALPWRDN_S 4 +/** USB_OTGFS_GHWCFG4_AHBFREQ : RO; bitpos: [5]; default: 1; + * Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + * - 1'b0: No + * - 1'b1: Yes + */ +#define USB_OTGFS_GHWCFG4_AHBFREQ (BIT(5)) +#define USB_OTGFS_GHWCFG4_AHBFREQ_M (USB_OTGFS_GHWCFG4_AHBFREQ_V << USB_OTGFS_GHWCFG4_AHBFREQ_S) +#define USB_OTGFS_GHWCFG4_AHBFREQ_V 0x00000001U +#define USB_OTGFS_GHWCFG4_AHBFREQ_S 5 +/** USB_OTGFS_GHWCFG4_HIBERNATION : RO; bitpos: [6]; default: 0; + * Enable Hibernation (Hibernation) + * - 1'b0: Hibernation feature not enabled + * - 1'b1: Hibernation feature enabled + */ +#define USB_OTGFS_GHWCFG4_HIBERNATION (BIT(6)) +#define USB_OTGFS_GHWCFG4_HIBERNATION_M (USB_OTGFS_GHWCFG4_HIBERNATION_V << USB_OTGFS_GHWCFG4_HIBERNATION_S) +#define USB_OTGFS_GHWCFG4_HIBERNATION_V 0x00000001U +#define USB_OTGFS_GHWCFG4_HIBERNATION_S 6 +/** USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION : RO; bitpos: [7]; default: 0; + * Enable Hibernation + * - 1'b0: Extended Hibernation feature not enabled + * - 1'b1: Extended Hibernation feature enabled + */ +#define USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION (BIT(7)) +#define USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION_M (USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION_V << USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION_S) +#define USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION_V 0x00000001U +#define USB_OTGFS_GHWCFG4_EXTENDEDHIBERNATION_S 7 +/** USB_OTGFS_GHWCFG4_ACGSUPT : RO; bitpos: [12]; default: 0; + * Active Clock Gating Support + * + * This bit indicates that the controller supports the Dynamic (Switching) Power + * Reduction during periods + * when there is no USB and AHB Traffic. + * - 1'b0: Active Clock Gating is not enabled. + * - 1'b1: Active Clock Gating Enabled. + */ +#define USB_OTGFS_GHWCFG4_ACGSUPT (BIT(12)) +#define USB_OTGFS_GHWCFG4_ACGSUPT_M (USB_OTGFS_GHWCFG4_ACGSUPT_V << USB_OTGFS_GHWCFG4_ACGSUPT_S) +#define USB_OTGFS_GHWCFG4_ACGSUPT_V 0x00000001U +#define USB_OTGFS_GHWCFG4_ACGSUPT_S 12 +/** USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT : RO; bitpos: [13]; default: 1; + * Enhanced LPM Support (EnhancedLPMSupt) + * + * This bit indicates that the controller supports the following behavior: + * L1 Entry Behavior based on FIFO Status + * - TX FIFO + * - Accept L1 Request even if ISOC OUT TX FIFO is not empty. + * - Reject L1 Request if Non-Periodic TX FIFO is not empty. + * - Ensure application can flush the TX FIFO while the Controller is in L1. + * - RX FIFO + * - Accept L1 Request even if RX FIFO (common to Periodic and Non-Periodic) is not + * empty. + * - Accept L1 Request but delay SLEEPM assertion until RX SINK Buffer is empty. + * + * Prevent L1 Entry if a Control Transfer is in progress on any Control Endpoint. + * Ability to Flush TxFIFO even if PHY Clock is gated. + * + */ +#define USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT (BIT(13)) +#define USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT_M (USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT_V << USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT_S) +#define USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT_V 0x00000001U +#define USB_OTGFS_GHWCFG4_ENHANCEDLPMSUPT_S 13 +/** USB_OTGFS_GHWCFG4_PHYDATAWIDTH : RO; bitpos: [15:14]; default: 2; + * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + * (PhyDataWidth)When a ULPI PHY is used, an internal wrapper converts ULPI to + * UTMI+. + * - 2'b00: 8 bits + * - 2'b01: 16 bits + * - 2'b10: 8/16 bits, software selectable + * - Others: Reserved + */ +#define USB_OTGFS_GHWCFG4_PHYDATAWIDTH 0x00000003U +#define USB_OTGFS_GHWCFG4_PHYDATAWIDTH_M (USB_OTGFS_GHWCFG4_PHYDATAWIDTH_V << USB_OTGFS_GHWCFG4_PHYDATAWIDTH_S) +#define USB_OTGFS_GHWCFG4_PHYDATAWIDTH_V 0x00000003U +#define USB_OTGFS_GHWCFG4_PHYDATAWIDTH_S 14 +/** USB_OTGFS_GHWCFG4_NUMCTLEPS : RO; bitpos: [19:16]; default: 0; + * Number of Device Mode Control Endpoints in Addition to + * Endpoint 0 (NumCtlEps) + * Range: 0-15 + */ +#define USB_OTGFS_GHWCFG4_NUMCTLEPS 0x0000000FU +#define USB_OTGFS_GHWCFG4_NUMCTLEPS_M (USB_OTGFS_GHWCFG4_NUMCTLEPS_V << USB_OTGFS_GHWCFG4_NUMCTLEPS_S) +#define USB_OTGFS_GHWCFG4_NUMCTLEPS_V 0x0000000FU +#define USB_OTGFS_GHWCFG4_NUMCTLEPS_S 16 +/** USB_OTGFS_GHWCFG4_IDDGFLTR : RO; bitpos: [20]; default: 1; + * IDDIG Filter Enable (IddgFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ +#define USB_OTGFS_GHWCFG4_IDDGFLTR (BIT(20)) +#define USB_OTGFS_GHWCFG4_IDDGFLTR_M (USB_OTGFS_GHWCFG4_IDDGFLTR_V << USB_OTGFS_GHWCFG4_IDDGFLTR_S) +#define USB_OTGFS_GHWCFG4_IDDGFLTR_V 0x00000001U +#define USB_OTGFS_GHWCFG4_IDDGFLTR_S 20 +/** USB_OTGFS_GHWCFG4_VBUSVALIDFLTR : RO; bitpos: [21]; default: 1; + * VBUS Valid Filter Enabled (VBusValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ +#define USB_OTGFS_GHWCFG4_VBUSVALIDFLTR (BIT(21)) +#define USB_OTGFS_GHWCFG4_VBUSVALIDFLTR_M (USB_OTGFS_GHWCFG4_VBUSVALIDFLTR_V << USB_OTGFS_GHWCFG4_VBUSVALIDFLTR_S) +#define USB_OTGFS_GHWCFG4_VBUSVALIDFLTR_V 0x00000001U +#define USB_OTGFS_GHWCFG4_VBUSVALIDFLTR_S 21 +/** USB_OTGFS_GHWCFG4_AVALIDFLTR : RO; bitpos: [22]; default: 1; + * a_valid Filter Enabled (AValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ +#define USB_OTGFS_GHWCFG4_AVALIDFLTR (BIT(22)) +#define USB_OTGFS_GHWCFG4_AVALIDFLTR_M (USB_OTGFS_GHWCFG4_AVALIDFLTR_V << USB_OTGFS_GHWCFG4_AVALIDFLTR_S) +#define USB_OTGFS_GHWCFG4_AVALIDFLTR_V 0x00000001U +#define USB_OTGFS_GHWCFG4_AVALIDFLTR_S 22 +/** USB_OTGFS_GHWCFG4_BVALIDFLTR : RO; bitpos: [23]; default: 1; + * b_valid Filter Enabled (BValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ +#define USB_OTGFS_GHWCFG4_BVALIDFLTR (BIT(23)) +#define USB_OTGFS_GHWCFG4_BVALIDFLTR_M (USB_OTGFS_GHWCFG4_BVALIDFLTR_V << USB_OTGFS_GHWCFG4_BVALIDFLTR_S) +#define USB_OTGFS_GHWCFG4_BVALIDFLTR_V 0x00000001U +#define USB_OTGFS_GHWCFG4_BVALIDFLTR_S 23 +/** USB_OTGFS_GHWCFG4_SESSENDFLTR : RO; bitpos: [24]; default: 1; + * session_end Filter Enabled (SessEndFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ +#define USB_OTGFS_GHWCFG4_SESSENDFLTR (BIT(24)) +#define USB_OTGFS_GHWCFG4_SESSENDFLTR_M (USB_OTGFS_GHWCFG4_SESSENDFLTR_V << USB_OTGFS_GHWCFG4_SESSENDFLTR_S) +#define USB_OTGFS_GHWCFG4_SESSENDFLTR_V 0x00000001U +#define USB_OTGFS_GHWCFG4_SESSENDFLTR_S 24 +/** USB_OTGFS_GHWCFG4_DEDFIFOMODE : RO; bitpos: [25]; default: 1; + * Enable Dedicated Transmit FIFO for device IN Endpoints + * (DedFifoMode) + * - 1'b0 : Dedicated Transmit FIFO Operation not enabled. + * - 1'b1 : Dedicated Transmit FIFO Operation enabled. + */ +#define USB_OTGFS_GHWCFG4_DEDFIFOMODE (BIT(25)) +#define USB_OTGFS_GHWCFG4_DEDFIFOMODE_M (USB_OTGFS_GHWCFG4_DEDFIFOMODE_V << USB_OTGFS_GHWCFG4_DEDFIFOMODE_S) +#define USB_OTGFS_GHWCFG4_DEDFIFOMODE_V 0x00000001U +#define USB_OTGFS_GHWCFG4_DEDFIFOMODE_S 25 +/** USB_OTGFS_GHWCFG4_INEPS : RO; bitpos: [29:26]; default: 4; + * Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + * - 0: 1 IN Endpoint + * - 1: 2 IN Endpoints + * .... + * - 15: 16 IN Endpoints + */ +#define USB_OTGFS_GHWCFG4_INEPS 0x0000000FU +#define USB_OTGFS_GHWCFG4_INEPS_M (USB_OTGFS_GHWCFG4_INEPS_V << USB_OTGFS_GHWCFG4_INEPS_S) +#define USB_OTGFS_GHWCFG4_INEPS_V 0x0000000FU +#define USB_OTGFS_GHWCFG4_INEPS_S 26 +/** USB_OTGFS_GHWCFG4_DESCDMAENABLED : RO; bitpos: [30]; default: 1; + * Scatter/Gather DMA configuration + * - 1'b0: Non-Scatter/Gather DMA configuration + * - 1'b1: Scatter/Gather DMA configuration + */ +#define USB_OTGFS_GHWCFG4_DESCDMAENABLED (BIT(30)) +#define USB_OTGFS_GHWCFG4_DESCDMAENABLED_M (USB_OTGFS_GHWCFG4_DESCDMAENABLED_V << USB_OTGFS_GHWCFG4_DESCDMAENABLED_S) +#define USB_OTGFS_GHWCFG4_DESCDMAENABLED_V 0x00000001U +#define USB_OTGFS_GHWCFG4_DESCDMAENABLED_S 30 +/** USB_OTGFS_GHWCFG4_DESCDMA : RO; bitpos: [31]; default: 1; + * Scatter/Gather DMA configuration + * - 1'b0: Non Dynamic configuration + * - 1'b1: Dynamic configuration + * Note: This field is configured using the OTG_EN_DESC_DMA parameter. + */ +#define USB_OTGFS_GHWCFG4_DESCDMA (BIT(31)) +#define USB_OTGFS_GHWCFG4_DESCDMA_M (USB_OTGFS_GHWCFG4_DESCDMA_V << USB_OTGFS_GHWCFG4_DESCDMA_S) +#define USB_OTGFS_GHWCFG4_DESCDMA_V 0x00000001U +#define USB_OTGFS_GHWCFG4_DESCDMA_S 31 + +/** USB_OTGFS_GDFIFOCFG_REG register + * Global DFIFO Configuration Register + */ +#define USB_OTGFS_GDFIFOCFG_REG(i) (DR_REG_USB_BASE(i) + 0x5c) +/** USB_OTGFS_GDFIFOCFG_GDFIFOCFG : R/W; bitpos: [15:0]; default: 256; + * GDFIFOCfg + * + * This field is for dynamic programming of the DFIFO Size. This value takes effect + * only when the application programs a non zero value to this register. The value + * programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The + * core does not have any corrective logic if the FIFO sizes are programmed + * incorrectly. + */ +#define USB_OTGFS_GDFIFOCFG_GDFIFOCFG 0x0000FFFFU +#define USB_OTGFS_GDFIFOCFG_GDFIFOCFG_M (USB_OTGFS_GDFIFOCFG_GDFIFOCFG_V << USB_OTGFS_GDFIFOCFG_GDFIFOCFG_S) +#define USB_OTGFS_GDFIFOCFG_GDFIFOCFG_V 0x0000FFFFU +#define USB_OTGFS_GDFIFOCFG_GDFIFOCFG_S 0 +/** USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR : R/W; bitpos: [31:16]; default: 200; + * EPInfoBaseAddr + * + * This field provides the start address of the EP info controller. + */ +#define USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR 0x0000FFFFU +#define USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR_M (USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR_V << USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR_S) +#define USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR_V 0x0000FFFFU +#define USB_OTGFS_GDFIFOCFG_EPINFOBASEADDR_S 16 + +/** USB_OTGFS_HPTXFSIZ_REG register + * Host Periodic Transmit FIFO Size Register This register holds the size and the + * memory start address of the Periodic TxFIFO. Note: Read the reset value of this + * register only after the following conditions: - If IDDIG_FILTER is disabled, read + * only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the + * filter timer expires. + */ +#define USB_OTGFS_HPTXFSIZ_REG(i) (DR_REG_USB_BASE(i) + 0x100) +/** USB_OTGFS_HPTXFSIZ_PTXFSTADDR : R/W; bitpos: [9:0]; default: 512; + * Host Periodic TxFIFO Start Address (PTxFStAddr) + * + * The power-on reset value of this register is the sum of the Largest Rx Data FIFO + * Depth and Largest Non-periodic Tx Data FIFO Depth.These parameters are: + * + * In shared FIFO operation: + * - OTG_RX_DFIFO_DEPTH + OTG_TX_NPERIO_DFIFO_DEPTH + * + * In dedicated FIFO mode: + * - OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH If Enable Dynamic FIFO Sizing? + * was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are + * optimized, and reads return the power-on value. If Enable Dynamic FIFO Sizing? was + * selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new + * value in this field. + * + * Programmed values must not exceed the power-on value set in coreConsultant. + */ +#define USB_OTGFS_HPTXFSIZ_PTXFSTADDR 0x000003FFU +#define USB_OTGFS_HPTXFSIZ_PTXFSTADDR_M (USB_OTGFS_HPTXFSIZ_PTXFSTADDR_V << USB_OTGFS_HPTXFSIZ_PTXFSTADDR_S) +#define USB_OTGFS_HPTXFSIZ_PTXFSTADDR_V 0x000003FFU +#define USB_OTGFS_HPTXFSIZ_PTXFSTADDR_S 0 +/** USB_OTGFS_HPTXFSIZ_PTXFSIZE : R/W; bitpos: [24:16]; default: 256; + * Host Periodic TxFIFO Depth (PTxFSize) + * + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * The power-on reset value of this register is specified as the Largest Host Mode + * Periodic Tx Data FIFO Depth. + * - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter + * OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on + * value. + * - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter + * OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + */ +#define USB_OTGFS_HPTXFSIZ_PTXFSIZE 0x000001FFU +#define USB_OTGFS_HPTXFSIZ_PTXFSIZE_M (USB_OTGFS_HPTXFSIZ_PTXFSIZE_V << USB_OTGFS_HPTXFSIZ_PTXFSIZE_S) +#define USB_OTGFS_HPTXFSIZ_PTXFSIZE_V 0x000001FFU +#define USB_OTGFS_HPTXFSIZ_PTXFSIZE_S 16 + +/** USB_OTGFS_DIEPTXF1_REG register + * Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in + * dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start + * address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data + * for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 + * to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and + * memory start address. + */ +#define USB_OTGFS_DIEPTXF1_REG(i) (DR_REG_USB_BASE(i) + 0x104) +/** USB_OTGFS_DIEPTXF1_INEPNTXFSTADDR : R/W; bitpos: [9:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * + * This field contains the memory start address for IN endpoint Transmit FIFOn (0 Slave mode + * - GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid + * - GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode + * - GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode + */ +#define USB_OTGFS_HCFG_DESCDMA (BIT(23)) +#define USB_OTGFS_HCFG_DESCDMA_M (USB_OTGFS_HCFG_DESCDMA_V << USB_OTGFS_HCFG_DESCDMA_S) +#define USB_OTGFS_HCFG_DESCDMA_V 0x00000001U +#define USB_OTGFS_HCFG_DESCDMA_S 23 +/** USB_OTGFS_HCFG_FRLISTEN : R/W; bitpos: [25:24]; default: 0; + * Frame List Entries(FrListEn) + * + * The value in the register specifies the number of entries in the Frame list. + * This field is valid only in Scatter/Gather DMA mode. + * - 2'b00: 8 Entries + * - 2'b01: 16 Entries + * - 2'b10: 32 Entries + * - 2'b11: 64 Entries + */ +#define USB_OTGFS_HCFG_FRLISTEN 0x00000003U +#define USB_OTGFS_HCFG_FRLISTEN_M (USB_OTGFS_HCFG_FRLISTEN_V << USB_OTGFS_HCFG_FRLISTEN_S) +#define USB_OTGFS_HCFG_FRLISTEN_V 0x00000003U +#define USB_OTGFS_HCFG_FRLISTEN_S 24 +/** USB_OTGFS_HCFG_PERSCHEDENA : R/W; bitpos: [26]; default: 0; + * Enable Periodic Scheduling (PerSchedEna): + * + * Applicable in host DDMA mode only. + * Enables periodic scheduling within the core. Initially, the bit is reset. + * The core will not process any periodic channels. + * + * As soon as this bit is set, + * the core will get ready to start scheduling periodic channels and + * sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core + * has enabled periodic scheduling. Once HCFG.PerSchedEna is set, + * the application is not supposed to again reset the bit unless HCFG.PerSchedStat + * is set. + * + * As soon as this bit is reset, the core will get ready to + * stop scheduling periodic channels and resets HCFG.PerSchedStat. + */ +#define USB_OTGFS_HCFG_PERSCHEDENA (BIT(26)) +#define USB_OTGFS_HCFG_PERSCHEDENA_M (USB_OTGFS_HCFG_PERSCHEDENA_V << USB_OTGFS_HCFG_PERSCHEDENA_S) +#define USB_OTGFS_HCFG_PERSCHEDENA_V 0x00000001U +#define USB_OTGFS_HCFG_PERSCHEDENA_S 26 +/** USB_OTGFS_HCFG_MODECHTIMEN : R/W; bitpos: [31]; default: 0; + * Mode Change Ready Timer Enable (ModeChTimEn) + * + * This bit is used to enable/disable the Host core to wait 200 PHY clock cycles at + * the end of Resume to change the opmode signal to the PHY to 00 + * after Suspend or LPM. + * - 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 + * at the end of resume to the change the opmode from 2'b10 to 2'b00 + * - 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to + * change the opmode from 2'b10 to 2'b00. + */ +#define USB_OTGFS_HCFG_MODECHTIMEN (BIT(31)) +#define USB_OTGFS_HCFG_MODECHTIMEN_M (USB_OTGFS_HCFG_MODECHTIMEN_V << USB_OTGFS_HCFG_MODECHTIMEN_S) +#define USB_OTGFS_HCFG_MODECHTIMEN_V 0x00000001U +#define USB_OTGFS_HCFG_MODECHTIMEN_S 31 + +/** USB_OTGFS_HFIR_REG register + * Host Frame Interval Register + */ +#define USB_OTGFS_HFIR_REG(i) (DR_REG_USB_BASE(i) + 0x404) +/** USB_OTGFS_HFIR_FRINT : R/W; bitpos: [15:0]; default: 60000; + * Frame Interval (FrInt) + * + * The value that the application programs to this field specifies + * the interval between two consecutive SOFs (FS) or micro- + * SOFs (HS) or Keep-Alive tokens (HS). This field contains the + * number of PHY clocks that constitute the required frame + * interval. The Default value set in this field is for FS operation + * when the PHY clock frequency is 60 MHz. The application can + * write a value to this register only after the Port Enable bit of the + * Host Port Control and Status register (HPRT.PrtEnaPort) has + * been Set. If no value is programmed, the core calculates the + * value based on the PHY clock specified in the FS/LS PHY + * Clock Select field of the Host Configuration register + * (HCFG.FSLSPclkSel). Do not change the value of this field + * after the initial configuration. + * - 125 s * (PHY clock frequency for HS) + * - 1 ms * (PHY clock frequency for FS/LS) + */ +#define USB_OTGFS_HFIR_FRINT 0x0000FFFFU +#define USB_OTGFS_HFIR_FRINT_M (USB_OTGFS_HFIR_FRINT_V << USB_OTGFS_HFIR_FRINT_S) +#define USB_OTGFS_HFIR_FRINT_V 0x0000FFFFU +#define USB_OTGFS_HFIR_FRINT_S 0 +/** USB_OTGFS_HFIR_HFIRRLDCTRL : R/W; bitpos: [16]; default: 0; + * Reload Control (HFIRRldCtrl) + * + * This bit allows dynamic reloading of the HFIR register during run time. + * - 1'b0 : The HFIR cannot be reloaded dynamically + * - 1'b1: the HFIR can be dynamically reloaded during runtime. + * This bit needs to be programmed during initial configuration and its value should + * not be changed during runtime. + */ +#define USB_OTGFS_HFIR_HFIRRLDCTRL (BIT(16)) +#define USB_OTGFS_HFIR_HFIRRLDCTRL_M (USB_OTGFS_HFIR_HFIRRLDCTRL_V << USB_OTGFS_HFIR_HFIRRLDCTRL_S) +#define USB_OTGFS_HFIR_HFIRRLDCTRL_V 0x00000001U +#define USB_OTGFS_HFIR_HFIRRLDCTRL_S 16 + +/** USB_OTGFS_HFNUM_REG register + * Host Frame Number/Frame Time Remaining Register This register indicates the + * current frame number. It also indicates the time remaining (in terms of the number + * of PHY clocks) in the current (micro)frame. Note: Read the reset value of this + * register only after the following conditions: - If IDDIG_FILTER is disabled, read + * only when the PHY clock is stable. - If IDDIG_FILTER is enabled, read only after + * the filter timer expires. + */ +#define USB_OTGFS_HFNUM_REG(i) (DR_REG_USB_BASE(i) + 0x408) +/** USB_OTGFS_HFNUM_FRNUM : RO; bitpos: [15:0]; default: 16383; + * Frame Number (FrNum) + * + * This field increments when a new SOF is transmitted on the + * USB, and is reset to 0 when it reaches 16'h3FFF. + */ +#define USB_OTGFS_HFNUM_FRNUM 0x0000FFFFU +#define USB_OTGFS_HFNUM_FRNUM_M (USB_OTGFS_HFNUM_FRNUM_V << USB_OTGFS_HFNUM_FRNUM_S) +#define USB_OTGFS_HFNUM_FRNUM_V 0x0000FFFFU +#define USB_OTGFS_HFNUM_FRNUM_S 0 +/** USB_OTGFS_HFNUM_FRREM : RO; bitpos: [31:16]; default: 0; + * Frame Time Remaining (FrRem) + * + * Indicates the amount of time remaining in the current + * microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This + * field decrements on each PHY clock. When it reaches zero, this + * field is reloaded with the value in the Frame Interval register and + * a new SOF is transmitted on the USB. + */ +#define USB_OTGFS_HFNUM_FRREM 0x0000FFFFU +#define USB_OTGFS_HFNUM_FRREM_M (USB_OTGFS_HFNUM_FRREM_V << USB_OTGFS_HFNUM_FRREM_S) +#define USB_OTGFS_HFNUM_FRREM_V 0x0000FFFFU +#define USB_OTGFS_HFNUM_FRREM_S 16 + +/** USB_OTGFS_HPTXSTS_REG register + * Host Periodic Transmit FIFO/Queue Status Register + */ +#define USB_OTGFS_HPTXSTS_REG(i) (DR_REG_USB_BASE(i) + 0x410) +/** USB_OTGFS_HPTXSTS_PTXFSPCAVAIL : RO; bitpos: [15:0]; default: 256; + * Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) + * + * Indicates the number of free locations available to be written to in the Periodic + * TxFIFO. + * + * Values are in terms of 32-bit words + * - 16'h0 : Periodic TxFIFO is full + * - 16'h1 : 1 word available + * - 16'h2 : 2 words available + * - 16'hn : n words available (where 0 n 32,768) + * - 16'h8000 : 32,768 words + * - Others : Reserved + */ +#define USB_OTGFS_HPTXSTS_PTXFSPCAVAIL 0x0000FFFFU +#define USB_OTGFS_HPTXSTS_PTXFSPCAVAIL_M (USB_OTGFS_HPTXSTS_PTXFSPCAVAIL_V << USB_OTGFS_HPTXSTS_PTXFSPCAVAIL_S) +#define USB_OTGFS_HPTXSTS_PTXFSPCAVAIL_V 0x0000FFFFU +#define USB_OTGFS_HPTXSTS_PTXFSPCAVAIL_S 0 +/** USB_OTGFS_HPTXSTS_PTXQSPCAVAIL : RO; bitpos: [23:16]; default: 8; + * Periodic Transmit Request Queue Space Available (PTxQSpcAvail) + * + * Indicates the number of free locations available to be written in the Periodic + * Transmit Request Queue. This queue holds both IN and OUT requests. + * - 8'h0: Periodic Transmit Request Queue is full + * - 8'h1: 1 location available + * - 8'h2: 2 locations available + * - n: n locations available (0 <= n <= 16) + * - Others: Reserved + */ +#define USB_OTGFS_HPTXSTS_PTXQSPCAVAIL 0x000000FFU +#define USB_OTGFS_HPTXSTS_PTXQSPCAVAIL_M (USB_OTGFS_HPTXSTS_PTXQSPCAVAIL_V << USB_OTGFS_HPTXSTS_PTXQSPCAVAIL_S) +#define USB_OTGFS_HPTXSTS_PTXQSPCAVAIL_V 0x000000FFU +#define USB_OTGFS_HPTXSTS_PTXQSPCAVAIL_S 16 +/** USB_OTGFS_HPTXSTS_PTXQTOP : RO; bitpos: [31:24]; default: 0; + * Top of the Periodic Transmit Request Queue (PTxQTop) + * + * This indicates the Entry in the Periodic Tx Request Queue that is + * currently being processes by the MAC. + * + * This register is used for debugging. + * - Bit [31]: Odd/Even (micro)Frame + * -- 1'b0: send in even (micro)Frame + * -- 1'b1: send in odd (micro)Frame + * - Bits [30:27]: Channel/endpoint number + * - Bits [26:25]: Type + * -- 2'b00: IN/OUT + * -- 2'b01: Zero-length packet + * -- 2'b10: CSPLIT + * -- 2'b11: Disable channel command + * - Bit [24]: Terminate (last Entry for the selected channel/endpoint) + */ +#define USB_OTGFS_HPTXSTS_PTXQTOP 0x000000FFU +#define USB_OTGFS_HPTXSTS_PTXQTOP_M (USB_OTGFS_HPTXSTS_PTXQTOP_V << USB_OTGFS_HPTXSTS_PTXQTOP_S) +#define USB_OTGFS_HPTXSTS_PTXQTOP_V 0x000000FFU +#define USB_OTGFS_HPTXSTS_PTXQTOP_S 24 + +/** USB_OTGFS_HAINT_REG register + * Host All Channels Interrupt Register When a significant event occurs on a channel, + * the Host All Channels Interrupt register interrupts the application using the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is + * shown in the Interrupt Hierarchy figure in the databook. There is one interrupt bit + * per channel, up to a maximum of 16 bits. Bits in this register are set and cleared + * when the application sets and clears bits in the corresponding Host Channel-n + * Interrupt register. + */ +#define USB_OTGFS_HAINT_REG(i) (DR_REG_USB_BASE(i) + 0x414) +/** USB_OTGFS_HAINT_HAINT : RO; bitpos: [7:0]; default: 0; + * + * Channel Interrupt for channel no. + */ +#define USB_OTGFS_HAINT_HAINT 0x000000FFU +#define USB_OTGFS_HAINT_HAINT_M (USB_OTGFS_HAINT_HAINT_V << USB_OTGFS_HAINT_HAINT_S) +#define USB_OTGFS_HAINT_HAINT_V 0x000000FFU +#define USB_OTGFS_HAINT_HAINT_S 0 + +/** USB_OTGFS_HAINTMSK_REG register + * Host All Channels Interrupt Mask Register The Host All Channel Interrupt Mask + * register works with the Host All Channel Interrupt register to interrupt the + * application when an event occurs on a channel. There is one interrupt mask bit per + * channel, up to a maximum of 16 bits. + */ +#define USB_OTGFS_HAINTMSK_REG(i) (DR_REG_USB_BASE(i) + 0x418) +/** USB_OTGFS_HAINTMSK_HAINTMSK : R/W; bitpos: [7:0]; default: 0; + * Channel Interrupt Mask (HAINTMsk) + * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 + */ +#define USB_OTGFS_HAINTMSK_HAINTMSK 0x000000FFU +#define USB_OTGFS_HAINTMSK_HAINTMSK_M (USB_OTGFS_HAINTMSK_HAINTMSK_V << USB_OTGFS_HAINTMSK_HAINTMSK_S) +#define USB_OTGFS_HAINTMSK_HAINTMSK_V 0x000000FFU +#define USB_OTGFS_HAINTMSK_HAINTMSK_S 0 + +/** USB_OTGFS_HFLBAddr_REG register + * Host Frame List Base Address Register This register is present only in case of + * Scatter/Gather DMA. It is implemented as flops. This register holds the starting + * address of the Frame list information. + */ +#define USB_OTGFS_HFLBADDR_REG(i) (DR_REG_USB_BASE(i) + 0x41c) +/** USB_OTGFS_HFLBADDR_HFLBADDR : R/W; bitpos: [31:0]; default: 0; + * The starting address of the Frame list. + * This register is used only for Isochronous and Interrupt Channels. + */ +#define USB_OTGFS_HFLBADDR_HFLBADDR 0xFFFFFFFFU +#define USB_OTGFS_HFLBADDR_HFLBADDR_M (USB_OTGFS_HFLBADDR_HFLBADDR_V << USB_OTGFS_HFLBADDR_HFLBADDR_S) +#define USB_OTGFS_HFLBADDR_HFLBADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HFLBADDR_HFLBADDR_S 0 + +/** USB_OTGFS_HPRT_REG register + * Host Port Control and Status Register This register is available only in Host + * mode. Currently, the OTG Host supports only one port. A single register holds USB + * port-related information such as USB reset, enable, suspend, resume, connect + * status, and test mode for each port. It is shown in the Interrupt Hierarchy figure + * in the databook. The R_SS_WC bits in this register can trigger an interrupt to the + * application through the Host Port Interrupt bit of the Core Interrupt register + * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and + * clear the bit that caused the interrupt. For the R_SS_WC bits, the application must + * write a 1 to the bit to clear the interrupt. + */ +#define USB_OTGFS_HPRT_REG(i) (DR_REG_USB_BASE(i) + 0x440) +/** USB_OTGFS_HPRT_PRTCONNSTS : RO; bitpos: [0]; default: 0; + * Port Connect Status (PrtConnSts) + * - 0: No device is attached to the port. + * - 1: A device is attached to the port. + */ +#define USB_OTGFS_HPRT_PRTCONNSTS (BIT(0)) +#define USB_OTGFS_HPRT_PRTCONNSTS_M (USB_OTGFS_HPRT_PRTCONNSTS_V << USB_OTGFS_HPRT_PRTCONNSTS_S) +#define USB_OTGFS_HPRT_PRTCONNSTS_V 0x00000001U +#define USB_OTGFS_HPRT_PRTCONNSTS_S 0 +/** USB_OTGFS_HPRT_PRTCONNDET : R/W; bitpos: [1]; default: 0; + * Port Connect Detected (PrtConnDet) + * + * The core sets this bit when a device connection is detected + * to trigger an interrupt to the application using the Host Port + * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set + * only by the core and the application should write 1 to clear it.The application + * must write a 1 to this bit to clear the + * interrupt. + */ +#define USB_OTGFS_HPRT_PRTCONNDET (BIT(1)) +#define USB_OTGFS_HPRT_PRTCONNDET_M (USB_OTGFS_HPRT_PRTCONNDET_V << USB_OTGFS_HPRT_PRTCONNDET_S) +#define USB_OTGFS_HPRT_PRTCONNDET_V 0x00000001U +#define USB_OTGFS_HPRT_PRTCONNDET_S 1 +/** USB_OTGFS_HPRT_PRTENA : R/W; bitpos: [2]; default: 0; + * Port Enable (PrtEna) + * + * A port is enabled only by the core after a reset sequence, + * and is disabled by an overcurrent condition, a disconnect + * condition, or by the application clearing this bit. The + * application cannot Set this bit by a register write. It can only + * clear it to disable the port by writing 1. This bit does not trigger any + * interrupt to the application. + * - 1'b0: Port disabled + * - 1'b1: Port enabled + */ +#define USB_OTGFS_HPRT_PRTENA (BIT(2)) +#define USB_OTGFS_HPRT_PRTENA_M (USB_OTGFS_HPRT_PRTENA_V << USB_OTGFS_HPRT_PRTENA_S) +#define USB_OTGFS_HPRT_PRTENA_V 0x00000001U +#define USB_OTGFS_HPRT_PRTENA_S 2 +/** USB_OTGFS_HPRT_PRTENCHNG : R/W; bitpos: [3]; default: 0; + * Port Enable/Disable Change (PrtEnChng) + * + * The core sets this bit when the status of the Port Enable bit [2] of this register + * changes.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HPRT_PRTENCHNG (BIT(3)) +#define USB_OTGFS_HPRT_PRTENCHNG_M (USB_OTGFS_HPRT_PRTENCHNG_V << USB_OTGFS_HPRT_PRTENCHNG_S) +#define USB_OTGFS_HPRT_PRTENCHNG_V 0x00000001U +#define USB_OTGFS_HPRT_PRTENCHNG_S 3 +/** USB_OTGFS_HPRT_PRTOVRCURRACT : RO; bitpos: [4]; default: 0; + * Port Overcurrent Active (PrtOvrCurrAct) + * + * Indicates the overcurrent condition of the port. + * - 1'b0: No overcurrent condition + * - 1'b1: Overcurrent condition + */ +#define USB_OTGFS_HPRT_PRTOVRCURRACT (BIT(4)) +#define USB_OTGFS_HPRT_PRTOVRCURRACT_M (USB_OTGFS_HPRT_PRTOVRCURRACT_V << USB_OTGFS_HPRT_PRTOVRCURRACT_S) +#define USB_OTGFS_HPRT_PRTOVRCURRACT_V 0x00000001U +#define USB_OTGFS_HPRT_PRTOVRCURRACT_S 4 +/** USB_OTGFS_HPRT_PRTOVRCURRCHNG : R/W; bitpos: [5]; default: 0; + * Port Overcurrent Change (PrtOvrCurrChng) + * + * The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) + * in this register changes.This bit can be set only by the core and the application + * should write 1 to clear it + */ +#define USB_OTGFS_HPRT_PRTOVRCURRCHNG (BIT(5)) +#define USB_OTGFS_HPRT_PRTOVRCURRCHNG_M (USB_OTGFS_HPRT_PRTOVRCURRCHNG_V << USB_OTGFS_HPRT_PRTOVRCURRCHNG_S) +#define USB_OTGFS_HPRT_PRTOVRCURRCHNG_V 0x00000001U +#define USB_OTGFS_HPRT_PRTOVRCURRCHNG_S 5 +/** USB_OTGFS_HPRT_PRTRES : R/W; bitpos: [6]; default: 0; + * Port Resume (PrtRes) + * + * The application sets this bit to drive resume signaling on the + * port. The core continues to drive the resume signal until the + * application clears this bit. + * + * If the core detects a USB remote wakeup sequence, as + * indicated by the Port Resume/Remote Wakeup Detected + * Interrupt bit of the Core Interrupt register + * (GINTSTS.WkUpInt), the core starts driving resume + * signaling without application intervention and clears this bit + * when it detects a disconnect condition. The read value of + * this bit indicates whether the core is currently driving + * resume signaling. + * - 1'b0: No resume driven + * - 1'b1: Resume driven + * When LPM is enabled, In L1 state the behavior of this bit is as follows: + * The application sets this bit to drive resume signaling on the port. + * The core continues to drive the resume signal until a pre-determined time + * specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote + * wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected + * Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), + * the core starts driving resume signaling without application intervention + * and clears this bit at the end of resume.This bit can be set by both core or + * application + * and also cleared by core or application. This bit is cleared by the core even if + * there is + * no device connected to the Host. + */ +#define USB_OTGFS_HPRT_PRTRES (BIT(6)) +#define USB_OTGFS_HPRT_PRTRES_M (USB_OTGFS_HPRT_PRTRES_V << USB_OTGFS_HPRT_PRTRES_S) +#define USB_OTGFS_HPRT_PRTRES_V 0x00000001U +#define USB_OTGFS_HPRT_PRTRES_S 6 +/** USB_OTGFS_HPRT_PRTSUSP : R/W; bitpos: [7]; default: 0; + * Port Suspend (PrtSusp) + * + * The application sets this bit to put this port in Suspend + * mode. The core only stops sending SOFs when this is Set. + * To stop the PHY clock, the application must Set the Port + * Clock Stop bit, which asserts the suspend input pin of the + * PHY. + * + * The read value of this bit reflects the current suspend status + * of the port. This bit is cleared by the core after a remote + * wakeup signal is detected or the application sets the Port + * Reset bit or Port Resume bit in this register or the + * Resume/Remote Wakeup Detected Interrupt bit or + * Disconnect Detected Interrupt bit in the Core Interrupt + * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, + * respectively).This bit is cleared by the core even if there is + * no device connected to the Host. + * - 1'b0: Port not in Suspend mode + * - 1'b1: Port in Suspend mode + */ +#define USB_OTGFS_HPRT_PRTSUSP (BIT(7)) +#define USB_OTGFS_HPRT_PRTSUSP_M (USB_OTGFS_HPRT_PRTSUSP_V << USB_OTGFS_HPRT_PRTSUSP_S) +#define USB_OTGFS_HPRT_PRTSUSP_V 0x00000001U +#define USB_OTGFS_HPRT_PRTSUSP_S 7 +/** USB_OTGFS_HPRT_PRTRST : R/W; bitpos: [8]; default: 0; + * Port Reset (PrtRst) + * + * When the application sets this bit, a reset sequence is + * started on this port. The application must time the reset + * period and clear this bit after the reset sequence is + * complete. + * - 1'b0: Port not in reset + * - 1'b1: Port in reset + * The application must leave this bit set for at least a + * minimum duration mentioned below to start a reset on the + * port. The application can leave it set for another 10 ms in + * addition to the required minimum duration, before clearing + * the bit, even though there is no maximum limit Set by the + * USB standard.This bit is cleared by the core even if there is + * no device connected to the Host. + * - High speed: 50 ms + * - Full speed/Low speed: 10 ms + */ +#define USB_OTGFS_HPRT_PRTRST (BIT(8)) +#define USB_OTGFS_HPRT_PRTRST_M (USB_OTGFS_HPRT_PRTRST_V << USB_OTGFS_HPRT_PRTRST_S) +#define USB_OTGFS_HPRT_PRTRST_V 0x00000001U +#define USB_OTGFS_HPRT_PRTRST_S 8 +/** USB_OTGFS_HPRT_PRTLNSTS : RO; bitpos: [11:10]; default: 0; + * Port Line Status (PrtLnSts) + * + * Indicates the current logic level USB data lines + * - Bit [10]: Logic level of D+ + * - Bit [11]: Logic level of D- + */ +#define USB_OTGFS_HPRT_PRTLNSTS 0x00000003U +#define USB_OTGFS_HPRT_PRTLNSTS_M (USB_OTGFS_HPRT_PRTLNSTS_V << USB_OTGFS_HPRT_PRTLNSTS_S) +#define USB_OTGFS_HPRT_PRTLNSTS_V 0x00000003U +#define USB_OTGFS_HPRT_PRTLNSTS_S 10 +/** USB_OTGFS_HPRT_PRTPWR : R/W; bitpos: [12]; default: 0; + * Port Power (PrtPwr) + * + * The application uses this field to control power to this port (write 1'b1 to set to + * 1'b1 + * and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current + * condition. + * - 1'b0: Power off + * - 1'b1: Power on + * + * Note: This bit is interface independent. The application needs to program this bit + * for all interfaces as described in the host programming flow in the Programming + * Guide. + */ +#define USB_OTGFS_HPRT_PRTPWR (BIT(12)) +#define USB_OTGFS_HPRT_PRTPWR_M (USB_OTGFS_HPRT_PRTPWR_V << USB_OTGFS_HPRT_PRTPWR_S) +#define USB_OTGFS_HPRT_PRTPWR_V 0x00000001U +#define USB_OTGFS_HPRT_PRTPWR_S 12 +/** USB_OTGFS_HPRT_PRTTSTCTL : R/W; bitpos: [16:13]; default: 0; + * Port Test Control (PrtTstCtl) + * + * The application writes a nonzero value to this field to put the port into a Test + * mode, and the corresponding pattern is signaled on the port. + * - 4'b0000: Test mode disabled + * - 4'b0001: Test_J mode + * - 4'b0010: Test_K mode + * - 4'b0011: Test_SE0_NAK mode + * - 4'b0100: Test_Packet mode + * - 4'b0101: Test_Force_Enable + * - Others: Reserved + * + * To move the DWC_otg controller to test mode, you must set this field. Complete the + * following steps to move the DWC_otg core to test mode: + * - 1. Power on the core. + * - 2. Load the DWC_otg driver. + * - 3. Connect an HS device and enumerate to HS mode. + * - 4. Access the HPRT register to send test packets. + * - 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core + * continues sending out test packets. + * - 6. Test the eye diagram. + */ +#define USB_OTGFS_HPRT_PRTTSTCTL 0x0000000FU +#define USB_OTGFS_HPRT_PRTTSTCTL_M (USB_OTGFS_HPRT_PRTTSTCTL_V << USB_OTGFS_HPRT_PRTTSTCTL_S) +#define USB_OTGFS_HPRT_PRTTSTCTL_V 0x0000000FU +#define USB_OTGFS_HPRT_PRTTSTCTL_S 13 +/** USB_OTGFS_HPRT_PRTSPD : RO; bitpos: [18:17]; default: 0; + * Port Speed (PrtSpd) + * + * Indicates the speed of the device attached to this port. + * - 2'b00: High speed + * - 2'b01: Full speed + * - 2'b10: Low speed + * - 2'b11: Reserved + */ +#define USB_OTGFS_HPRT_PRTSPD 0x00000003U +#define USB_OTGFS_HPRT_PRTSPD_M (USB_OTGFS_HPRT_PRTSPD_V << USB_OTGFS_HPRT_PRTSPD_S) +#define USB_OTGFS_HPRT_PRTSPD_V 0x00000003U +#define USB_OTGFS_HPRT_PRTSPD_S 17 + +/** USB_OTGFS_HCCHAR0_REG register + * Host Channel 0 Characteristics Register + */ +#define USB_OTGFS_HCCHAR0_REG(i) (DR_REG_USB_BASE(i) + 0x500) +/** USB_OTGFS_HCCHAR0_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR0_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR0_MPS_M (USB_OTGFS_HCCHAR0_MPS_V << USB_OTGFS_HCCHAR0_MPS_S) +#define USB_OTGFS_HCCHAR0_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR0_MPS_S 0 +/** USB_OTGFS_HCCHAR0_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR0_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR0_EPNUM_M (USB_OTGFS_HCCHAR0_EPNUM_V << USB_OTGFS_HCCHAR0_EPNUM_S) +#define USB_OTGFS_HCCHAR0_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR0_EPNUM_S 11 +/** USB_OTGFS_HCCHAR0_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR0_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR0_EPDIR_M (USB_OTGFS_HCCHAR0_EPDIR_V << USB_OTGFS_HCCHAR0_EPDIR_S) +#define USB_OTGFS_HCCHAR0_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR0_EPDIR_S 15 +/** USB_OTGFS_HCCHAR0_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR0_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR0_LSPDDEV_M (USB_OTGFS_HCCHAR0_LSPDDEV_V << USB_OTGFS_HCCHAR0_LSPDDEV_S) +#define USB_OTGFS_HCCHAR0_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR0_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR0_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR0_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR0_EPTYPE_M (USB_OTGFS_HCCHAR0_EPTYPE_V << USB_OTGFS_HCCHAR0_EPTYPE_S) +#define USB_OTGFS_HCCHAR0_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR0_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR0_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR0_EC 0x00000003U +#define USB_OTGFS_HCCHAR0_EC_M (USB_OTGFS_HCCHAR0_EC_V << USB_OTGFS_HCCHAR0_EC_S) +#define USB_OTGFS_HCCHAR0_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR0_EC_S 20 +/** USB_OTGFS_HCCHAR0_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR0_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR0_DEVADDR_M (USB_OTGFS_HCCHAR0_DEVADDR_V << USB_OTGFS_HCCHAR0_DEVADDR_S) +#define USB_OTGFS_HCCHAR0_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR0_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR0_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR0_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR0_ODDFRM_M (USB_OTGFS_HCCHAR0_ODDFRM_V << USB_OTGFS_HCCHAR0_ODDFRM_S) +#define USB_OTGFS_HCCHAR0_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR0_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR0_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR0_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR0_CHDIS_M (USB_OTGFS_HCCHAR0_CHDIS_V << USB_OTGFS_HCCHAR0_CHDIS_S) +#define USB_OTGFS_HCCHAR0_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR0_CHDIS_S 30 +/** USB_OTGFS_HCCHAR0_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR0_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR0_CHENA_M (USB_OTGFS_HCCHAR0_CHENA_V << USB_OTGFS_HCCHAR0_CHENA_S) +#define USB_OTGFS_HCCHAR0_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR0_CHENA_S 31 + +/** USB_OTGFS_HCINT0_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT0_REG(i) (DR_REG_USB_BASE(i) + 0x508) +/** USB_OTGFS_HCINT0_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT0_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT0_XFERCOMPL_M (USB_OTGFS_HCINT0_XFERCOMPL_V << USB_OTGFS_HCINT0_XFERCOMPL_S) +#define USB_OTGFS_HCINT0_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT0_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT0_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT0_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT0_CHHLTD_M (USB_OTGFS_HCINT0_CHHLTD_V << USB_OTGFS_HCINT0_CHHLTD_S) +#define USB_OTGFS_HCINT0_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT0_CHHLTD_S 1 +/** USB_OTGFS_HCINT0_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT0_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT0_AHBERR_M (USB_OTGFS_HCINT0_AHBERR_V << USB_OTGFS_HCINT0_AHBERR_S) +#define USB_OTGFS_HCINT0_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT0_AHBERR_S 2 +/** USB_OTGFS_HCINT0_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT0_STALL (BIT(3)) +#define USB_OTGFS_HCINT0_STALL_M (USB_OTGFS_HCINT0_STALL_V << USB_OTGFS_HCINT0_STALL_S) +#define USB_OTGFS_HCINT0_STALL_V 0x00000001U +#define USB_OTGFS_HCINT0_STALL_S 3 +/** USB_OTGFS_HCINT0_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT0_NAK (BIT(4)) +#define USB_OTGFS_HCINT0_NAK_M (USB_OTGFS_HCINT0_NAK_V << USB_OTGFS_HCINT0_NAK_S) +#define USB_OTGFS_HCINT0_NAK_V 0x00000001U +#define USB_OTGFS_HCINT0_NAK_S 4 +/** USB_OTGFS_HCINT0_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT0_ACK (BIT(5)) +#define USB_OTGFS_HCINT0_ACK_M (USB_OTGFS_HCINT0_ACK_V << USB_OTGFS_HCINT0_ACK_S) +#define USB_OTGFS_HCINT0_ACK_V 0x00000001U +#define USB_OTGFS_HCINT0_ACK_S 5 +/** USB_OTGFS_HCINT0_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT0_NYET (BIT(6)) +#define USB_OTGFS_HCINT0_NYET_M (USB_OTGFS_HCINT0_NYET_V << USB_OTGFS_HCINT0_NYET_S) +#define USB_OTGFS_HCINT0_NYET_V 0x00000001U +#define USB_OTGFS_HCINT0_NYET_S 6 +/** USB_OTGFS_HCINT0_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT0_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT0_XACTERR_M (USB_OTGFS_HCINT0_XACTERR_V << USB_OTGFS_HCINT0_XACTERR_S) +#define USB_OTGFS_HCINT0_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT0_XACTERR_S 7 +/** USB_OTGFS_HCINT0_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT0_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT0_BBLERR_M (USB_OTGFS_HCINT0_BBLERR_V << USB_OTGFS_HCINT0_BBLERR_S) +#define USB_OTGFS_HCINT0_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT0_BBLERR_S 8 +/** USB_OTGFS_HCINT0_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT0_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT0_FRMOVRUN_M (USB_OTGFS_HCINT0_FRMOVRUN_V << USB_OTGFS_HCINT0_FRMOVRUN_S) +#define USB_OTGFS_HCINT0_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT0_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT0_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT0_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT0_DATATGLERR_M (USB_OTGFS_HCINT0_DATATGLERR_V << USB_OTGFS_HCINT0_DATATGLERR_S) +#define USB_OTGFS_HCINT0_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT0_DATATGLERR_S 10 +/** USB_OTGFS_HCINT0_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT0_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT0_BNAINTR_M (USB_OTGFS_HCINT0_BNAINTR_V << USB_OTGFS_HCINT0_BNAINTR_S) +#define USB_OTGFS_HCINT0_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT0_BNAINTR_S 11 +/** USB_OTGFS_HCINT0_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT0_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT0_XCS_XACT_ERR_M (USB_OTGFS_HCINT0_XCS_XACT_ERR_V << USB_OTGFS_HCINT0_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT0_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT0_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT0_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT0_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT0_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT0_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT0_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT0_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT0_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK0_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK0_REG(i) (DR_REG_USB_BASE(i) + 0x50c) +/** USB_OTGFS_HCINTMSK0_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK0_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK0_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK0_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK0_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK0_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK0_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK0_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK0_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK0_CHHLTDMSK_M (USB_OTGFS_HCINTMSK0_CHHLTDMSK_V << USB_OTGFS_HCINTMSK0_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK0_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK0_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK0_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK0_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK0_AHBERRMSK_M (USB_OTGFS_HCINTMSK0_AHBERRMSK_V << USB_OTGFS_HCINTMSK0_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK0_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK0_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK0_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK0_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK0_BNAINTRMSK_M (USB_OTGFS_HCINTMSK0_BNAINTRMSK_V << USB_OTGFS_HCINTMSK0_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK0_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK0_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK0_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ0_REG register + * Host Channel 0 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ0_REG(i) (DR_REG_USB_BASE(i) + 0x510) +/** USB_OTGFS_HCTSIZ0_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ0_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ0_XFERSIZE_M (USB_OTGFS_HCTSIZ0_XFERSIZE_V << USB_OTGFS_HCTSIZ0_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ0_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ0_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ0_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ0_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ0_PKTCNT_M (USB_OTGFS_HCTSIZ0_PKTCNT_V << USB_OTGFS_HCTSIZ0_PKTCNT_S) +#define USB_OTGFS_HCTSIZ0_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ0_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ0_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ0_PID 0x00000003U +#define USB_OTGFS_HCTSIZ0_PID_M (USB_OTGFS_HCTSIZ0_PID_V << USB_OTGFS_HCTSIZ0_PID_S) +#define USB_OTGFS_HCTSIZ0_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ0_PID_S 29 +/** USB_OTGFS_HCTSIZ0_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ0_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ0_DOPNG_M (USB_OTGFS_HCTSIZ0_DOPNG_V << USB_OTGFS_HCTSIZ0_DOPNG_S) +#define USB_OTGFS_HCTSIZ0_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ0_DOPNG_S 31 + +/** USB_OTGFS_HCDMA0_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA0_REG(i) (DR_REG_USB_BASE(i) + 0x514) +/** USB_OTGFS_HCDMA0_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA0_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA0_DMAADDR_M (USB_OTGFS_HCDMA0_DMAADDR_V << USB_OTGFS_HCDMA0_DMAADDR_S) +#define USB_OTGFS_HCDMA0_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA0_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB0_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB0_REG(i) (DR_REG_USB_BASE(i) + 0x51c) +/** USB_OTGFS_HCDMAB0_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB0_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB0_HCDMAB_M (USB_OTGFS_HCDMAB0_HCDMAB_V << USB_OTGFS_HCDMAB0_HCDMAB_S) +#define USB_OTGFS_HCDMAB0_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB0_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR1_REG register + * Host Channel 1 Characteristics Register + */ +#define USB_OTGFS_HCCHAR1_REG(i) (DR_REG_USB_BASE(i) + 0x520) +/** USB_OTGFS_HCCHAR1_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR1_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR1_MPS_M (USB_OTGFS_HCCHAR1_MPS_V << USB_OTGFS_HCCHAR1_MPS_S) +#define USB_OTGFS_HCCHAR1_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR1_MPS_S 0 +/** USB_OTGFS_HCCHAR1_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR1_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR1_EPNUM_M (USB_OTGFS_HCCHAR1_EPNUM_V << USB_OTGFS_HCCHAR1_EPNUM_S) +#define USB_OTGFS_HCCHAR1_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR1_EPNUM_S 11 +/** USB_OTGFS_HCCHAR1_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR1_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR1_EPDIR_M (USB_OTGFS_HCCHAR1_EPDIR_V << USB_OTGFS_HCCHAR1_EPDIR_S) +#define USB_OTGFS_HCCHAR1_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR1_EPDIR_S 15 +/** USB_OTGFS_HCCHAR1_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR1_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR1_LSPDDEV_M (USB_OTGFS_HCCHAR1_LSPDDEV_V << USB_OTGFS_HCCHAR1_LSPDDEV_S) +#define USB_OTGFS_HCCHAR1_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR1_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR1_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR1_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR1_EPTYPE_M (USB_OTGFS_HCCHAR1_EPTYPE_V << USB_OTGFS_HCCHAR1_EPTYPE_S) +#define USB_OTGFS_HCCHAR1_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR1_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR1_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR1_EC 0x00000003U +#define USB_OTGFS_HCCHAR1_EC_M (USB_OTGFS_HCCHAR1_EC_V << USB_OTGFS_HCCHAR1_EC_S) +#define USB_OTGFS_HCCHAR1_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR1_EC_S 20 +/** USB_OTGFS_HCCHAR1_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR1_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR1_DEVADDR_M (USB_OTGFS_HCCHAR1_DEVADDR_V << USB_OTGFS_HCCHAR1_DEVADDR_S) +#define USB_OTGFS_HCCHAR1_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR1_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR1_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR1_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR1_ODDFRM_M (USB_OTGFS_HCCHAR1_ODDFRM_V << USB_OTGFS_HCCHAR1_ODDFRM_S) +#define USB_OTGFS_HCCHAR1_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR1_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR1_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR1_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR1_CHDIS_M (USB_OTGFS_HCCHAR1_CHDIS_V << USB_OTGFS_HCCHAR1_CHDIS_S) +#define USB_OTGFS_HCCHAR1_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR1_CHDIS_S 30 +/** USB_OTGFS_HCCHAR1_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR1_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR1_CHENA_M (USB_OTGFS_HCCHAR1_CHENA_V << USB_OTGFS_HCCHAR1_CHENA_S) +#define USB_OTGFS_HCCHAR1_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR1_CHENA_S 31 + +/** USB_OTGFS_HCINT1_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT1_REG(i) (DR_REG_USB_BASE(i) + 0x528) +/** USB_OTGFS_HCINT1_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT1_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT1_XFERCOMPL_M (USB_OTGFS_HCINT1_XFERCOMPL_V << USB_OTGFS_HCINT1_XFERCOMPL_S) +#define USB_OTGFS_HCINT1_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT1_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT1_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT1_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT1_CHHLTD_M (USB_OTGFS_HCINT1_CHHLTD_V << USB_OTGFS_HCINT1_CHHLTD_S) +#define USB_OTGFS_HCINT1_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT1_CHHLTD_S 1 +/** USB_OTGFS_HCINT1_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT1_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT1_AHBERR_M (USB_OTGFS_HCINT1_AHBERR_V << USB_OTGFS_HCINT1_AHBERR_S) +#define USB_OTGFS_HCINT1_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT1_AHBERR_S 2 +/** USB_OTGFS_HCINT1_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT1_STALL (BIT(3)) +#define USB_OTGFS_HCINT1_STALL_M (USB_OTGFS_HCINT1_STALL_V << USB_OTGFS_HCINT1_STALL_S) +#define USB_OTGFS_HCINT1_STALL_V 0x00000001U +#define USB_OTGFS_HCINT1_STALL_S 3 +/** USB_OTGFS_HCINT1_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT1_NAK (BIT(4)) +#define USB_OTGFS_HCINT1_NAK_M (USB_OTGFS_HCINT1_NAK_V << USB_OTGFS_HCINT1_NAK_S) +#define USB_OTGFS_HCINT1_NAK_V 0x00000001U +#define USB_OTGFS_HCINT1_NAK_S 4 +/** USB_OTGFS_HCINT1_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT1_ACK (BIT(5)) +#define USB_OTGFS_HCINT1_ACK_M (USB_OTGFS_HCINT1_ACK_V << USB_OTGFS_HCINT1_ACK_S) +#define USB_OTGFS_HCINT1_ACK_V 0x00000001U +#define USB_OTGFS_HCINT1_ACK_S 5 +/** USB_OTGFS_HCINT1_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT1_NYET (BIT(6)) +#define USB_OTGFS_HCINT1_NYET_M (USB_OTGFS_HCINT1_NYET_V << USB_OTGFS_HCINT1_NYET_S) +#define USB_OTGFS_HCINT1_NYET_V 0x00000001U +#define USB_OTGFS_HCINT1_NYET_S 6 +/** USB_OTGFS_HCINT1_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT1_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT1_XACTERR_M (USB_OTGFS_HCINT1_XACTERR_V << USB_OTGFS_HCINT1_XACTERR_S) +#define USB_OTGFS_HCINT1_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT1_XACTERR_S 7 +/** USB_OTGFS_HCINT1_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT1_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT1_BBLERR_M (USB_OTGFS_HCINT1_BBLERR_V << USB_OTGFS_HCINT1_BBLERR_S) +#define USB_OTGFS_HCINT1_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT1_BBLERR_S 8 +/** USB_OTGFS_HCINT1_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT1_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT1_FRMOVRUN_M (USB_OTGFS_HCINT1_FRMOVRUN_V << USB_OTGFS_HCINT1_FRMOVRUN_S) +#define USB_OTGFS_HCINT1_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT1_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT1_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT1_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT1_DATATGLERR_M (USB_OTGFS_HCINT1_DATATGLERR_V << USB_OTGFS_HCINT1_DATATGLERR_S) +#define USB_OTGFS_HCINT1_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT1_DATATGLERR_S 10 +/** USB_OTGFS_HCINT1_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT1_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT1_BNAINTR_M (USB_OTGFS_HCINT1_BNAINTR_V << USB_OTGFS_HCINT1_BNAINTR_S) +#define USB_OTGFS_HCINT1_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT1_BNAINTR_S 11 +/** USB_OTGFS_HCINT1_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT1_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT1_XCS_XACT_ERR_M (USB_OTGFS_HCINT1_XCS_XACT_ERR_V << USB_OTGFS_HCINT1_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT1_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT1_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT1_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT1_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT1_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT1_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT1_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT1_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT1_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK1_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK1_REG(i) (DR_REG_USB_BASE(i) + 0x52c) +/** USB_OTGFS_HCINTMSK1_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK1_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK1_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK1_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK1_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK1_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK1_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK1_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK1_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK1_CHHLTDMSK_M (USB_OTGFS_HCINTMSK1_CHHLTDMSK_V << USB_OTGFS_HCINTMSK1_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK1_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK1_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK1_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK1_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK1_AHBERRMSK_M (USB_OTGFS_HCINTMSK1_AHBERRMSK_V << USB_OTGFS_HCINTMSK1_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK1_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK1_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK1_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK1_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK1_BNAINTRMSK_M (USB_OTGFS_HCINTMSK1_BNAINTRMSK_V << USB_OTGFS_HCINTMSK1_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK1_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK1_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK1_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ1_REG register + * Host Channel 1 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ1_REG(i) (DR_REG_USB_BASE(i) + 0x530) +/** USB_OTGFS_HCTSIZ1_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ1_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ1_XFERSIZE_M (USB_OTGFS_HCTSIZ1_XFERSIZE_V << USB_OTGFS_HCTSIZ1_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ1_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ1_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ1_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ1_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ1_PKTCNT_M (USB_OTGFS_HCTSIZ1_PKTCNT_V << USB_OTGFS_HCTSIZ1_PKTCNT_S) +#define USB_OTGFS_HCTSIZ1_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ1_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ1_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ1_PID 0x00000003U +#define USB_OTGFS_HCTSIZ1_PID_M (USB_OTGFS_HCTSIZ1_PID_V << USB_OTGFS_HCTSIZ1_PID_S) +#define USB_OTGFS_HCTSIZ1_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ1_PID_S 29 +/** USB_OTGFS_HCTSIZ1_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ1_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ1_DOPNG_M (USB_OTGFS_HCTSIZ1_DOPNG_V << USB_OTGFS_HCTSIZ1_DOPNG_S) +#define USB_OTGFS_HCTSIZ1_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ1_DOPNG_S 31 + +/** USB_OTGFS_HCDMA1_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA1_REG(i) (DR_REG_USB_BASE(i) + 0x534) +/** USB_OTGFS_HCDMA1_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA1_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA1_DMAADDR_M (USB_OTGFS_HCDMA1_DMAADDR_V << USB_OTGFS_HCDMA1_DMAADDR_S) +#define USB_OTGFS_HCDMA1_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA1_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB1_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB1_REG(i) (DR_REG_USB_BASE(i) + 0x53c) +/** USB_OTGFS_HCDMAB1_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB1_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB1_HCDMAB_M (USB_OTGFS_HCDMAB1_HCDMAB_V << USB_OTGFS_HCDMAB1_HCDMAB_S) +#define USB_OTGFS_HCDMAB1_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB1_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR2_REG register + * Host Channel 2 Characteristics Register + */ +#define USB_OTGFS_HCCHAR2_REG(i) (DR_REG_USB_BASE(i) + 0x540) +/** USB_OTGFS_HCCHAR2_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR2_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR2_MPS_M (USB_OTGFS_HCCHAR2_MPS_V << USB_OTGFS_HCCHAR2_MPS_S) +#define USB_OTGFS_HCCHAR2_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR2_MPS_S 0 +/** USB_OTGFS_HCCHAR2_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR2_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR2_EPNUM_M (USB_OTGFS_HCCHAR2_EPNUM_V << USB_OTGFS_HCCHAR2_EPNUM_S) +#define USB_OTGFS_HCCHAR2_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR2_EPNUM_S 11 +/** USB_OTGFS_HCCHAR2_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR2_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR2_EPDIR_M (USB_OTGFS_HCCHAR2_EPDIR_V << USB_OTGFS_HCCHAR2_EPDIR_S) +#define USB_OTGFS_HCCHAR2_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR2_EPDIR_S 15 +/** USB_OTGFS_HCCHAR2_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR2_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR2_LSPDDEV_M (USB_OTGFS_HCCHAR2_LSPDDEV_V << USB_OTGFS_HCCHAR2_LSPDDEV_S) +#define USB_OTGFS_HCCHAR2_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR2_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR2_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR2_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR2_EPTYPE_M (USB_OTGFS_HCCHAR2_EPTYPE_V << USB_OTGFS_HCCHAR2_EPTYPE_S) +#define USB_OTGFS_HCCHAR2_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR2_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR2_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR2_EC 0x00000003U +#define USB_OTGFS_HCCHAR2_EC_M (USB_OTGFS_HCCHAR2_EC_V << USB_OTGFS_HCCHAR2_EC_S) +#define USB_OTGFS_HCCHAR2_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR2_EC_S 20 +/** USB_OTGFS_HCCHAR2_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR2_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR2_DEVADDR_M (USB_OTGFS_HCCHAR2_DEVADDR_V << USB_OTGFS_HCCHAR2_DEVADDR_S) +#define USB_OTGFS_HCCHAR2_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR2_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR2_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR2_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR2_ODDFRM_M (USB_OTGFS_HCCHAR2_ODDFRM_V << USB_OTGFS_HCCHAR2_ODDFRM_S) +#define USB_OTGFS_HCCHAR2_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR2_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR2_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR2_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR2_CHDIS_M (USB_OTGFS_HCCHAR2_CHDIS_V << USB_OTGFS_HCCHAR2_CHDIS_S) +#define USB_OTGFS_HCCHAR2_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR2_CHDIS_S 30 +/** USB_OTGFS_HCCHAR2_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR2_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR2_CHENA_M (USB_OTGFS_HCCHAR2_CHENA_V << USB_OTGFS_HCCHAR2_CHENA_S) +#define USB_OTGFS_HCCHAR2_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR2_CHENA_S 31 + +/** USB_OTGFS_HCINT2_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT2_REG(i) (DR_REG_USB_BASE(i) + 0x548) +/** USB_OTGFS_HCINT2_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT2_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT2_XFERCOMPL_M (USB_OTGFS_HCINT2_XFERCOMPL_V << USB_OTGFS_HCINT2_XFERCOMPL_S) +#define USB_OTGFS_HCINT2_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT2_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT2_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT2_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT2_CHHLTD_M (USB_OTGFS_HCINT2_CHHLTD_V << USB_OTGFS_HCINT2_CHHLTD_S) +#define USB_OTGFS_HCINT2_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT2_CHHLTD_S 1 +/** USB_OTGFS_HCINT2_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT2_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT2_AHBERR_M (USB_OTGFS_HCINT2_AHBERR_V << USB_OTGFS_HCINT2_AHBERR_S) +#define USB_OTGFS_HCINT2_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT2_AHBERR_S 2 +/** USB_OTGFS_HCINT2_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT2_STALL (BIT(3)) +#define USB_OTGFS_HCINT2_STALL_M (USB_OTGFS_HCINT2_STALL_V << USB_OTGFS_HCINT2_STALL_S) +#define USB_OTGFS_HCINT2_STALL_V 0x00000001U +#define USB_OTGFS_HCINT2_STALL_S 3 +/** USB_OTGFS_HCINT2_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT2_NAK (BIT(4)) +#define USB_OTGFS_HCINT2_NAK_M (USB_OTGFS_HCINT2_NAK_V << USB_OTGFS_HCINT2_NAK_S) +#define USB_OTGFS_HCINT2_NAK_V 0x00000001U +#define USB_OTGFS_HCINT2_NAK_S 4 +/** USB_OTGFS_HCINT2_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT2_ACK (BIT(5)) +#define USB_OTGFS_HCINT2_ACK_M (USB_OTGFS_HCINT2_ACK_V << USB_OTGFS_HCINT2_ACK_S) +#define USB_OTGFS_HCINT2_ACK_V 0x00000001U +#define USB_OTGFS_HCINT2_ACK_S 5 +/** USB_OTGFS_HCINT2_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT2_NYET (BIT(6)) +#define USB_OTGFS_HCINT2_NYET_M (USB_OTGFS_HCINT2_NYET_V << USB_OTGFS_HCINT2_NYET_S) +#define USB_OTGFS_HCINT2_NYET_V 0x00000001U +#define USB_OTGFS_HCINT2_NYET_S 6 +/** USB_OTGFS_HCINT2_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT2_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT2_XACTERR_M (USB_OTGFS_HCINT2_XACTERR_V << USB_OTGFS_HCINT2_XACTERR_S) +#define USB_OTGFS_HCINT2_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT2_XACTERR_S 7 +/** USB_OTGFS_HCINT2_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT2_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT2_BBLERR_M (USB_OTGFS_HCINT2_BBLERR_V << USB_OTGFS_HCINT2_BBLERR_S) +#define USB_OTGFS_HCINT2_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT2_BBLERR_S 8 +/** USB_OTGFS_HCINT2_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT2_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT2_FRMOVRUN_M (USB_OTGFS_HCINT2_FRMOVRUN_V << USB_OTGFS_HCINT2_FRMOVRUN_S) +#define USB_OTGFS_HCINT2_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT2_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT2_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT2_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT2_DATATGLERR_M (USB_OTGFS_HCINT2_DATATGLERR_V << USB_OTGFS_HCINT2_DATATGLERR_S) +#define USB_OTGFS_HCINT2_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT2_DATATGLERR_S 10 +/** USB_OTGFS_HCINT2_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT2_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT2_BNAINTR_M (USB_OTGFS_HCINT2_BNAINTR_V << USB_OTGFS_HCINT2_BNAINTR_S) +#define USB_OTGFS_HCINT2_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT2_BNAINTR_S 11 +/** USB_OTGFS_HCINT2_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT2_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT2_XCS_XACT_ERR_M (USB_OTGFS_HCINT2_XCS_XACT_ERR_V << USB_OTGFS_HCINT2_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT2_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT2_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT2_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT2_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT2_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT2_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT2_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT2_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT2_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK2_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK2_REG(i) (DR_REG_USB_BASE(i) + 0x54c) +/** USB_OTGFS_HCINTMSK2_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK2_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK2_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK2_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK2_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK2_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK2_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK2_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK2_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK2_CHHLTDMSK_M (USB_OTGFS_HCINTMSK2_CHHLTDMSK_V << USB_OTGFS_HCINTMSK2_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK2_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK2_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK2_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK2_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK2_AHBERRMSK_M (USB_OTGFS_HCINTMSK2_AHBERRMSK_V << USB_OTGFS_HCINTMSK2_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK2_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK2_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK2_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK2_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK2_BNAINTRMSK_M (USB_OTGFS_HCINTMSK2_BNAINTRMSK_V << USB_OTGFS_HCINTMSK2_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK2_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK2_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK2_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ2_REG register + * Host Channel 2 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ2_REG(i) (DR_REG_USB_BASE(i) + 0x550) +/** USB_OTGFS_HCTSIZ2_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ2_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ2_XFERSIZE_M (USB_OTGFS_HCTSIZ2_XFERSIZE_V << USB_OTGFS_HCTSIZ2_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ2_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ2_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ2_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ2_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ2_PKTCNT_M (USB_OTGFS_HCTSIZ2_PKTCNT_V << USB_OTGFS_HCTSIZ2_PKTCNT_S) +#define USB_OTGFS_HCTSIZ2_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ2_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ2_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ2_PID 0x00000003U +#define USB_OTGFS_HCTSIZ2_PID_M (USB_OTGFS_HCTSIZ2_PID_V << USB_OTGFS_HCTSIZ2_PID_S) +#define USB_OTGFS_HCTSIZ2_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ2_PID_S 29 +/** USB_OTGFS_HCTSIZ2_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ2_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ2_DOPNG_M (USB_OTGFS_HCTSIZ2_DOPNG_V << USB_OTGFS_HCTSIZ2_DOPNG_S) +#define USB_OTGFS_HCTSIZ2_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ2_DOPNG_S 31 + +/** USB_OTGFS_HCDMA2_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA2_REG(i) (DR_REG_USB_BASE(i) + 0x554) +/** USB_OTGFS_HCDMA2_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA2_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA2_DMAADDR_M (USB_OTGFS_HCDMA2_DMAADDR_V << USB_OTGFS_HCDMA2_DMAADDR_S) +#define USB_OTGFS_HCDMA2_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA2_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB2_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB2_REG(i) (DR_REG_USB_BASE(i) + 0x55c) +/** USB_OTGFS_HCDMAB2_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB2_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB2_HCDMAB_M (USB_OTGFS_HCDMAB2_HCDMAB_V << USB_OTGFS_HCDMAB2_HCDMAB_S) +#define USB_OTGFS_HCDMAB2_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB2_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR3_REG register + * Host Channel 3 Characteristics Register + */ +#define USB_OTGFS_HCCHAR3_REG(i) (DR_REG_USB_BASE(i) + 0x560) +/** USB_OTGFS_HCCHAR3_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR3_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR3_MPS_M (USB_OTGFS_HCCHAR3_MPS_V << USB_OTGFS_HCCHAR3_MPS_S) +#define USB_OTGFS_HCCHAR3_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR3_MPS_S 0 +/** USB_OTGFS_HCCHAR3_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR3_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR3_EPNUM_M (USB_OTGFS_HCCHAR3_EPNUM_V << USB_OTGFS_HCCHAR3_EPNUM_S) +#define USB_OTGFS_HCCHAR3_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR3_EPNUM_S 11 +/** USB_OTGFS_HCCHAR3_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR3_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR3_EPDIR_M (USB_OTGFS_HCCHAR3_EPDIR_V << USB_OTGFS_HCCHAR3_EPDIR_S) +#define USB_OTGFS_HCCHAR3_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR3_EPDIR_S 15 +/** USB_OTGFS_HCCHAR3_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR3_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR3_LSPDDEV_M (USB_OTGFS_HCCHAR3_LSPDDEV_V << USB_OTGFS_HCCHAR3_LSPDDEV_S) +#define USB_OTGFS_HCCHAR3_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR3_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR3_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR3_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR3_EPTYPE_M (USB_OTGFS_HCCHAR3_EPTYPE_V << USB_OTGFS_HCCHAR3_EPTYPE_S) +#define USB_OTGFS_HCCHAR3_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR3_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR3_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR3_EC 0x00000003U +#define USB_OTGFS_HCCHAR3_EC_M (USB_OTGFS_HCCHAR3_EC_V << USB_OTGFS_HCCHAR3_EC_S) +#define USB_OTGFS_HCCHAR3_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR3_EC_S 20 +/** USB_OTGFS_HCCHAR3_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR3_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR3_DEVADDR_M (USB_OTGFS_HCCHAR3_DEVADDR_V << USB_OTGFS_HCCHAR3_DEVADDR_S) +#define USB_OTGFS_HCCHAR3_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR3_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR3_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR3_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR3_ODDFRM_M (USB_OTGFS_HCCHAR3_ODDFRM_V << USB_OTGFS_HCCHAR3_ODDFRM_S) +#define USB_OTGFS_HCCHAR3_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR3_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR3_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR3_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR3_CHDIS_M (USB_OTGFS_HCCHAR3_CHDIS_V << USB_OTGFS_HCCHAR3_CHDIS_S) +#define USB_OTGFS_HCCHAR3_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR3_CHDIS_S 30 +/** USB_OTGFS_HCCHAR3_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR3_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR3_CHENA_M (USB_OTGFS_HCCHAR3_CHENA_V << USB_OTGFS_HCCHAR3_CHENA_S) +#define USB_OTGFS_HCCHAR3_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR3_CHENA_S 31 + +/** USB_OTGFS_HCINT3_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT3_REG(i) (DR_REG_USB_BASE(i) + 0x568) +/** USB_OTGFS_HCINT3_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT3_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT3_XFERCOMPL_M (USB_OTGFS_HCINT3_XFERCOMPL_V << USB_OTGFS_HCINT3_XFERCOMPL_S) +#define USB_OTGFS_HCINT3_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT3_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT3_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT3_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT3_CHHLTD_M (USB_OTGFS_HCINT3_CHHLTD_V << USB_OTGFS_HCINT3_CHHLTD_S) +#define USB_OTGFS_HCINT3_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT3_CHHLTD_S 1 +/** USB_OTGFS_HCINT3_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT3_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT3_AHBERR_M (USB_OTGFS_HCINT3_AHBERR_V << USB_OTGFS_HCINT3_AHBERR_S) +#define USB_OTGFS_HCINT3_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT3_AHBERR_S 2 +/** USB_OTGFS_HCINT3_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT3_STALL (BIT(3)) +#define USB_OTGFS_HCINT3_STALL_M (USB_OTGFS_HCINT3_STALL_V << USB_OTGFS_HCINT3_STALL_S) +#define USB_OTGFS_HCINT3_STALL_V 0x00000001U +#define USB_OTGFS_HCINT3_STALL_S 3 +/** USB_OTGFS_HCINT3_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT3_NAK (BIT(4)) +#define USB_OTGFS_HCINT3_NAK_M (USB_OTGFS_HCINT3_NAK_V << USB_OTGFS_HCINT3_NAK_S) +#define USB_OTGFS_HCINT3_NAK_V 0x00000001U +#define USB_OTGFS_HCINT3_NAK_S 4 +/** USB_OTGFS_HCINT3_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT3_ACK (BIT(5)) +#define USB_OTGFS_HCINT3_ACK_M (USB_OTGFS_HCINT3_ACK_V << USB_OTGFS_HCINT3_ACK_S) +#define USB_OTGFS_HCINT3_ACK_V 0x00000001U +#define USB_OTGFS_HCINT3_ACK_S 5 +/** USB_OTGFS_HCINT3_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT3_NYET (BIT(6)) +#define USB_OTGFS_HCINT3_NYET_M (USB_OTGFS_HCINT3_NYET_V << USB_OTGFS_HCINT3_NYET_S) +#define USB_OTGFS_HCINT3_NYET_V 0x00000001U +#define USB_OTGFS_HCINT3_NYET_S 6 +/** USB_OTGFS_HCINT3_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT3_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT3_XACTERR_M (USB_OTGFS_HCINT3_XACTERR_V << USB_OTGFS_HCINT3_XACTERR_S) +#define USB_OTGFS_HCINT3_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT3_XACTERR_S 7 +/** USB_OTGFS_HCINT3_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT3_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT3_BBLERR_M (USB_OTGFS_HCINT3_BBLERR_V << USB_OTGFS_HCINT3_BBLERR_S) +#define USB_OTGFS_HCINT3_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT3_BBLERR_S 8 +/** USB_OTGFS_HCINT3_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT3_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT3_FRMOVRUN_M (USB_OTGFS_HCINT3_FRMOVRUN_V << USB_OTGFS_HCINT3_FRMOVRUN_S) +#define USB_OTGFS_HCINT3_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT3_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT3_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT3_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT3_DATATGLERR_M (USB_OTGFS_HCINT3_DATATGLERR_V << USB_OTGFS_HCINT3_DATATGLERR_S) +#define USB_OTGFS_HCINT3_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT3_DATATGLERR_S 10 +/** USB_OTGFS_HCINT3_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT3_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT3_BNAINTR_M (USB_OTGFS_HCINT3_BNAINTR_V << USB_OTGFS_HCINT3_BNAINTR_S) +#define USB_OTGFS_HCINT3_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT3_BNAINTR_S 11 +/** USB_OTGFS_HCINT3_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT3_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT3_XCS_XACT_ERR_M (USB_OTGFS_HCINT3_XCS_XACT_ERR_V << USB_OTGFS_HCINT3_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT3_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT3_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT3_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT3_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT3_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT3_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT3_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT3_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT3_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK3_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK3_REG(i) (DR_REG_USB_BASE(i) + 0x56c) +/** USB_OTGFS_HCINTMSK3_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK3_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK3_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK3_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK3_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK3_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK3_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK3_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK3_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK3_CHHLTDMSK_M (USB_OTGFS_HCINTMSK3_CHHLTDMSK_V << USB_OTGFS_HCINTMSK3_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK3_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK3_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK3_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK3_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK3_AHBERRMSK_M (USB_OTGFS_HCINTMSK3_AHBERRMSK_V << USB_OTGFS_HCINTMSK3_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK3_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK3_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK3_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK3_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK3_BNAINTRMSK_M (USB_OTGFS_HCINTMSK3_BNAINTRMSK_V << USB_OTGFS_HCINTMSK3_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK3_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK3_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK3_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ3_REG register + * Host Channel 3 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ3_REG(i) (DR_REG_USB_BASE(i) + 0x570) +/** USB_OTGFS_HCTSIZ3_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ3_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ3_XFERSIZE_M (USB_OTGFS_HCTSIZ3_XFERSIZE_V << USB_OTGFS_HCTSIZ3_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ3_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ3_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ3_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ3_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ3_PKTCNT_M (USB_OTGFS_HCTSIZ3_PKTCNT_V << USB_OTGFS_HCTSIZ3_PKTCNT_S) +#define USB_OTGFS_HCTSIZ3_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ3_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ3_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ3_PID 0x00000003U +#define USB_OTGFS_HCTSIZ3_PID_M (USB_OTGFS_HCTSIZ3_PID_V << USB_OTGFS_HCTSIZ3_PID_S) +#define USB_OTGFS_HCTSIZ3_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ3_PID_S 29 +/** USB_OTGFS_HCTSIZ3_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ3_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ3_DOPNG_M (USB_OTGFS_HCTSIZ3_DOPNG_V << USB_OTGFS_HCTSIZ3_DOPNG_S) +#define USB_OTGFS_HCTSIZ3_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ3_DOPNG_S 31 + +/** USB_OTGFS_HCDMA3_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA3_REG(i) (DR_REG_USB_BASE(i) + 0x574) +/** USB_OTGFS_HCDMA3_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA3_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA3_DMAADDR_M (USB_OTGFS_HCDMA3_DMAADDR_V << USB_OTGFS_HCDMA3_DMAADDR_S) +#define USB_OTGFS_HCDMA3_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA3_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB3_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB3_REG(i) (DR_REG_USB_BASE(i) + 0x57c) +/** USB_OTGFS_HCDMAB3_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB3_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB3_HCDMAB_M (USB_OTGFS_HCDMAB3_HCDMAB_V << USB_OTGFS_HCDMAB3_HCDMAB_S) +#define USB_OTGFS_HCDMAB3_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB3_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR4_REG register + * Host Channel 4 Characteristics Register + */ +#define USB_OTGFS_HCCHAR4_REG(i) (DR_REG_USB_BASE(i) + 0x580) +/** USB_OTGFS_HCCHAR4_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR4_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR4_MPS_M (USB_OTGFS_HCCHAR4_MPS_V << USB_OTGFS_HCCHAR4_MPS_S) +#define USB_OTGFS_HCCHAR4_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR4_MPS_S 0 +/** USB_OTGFS_HCCHAR4_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR4_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR4_EPNUM_M (USB_OTGFS_HCCHAR4_EPNUM_V << USB_OTGFS_HCCHAR4_EPNUM_S) +#define USB_OTGFS_HCCHAR4_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR4_EPNUM_S 11 +/** USB_OTGFS_HCCHAR4_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR4_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR4_EPDIR_M (USB_OTGFS_HCCHAR4_EPDIR_V << USB_OTGFS_HCCHAR4_EPDIR_S) +#define USB_OTGFS_HCCHAR4_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR4_EPDIR_S 15 +/** USB_OTGFS_HCCHAR4_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR4_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR4_LSPDDEV_M (USB_OTGFS_HCCHAR4_LSPDDEV_V << USB_OTGFS_HCCHAR4_LSPDDEV_S) +#define USB_OTGFS_HCCHAR4_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR4_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR4_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR4_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR4_EPTYPE_M (USB_OTGFS_HCCHAR4_EPTYPE_V << USB_OTGFS_HCCHAR4_EPTYPE_S) +#define USB_OTGFS_HCCHAR4_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR4_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR4_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR4_EC 0x00000003U +#define USB_OTGFS_HCCHAR4_EC_M (USB_OTGFS_HCCHAR4_EC_V << USB_OTGFS_HCCHAR4_EC_S) +#define USB_OTGFS_HCCHAR4_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR4_EC_S 20 +/** USB_OTGFS_HCCHAR4_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR4_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR4_DEVADDR_M (USB_OTGFS_HCCHAR4_DEVADDR_V << USB_OTGFS_HCCHAR4_DEVADDR_S) +#define USB_OTGFS_HCCHAR4_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR4_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR4_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR4_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR4_ODDFRM_M (USB_OTGFS_HCCHAR4_ODDFRM_V << USB_OTGFS_HCCHAR4_ODDFRM_S) +#define USB_OTGFS_HCCHAR4_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR4_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR4_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR4_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR4_CHDIS_M (USB_OTGFS_HCCHAR4_CHDIS_V << USB_OTGFS_HCCHAR4_CHDIS_S) +#define USB_OTGFS_HCCHAR4_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR4_CHDIS_S 30 +/** USB_OTGFS_HCCHAR4_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR4_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR4_CHENA_M (USB_OTGFS_HCCHAR4_CHENA_V << USB_OTGFS_HCCHAR4_CHENA_S) +#define USB_OTGFS_HCCHAR4_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR4_CHENA_S 31 + +/** USB_OTGFS_HCINT4_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT4_REG(i) (DR_REG_USB_BASE(i) + 0x588) +/** USB_OTGFS_HCINT4_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT4_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT4_XFERCOMPL_M (USB_OTGFS_HCINT4_XFERCOMPL_V << USB_OTGFS_HCINT4_XFERCOMPL_S) +#define USB_OTGFS_HCINT4_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT4_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT4_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT4_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT4_CHHLTD_M (USB_OTGFS_HCINT4_CHHLTD_V << USB_OTGFS_HCINT4_CHHLTD_S) +#define USB_OTGFS_HCINT4_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT4_CHHLTD_S 1 +/** USB_OTGFS_HCINT4_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT4_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT4_AHBERR_M (USB_OTGFS_HCINT4_AHBERR_V << USB_OTGFS_HCINT4_AHBERR_S) +#define USB_OTGFS_HCINT4_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT4_AHBERR_S 2 +/** USB_OTGFS_HCINT4_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT4_STALL (BIT(3)) +#define USB_OTGFS_HCINT4_STALL_M (USB_OTGFS_HCINT4_STALL_V << USB_OTGFS_HCINT4_STALL_S) +#define USB_OTGFS_HCINT4_STALL_V 0x00000001U +#define USB_OTGFS_HCINT4_STALL_S 3 +/** USB_OTGFS_HCINT4_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT4_NAK (BIT(4)) +#define USB_OTGFS_HCINT4_NAK_M (USB_OTGFS_HCINT4_NAK_V << USB_OTGFS_HCINT4_NAK_S) +#define USB_OTGFS_HCINT4_NAK_V 0x00000001U +#define USB_OTGFS_HCINT4_NAK_S 4 +/** USB_OTGFS_HCINT4_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT4_ACK (BIT(5)) +#define USB_OTGFS_HCINT4_ACK_M (USB_OTGFS_HCINT4_ACK_V << USB_OTGFS_HCINT4_ACK_S) +#define USB_OTGFS_HCINT4_ACK_V 0x00000001U +#define USB_OTGFS_HCINT4_ACK_S 5 +/** USB_OTGFS_HCINT4_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT4_NYET (BIT(6)) +#define USB_OTGFS_HCINT4_NYET_M (USB_OTGFS_HCINT4_NYET_V << USB_OTGFS_HCINT4_NYET_S) +#define USB_OTGFS_HCINT4_NYET_V 0x00000001U +#define USB_OTGFS_HCINT4_NYET_S 6 +/** USB_OTGFS_HCINT4_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT4_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT4_XACTERR_M (USB_OTGFS_HCINT4_XACTERR_V << USB_OTGFS_HCINT4_XACTERR_S) +#define USB_OTGFS_HCINT4_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT4_XACTERR_S 7 +/** USB_OTGFS_HCINT4_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT4_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT4_BBLERR_M (USB_OTGFS_HCINT4_BBLERR_V << USB_OTGFS_HCINT4_BBLERR_S) +#define USB_OTGFS_HCINT4_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT4_BBLERR_S 8 +/** USB_OTGFS_HCINT4_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT4_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT4_FRMOVRUN_M (USB_OTGFS_HCINT4_FRMOVRUN_V << USB_OTGFS_HCINT4_FRMOVRUN_S) +#define USB_OTGFS_HCINT4_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT4_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT4_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT4_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT4_DATATGLERR_M (USB_OTGFS_HCINT4_DATATGLERR_V << USB_OTGFS_HCINT4_DATATGLERR_S) +#define USB_OTGFS_HCINT4_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT4_DATATGLERR_S 10 +/** USB_OTGFS_HCINT4_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT4_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT4_BNAINTR_M (USB_OTGFS_HCINT4_BNAINTR_V << USB_OTGFS_HCINT4_BNAINTR_S) +#define USB_OTGFS_HCINT4_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT4_BNAINTR_S 11 +/** USB_OTGFS_HCINT4_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT4_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT4_XCS_XACT_ERR_M (USB_OTGFS_HCINT4_XCS_XACT_ERR_V << USB_OTGFS_HCINT4_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT4_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT4_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT4_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT4_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT4_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT4_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT4_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT4_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT4_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK4_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK4_REG(i) (DR_REG_USB_BASE(i) + 0x58c) +/** USB_OTGFS_HCINTMSK4_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK4_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK4_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK4_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK4_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK4_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK4_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK4_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK4_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK4_CHHLTDMSK_M (USB_OTGFS_HCINTMSK4_CHHLTDMSK_V << USB_OTGFS_HCINTMSK4_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK4_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK4_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK4_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK4_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK4_AHBERRMSK_M (USB_OTGFS_HCINTMSK4_AHBERRMSK_V << USB_OTGFS_HCINTMSK4_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK4_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK4_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK4_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK4_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK4_BNAINTRMSK_M (USB_OTGFS_HCINTMSK4_BNAINTRMSK_V << USB_OTGFS_HCINTMSK4_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK4_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK4_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK4_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ4_REG register + * Host Channel 4 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ4_REG(i) (DR_REG_USB_BASE(i) + 0x590) +/** USB_OTGFS_HCTSIZ4_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ4_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ4_XFERSIZE_M (USB_OTGFS_HCTSIZ4_XFERSIZE_V << USB_OTGFS_HCTSIZ4_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ4_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ4_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ4_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ4_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ4_PKTCNT_M (USB_OTGFS_HCTSIZ4_PKTCNT_V << USB_OTGFS_HCTSIZ4_PKTCNT_S) +#define USB_OTGFS_HCTSIZ4_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ4_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ4_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ4_PID 0x00000003U +#define USB_OTGFS_HCTSIZ4_PID_M (USB_OTGFS_HCTSIZ4_PID_V << USB_OTGFS_HCTSIZ4_PID_S) +#define USB_OTGFS_HCTSIZ4_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ4_PID_S 29 +/** USB_OTGFS_HCTSIZ4_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ4_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ4_DOPNG_M (USB_OTGFS_HCTSIZ4_DOPNG_V << USB_OTGFS_HCTSIZ4_DOPNG_S) +#define USB_OTGFS_HCTSIZ4_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ4_DOPNG_S 31 + +/** USB_OTGFS_HCDMA4_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA4_REG(i) (DR_REG_USB_BASE(i) + 0x594) +/** USB_OTGFS_HCDMA4_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA4_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA4_DMAADDR_M (USB_OTGFS_HCDMA4_DMAADDR_V << USB_OTGFS_HCDMA4_DMAADDR_S) +#define USB_OTGFS_HCDMA4_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA4_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB4_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB4_REG(i) (DR_REG_USB_BASE(i) + 0x59c) +/** USB_OTGFS_HCDMAB4_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB4_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB4_HCDMAB_M (USB_OTGFS_HCDMAB4_HCDMAB_V << USB_OTGFS_HCDMAB4_HCDMAB_S) +#define USB_OTGFS_HCDMAB4_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB4_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR5_REG register + * Host Channel 5 Characteristics Register + */ +#define USB_OTGFS_HCCHAR5_REG(i) (DR_REG_USB_BASE(i) + 0x5a0) +/** USB_OTGFS_HCCHAR5_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR5_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR5_MPS_M (USB_OTGFS_HCCHAR5_MPS_V << USB_OTGFS_HCCHAR5_MPS_S) +#define USB_OTGFS_HCCHAR5_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR5_MPS_S 0 +/** USB_OTGFS_HCCHAR5_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR5_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR5_EPNUM_M (USB_OTGFS_HCCHAR5_EPNUM_V << USB_OTGFS_HCCHAR5_EPNUM_S) +#define USB_OTGFS_HCCHAR5_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR5_EPNUM_S 11 +/** USB_OTGFS_HCCHAR5_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR5_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR5_EPDIR_M (USB_OTGFS_HCCHAR5_EPDIR_V << USB_OTGFS_HCCHAR5_EPDIR_S) +#define USB_OTGFS_HCCHAR5_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR5_EPDIR_S 15 +/** USB_OTGFS_HCCHAR5_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR5_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR5_LSPDDEV_M (USB_OTGFS_HCCHAR5_LSPDDEV_V << USB_OTGFS_HCCHAR5_LSPDDEV_S) +#define USB_OTGFS_HCCHAR5_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR5_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR5_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR5_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR5_EPTYPE_M (USB_OTGFS_HCCHAR5_EPTYPE_V << USB_OTGFS_HCCHAR5_EPTYPE_S) +#define USB_OTGFS_HCCHAR5_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR5_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR5_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR5_EC 0x00000003U +#define USB_OTGFS_HCCHAR5_EC_M (USB_OTGFS_HCCHAR5_EC_V << USB_OTGFS_HCCHAR5_EC_S) +#define USB_OTGFS_HCCHAR5_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR5_EC_S 20 +/** USB_OTGFS_HCCHAR5_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR5_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR5_DEVADDR_M (USB_OTGFS_HCCHAR5_DEVADDR_V << USB_OTGFS_HCCHAR5_DEVADDR_S) +#define USB_OTGFS_HCCHAR5_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR5_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR5_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR5_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR5_ODDFRM_M (USB_OTGFS_HCCHAR5_ODDFRM_V << USB_OTGFS_HCCHAR5_ODDFRM_S) +#define USB_OTGFS_HCCHAR5_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR5_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR5_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR5_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR5_CHDIS_M (USB_OTGFS_HCCHAR5_CHDIS_V << USB_OTGFS_HCCHAR5_CHDIS_S) +#define USB_OTGFS_HCCHAR5_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR5_CHDIS_S 30 +/** USB_OTGFS_HCCHAR5_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR5_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR5_CHENA_M (USB_OTGFS_HCCHAR5_CHENA_V << USB_OTGFS_HCCHAR5_CHENA_S) +#define USB_OTGFS_HCCHAR5_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR5_CHENA_S 31 + +/** USB_OTGFS_HCINT5_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT5_REG(i) (DR_REG_USB_BASE(i) + 0x5a8) +/** USB_OTGFS_HCINT5_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT5_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT5_XFERCOMPL_M (USB_OTGFS_HCINT5_XFERCOMPL_V << USB_OTGFS_HCINT5_XFERCOMPL_S) +#define USB_OTGFS_HCINT5_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT5_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT5_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT5_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT5_CHHLTD_M (USB_OTGFS_HCINT5_CHHLTD_V << USB_OTGFS_HCINT5_CHHLTD_S) +#define USB_OTGFS_HCINT5_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT5_CHHLTD_S 1 +/** USB_OTGFS_HCINT5_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT5_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT5_AHBERR_M (USB_OTGFS_HCINT5_AHBERR_V << USB_OTGFS_HCINT5_AHBERR_S) +#define USB_OTGFS_HCINT5_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT5_AHBERR_S 2 +/** USB_OTGFS_HCINT5_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT5_STALL (BIT(3)) +#define USB_OTGFS_HCINT5_STALL_M (USB_OTGFS_HCINT5_STALL_V << USB_OTGFS_HCINT5_STALL_S) +#define USB_OTGFS_HCINT5_STALL_V 0x00000001U +#define USB_OTGFS_HCINT5_STALL_S 3 +/** USB_OTGFS_HCINT5_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT5_NAK (BIT(4)) +#define USB_OTGFS_HCINT5_NAK_M (USB_OTGFS_HCINT5_NAK_V << USB_OTGFS_HCINT5_NAK_S) +#define USB_OTGFS_HCINT5_NAK_V 0x00000001U +#define USB_OTGFS_HCINT5_NAK_S 4 +/** USB_OTGFS_HCINT5_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT5_ACK (BIT(5)) +#define USB_OTGFS_HCINT5_ACK_M (USB_OTGFS_HCINT5_ACK_V << USB_OTGFS_HCINT5_ACK_S) +#define USB_OTGFS_HCINT5_ACK_V 0x00000001U +#define USB_OTGFS_HCINT5_ACK_S 5 +/** USB_OTGFS_HCINT5_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT5_NYET (BIT(6)) +#define USB_OTGFS_HCINT5_NYET_M (USB_OTGFS_HCINT5_NYET_V << USB_OTGFS_HCINT5_NYET_S) +#define USB_OTGFS_HCINT5_NYET_V 0x00000001U +#define USB_OTGFS_HCINT5_NYET_S 6 +/** USB_OTGFS_HCINT5_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT5_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT5_XACTERR_M (USB_OTGFS_HCINT5_XACTERR_V << USB_OTGFS_HCINT5_XACTERR_S) +#define USB_OTGFS_HCINT5_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT5_XACTERR_S 7 +/** USB_OTGFS_HCINT5_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT5_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT5_BBLERR_M (USB_OTGFS_HCINT5_BBLERR_V << USB_OTGFS_HCINT5_BBLERR_S) +#define USB_OTGFS_HCINT5_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT5_BBLERR_S 8 +/** USB_OTGFS_HCINT5_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT5_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT5_FRMOVRUN_M (USB_OTGFS_HCINT5_FRMOVRUN_V << USB_OTGFS_HCINT5_FRMOVRUN_S) +#define USB_OTGFS_HCINT5_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT5_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT5_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT5_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT5_DATATGLERR_M (USB_OTGFS_HCINT5_DATATGLERR_V << USB_OTGFS_HCINT5_DATATGLERR_S) +#define USB_OTGFS_HCINT5_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT5_DATATGLERR_S 10 +/** USB_OTGFS_HCINT5_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT5_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT5_BNAINTR_M (USB_OTGFS_HCINT5_BNAINTR_V << USB_OTGFS_HCINT5_BNAINTR_S) +#define USB_OTGFS_HCINT5_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT5_BNAINTR_S 11 +/** USB_OTGFS_HCINT5_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT5_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT5_XCS_XACT_ERR_M (USB_OTGFS_HCINT5_XCS_XACT_ERR_V << USB_OTGFS_HCINT5_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT5_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT5_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT5_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT5_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT5_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT5_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT5_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT5_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT5_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK5_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK5_REG(i) (DR_REG_USB_BASE(i) + 0x5ac) +/** USB_OTGFS_HCINTMSK5_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK5_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK5_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK5_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK5_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK5_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK5_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK5_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK5_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK5_CHHLTDMSK_M (USB_OTGFS_HCINTMSK5_CHHLTDMSK_V << USB_OTGFS_HCINTMSK5_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK5_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK5_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK5_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK5_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK5_AHBERRMSK_M (USB_OTGFS_HCINTMSK5_AHBERRMSK_V << USB_OTGFS_HCINTMSK5_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK5_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK5_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK5_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK5_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK5_BNAINTRMSK_M (USB_OTGFS_HCINTMSK5_BNAINTRMSK_V << USB_OTGFS_HCINTMSK5_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK5_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK5_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK5_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ5_REG register + * Host Channel 5 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ5_REG(i) (DR_REG_USB_BASE(i) + 0x5b0) +/** USB_OTGFS_HCTSIZ5_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ5_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ5_XFERSIZE_M (USB_OTGFS_HCTSIZ5_XFERSIZE_V << USB_OTGFS_HCTSIZ5_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ5_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ5_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ5_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ5_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ5_PKTCNT_M (USB_OTGFS_HCTSIZ5_PKTCNT_V << USB_OTGFS_HCTSIZ5_PKTCNT_S) +#define USB_OTGFS_HCTSIZ5_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ5_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ5_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ5_PID 0x00000003U +#define USB_OTGFS_HCTSIZ5_PID_M (USB_OTGFS_HCTSIZ5_PID_V << USB_OTGFS_HCTSIZ5_PID_S) +#define USB_OTGFS_HCTSIZ5_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ5_PID_S 29 +/** USB_OTGFS_HCTSIZ5_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ5_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ5_DOPNG_M (USB_OTGFS_HCTSIZ5_DOPNG_V << USB_OTGFS_HCTSIZ5_DOPNG_S) +#define USB_OTGFS_HCTSIZ5_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ5_DOPNG_S 31 + +/** USB_OTGFS_HCDMA5_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA5_REG(i) (DR_REG_USB_BASE(i) + 0x5b4) +/** USB_OTGFS_HCDMA5_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA5_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA5_DMAADDR_M (USB_OTGFS_HCDMA5_DMAADDR_V << USB_OTGFS_HCDMA5_DMAADDR_S) +#define USB_OTGFS_HCDMA5_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA5_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB5_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB5_REG(i) (DR_REG_USB_BASE(i) + 0x5bc) +/** USB_OTGFS_HCDMAB5_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB5_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB5_HCDMAB_M (USB_OTGFS_HCDMAB5_HCDMAB_V << USB_OTGFS_HCDMAB5_HCDMAB_S) +#define USB_OTGFS_HCDMAB5_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB5_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR6_REG register + * Host Channel 6 Characteristics Register + */ +#define USB_OTGFS_HCCHAR6_REG(i) (DR_REG_USB_BASE(i) + 0x5c0) +/** USB_OTGFS_HCCHAR6_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR6_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR6_MPS_M (USB_OTGFS_HCCHAR6_MPS_V << USB_OTGFS_HCCHAR6_MPS_S) +#define USB_OTGFS_HCCHAR6_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR6_MPS_S 0 +/** USB_OTGFS_HCCHAR6_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR6_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR6_EPNUM_M (USB_OTGFS_HCCHAR6_EPNUM_V << USB_OTGFS_HCCHAR6_EPNUM_S) +#define USB_OTGFS_HCCHAR6_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR6_EPNUM_S 11 +/** USB_OTGFS_HCCHAR6_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR6_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR6_EPDIR_M (USB_OTGFS_HCCHAR6_EPDIR_V << USB_OTGFS_HCCHAR6_EPDIR_S) +#define USB_OTGFS_HCCHAR6_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR6_EPDIR_S 15 +/** USB_OTGFS_HCCHAR6_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR6_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR6_LSPDDEV_M (USB_OTGFS_HCCHAR6_LSPDDEV_V << USB_OTGFS_HCCHAR6_LSPDDEV_S) +#define USB_OTGFS_HCCHAR6_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR6_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR6_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR6_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR6_EPTYPE_M (USB_OTGFS_HCCHAR6_EPTYPE_V << USB_OTGFS_HCCHAR6_EPTYPE_S) +#define USB_OTGFS_HCCHAR6_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR6_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR6_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR6_EC 0x00000003U +#define USB_OTGFS_HCCHAR6_EC_M (USB_OTGFS_HCCHAR6_EC_V << USB_OTGFS_HCCHAR6_EC_S) +#define USB_OTGFS_HCCHAR6_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR6_EC_S 20 +/** USB_OTGFS_HCCHAR6_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR6_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR6_DEVADDR_M (USB_OTGFS_HCCHAR6_DEVADDR_V << USB_OTGFS_HCCHAR6_DEVADDR_S) +#define USB_OTGFS_HCCHAR6_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR6_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR6_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR6_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR6_ODDFRM_M (USB_OTGFS_HCCHAR6_ODDFRM_V << USB_OTGFS_HCCHAR6_ODDFRM_S) +#define USB_OTGFS_HCCHAR6_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR6_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR6_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR6_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR6_CHDIS_M (USB_OTGFS_HCCHAR6_CHDIS_V << USB_OTGFS_HCCHAR6_CHDIS_S) +#define USB_OTGFS_HCCHAR6_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR6_CHDIS_S 30 +/** USB_OTGFS_HCCHAR6_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR6_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR6_CHENA_M (USB_OTGFS_HCCHAR6_CHENA_V << USB_OTGFS_HCCHAR6_CHENA_S) +#define USB_OTGFS_HCCHAR6_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR6_CHENA_S 31 + +/** USB_OTGFS_HCINT6_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT6_REG(i) (DR_REG_USB_BASE(i) + 0x5c8) +/** USB_OTGFS_HCINT6_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT6_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT6_XFERCOMPL_M (USB_OTGFS_HCINT6_XFERCOMPL_V << USB_OTGFS_HCINT6_XFERCOMPL_S) +#define USB_OTGFS_HCINT6_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT6_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT6_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT6_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT6_CHHLTD_M (USB_OTGFS_HCINT6_CHHLTD_V << USB_OTGFS_HCINT6_CHHLTD_S) +#define USB_OTGFS_HCINT6_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT6_CHHLTD_S 1 +/** USB_OTGFS_HCINT6_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT6_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT6_AHBERR_M (USB_OTGFS_HCINT6_AHBERR_V << USB_OTGFS_HCINT6_AHBERR_S) +#define USB_OTGFS_HCINT6_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT6_AHBERR_S 2 +/** USB_OTGFS_HCINT6_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT6_STALL (BIT(3)) +#define USB_OTGFS_HCINT6_STALL_M (USB_OTGFS_HCINT6_STALL_V << USB_OTGFS_HCINT6_STALL_S) +#define USB_OTGFS_HCINT6_STALL_V 0x00000001U +#define USB_OTGFS_HCINT6_STALL_S 3 +/** USB_OTGFS_HCINT6_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT6_NAK (BIT(4)) +#define USB_OTGFS_HCINT6_NAK_M (USB_OTGFS_HCINT6_NAK_V << USB_OTGFS_HCINT6_NAK_S) +#define USB_OTGFS_HCINT6_NAK_V 0x00000001U +#define USB_OTGFS_HCINT6_NAK_S 4 +/** USB_OTGFS_HCINT6_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT6_ACK (BIT(5)) +#define USB_OTGFS_HCINT6_ACK_M (USB_OTGFS_HCINT6_ACK_V << USB_OTGFS_HCINT6_ACK_S) +#define USB_OTGFS_HCINT6_ACK_V 0x00000001U +#define USB_OTGFS_HCINT6_ACK_S 5 +/** USB_OTGFS_HCINT6_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT6_NYET (BIT(6)) +#define USB_OTGFS_HCINT6_NYET_M (USB_OTGFS_HCINT6_NYET_V << USB_OTGFS_HCINT6_NYET_S) +#define USB_OTGFS_HCINT6_NYET_V 0x00000001U +#define USB_OTGFS_HCINT6_NYET_S 6 +/** USB_OTGFS_HCINT6_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT6_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT6_XACTERR_M (USB_OTGFS_HCINT6_XACTERR_V << USB_OTGFS_HCINT6_XACTERR_S) +#define USB_OTGFS_HCINT6_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT6_XACTERR_S 7 +/** USB_OTGFS_HCINT6_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT6_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT6_BBLERR_M (USB_OTGFS_HCINT6_BBLERR_V << USB_OTGFS_HCINT6_BBLERR_S) +#define USB_OTGFS_HCINT6_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT6_BBLERR_S 8 +/** USB_OTGFS_HCINT6_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT6_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT6_FRMOVRUN_M (USB_OTGFS_HCINT6_FRMOVRUN_V << USB_OTGFS_HCINT6_FRMOVRUN_S) +#define USB_OTGFS_HCINT6_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT6_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT6_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT6_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT6_DATATGLERR_M (USB_OTGFS_HCINT6_DATATGLERR_V << USB_OTGFS_HCINT6_DATATGLERR_S) +#define USB_OTGFS_HCINT6_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT6_DATATGLERR_S 10 +/** USB_OTGFS_HCINT6_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT6_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT6_BNAINTR_M (USB_OTGFS_HCINT6_BNAINTR_V << USB_OTGFS_HCINT6_BNAINTR_S) +#define USB_OTGFS_HCINT6_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT6_BNAINTR_S 11 +/** USB_OTGFS_HCINT6_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT6_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT6_XCS_XACT_ERR_M (USB_OTGFS_HCINT6_XCS_XACT_ERR_V << USB_OTGFS_HCINT6_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT6_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT6_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT6_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT6_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT6_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT6_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT6_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT6_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT6_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK6_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK6_REG(i) (DR_REG_USB_BASE(i) + 0x5cc) +/** USB_OTGFS_HCINTMSK6_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK6_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK6_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK6_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK6_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK6_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK6_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK6_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK6_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK6_CHHLTDMSK_M (USB_OTGFS_HCINTMSK6_CHHLTDMSK_V << USB_OTGFS_HCINTMSK6_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK6_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK6_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK6_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK6_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK6_AHBERRMSK_M (USB_OTGFS_HCINTMSK6_AHBERRMSK_V << USB_OTGFS_HCINTMSK6_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK6_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK6_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK6_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK6_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK6_BNAINTRMSK_M (USB_OTGFS_HCINTMSK6_BNAINTRMSK_V << USB_OTGFS_HCINTMSK6_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK6_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK6_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK6_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ6_REG register + * Host Channel 6 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ6_REG(i) (DR_REG_USB_BASE(i) + 0x5d0) +/** USB_OTGFS_HCTSIZ6_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ6_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ6_XFERSIZE_M (USB_OTGFS_HCTSIZ6_XFERSIZE_V << USB_OTGFS_HCTSIZ6_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ6_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ6_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ6_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ6_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ6_PKTCNT_M (USB_OTGFS_HCTSIZ6_PKTCNT_V << USB_OTGFS_HCTSIZ6_PKTCNT_S) +#define USB_OTGFS_HCTSIZ6_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ6_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ6_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ6_PID 0x00000003U +#define USB_OTGFS_HCTSIZ6_PID_M (USB_OTGFS_HCTSIZ6_PID_V << USB_OTGFS_HCTSIZ6_PID_S) +#define USB_OTGFS_HCTSIZ6_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ6_PID_S 29 +/** USB_OTGFS_HCTSIZ6_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ6_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ6_DOPNG_M (USB_OTGFS_HCTSIZ6_DOPNG_V << USB_OTGFS_HCTSIZ6_DOPNG_S) +#define USB_OTGFS_HCTSIZ6_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ6_DOPNG_S 31 + +/** USB_OTGFS_HCDMA6_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA6_REG(i) (DR_REG_USB_BASE(i) + 0x5d4) +/** USB_OTGFS_HCDMA6_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA6_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA6_DMAADDR_M (USB_OTGFS_HCDMA6_DMAADDR_V << USB_OTGFS_HCDMA6_DMAADDR_S) +#define USB_OTGFS_HCDMA6_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA6_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB6_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB6_REG(i) (DR_REG_USB_BASE(i) + 0x5dc) +/** USB_OTGFS_HCDMAB6_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB6_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB6_HCDMAB_M (USB_OTGFS_HCDMAB6_HCDMAB_V << USB_OTGFS_HCDMAB6_HCDMAB_S) +#define USB_OTGFS_HCDMAB6_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB6_HCDMAB_S 0 + +/** USB_OTGFS_HCCHAR7_REG register + * Host Channel 7 Characteristics Register + */ +#define USB_OTGFS_HCCHAR7_REG(i) (DR_REG_USB_BASE(i) + 0x5e0) +/** USB_OTGFS_HCCHAR7_MPS : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ +#define USB_OTGFS_HCCHAR7_MPS 0x000007FFU +#define USB_OTGFS_HCCHAR7_MPS_M (USB_OTGFS_HCCHAR7_MPS_V << USB_OTGFS_HCCHAR7_MPS_S) +#define USB_OTGFS_HCCHAR7_MPS_V 0x000007FFU +#define USB_OTGFS_HCCHAR7_MPS_S 0 +/** USB_OTGFS_HCCHAR7_EPNUM : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ +#define USB_OTGFS_HCCHAR7_EPNUM 0x0000000FU +#define USB_OTGFS_HCCHAR7_EPNUM_M (USB_OTGFS_HCCHAR7_EPNUM_V << USB_OTGFS_HCCHAR7_EPNUM_S) +#define USB_OTGFS_HCCHAR7_EPNUM_V 0x0000000FU +#define USB_OTGFS_HCCHAR7_EPNUM_S 11 +/** USB_OTGFS_HCCHAR7_EPDIR : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ +#define USB_OTGFS_HCCHAR7_EPDIR (BIT(15)) +#define USB_OTGFS_HCCHAR7_EPDIR_M (USB_OTGFS_HCCHAR7_EPDIR_V << USB_OTGFS_HCCHAR7_EPDIR_S) +#define USB_OTGFS_HCCHAR7_EPDIR_V 0x00000001U +#define USB_OTGFS_HCCHAR7_EPDIR_S 15 +/** USB_OTGFS_HCCHAR7_LSPDDEV : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ +#define USB_OTGFS_HCCHAR7_LSPDDEV (BIT(17)) +#define USB_OTGFS_HCCHAR7_LSPDDEV_M (USB_OTGFS_HCCHAR7_LSPDDEV_V << USB_OTGFS_HCCHAR7_LSPDDEV_S) +#define USB_OTGFS_HCCHAR7_LSPDDEV_V 0x00000001U +#define USB_OTGFS_HCCHAR7_LSPDDEV_S 17 +/** USB_OTGFS_HCCHAR7_EPTYPE : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ +#define USB_OTGFS_HCCHAR7_EPTYPE 0x00000003U +#define USB_OTGFS_HCCHAR7_EPTYPE_M (USB_OTGFS_HCCHAR7_EPTYPE_V << USB_OTGFS_HCCHAR7_EPTYPE_S) +#define USB_OTGFS_HCCHAR7_EPTYPE_V 0x00000003U +#define USB_OTGFS_HCCHAR7_EPTYPE_S 18 +/** USB_OTGFS_HCCHAR7_EC : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ +#define USB_OTGFS_HCCHAR7_EC 0x00000003U +#define USB_OTGFS_HCCHAR7_EC_M (USB_OTGFS_HCCHAR7_EC_V << USB_OTGFS_HCCHAR7_EC_S) +#define USB_OTGFS_HCCHAR7_EC_V 0x00000003U +#define USB_OTGFS_HCCHAR7_EC_S 20 +/** USB_OTGFS_HCCHAR7_DEVADDR : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ +#define USB_OTGFS_HCCHAR7_DEVADDR 0x0000007FU +#define USB_OTGFS_HCCHAR7_DEVADDR_M (USB_OTGFS_HCCHAR7_DEVADDR_V << USB_OTGFS_HCCHAR7_DEVADDR_S) +#define USB_OTGFS_HCCHAR7_DEVADDR_V 0x0000007FU +#define USB_OTGFS_HCCHAR7_DEVADDR_S 22 +/** USB_OTGFS_HCCHAR7_ODDFRM : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ +#define USB_OTGFS_HCCHAR7_ODDFRM (BIT(29)) +#define USB_OTGFS_HCCHAR7_ODDFRM_M (USB_OTGFS_HCCHAR7_ODDFRM_V << USB_OTGFS_HCCHAR7_ODDFRM_S) +#define USB_OTGFS_HCCHAR7_ODDFRM_V 0x00000001U +#define USB_OTGFS_HCCHAR7_ODDFRM_S 29 +/** USB_OTGFS_HCCHAR7_CHDIS : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ +#define USB_OTGFS_HCCHAR7_CHDIS (BIT(30)) +#define USB_OTGFS_HCCHAR7_CHDIS_M (USB_OTGFS_HCCHAR7_CHDIS_V << USB_OTGFS_HCCHAR7_CHDIS_S) +#define USB_OTGFS_HCCHAR7_CHDIS_V 0x00000001U +#define USB_OTGFS_HCCHAR7_CHDIS_S 30 +/** USB_OTGFS_HCCHAR7_CHENA : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ +#define USB_OTGFS_HCCHAR7_CHENA (BIT(31)) +#define USB_OTGFS_HCCHAR7_CHENA_M (USB_OTGFS_HCCHAR7_CHENA_V << USB_OTGFS_HCCHAR7_CHENA_S) +#define USB_OTGFS_HCCHAR7_CHENA_V 0x00000001U +#define USB_OTGFS_HCCHAR7_CHENA_S 31 + +/** USB_OTGFS_HCINT7_REG register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +#define USB_OTGFS_HCINT7_REG(i) (DR_REG_USB_BASE(i) + 0x5e8) +/** USB_OTGFS_HCINT7_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ +#define USB_OTGFS_HCINT7_XFERCOMPL (BIT(0)) +#define USB_OTGFS_HCINT7_XFERCOMPL_M (USB_OTGFS_HCINT7_XFERCOMPL_V << USB_OTGFS_HCINT7_XFERCOMPL_S) +#define USB_OTGFS_HCINT7_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_HCINT7_XFERCOMPL_S 0 +/** USB_OTGFS_HCINT7_CHHLTD : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ +#define USB_OTGFS_HCINT7_CHHLTD (BIT(1)) +#define USB_OTGFS_HCINT7_CHHLTD_M (USB_OTGFS_HCINT7_CHHLTD_V << USB_OTGFS_HCINT7_CHHLTD_S) +#define USB_OTGFS_HCINT7_CHHLTD_V 0x00000001U +#define USB_OTGFS_HCINT7_CHHLTD_S 1 +/** USB_OTGFS_HCINT7_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ +#define USB_OTGFS_HCINT7_AHBERR (BIT(2)) +#define USB_OTGFS_HCINT7_AHBERR_M (USB_OTGFS_HCINT7_AHBERR_V << USB_OTGFS_HCINT7_AHBERR_S) +#define USB_OTGFS_HCINT7_AHBERR_V 0x00000001U +#define USB_OTGFS_HCINT7_AHBERR_S 2 +/** USB_OTGFS_HCINT7_STALL : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT7_STALL (BIT(3)) +#define USB_OTGFS_HCINT7_STALL_M (USB_OTGFS_HCINT7_STALL_V << USB_OTGFS_HCINT7_STALL_S) +#define USB_OTGFS_HCINT7_STALL_V 0x00000001U +#define USB_OTGFS_HCINT7_STALL_S 3 +/** USB_OTGFS_HCINT7_NAK : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT7_NAK (BIT(4)) +#define USB_OTGFS_HCINT7_NAK_M (USB_OTGFS_HCINT7_NAK_V << USB_OTGFS_HCINT7_NAK_S) +#define USB_OTGFS_HCINT7_NAK_V 0x00000001U +#define USB_OTGFS_HCINT7_NAK_S 4 +/** USB_OTGFS_HCINT7_ACK : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT7_ACK (BIT(5)) +#define USB_OTGFS_HCINT7_ACK_M (USB_OTGFS_HCINT7_ACK_V << USB_OTGFS_HCINT7_ACK_S) +#define USB_OTGFS_HCINT7_ACK_V 0x00000001U +#define USB_OTGFS_HCINT7_ACK_S 5 +/** USB_OTGFS_HCINT7_NYET : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT7_NYET (BIT(6)) +#define USB_OTGFS_HCINT7_NYET_M (USB_OTGFS_HCINT7_NYET_V << USB_OTGFS_HCINT7_NYET_S) +#define USB_OTGFS_HCINT7_NYET_V 0x00000001U +#define USB_OTGFS_HCINT7_NYET_S 6 +/** USB_OTGFS_HCINT7_XACTERR : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ +#define USB_OTGFS_HCINT7_XACTERR (BIT(7)) +#define USB_OTGFS_HCINT7_XACTERR_M (USB_OTGFS_HCINT7_XACTERR_V << USB_OTGFS_HCINT7_XACTERR_S) +#define USB_OTGFS_HCINT7_XACTERR_V 0x00000001U +#define USB_OTGFS_HCINT7_XACTERR_S 7 +/** USB_OTGFS_HCINT7_BBLERR : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ +#define USB_OTGFS_HCINT7_BBLERR (BIT(8)) +#define USB_OTGFS_HCINT7_BBLERR_M (USB_OTGFS_HCINT7_BBLERR_V << USB_OTGFS_HCINT7_BBLERR_S) +#define USB_OTGFS_HCINT7_BBLERR_V 0x00000001U +#define USB_OTGFS_HCINT7_BBLERR_S 8 +/** USB_OTGFS_HCINT7_FRMOVRUN : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ +#define USB_OTGFS_HCINT7_FRMOVRUN (BIT(9)) +#define USB_OTGFS_HCINT7_FRMOVRUN_M (USB_OTGFS_HCINT7_FRMOVRUN_V << USB_OTGFS_HCINT7_FRMOVRUN_S) +#define USB_OTGFS_HCINT7_FRMOVRUN_V 0x00000001U +#define USB_OTGFS_HCINT7_FRMOVRUN_S 9 +/** USB_OTGFS_HCINT7_DATATGLERR : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ +#define USB_OTGFS_HCINT7_DATATGLERR (BIT(10)) +#define USB_OTGFS_HCINT7_DATATGLERR_M (USB_OTGFS_HCINT7_DATATGLERR_V << USB_OTGFS_HCINT7_DATATGLERR_S) +#define USB_OTGFS_HCINT7_DATATGLERR_V 0x00000001U +#define USB_OTGFS_HCINT7_DATATGLERR_S 10 +/** USB_OTGFS_HCINT7_BNAINTR : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT7_BNAINTR (BIT(11)) +#define USB_OTGFS_HCINT7_BNAINTR_M (USB_OTGFS_HCINT7_BNAINTR_V << USB_OTGFS_HCINT7_BNAINTR_S) +#define USB_OTGFS_HCINT7_BNAINTR_V 0x00000001U +#define USB_OTGFS_HCINT7_BNAINTR_S 11 +/** USB_OTGFS_HCINT7_XCS_XACT_ERR : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT7_XCS_XACT_ERR (BIT(12)) +#define USB_OTGFS_HCINT7_XCS_XACT_ERR_M (USB_OTGFS_HCINT7_XCS_XACT_ERR_V << USB_OTGFS_HCINT7_XCS_XACT_ERR_S) +#define USB_OTGFS_HCINT7_XCS_XACT_ERR_V 0x00000001U +#define USB_OTGFS_HCINT7_XCS_XACT_ERR_S 12 +/** USB_OTGFS_HCINT7_DESC_LST_ROLLINTR : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ +#define USB_OTGFS_HCINT7_DESC_LST_ROLLINTR (BIT(13)) +#define USB_OTGFS_HCINT7_DESC_LST_ROLLINTR_M (USB_OTGFS_HCINT7_DESC_LST_ROLLINTR_V << USB_OTGFS_HCINT7_DESC_LST_ROLLINTR_S) +#define USB_OTGFS_HCINT7_DESC_LST_ROLLINTR_V 0x00000001U +#define USB_OTGFS_HCINT7_DESC_LST_ROLLINTR_S 13 + +/** USB_OTGFS_HCINTMSK7_REG register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +#define USB_OTGFS_HCINTMSK7_REG(i) (DR_REG_USB_BASE(i) + 0x5ec) +/** USB_OTGFS_HCINTMSK7_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ +#define USB_OTGFS_HCINTMSK7_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_HCINTMSK7_XFERCOMPLMSK_M (USB_OTGFS_HCINTMSK7_XFERCOMPLMSK_V << USB_OTGFS_HCINTMSK7_XFERCOMPLMSK_S) +#define USB_OTGFS_HCINTMSK7_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK7_XFERCOMPLMSK_S 0 +/** USB_OTGFS_HCINTMSK7_CHHLTDMSK : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ +#define USB_OTGFS_HCINTMSK7_CHHLTDMSK (BIT(1)) +#define USB_OTGFS_HCINTMSK7_CHHLTDMSK_M (USB_OTGFS_HCINTMSK7_CHHLTDMSK_V << USB_OTGFS_HCINTMSK7_CHHLTDMSK_S) +#define USB_OTGFS_HCINTMSK7_CHHLTDMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK7_CHHLTDMSK_S 1 +/** USB_OTGFS_HCINTMSK7_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ +#define USB_OTGFS_HCINTMSK7_AHBERRMSK (BIT(2)) +#define USB_OTGFS_HCINTMSK7_AHBERRMSK_M (USB_OTGFS_HCINTMSK7_AHBERRMSK_V << USB_OTGFS_HCINTMSK7_AHBERRMSK_S) +#define USB_OTGFS_HCINTMSK7_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK7_AHBERRMSK_S 2 +/** USB_OTGFS_HCINTMSK7_BNAINTRMSK : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK7_BNAINTRMSK (BIT(11)) +#define USB_OTGFS_HCINTMSK7_BNAINTRMSK_M (USB_OTGFS_HCINTMSK7_BNAINTRMSK_V << USB_OTGFS_HCINTMSK7_BNAINTRMSK_S) +#define USB_OTGFS_HCINTMSK7_BNAINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK7_BNAINTRMSK_S 11 +/** USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ +#define USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK (BIT(13)) +#define USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK_M (USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK_V << USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK_S) +#define USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK_V 0x00000001U +#define USB_OTGFS_HCINTMSK7_DESC_LST_ROLLINTRMSK_S 13 + +/** USB_OTGFS_HCTSIZ7_REG register + * Host Channel 7 Transfer Size Register + */ +#define USB_OTGFS_HCTSIZ7_REG(i) (DR_REG_USB_BASE(i) + 0x5f0) +/** USB_OTGFS_HCTSIZ7_XFERSIZE : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ7_XFERSIZE 0x0000FFFFU +#define USB_OTGFS_HCTSIZ7_XFERSIZE_M (USB_OTGFS_HCTSIZ7_XFERSIZE_V << USB_OTGFS_HCTSIZ7_XFERSIZE_S) +#define USB_OTGFS_HCTSIZ7_XFERSIZE_V 0x0000FFFFU +#define USB_OTGFS_HCTSIZ7_XFERSIZE_S 0 +/** USB_OTGFS_HCTSIZ7_PKTCNT : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ +#define USB_OTGFS_HCTSIZ7_PKTCNT 0x0000007FU +#define USB_OTGFS_HCTSIZ7_PKTCNT_M (USB_OTGFS_HCTSIZ7_PKTCNT_V << USB_OTGFS_HCTSIZ7_PKTCNT_S) +#define USB_OTGFS_HCTSIZ7_PKTCNT_V 0x0000007FU +#define USB_OTGFS_HCTSIZ7_PKTCNT_S 19 +/** USB_OTGFS_HCTSIZ7_PID : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_OTGFS_HCTSIZ7_PID 0x00000003U +#define USB_OTGFS_HCTSIZ7_PID_M (USB_OTGFS_HCTSIZ7_PID_V << USB_OTGFS_HCTSIZ7_PID_S) +#define USB_OTGFS_HCTSIZ7_PID_V 0x00000003U +#define USB_OTGFS_HCTSIZ7_PID_S 29 +/** USB_OTGFS_HCTSIZ7_DOPNG : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ +#define USB_OTGFS_HCTSIZ7_DOPNG (BIT(31)) +#define USB_OTGFS_HCTSIZ7_DOPNG_M (USB_OTGFS_HCTSIZ7_DOPNG_V << USB_OTGFS_HCTSIZ7_DOPNG_S) +#define USB_OTGFS_HCTSIZ7_DOPNG_V 0x00000001U +#define USB_OTGFS_HCTSIZ7_DOPNG_S 31 + +/** USB_OTGFS_HCDMA7_REG register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +#define USB_OTGFS_HCDMA7_REG(i) (DR_REG_USB_BASE(i) + 0x5f4) +/** USB_OTGFS_HCDMA7_DMAADDR : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ +#define USB_OTGFS_HCDMA7_DMAADDR 0xFFFFFFFFU +#define USB_OTGFS_HCDMA7_DMAADDR_M (USB_OTGFS_HCDMA7_DMAADDR_V << USB_OTGFS_HCDMA7_DMAADDR_S) +#define USB_OTGFS_HCDMA7_DMAADDR_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMA7_DMAADDR_S 0 + +/** USB_OTGFS_HCDMAB7_REG register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +#define USB_OTGFS_HCDMAB7_REG(i) (DR_REG_USB_BASE(i) + 0x5fc) +/** USB_OTGFS_HCDMAB7_HCDMAB : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ +#define USB_OTGFS_HCDMAB7_HCDMAB 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB7_HCDMAB_M (USB_OTGFS_HCDMAB7_HCDMAB_V << USB_OTGFS_HCDMAB7_HCDMAB_S) +#define USB_OTGFS_HCDMAB7_HCDMAB_V 0xFFFFFFFFU +#define USB_OTGFS_HCDMAB7_HCDMAB_S 0 + +/** USB_OTGFS_DCFG_REG register + * Device Configuration Register This register configures the core in Device mode + * after power-on or after certain control commands or enumeration. Do not make + * changes to this register after initial programming. + */ +#define USB_OTGFS_DCFG_REG(i) (DR_REG_USB_BASE(i) + 0x800) +/** USB_OTGFS_DCFG_DEVSPD : R/W; bitpos: [1:0]; default: 0; + * Device Speed (DevSpd) + * + * Indicates the speed at which the application requires the core to + * enumerate, or the maximum speed the application can support. + * However, the actual bus speed is determined only after the connect + * sequence is completed, and is based on the speed of the USB + * host to which the core is connected. + */ +#define USB_OTGFS_DCFG_DEVSPD 0x00000003U +#define USB_OTGFS_DCFG_DEVSPD_M (USB_OTGFS_DCFG_DEVSPD_V << USB_OTGFS_DCFG_DEVSPD_S) +#define USB_OTGFS_DCFG_DEVSPD_V 0x00000003U +#define USB_OTGFS_DCFG_DEVSPD_S 0 +/** USB_OTGFS_DCFG_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0; + * Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + * + * The application can use this field to select the handshake the core sends on + * receiving a nonzero-length data packet during the OUT transaction of a control + * transfer's Status stage. + * - 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do + * not send the received OUT packet to the application. + * - 1'b0: Send the received OUT packet to the application (zerolength or + * nonzero-length) and send a handshake based on the NAK and STALL bits for the + * endpoint in the Device Endpoint Control register. + */ +#define USB_OTGFS_DCFG_NZSTSOUTHSHK (BIT(2)) +#define USB_OTGFS_DCFG_NZSTSOUTHSHK_M (USB_OTGFS_DCFG_NZSTSOUTHSHK_V << USB_OTGFS_DCFG_NZSTSOUTHSHK_S) +#define USB_OTGFS_DCFG_NZSTSOUTHSHK_V 0x00000001U +#define USB_OTGFS_DCFG_NZSTSOUTHSHK_S 2 +/** USB_OTGFS_DCFG_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0; + * Enable 32 KHz Suspend mode (Ena32KHzSusp) + * + * This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs + * to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock + * during Suspend must be switched from 48 MHz to 32 KHz. + */ +#define USB_OTGFS_DCFG_ENA32KHZSUSP (BIT(3)) +#define USB_OTGFS_DCFG_ENA32KHZSUSP_M (USB_OTGFS_DCFG_ENA32KHZSUSP_V << USB_OTGFS_DCFG_ENA32KHZSUSP_S) +#define USB_OTGFS_DCFG_ENA32KHZSUSP_V 0x00000001U +#define USB_OTGFS_DCFG_ENA32KHZSUSP_S 3 +/** USB_OTGFS_DCFG_DEVADDR : R/W; bitpos: [10:4]; default: 0; + * Device Address (DevAddr) + * + * The application must program this field after every SetAddress control command. + */ +#define USB_OTGFS_DCFG_DEVADDR 0x0000007FU +#define USB_OTGFS_DCFG_DEVADDR_M (USB_OTGFS_DCFG_DEVADDR_V << USB_OTGFS_DCFG_DEVADDR_S) +#define USB_OTGFS_DCFG_DEVADDR_V 0x0000007FU +#define USB_OTGFS_DCFG_DEVADDR_S 4 +/** USB_OTGFS_DCFG_PERFRINT : R/W; bitpos: [12:11]; default: 0; + * Periodic Frame Interval (PerFrInt) + * + * Indicates the time within a (micro)Frame at which the application + * must be notified using the End Of Periodic Frame Interrupt. This + * can be used to determine If all the isochronous traffic for that + * (micro)Frame is complete. + * - 2'b00: 80% of the (micro)Frame interval + * - 2'b01: 85% of the (micro)Frame interval + * - 2'b10: 90% of the (micro)Frame interval + * - 2'b11: 95% of the (micro)Frame interval + */ +#define USB_OTGFS_DCFG_PERFRINT 0x00000003U +#define USB_OTGFS_DCFG_PERFRINT_M (USB_OTGFS_DCFG_PERFRINT_V << USB_OTGFS_DCFG_PERFRINT_S) +#define USB_OTGFS_DCFG_PERFRINT_V 0x00000003U +#define USB_OTGFS_DCFG_PERFRINT_S 11 +/** USB_OTGFS_DCFG_ENDEVOUTNAK : R/W; bitpos: [13]; default: 0; + * Enable Device OUT NAK (EnDevOutNak) + * + * This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed + * for Device mode Descriptor DMA + * - 1'b0 : The core does not set NAK after Bulk OUT transfer complete + * - 1'b1 : The core sets NAK after Bulk OUT transfer complete + * It bit is one time programmable after reset like any other DCFG register bits. + */ +#define USB_OTGFS_DCFG_ENDEVOUTNAK (BIT(13)) +#define USB_OTGFS_DCFG_ENDEVOUTNAK_M (USB_OTGFS_DCFG_ENDEVOUTNAK_V << USB_OTGFS_DCFG_ENDEVOUTNAK_S) +#define USB_OTGFS_DCFG_ENDEVOUTNAK_V 0x00000001U +#define USB_OTGFS_DCFG_ENDEVOUTNAK_S 13 +/** USB_OTGFS_DCFG_XCVRDLY : R/W; bitpos: [14]; default: 0; + * XCVRDLY + * + * Enables or disables delay between xcvr_sel and txvalid during device chirp + */ +#define USB_OTGFS_DCFG_XCVRDLY (BIT(14)) +#define USB_OTGFS_DCFG_XCVRDLY_M (USB_OTGFS_DCFG_XCVRDLY_V << USB_OTGFS_DCFG_XCVRDLY_S) +#define USB_OTGFS_DCFG_XCVRDLY_V 0x00000001U +#define USB_OTGFS_DCFG_XCVRDLY_S 14 +/** USB_OTGFS_DCFG_ERRATICINTMSK : R/W; bitpos: [15]; default: 0; + * Erratic Error Interrupt Mask + */ +#define USB_OTGFS_DCFG_ERRATICINTMSK (BIT(15)) +#define USB_OTGFS_DCFG_ERRATICINTMSK_M (USB_OTGFS_DCFG_ERRATICINTMSK_V << USB_OTGFS_DCFG_ERRATICINTMSK_S) +#define USB_OTGFS_DCFG_ERRATICINTMSK_V 0x00000001U +#define USB_OTGFS_DCFG_ERRATICINTMSK_S 15 +/** USB_OTGFS_DCFG_DESCDMA : R/W; bitpos: [23]; default: 0; + * Enable Scatter/gather DMA in device mode (DescDMA). + * + * When the Scatter/Gather DMA option selected during configuration of the RTL, the + * application can Set this bit during initialization to enable the Scatter/Gather DMA + * operation. + * + * Note: This bit must be modified only once after a reset. The following combinations + * are available for programming: + * - GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode + * - GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid + * - GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA mode + * - GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode + */ +#define USB_OTGFS_DCFG_DESCDMA (BIT(23)) +#define USB_OTGFS_DCFG_DESCDMA_M (USB_OTGFS_DCFG_DESCDMA_V << USB_OTGFS_DCFG_DESCDMA_S) +#define USB_OTGFS_DCFG_DESCDMA_V 0x00000001U +#define USB_OTGFS_DCFG_DESCDMA_S 23 +/** USB_OTGFS_DCFG_PERSCHINTVL : R/W; bitpos: [25:24]; default: 0; + * Periodic Scheduling Interval (PerSchIntvl) + * + * PerSchIntvl must be programmed for Scatter/Gather DMA mode. + * + * This field specifies the amount of time the Internal + * DMA engine must allocate for fetching periodic IN endpoint data. + * Based on the number of periodic endpoints, this value must be + * specified as 25,50 or 75% of (micro)Frame. + * - When any periodic endpoints are active, the internal DMA engine allocates the + * specified amount of time in fetching periodic IN endpoint data . + * - When no periodic endpoints are active, Then the internal DMA engine services + * non-periodic endpoints, ignoring this field. + * - After the specified time within a (micro)Frame, the DMA switches to fetching for + * non-periodic endpoints. + * -- 2'b00: 25% of (micro)Frame. + * -- 2'b01: 50% of (micro)Frame. + * -- 2'b10: 75% of (micro)Frame. + * -- 2'b11: Reserved. + * Reset: 2'b00 + */ +#define USB_OTGFS_DCFG_PERSCHINTVL 0x00000003U +#define USB_OTGFS_DCFG_PERSCHINTVL_M (USB_OTGFS_DCFG_PERSCHINTVL_V << USB_OTGFS_DCFG_PERSCHINTVL_S) +#define USB_OTGFS_DCFG_PERSCHINTVL_V 0x00000003U +#define USB_OTGFS_DCFG_PERSCHINTVL_S 24 +/** USB_OTGFS_DCFG_RESVALID : R/W; bitpos: [31:26]; default: 2; + * Resume Validation Period (ResValid) + * + * This field is effective only when DCFG.Ena32KHzSusp is set. + * It controls the resume period when the core resumes from + * suspend. The core counts for ResValid number of clock cycles + * to detect a valid resume when this bit is set + */ +#define USB_OTGFS_DCFG_RESVALID 0x0000003FU +#define USB_OTGFS_DCFG_RESVALID_M (USB_OTGFS_DCFG_RESVALID_V << USB_OTGFS_DCFG_RESVALID_S) +#define USB_OTGFS_DCFG_RESVALID_V 0x0000003FU +#define USB_OTGFS_DCFG_RESVALID_S 26 + +/** USB_OTGFS_DCTL_REG register + * Device Control Register + */ +#define USB_OTGFS_DCTL_REG(i) (DR_REG_USB_BASE(i) + 0x804) +/** USB_OTGFS_DCTL_RMTWKUPSIG : R/W; bitpos: [0]; default: 0; + * Remote Wakeup Signaling (RmtWkUpSig) + * + * When the application sets this bit, the core initiates remote + * signaling to wake up the USB host. The application must Set this + * bit to instruct the core to exit the Suspend state. As specified in + * the USB 2.0 specification, the application must clear this bit + * 1-15 ms after setting it. + * + * + * If LPM is enabled and the core is in the L1 (Sleep) state, when the application + * sets this bit, the core initiates L1 remote signaling to wake up the USB host. The + * application must set this bit to instruct the core to exit the Sleep state. As + * specified in the LPM specification, the hardware automatically clears this bit 50 + * microseconds (TL1DevDrvResume) after being set by the application. The application + * must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is + * zero. + */ +#define USB_OTGFS_DCTL_RMTWKUPSIG (BIT(0)) +#define USB_OTGFS_DCTL_RMTWKUPSIG_M (USB_OTGFS_DCTL_RMTWKUPSIG_V << USB_OTGFS_DCTL_RMTWKUPSIG_S) +#define USB_OTGFS_DCTL_RMTWKUPSIG_V 0x00000001U +#define USB_OTGFS_DCTL_RMTWKUPSIG_S 0 +/** USB_OTGFS_DCTL_SFTDISCON : R/W; bitpos: [1]; default: 1; + * Soft Disconnect (SftDiscon) + * + * The application uses this bit to signal the controller to do a soft disconnect. As + * long as this bit is Set, the host does not see that the device is connected, and + * the device does not receive + * signals on the USB. The core stays in the disconnected state until the application + * clears this bit. + * - 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the + * core drives the phy_opmode_o signal on the + * UTMI+ to 2'b00, which generates a device connect event to the USB host. When the + * device is reconnected, the USB host restarts device enumeration. + * - 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which + * generates a device disconnect event to the USB host. + * The following is the minimum duration under various conditions for which this bit + * must be set for the USB host to detect a device disconnect. To accommodate clock + * jitter, it is + * recommended that the application adds some extra delay to the specified minimum + * duration. + * + * For high speed, if the device state is, + * - Suspended, the minimum duration is 1ms + 2.5us + * - Idle, the minimum duration is 3ms + 2.5us + * - Not Idle or Suspended (performing transactions), the minimum duration 125 us + * For full speed/low speed, if the device state is, + * - Suspended, the minimum duration is 1ms + 2.5us + * - Idle, the minimum duration is 2.5us + * - Not Idle or Suspended (performing transactions), the minimum duration 125 us + * Note: + * - This bit can be also used for ULPI/FS Serial interfaces. + * - This bit is not impacted by a soft reset. + */ +#define USB_OTGFS_DCTL_SFTDISCON (BIT(1)) +#define USB_OTGFS_DCTL_SFTDISCON_M (USB_OTGFS_DCTL_SFTDISCON_V << USB_OTGFS_DCTL_SFTDISCON_S) +#define USB_OTGFS_DCTL_SFTDISCON_V 0x00000001U +#define USB_OTGFS_DCTL_SFTDISCON_S 1 +/** USB_OTGFS_DCTL_GNPINNAKSTS : RO; bitpos: [2]; default: 0; + * Global Non-periodic IN NAK Status (GNPINNakSts) + * - 1'b0: A handshake is sent out based on the data availability in the transmit FIFO. + * - 1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective + * of the data availability in the transmit FIFO. + */ +#define USB_OTGFS_DCTL_GNPINNAKSTS (BIT(2)) +#define USB_OTGFS_DCTL_GNPINNAKSTS_M (USB_OTGFS_DCTL_GNPINNAKSTS_V << USB_OTGFS_DCTL_GNPINNAKSTS_S) +#define USB_OTGFS_DCTL_GNPINNAKSTS_V 0x00000001U +#define USB_OTGFS_DCTL_GNPINNAKSTS_S 2 +/** USB_OTGFS_DCTL_GOUTNAKSTS : RO; bitpos: [3]; default: 0; + * Global OUT NAK Status (GOUTNakSts) + * - 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit + * settings. + * - 1'b1: No data is written to the RxFIFO, irrespective of space availability. Sends + * a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT + * packets are dropped. + */ +#define USB_OTGFS_DCTL_GOUTNAKSTS (BIT(3)) +#define USB_OTGFS_DCTL_GOUTNAKSTS_M (USB_OTGFS_DCTL_GOUTNAKSTS_V << USB_OTGFS_DCTL_GOUTNAKSTS_S) +#define USB_OTGFS_DCTL_GOUTNAKSTS_V 0x00000001U +#define USB_OTGFS_DCTL_GOUTNAKSTS_S 3 +/** USB_OTGFS_DCTL_TSTCTL : R/W; bitpos: [6:4]; default: 0; + * Test Control (TstCtl) + * - 3'b000: Test mode disabled + * - 3'b001: Test_J mode + * - 3'b010: Test_K mode + * - 3'b011: Test_SE0_NAK mode + * - 3'b100: Test_Packet mode + * - 3'b101: Test_Force_Enable + * - Others: Reserved + */ +#define USB_OTGFS_DCTL_TSTCTL 0x00000007U +#define USB_OTGFS_DCTL_TSTCTL_M (USB_OTGFS_DCTL_TSTCTL_V << USB_OTGFS_DCTL_TSTCTL_S) +#define USB_OTGFS_DCTL_TSTCTL_V 0x00000007U +#define USB_OTGFS_DCTL_TSTCTL_S 4 +/** USB_OTGFS_DCTL_SGNPINNAK : R/W; bitpos: [7]; default: 0; + * Set Global Non-periodic IN NAK (SGNPInNak) + * + * A write to this field sets the Global Non-periodic IN NAK.The application uses this + * bit to send a NAK handshake on all non-periodic IN endpoints. + * The core can also Set this bit when a timeout condition is detected on a + * non-periodic endpoint in shared FIFO operation. + * The application must Set this bit only after making sure that the Global IN NAK + * Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared + */ +#define USB_OTGFS_DCTL_SGNPINNAK (BIT(7)) +#define USB_OTGFS_DCTL_SGNPINNAK_M (USB_OTGFS_DCTL_SGNPINNAK_V << USB_OTGFS_DCTL_SGNPINNAK_S) +#define USB_OTGFS_DCTL_SGNPINNAK_V 0x00000001U +#define USB_OTGFS_DCTL_SGNPINNAK_S 7 +/** USB_OTGFS_DCTL_CGNPINNAK : R/W; bitpos: [8]; default: 0; + * Clear Global Non-periodic IN NAK (CGNPInNak) + * + * A write to this field clears the Global Non-periodic IN NAK. + */ +#define USB_OTGFS_DCTL_CGNPINNAK (BIT(8)) +#define USB_OTGFS_DCTL_CGNPINNAK_M (USB_OTGFS_DCTL_CGNPINNAK_V << USB_OTGFS_DCTL_CGNPINNAK_S) +#define USB_OTGFS_DCTL_CGNPINNAK_V 0x00000001U +#define USB_OTGFS_DCTL_CGNPINNAK_S 8 +/** USB_OTGFS_DCTL_SGOUTNAK : R/W; bitpos: [9]; default: 0; + * Set Global OUT NAK (SGOUTNak) + * + * A write to this field sets the Global OUT NAK. The application uses this bit to + * send a NAK handshake on all OUT endpoints. + * The application must set the this bit only after making sure that the Global OUT + * NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. + */ +#define USB_OTGFS_DCTL_SGOUTNAK (BIT(9)) +#define USB_OTGFS_DCTL_SGOUTNAK_M (USB_OTGFS_DCTL_SGOUTNAK_V << USB_OTGFS_DCTL_SGOUTNAK_S) +#define USB_OTGFS_DCTL_SGOUTNAK_V 0x00000001U +#define USB_OTGFS_DCTL_SGOUTNAK_S 9 +/** USB_OTGFS_DCTL_CGOUTNAK : R/W; bitpos: [10]; default: 0; + * Clear Global OUT NAK (CGOUTNak) + * + * A write to this field clears the Global OUT NAK. + */ +#define USB_OTGFS_DCTL_CGOUTNAK (BIT(10)) +#define USB_OTGFS_DCTL_CGOUTNAK_M (USB_OTGFS_DCTL_CGOUTNAK_V << USB_OTGFS_DCTL_CGOUTNAK_S) +#define USB_OTGFS_DCTL_CGOUTNAK_V 0x00000001U +#define USB_OTGFS_DCTL_CGOUTNAK_S 10 +/** USB_OTGFS_DCTL_PWRONPRGDONE : R/W; bitpos: [11]; default: 0; + * Power-On Programming Done (PWROnPrgDone) + * + * The application uses this bit to indicate that register programming is completed + * after a wake-up from Power Down mode. + */ +#define USB_OTGFS_DCTL_PWRONPRGDONE (BIT(11)) +#define USB_OTGFS_DCTL_PWRONPRGDONE_M (USB_OTGFS_DCTL_PWRONPRGDONE_V << USB_OTGFS_DCTL_PWRONPRGDONE_S) +#define USB_OTGFS_DCTL_PWRONPRGDONE_V 0x00000001U +#define USB_OTGFS_DCTL_PWRONPRGDONE_S 11 +/** USB_OTGFS_DCTL_GMC : R/W; bitpos: [14:13]; default: 0; + * Global Multi Count (GMC) + * + * GMC must be programmed only once after initialization. + * Applicable only for Scatter/Gather DMA mode. This indicates the number of packets + * to be serviced for that end point before moving to the next end point. It is only + * for non-periodic endpoints. + * - 2'b00: Invalid. + * - 2'b01: 1 packet. + * - 2'b10: 2 packets. + * - 2'b11: 3 packets. + * The value of this field automatically changes to 2'h1 when DCFG.DescDMA is set to + * 1. When Scatter/Gather DMA mode is disabled, this field is reserved. and reads + * 2'b00. + */ +#define USB_OTGFS_DCTL_GMC 0x00000003U +#define USB_OTGFS_DCTL_GMC_M (USB_OTGFS_DCTL_GMC_V << USB_OTGFS_DCTL_GMC_S) +#define USB_OTGFS_DCTL_GMC_V 0x00000003U +#define USB_OTGFS_DCTL_GMC_S 13 +/** USB_OTGFS_DCTL_IGNRFRMNUM : R/W; bitpos: [15]; default: 0; + * Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + * + * This field is also used to control the Periodic Transfer Interrupt (PTI) feature. + * + * Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold + * mode. + * + * Slave Mode (GAHBCFG.DMAEn=0): + * + * This bit is not valid in Slave mode and should not be programmed to 1. + * + * Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1): + * + * Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to + * High Speed, High bandwidth transfers. + * + * When this bit is enabled, there must be only one packet per descriptor. + * - 0: The core transmits the packets only in the frame number in which they are + * intended to be transmitted. + * - 1: The core ignores the frame number, sending packets immediately as the packets + * are ready. + * In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed + * when a ISOC IN token is received for an elapsed frame. + * + * Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode + * (GAHBCFG.DMAEn=1,DCFG.DescDMA=0): + * + * When Scatter/Gather DMA mode is disabled, this field is used by the application to + * enable Periodic Transfer Interrupt (PTI) Mode. + * + * The application can program Periodic Endpoint transfers for multiple (micro)Frames. + * - 0: Periodic Transfer Interrupt feature is disabled, application needs to program + * transfers for periodic endpoints every (micro)Frame + * - 1: Periodic Transfer Interrupt feature is enabled, application can program + * transfers for multiple (micro)Frames for periodic endpoints. + * In the PTI mode, the application will receive Transfer Complete Interrupt after + * transfers for multiple (micro)Frames are completed. + */ +#define USB_OTGFS_DCTL_IGNRFRMNUM (BIT(15)) +#define USB_OTGFS_DCTL_IGNRFRMNUM_M (USB_OTGFS_DCTL_IGNRFRMNUM_V << USB_OTGFS_DCTL_IGNRFRMNUM_S) +#define USB_OTGFS_DCTL_IGNRFRMNUM_V 0x00000001U +#define USB_OTGFS_DCTL_IGNRFRMNUM_S 15 +/** USB_OTGFS_DCTL_NAKONBBLE : R/W; bitpos: [16]; default: 0; + * NAK on Babble Error (NakOnBble) + * + * Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for + * the endpoint on which babble is received. + */ +#define USB_OTGFS_DCTL_NAKONBBLE (BIT(16)) +#define USB_OTGFS_DCTL_NAKONBBLE_M (USB_OTGFS_DCTL_NAKONBBLE_V << USB_OTGFS_DCTL_NAKONBBLE_S) +#define USB_OTGFS_DCTL_NAKONBBLE_V 0x00000001U +#define USB_OTGFS_DCTL_NAKONBBLE_S 16 +/** USB_OTGFS_DCTL_ENCONTONBNA : R/W; bitpos: [17]; default: 0; + * Enable Continue on BNA (EnContOnBNA) + * + * This bit enables the core to continue on BNA for Bulk OUT endpoints. + * With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA + * interrupt + * the core starts processing the descriptor that caused the BNA interrupt after + * the endpoint re-enables the endpoint. + * - 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the + * endpoint is re-enabled by the application,the core starts processing from the + * DOEPDMA descriptor. + * - 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the + * endpoint is re-enabled by the application, the core starts processing from the + * descriptor that received the BNA interrupt. + * + * This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable + * after reset bit like any other DCTL register bits. + */ +#define USB_OTGFS_DCTL_ENCONTONBNA (BIT(17)) +#define USB_OTGFS_DCTL_ENCONTONBNA_M (USB_OTGFS_DCTL_ENCONTONBNA_V << USB_OTGFS_DCTL_ENCONTONBNA_S) +#define USB_OTGFS_DCTL_ENCONTONBNA_V 0x00000001U +#define USB_OTGFS_DCTL_ENCONTONBNA_S 17 + +/** USB_OTGFS_DSTS_REG register + * Device Status Register This register indicates the status of the core with respect + * to USB-related events. It must be read on interrupts from Device All Interrupts + * (DAINT) register. + */ +#define USB_OTGFS_DSTS_REG(i) (DR_REG_USB_BASE(i) + 0x808) +/** USB_OTGFS_DSTS_SUSPSTS : RO; bitpos: [0]; default: 0; + * Suspend Status (SuspSts) + * + * In Device mode, this bit is set as long as a Suspend condition is + * detected on the USB. The core enters the Suspend state + * when there is no activity on the phy_line_state_i signal for an + * extended period of time. The core comes out of the suspend under the following + * conditions : + * - If there is any activity on the phy_line_state_i signal, or + * - If the application writes to the Remote Wakeup Signaling bit in the Device + * Control register (DCTL.RmtWkUpSig). + * When the core comes out of the suspend, this bit is set to 1'b0. + */ +#define USB_OTGFS_DSTS_SUSPSTS (BIT(0)) +#define USB_OTGFS_DSTS_SUSPSTS_M (USB_OTGFS_DSTS_SUSPSTS_V << USB_OTGFS_DSTS_SUSPSTS_S) +#define USB_OTGFS_DSTS_SUSPSTS_V 0x00000001U +#define USB_OTGFS_DSTS_SUSPSTS_S 0 +/** USB_OTGFS_DSTS_ENUMSPD : RO; bitpos: [2:1]; default: 1; + * Enumerated Speed (EnumSpd) + * + * Indicates the speed at which the controller has come up + * after speed detection through a connect or reset sequence. + * - 2'b00: High speed (PHY clock is running at 30 or 60 MHz) + * - 2'b01: Full speed (PHY clock is running at 30 or 60 MHz) + * - 2'b10: Low speed (PHY clock is running at 6 MHz) + * - 2'b11: Full speed (PHY clock is running at 48 MHz) + * Low speed is not supported for devices using a UTMI+ PHY. + */ +#define USB_OTGFS_DSTS_ENUMSPD 0x00000003U +#define USB_OTGFS_DSTS_ENUMSPD_M (USB_OTGFS_DSTS_ENUMSPD_V << USB_OTGFS_DSTS_ENUMSPD_S) +#define USB_OTGFS_DSTS_ENUMSPD_V 0x00000003U +#define USB_OTGFS_DSTS_ENUMSPD_S 1 +/** USB_OTGFS_DSTS_ERRTICERR : RO; bitpos: [3]; default: 0; + * Erratic Error (ErrticErr) + * + * The core sets this bit to report any erratic errors + * (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at + * least 2 ms, due to PHY error) seen on the UTMI+. + * Due to erratic errors, the DWC_otg core goes into Suspended + * state and an interrupt is generated to the application with Early + * Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). + * If the early suspend is asserted due to an erratic error, the + * application can only perform a soft disconnect recover. + */ +#define USB_OTGFS_DSTS_ERRTICERR (BIT(3)) +#define USB_OTGFS_DSTS_ERRTICERR_M (USB_OTGFS_DSTS_ERRTICERR_V << USB_OTGFS_DSTS_ERRTICERR_S) +#define USB_OTGFS_DSTS_ERRTICERR_V 0x00000001U +#define USB_OTGFS_DSTS_ERRTICERR_S 3 +/** USB_OTGFS_DSTS_SOFFN : RO; bitpos: [21:8]; default: 0; + * Frame or Microframe Number of the Received SOF (SOFFN) + * + * When the core is operating at high speed, this field contains a microframe number. + * When the core is operating at full or low speed, this field contains a Frame number. + * + * Note: This register may return a non-zero value if read immediately after power-on + * reset. + * In case the register bit reads non-zero immediately after power-on reset, it does + * not + * indicate that SOF has been received from the host. The read value of this interrupt + * is + * valid only after a valid connection between host and device is established. + */ +#define USB_OTGFS_DSTS_SOFFN 0x00003FFFU +#define USB_OTGFS_DSTS_SOFFN_M (USB_OTGFS_DSTS_SOFFN_V << USB_OTGFS_DSTS_SOFFN_S) +#define USB_OTGFS_DSTS_SOFFN_V 0x00003FFFU +#define USB_OTGFS_DSTS_SOFFN_S 8 +/** USB_OTGFS_DSTS_DEVLNSTS : RO; bitpos: [23:22]; default: 0; + * Device Line Status (DevLnSts) + * + * Indicates the current logic level USB data lines + * - DevLnSts[1]: Logic level of D+ + * - DevLnSts[0]: Logic level of D- + */ +#define USB_OTGFS_DSTS_DEVLNSTS 0x00000003U +#define USB_OTGFS_DSTS_DEVLNSTS_M (USB_OTGFS_DSTS_DEVLNSTS_V << USB_OTGFS_DSTS_DEVLNSTS_S) +#define USB_OTGFS_DSTS_DEVLNSTS_V 0x00000003U +#define USB_OTGFS_DSTS_DEVLNSTS_S 22 + +/** USB_OTGFS_DIEPMSK_REG register + * Device IN Endpoint Common Interrupt Mask Register This register works with each of + * the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate + * an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in + * the DIEPINTn register can be masked by writing to the corresponding bit in this + * register. Status bits are masked by default. + */ +#define USB_OTGFS_DIEPMSK_REG(i) (DR_REG_USB_BASE(i) + 0x810) +/** USB_OTGFS_DIEPMSK_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt Mask (XferComplMsk) + */ +#define USB_OTGFS_DIEPMSK_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_DIEPMSK_XFERCOMPLMSK_M (USB_OTGFS_DIEPMSK_XFERCOMPLMSK_V << USB_OTGFS_DIEPMSK_XFERCOMPLMSK_S) +#define USB_OTGFS_DIEPMSK_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_XFERCOMPLMSK_S 0 +/** USB_OTGFS_DIEPMSK_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt Mask (EPDisbldMsk) + */ +#define USB_OTGFS_DIEPMSK_EPDISBLDMSK (BIT(1)) +#define USB_OTGFS_DIEPMSK_EPDISBLDMSK_M (USB_OTGFS_DIEPMSK_EPDISBLDMSK_V << USB_OTGFS_DIEPMSK_EPDISBLDMSK_S) +#define USB_OTGFS_DIEPMSK_EPDISBLDMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_EPDISBLDMSK_S 1 +/** USB_OTGFS_DIEPMSK_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * AHB Error Mask (AHBErrMsk) + */ +#define USB_OTGFS_DIEPMSK_AHBERRMSK (BIT(2)) +#define USB_OTGFS_DIEPMSK_AHBERRMSK_M (USB_OTGFS_DIEPMSK_AHBERRMSK_V << USB_OTGFS_DIEPMSK_AHBERRMSK_S) +#define USB_OTGFS_DIEPMSK_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_AHBERRMSK_S 2 +/** USB_OTGFS_DIEPMSK_TIMEOUTMSK : R/W; bitpos: [3]; default: 0; + * Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + */ +#define USB_OTGFS_DIEPMSK_TIMEOUTMSK (BIT(3)) +#define USB_OTGFS_DIEPMSK_TIMEOUTMSK_M (USB_OTGFS_DIEPMSK_TIMEOUTMSK_V << USB_OTGFS_DIEPMSK_TIMEOUTMSK_S) +#define USB_OTGFS_DIEPMSK_TIMEOUTMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_TIMEOUTMSK_S 3 +/** USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK : R/W; bitpos: [4]; default: 0; + * IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + */ +#define USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK (BIT(4)) +#define USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK_M (USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK_V << USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK_S) +#define USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_INTKNTXFEMPMSK_S 4 +/** USB_OTGFS_DIEPMSK_INTKNEPMISMSK : R/W; bitpos: [5]; default: 0; + * IN Token received with EP Mismatch Mask (INTknEPMisMsk) + */ +#define USB_OTGFS_DIEPMSK_INTKNEPMISMSK (BIT(5)) +#define USB_OTGFS_DIEPMSK_INTKNEPMISMSK_M (USB_OTGFS_DIEPMSK_INTKNEPMISMSK_V << USB_OTGFS_DIEPMSK_INTKNEPMISMSK_S) +#define USB_OTGFS_DIEPMSK_INTKNEPMISMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_INTKNEPMISMSK_S 5 +/** USB_OTGFS_DIEPMSK_INEPNAKEFFMSK : R/W; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective Mask (INEPNakEffMsk) + */ +#define USB_OTGFS_DIEPMSK_INEPNAKEFFMSK (BIT(6)) +#define USB_OTGFS_DIEPMSK_INEPNAKEFFMSK_M (USB_OTGFS_DIEPMSK_INEPNAKEFFMSK_V << USB_OTGFS_DIEPMSK_INEPNAKEFFMSK_S) +#define USB_OTGFS_DIEPMSK_INEPNAKEFFMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_INEPNAKEFFMSK_S 6 +/** USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK : R/W; bitpos: [8]; default: 0; + * Fifo Underrun Mask (TxfifoUndrnMsk) + */ +#define USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK (BIT(8)) +#define USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK_M (USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK_V << USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK_S) +#define USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_TXFIFOUNDRNMSK_S 8 +/** USB_OTGFS_DIEPMSK_BNAININTRMSK : R/W; bitpos: [9]; default: 0; + * BNA interrupt Mask (BNAInIntrMsk) + */ +#define USB_OTGFS_DIEPMSK_BNAININTRMSK (BIT(9)) +#define USB_OTGFS_DIEPMSK_BNAININTRMSK_M (USB_OTGFS_DIEPMSK_BNAININTRMSK_V << USB_OTGFS_DIEPMSK_BNAININTRMSK_S) +#define USB_OTGFS_DIEPMSK_BNAININTRMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_BNAININTRMSK_S 9 +/** USB_OTGFS_DIEPMSK_NAKMSK : R/W; bitpos: [13]; default: 0; + * NAK interrupt Mask (NAKMsk) + */ +#define USB_OTGFS_DIEPMSK_NAKMSK (BIT(13)) +#define USB_OTGFS_DIEPMSK_NAKMSK_M (USB_OTGFS_DIEPMSK_NAKMSK_V << USB_OTGFS_DIEPMSK_NAKMSK_S) +#define USB_OTGFS_DIEPMSK_NAKMSK_V 0x00000001U +#define USB_OTGFS_DIEPMSK_NAKMSK_S 13 + +/** USB_OTGFS_DOEPMSK_REG register + * Device OUT Endpoint Common Interrupt Mask Register This register works with each + * of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to + * generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific + * status in the DOEPINTn register can be masked by writing into the corresponding bit + * in this register. Status bits are masked by default. + */ +#define USB_OTGFS_DOEPMSK_REG(i) (DR_REG_USB_BASE(i) + 0x814) +/** USB_OTGFS_DOEPMSK_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt Mask (XferComplMsk) + */ +#define USB_OTGFS_DOEPMSK_XFERCOMPLMSK (BIT(0)) +#define USB_OTGFS_DOEPMSK_XFERCOMPLMSK_M (USB_OTGFS_DOEPMSK_XFERCOMPLMSK_V << USB_OTGFS_DOEPMSK_XFERCOMPLMSK_S) +#define USB_OTGFS_DOEPMSK_XFERCOMPLMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_XFERCOMPLMSK_S 0 +/** USB_OTGFS_DOEPMSK_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt Mask (EPDisbldMsk) + */ +#define USB_OTGFS_DOEPMSK_EPDISBLDMSK (BIT(1)) +#define USB_OTGFS_DOEPMSK_EPDISBLDMSK_M (USB_OTGFS_DOEPMSK_EPDISBLDMSK_V << USB_OTGFS_DOEPMSK_EPDISBLDMSK_S) +#define USB_OTGFS_DOEPMSK_EPDISBLDMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_EPDISBLDMSK_S 1 +/** USB_OTGFS_DOEPMSK_AHBERRMSK : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErrMsk) + */ +#define USB_OTGFS_DOEPMSK_AHBERRMSK (BIT(2)) +#define USB_OTGFS_DOEPMSK_AHBERRMSK_M (USB_OTGFS_DOEPMSK_AHBERRMSK_V << USB_OTGFS_DOEPMSK_AHBERRMSK_S) +#define USB_OTGFS_DOEPMSK_AHBERRMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_AHBERRMSK_S 2 +/** USB_OTGFS_DOEPMSK_SETUPMSK : R/W; bitpos: [3]; default: 0; + * SETUP Phase Done Mask (SetUPMsk) + * + * Applies to control endpoints only. + */ +#define USB_OTGFS_DOEPMSK_SETUPMSK (BIT(3)) +#define USB_OTGFS_DOEPMSK_SETUPMSK_M (USB_OTGFS_DOEPMSK_SETUPMSK_V << USB_OTGFS_DOEPMSK_SETUPMSK_S) +#define USB_OTGFS_DOEPMSK_SETUPMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_SETUPMSK_S 3 +/** USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK : R/W; bitpos: [4]; default: 0; + * OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + * + * Applies to control OUT endpoints only. + */ +#define USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK (BIT(4)) +#define USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK_M (USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK_V << USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK_S) +#define USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_OUTTKNEPDISMSK_S 4 +/** USB_OTGFS_DOEPMSK_STSPHSERCVDMSK : R/W; bitpos: [5]; default: 0; + * Status Phase Received Mask (StsPhseRcvdMsk) + * + * Applies to control OUT endpoints only. + */ +#define USB_OTGFS_DOEPMSK_STSPHSERCVDMSK (BIT(5)) +#define USB_OTGFS_DOEPMSK_STSPHSERCVDMSK_M (USB_OTGFS_DOEPMSK_STSPHSERCVDMSK_V << USB_OTGFS_DOEPMSK_STSPHSERCVDMSK_S) +#define USB_OTGFS_DOEPMSK_STSPHSERCVDMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_STSPHSERCVDMSK_S 5 +/** USB_OTGFS_DOEPMSK_BACK2BACKSETUP : R/W; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + * + * Applies to control OUT endpoints only. + */ +#define USB_OTGFS_DOEPMSK_BACK2BACKSETUP (BIT(6)) +#define USB_OTGFS_DOEPMSK_BACK2BACKSETUP_M (USB_OTGFS_DOEPMSK_BACK2BACKSETUP_V << USB_OTGFS_DOEPMSK_BACK2BACKSETUP_S) +#define USB_OTGFS_DOEPMSK_BACK2BACKSETUP_V 0x00000001U +#define USB_OTGFS_DOEPMSK_BACK2BACKSETUP_S 6 +/** USB_OTGFS_DOEPMSK_OUTPKTERRMSK : R/W; bitpos: [8]; default: 0; + * OUT Packet Error Mask (OutPktErrMsk) + */ +#define USB_OTGFS_DOEPMSK_OUTPKTERRMSK (BIT(8)) +#define USB_OTGFS_DOEPMSK_OUTPKTERRMSK_M (USB_OTGFS_DOEPMSK_OUTPKTERRMSK_V << USB_OTGFS_DOEPMSK_OUTPKTERRMSK_S) +#define USB_OTGFS_DOEPMSK_OUTPKTERRMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_OUTPKTERRMSK_S 8 +/** USB_OTGFS_DOEPMSK_BNAOUTINTRMSK : R/W; bitpos: [9]; default: 0; + * BNA interrupt Mask (BnaOutIntrMsk) + */ +#define USB_OTGFS_DOEPMSK_BNAOUTINTRMSK (BIT(9)) +#define USB_OTGFS_DOEPMSK_BNAOUTINTRMSK_M (USB_OTGFS_DOEPMSK_BNAOUTINTRMSK_V << USB_OTGFS_DOEPMSK_BNAOUTINTRMSK_S) +#define USB_OTGFS_DOEPMSK_BNAOUTINTRMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_BNAOUTINTRMSK_S 9 +/** USB_OTGFS_DOEPMSK_BBLEERRMSK : R/W; bitpos: [12]; default: 0; + * Babble Error interrupt Mask (BbleErrMsk) + */ +#define USB_OTGFS_DOEPMSK_BBLEERRMSK (BIT(12)) +#define USB_OTGFS_DOEPMSK_BBLEERRMSK_M (USB_OTGFS_DOEPMSK_BBLEERRMSK_V << USB_OTGFS_DOEPMSK_BBLEERRMSK_S) +#define USB_OTGFS_DOEPMSK_BBLEERRMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_BBLEERRMSK_S 12 +/** USB_OTGFS_DOEPMSK_NAKMSK : R/W; bitpos: [13]; default: 0; + * NAK interrupt Mask (NAKMsk) + */ +#define USB_OTGFS_DOEPMSK_NAKMSK (BIT(13)) +#define USB_OTGFS_DOEPMSK_NAKMSK_M (USB_OTGFS_DOEPMSK_NAKMSK_V << USB_OTGFS_DOEPMSK_NAKMSK_S) +#define USB_OTGFS_DOEPMSK_NAKMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_NAKMSK_S 13 +/** USB_OTGFS_DOEPMSK_NYETMSK : R/W; bitpos: [14]; default: 0; + * NYET interrupt Mask (NYETMsk) + */ +#define USB_OTGFS_DOEPMSK_NYETMSK (BIT(14)) +#define USB_OTGFS_DOEPMSK_NYETMSK_M (USB_OTGFS_DOEPMSK_NYETMSK_V << USB_OTGFS_DOEPMSK_NYETMSK_S) +#define USB_OTGFS_DOEPMSK_NYETMSK_V 0x00000001U +#define USB_OTGFS_DOEPMSK_NYETMSK_S 14 + +/** USB_OTGFS_DAINT_REG register + * Device All Endpoints Interrupt Register When a significant event occurs on an + * endpoint, a Device All Endpoints Interrupt register interrupts the application + * using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit + * of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). + * This is shown in Figure 5-2. There is one interrupt bit per endpoint, up to a + * maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a + * bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits + * in this register are set and cleared when the application sets and clears bits in + * the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). + */ +#define USB_OTGFS_DAINT_REG(i) (DR_REG_USB_BASE(i) + 0x818) +/** USB_OTGFS_DAINT_INEPINT0 : RO; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT0 (BIT(0)) +#define USB_OTGFS_DAINT_INEPINT0_M (USB_OTGFS_DAINT_INEPINT0_V << USB_OTGFS_DAINT_INEPINT0_S) +#define USB_OTGFS_DAINT_INEPINT0_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT0_S 0 +/** USB_OTGFS_DAINT_INEPINT1 : RO; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT1 (BIT(1)) +#define USB_OTGFS_DAINT_INEPINT1_M (USB_OTGFS_DAINT_INEPINT1_V << USB_OTGFS_DAINT_INEPINT1_S) +#define USB_OTGFS_DAINT_INEPINT1_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT1_S 1 +/** USB_OTGFS_DAINT_INEPINT2 : RO; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT2 (BIT(2)) +#define USB_OTGFS_DAINT_INEPINT2_M (USB_OTGFS_DAINT_INEPINT2_V << USB_OTGFS_DAINT_INEPINT2_S) +#define USB_OTGFS_DAINT_INEPINT2_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT2_S 2 +/** USB_OTGFS_DAINT_INEPINT3 : RO; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT3 (BIT(3)) +#define USB_OTGFS_DAINT_INEPINT3_M (USB_OTGFS_DAINT_INEPINT3_V << USB_OTGFS_DAINT_INEPINT3_S) +#define USB_OTGFS_DAINT_INEPINT3_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT3_S 3 +/** USB_OTGFS_DAINT_INEPINT4 : RO; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT4 (BIT(4)) +#define USB_OTGFS_DAINT_INEPINT4_M (USB_OTGFS_DAINT_INEPINT4_V << USB_OTGFS_DAINT_INEPINT4_S) +#define USB_OTGFS_DAINT_INEPINT4_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT4_S 4 +/** USB_OTGFS_DAINT_INEPINT5 : RO; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT5 (BIT(5)) +#define USB_OTGFS_DAINT_INEPINT5_M (USB_OTGFS_DAINT_INEPINT5_V << USB_OTGFS_DAINT_INEPINT5_S) +#define USB_OTGFS_DAINT_INEPINT5_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT5_S 5 +/** USB_OTGFS_DAINT_INEPINT6 : RO; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt Bit + */ +#define USB_OTGFS_DAINT_INEPINT6 (BIT(6)) +#define USB_OTGFS_DAINT_INEPINT6_M (USB_OTGFS_DAINT_INEPINT6_V << USB_OTGFS_DAINT_INEPINT6_S) +#define USB_OTGFS_DAINT_INEPINT6_V 0x00000001U +#define USB_OTGFS_DAINT_INEPINT6_S 6 +/** USB_OTGFS_DAINT_OUTEPINT0 : RO; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT0 (BIT(16)) +#define USB_OTGFS_DAINT_OUTEPINT0_M (USB_OTGFS_DAINT_OUTEPINT0_V << USB_OTGFS_DAINT_OUTEPINT0_S) +#define USB_OTGFS_DAINT_OUTEPINT0_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT0_S 16 +/** USB_OTGFS_DAINT_OUTEPINT1 : RO; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT1 (BIT(17)) +#define USB_OTGFS_DAINT_OUTEPINT1_M (USB_OTGFS_DAINT_OUTEPINT1_V << USB_OTGFS_DAINT_OUTEPINT1_S) +#define USB_OTGFS_DAINT_OUTEPINT1_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT1_S 17 +/** USB_OTGFS_DAINT_OUTEPINT2 : RO; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT2 (BIT(18)) +#define USB_OTGFS_DAINT_OUTEPINT2_M (USB_OTGFS_DAINT_OUTEPINT2_V << USB_OTGFS_DAINT_OUTEPINT2_S) +#define USB_OTGFS_DAINT_OUTEPINT2_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT2_S 18 +/** USB_OTGFS_DAINT_OUTEPINT3 : RO; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT3 (BIT(19)) +#define USB_OTGFS_DAINT_OUTEPINT3_M (USB_OTGFS_DAINT_OUTEPINT3_V << USB_OTGFS_DAINT_OUTEPINT3_S) +#define USB_OTGFS_DAINT_OUTEPINT3_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT3_S 19 +/** USB_OTGFS_DAINT_OUTEPINT4 : RO; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT4 (BIT(20)) +#define USB_OTGFS_DAINT_OUTEPINT4_M (USB_OTGFS_DAINT_OUTEPINT4_V << USB_OTGFS_DAINT_OUTEPINT4_S) +#define USB_OTGFS_DAINT_OUTEPINT4_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT4_S 20 +/** USB_OTGFS_DAINT_OUTEPINT5 : RO; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT5 (BIT(21)) +#define USB_OTGFS_DAINT_OUTEPINT5_M (USB_OTGFS_DAINT_OUTEPINT5_V << USB_OTGFS_DAINT_OUTEPINT5_S) +#define USB_OTGFS_DAINT_OUTEPINT5_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT5_S 21 +/** USB_OTGFS_DAINT_OUTEPINT6 : RO; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt Bit + */ +#define USB_OTGFS_DAINT_OUTEPINT6 (BIT(22)) +#define USB_OTGFS_DAINT_OUTEPINT6_M (USB_OTGFS_DAINT_OUTEPINT6_V << USB_OTGFS_DAINT_OUTEPINT6_S) +#define USB_OTGFS_DAINT_OUTEPINT6_V 0x00000001U +#define USB_OTGFS_DAINT_OUTEPINT6_S 22 + +/** USB_OTGFS_DAINTMSK_REG register + * Device All Endpoints Interrupt Mask Register The Device Endpoint Interrupt Mask + * register works with the Device Endpoint Interrupt register to interrupt the + * application when an event occurs on a device endpoint. However, the Device All + * Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still + * set. + */ +#define USB_OTGFS_DAINTMSK_REG(i) (DR_REG_USB_BASE(i) + 0x81c) +/** USB_OTGFS_DAINTMSK_INEPMSK0 : R/W; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK0 (BIT(0)) +#define USB_OTGFS_DAINTMSK_INEPMSK0_M (USB_OTGFS_DAINTMSK_INEPMSK0_V << USB_OTGFS_DAINTMSK_INEPMSK0_S) +#define USB_OTGFS_DAINTMSK_INEPMSK0_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK0_S 0 +/** USB_OTGFS_DAINTMSK_INEPMSK1 : R/W; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK1 (BIT(1)) +#define USB_OTGFS_DAINTMSK_INEPMSK1_M (USB_OTGFS_DAINTMSK_INEPMSK1_V << USB_OTGFS_DAINTMSK_INEPMSK1_S) +#define USB_OTGFS_DAINTMSK_INEPMSK1_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK1_S 1 +/** USB_OTGFS_DAINTMSK_INEPMSK2 : R/W; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK2 (BIT(2)) +#define USB_OTGFS_DAINTMSK_INEPMSK2_M (USB_OTGFS_DAINTMSK_INEPMSK2_V << USB_OTGFS_DAINTMSK_INEPMSK2_S) +#define USB_OTGFS_DAINTMSK_INEPMSK2_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK2_S 2 +/** USB_OTGFS_DAINTMSK_INEPMSK3 : R/W; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK3 (BIT(3)) +#define USB_OTGFS_DAINTMSK_INEPMSK3_M (USB_OTGFS_DAINTMSK_INEPMSK3_V << USB_OTGFS_DAINTMSK_INEPMSK3_S) +#define USB_OTGFS_DAINTMSK_INEPMSK3_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK3_S 3 +/** USB_OTGFS_DAINTMSK_INEPMSK4 : R/W; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK4 (BIT(4)) +#define USB_OTGFS_DAINTMSK_INEPMSK4_M (USB_OTGFS_DAINTMSK_INEPMSK4_V << USB_OTGFS_DAINTMSK_INEPMSK4_S) +#define USB_OTGFS_DAINTMSK_INEPMSK4_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK4_S 4 +/** USB_OTGFS_DAINTMSK_INEPMSK5 : R/W; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK5 (BIT(5)) +#define USB_OTGFS_DAINTMSK_INEPMSK5_M (USB_OTGFS_DAINTMSK_INEPMSK5_V << USB_OTGFS_DAINTMSK_INEPMSK5_S) +#define USB_OTGFS_DAINTMSK_INEPMSK5_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK5_S 5 +/** USB_OTGFS_DAINTMSK_INEPMSK6 : R/W; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_INEPMSK6 (BIT(6)) +#define USB_OTGFS_DAINTMSK_INEPMSK6_M (USB_OTGFS_DAINTMSK_INEPMSK6_V << USB_OTGFS_DAINTMSK_INEPMSK6_S) +#define USB_OTGFS_DAINTMSK_INEPMSK6_V 0x00000001U +#define USB_OTGFS_DAINTMSK_INEPMSK6_S 6 +/** USB_OTGFS_DAINTMSK_OUTEPMSK0 : R/W; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK0 (BIT(16)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK0_M (USB_OTGFS_DAINTMSK_OUTEPMSK0_V << USB_OTGFS_DAINTMSK_OUTEPMSK0_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK0_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK0_S 16 +/** USB_OTGFS_DAINTMSK_OUTEPMSK1 : R/W; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK1 (BIT(17)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK1_M (USB_OTGFS_DAINTMSK_OUTEPMSK1_V << USB_OTGFS_DAINTMSK_OUTEPMSK1_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK1_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK1_S 17 +/** USB_OTGFS_DAINTMSK_OUTEPMSK2 : R/W; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK2 (BIT(18)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK2_M (USB_OTGFS_DAINTMSK_OUTEPMSK2_V << USB_OTGFS_DAINTMSK_OUTEPMSK2_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK2_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK2_S 18 +/** USB_OTGFS_DAINTMSK_OUTEPMSK3 : R/W; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK3 (BIT(19)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK3_M (USB_OTGFS_DAINTMSK_OUTEPMSK3_V << USB_OTGFS_DAINTMSK_OUTEPMSK3_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK3_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK3_S 19 +/** USB_OTGFS_DAINTMSK_OUTEPMSK4 : R/W; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK4 (BIT(20)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK4_M (USB_OTGFS_DAINTMSK_OUTEPMSK4_V << USB_OTGFS_DAINTMSK_OUTEPMSK4_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK4_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK4_S 20 +/** USB_OTGFS_DAINTMSK_OUTEPMSK5 : R/W; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK5 (BIT(21)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK5_M (USB_OTGFS_DAINTMSK_OUTEPMSK5_V << USB_OTGFS_DAINTMSK_OUTEPMSK5_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK5_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK5_S 21 +/** USB_OTGFS_DAINTMSK_OUTEPMSK6 : R/W; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt mask Bit + */ +#define USB_OTGFS_DAINTMSK_OUTEPMSK6 (BIT(22)) +#define USB_OTGFS_DAINTMSK_OUTEPMSK6_M (USB_OTGFS_DAINTMSK_OUTEPMSK6_V << USB_OTGFS_DAINTMSK_OUTEPMSK6_S) +#define USB_OTGFS_DAINTMSK_OUTEPMSK6_V 0x00000001U +#define USB_OTGFS_DAINTMSK_OUTEPMSK6_S 22 + +/** USB_OTGFS_DVBUSDIS_REG register + * Device VBUS Discharge Time Register This register specifies the VBUS discharge + * time after VBUS pulsing during SRP. + */ +#define USB_OTGFS_DVBUSDIS_REG(i) (DR_REG_USB_BASE(i) + 0x828) +/** USB_OTGFS_DVBUSDIS_DVBUSDIS : R/W; bitpos: [15:0]; default: 6103; + * Device VBUS Discharge Time (DVBUSDis) + * + * Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals + * (VBUS discharge time in PHY clocks) / 1, 024. + * + * The value you use depends whether the PHY is operating at 30MHz (16-bit data width) + * or 60 MHz (8-bit data width). + * + * Depending on your VBUS load, this value can need adjustment. + */ +#define USB_OTGFS_DVBUSDIS_DVBUSDIS 0x0000FFFFU +#define USB_OTGFS_DVBUSDIS_DVBUSDIS_M (USB_OTGFS_DVBUSDIS_DVBUSDIS_V << USB_OTGFS_DVBUSDIS_DVBUSDIS_S) +#define USB_OTGFS_DVBUSDIS_DVBUSDIS_V 0x0000FFFFU +#define USB_OTGFS_DVBUSDIS_DVBUSDIS_S 0 + +/** USB_OTGFS_DVBUSPULSE_REG register + * Device VBUS Pulsing Time Register + */ +#define USB_OTGFS_DVBUSPULSE_REG(i) (DR_REG_USB_BASE(i) + 0x82c) +/** USB_OTGFS_DVBUSPULSE_DVBUSPULSE : R/W; bitpos: [11:0]; default: 1464; + * Device VBUS Pulsing Time (DVBUSPulse) + * + * Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in + * PHY clocks) / 1, 024 + * + * The value you use depends whether the PHY is operating at 30MHz (16-bit data width) + * or 60 MHz (8-bit data width). + */ +#define USB_OTGFS_DVBUSPULSE_DVBUSPULSE 0x00000FFFU +#define USB_OTGFS_DVBUSPULSE_DVBUSPULSE_M (USB_OTGFS_DVBUSPULSE_DVBUSPULSE_V << USB_OTGFS_DVBUSPULSE_DVBUSPULSE_S) +#define USB_OTGFS_DVBUSPULSE_DVBUSPULSE_V 0x00000FFFU +#define USB_OTGFS_DVBUSPULSE_DVBUSPULSE_S 0 + +/** USB_OTGFS_DTHRCTL_REG register + * Device Threshold Control Register + */ +#define USB_OTGFS_DTHRCTL_REG(i) (DR_REG_USB_BASE(i) + 0x830) +/** USB_OTGFS_DTHRCTL_NONISOTHREN : R/W; bitpos: [0]; default: 0; + * Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + * + * When this bit is Set, the core enables thresholding for Non Isochronous IN + * endpoints. + */ +#define USB_OTGFS_DTHRCTL_NONISOTHREN (BIT(0)) +#define USB_OTGFS_DTHRCTL_NONISOTHREN_M (USB_OTGFS_DTHRCTL_NONISOTHREN_V << USB_OTGFS_DTHRCTL_NONISOTHREN_S) +#define USB_OTGFS_DTHRCTL_NONISOTHREN_V 0x00000001U +#define USB_OTGFS_DTHRCTL_NONISOTHREN_S 0 +/** USB_OTGFS_DTHRCTL_ISOTHREN : R/W; bitpos: [1]; default: 0; + * + * ISO IN Endpoints Threshold Enable. (ISOThrEn) + * + * When this bit is Set, the core enables thresholding for isochronous IN + * endpoints. + */ +#define USB_OTGFS_DTHRCTL_ISOTHREN (BIT(1)) +#define USB_OTGFS_DTHRCTL_ISOTHREN_M (USB_OTGFS_DTHRCTL_ISOTHREN_V << USB_OTGFS_DTHRCTL_ISOTHREN_S) +#define USB_OTGFS_DTHRCTL_ISOTHREN_V 0x00000001U +#define USB_OTGFS_DTHRCTL_ISOTHREN_S 1 +/** USB_OTGFS_DTHRCTL_TXTHRLEN : R/W; bitpos: [10:2]; default: 8; + * Transmit Threshold Length (TxThrLen) + * + * This field specifies Transmit thresholding size in DWORDS. This also forms + * the MAC threshold and specifies the amount of data in bytes to be in the + * corresponding endpoint transmit FIFO, before the core can start transmit + * on the USB. The threshold length has to be at least eight DWORDS when the + * value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the + * application needs to ensure that the AHB Threshold value does not go below + * the recommended eight DWORD. This field controls both isochronous and + * non-isochronous IN endpoint thresholds. The recommended value for ThrLen + * is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen). + * + * Note: + * - When OTG_ARCHITECTURE=0, the reset value of this register field is 0. + * - When OTG_ARCHITECTURE=2, the reset value of this register field is 8. + */ +#define USB_OTGFS_DTHRCTL_TXTHRLEN 0x000001FFU +#define USB_OTGFS_DTHRCTL_TXTHRLEN_M (USB_OTGFS_DTHRCTL_TXTHRLEN_V << USB_OTGFS_DTHRCTL_TXTHRLEN_S) +#define USB_OTGFS_DTHRCTL_TXTHRLEN_V 0x000001FFU +#define USB_OTGFS_DTHRCTL_TXTHRLEN_S 2 +/** USB_OTGFS_DTHRCTL_AHBTHRRATIO : R/W; bitpos: [12:11]; default: 0; + * AHB Threshold Ratio (AHBThrRatio) + * + * These bits define the ratio between the AHB threshold and the MAC threshold for the + * transmit path only. The AHB threshold always remains less than or equal to the USB + * threshold, because this does not increase overhead. Both the AHB and the MAC + * threshold must be DWORD-aligned. The application needs to program TxThrLen and the + * AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold + * value is not DWORD aligned, the core might not behave correctly. When programming + * the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB + * threshold value does not go below 8 DWORDS to meet the USB turnaround time + * requirements. + * - 2'b00: AHB threshold = MAC threshold + * - 2'b01: AHB threshold = MAC threshold / 2 + * - 2'b10: AHB threshold = MAC threshold / 4 + * - 2'b11: AHB threshold = MAC threshold / 8 + */ +#define USB_OTGFS_DTHRCTL_AHBTHRRATIO 0x00000003U +#define USB_OTGFS_DTHRCTL_AHBTHRRATIO_M (USB_OTGFS_DTHRCTL_AHBTHRRATIO_V << USB_OTGFS_DTHRCTL_AHBTHRRATIO_S) +#define USB_OTGFS_DTHRCTL_AHBTHRRATIO_V 0x00000003U +#define USB_OTGFS_DTHRCTL_AHBTHRRATIO_S 11 +/** USB_OTGFS_DTHRCTL_RXTHREN : R/W; bitpos: [16]; default: 0; + * Receive Threshold Enable (RxThrEn) + * + * When this bit is set, the core enables thresholding in the receive direction. + * + * Note: We recommends that you do not enable RxThrEn, because it may cause issues in + * the RxFIFO especially during error conditions such as RxError and Babble. + */ +#define USB_OTGFS_DTHRCTL_RXTHREN (BIT(16)) +#define USB_OTGFS_DTHRCTL_RXTHREN_M (USB_OTGFS_DTHRCTL_RXTHREN_V << USB_OTGFS_DTHRCTL_RXTHREN_S) +#define USB_OTGFS_DTHRCTL_RXTHREN_V 0x00000001U +#define USB_OTGFS_DTHRCTL_RXTHREN_S 16 +/** USB_OTGFS_DTHRCTL_RXTHRLEN : R/W; bitpos: [25:17]; default: 8; + * Receive Threshold Length (RxThrLen) + * + * This field specifies Receive thresholding size in DWORDS. + * This field also specifies the amount of data received on the USB before the core + * can start transmitting on the AHB. + * The threshold length has to be at least eight DWORDS. + * The recommended value for ThrLen is to be the same as the programmed + * AHB Burst Length (GAHBCFG.HBstLen). + */ +#define USB_OTGFS_DTHRCTL_RXTHRLEN 0x000001FFU +#define USB_OTGFS_DTHRCTL_RXTHRLEN_M (USB_OTGFS_DTHRCTL_RXTHRLEN_V << USB_OTGFS_DTHRCTL_RXTHRLEN_S) +#define USB_OTGFS_DTHRCTL_RXTHRLEN_V 0x000001FFU +#define USB_OTGFS_DTHRCTL_RXTHRLEN_S 17 +/** USB_OTGFS_DTHRCTL_ARBPRKEN : R/W; bitpos: [27]; default: 1; + * Arbiter Parking Enable (ArbPrkEn) + * + * This bit controls internal DMA arbiter parking for IN endpoints. If thresholding is + * enabled and this bit is set to one, then the arbiter parks on the IN endpoint for + * which there is a token received on the USB. This is done to avoid getting into + * underrun conditions. By default, arbiter parking is enabled. + */ +#define USB_OTGFS_DTHRCTL_ARBPRKEN (BIT(27)) +#define USB_OTGFS_DTHRCTL_ARBPRKEN_M (USB_OTGFS_DTHRCTL_ARBPRKEN_V << USB_OTGFS_DTHRCTL_ARBPRKEN_S) +#define USB_OTGFS_DTHRCTL_ARBPRKEN_V 0x00000001U +#define USB_OTGFS_DTHRCTL_ARBPRKEN_S 27 + +/** USB_OTGFS_DIEPEMPMSK_REG register + * Device IN Endpoint FIFO Empty Interrupt Mask Register This register is valid only + * in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to + * control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp). + */ +#define USB_OTGFS_DIEPEMPMSK_REG(i) (DR_REG_USB_BASE(i) + 0x834) +/** USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK : R/W; bitpos: [15:0]; default: 0; + * IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + * + * These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint: + * + * Bit 0 for IN EP 0, bit 15 for IN EP 15 + */ +#define USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK 0x0000FFFFU +#define USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK_M (USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK_V << USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK_S) +#define USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK_V 0x0000FFFFU +#define USB_OTGFS_DIEPEMPMSK_INEPTXFEMPMSK_S 0 + +/** USB_OTGFS_DIEPCTL0_REG register + * Device Control IN Endpoint 0 Control Register + */ +#define USB_OTGFS_DIEPCTL0_REG(i) (DR_REG_USB_BASE(i) + 0x900) +/** USB_OTGFS_DIEPCTL0_MPS : R/W; bitpos: [1:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Applies to IN and OUT endpoints. + * + * The application must program this field with the maximum packet size for the + * current logical endpoint. + * - 2'b00: 64 bytes + * - 2'b01: 32 bytes + * - 2'b10: 16 bytes + * - 2'b11: 8 bytes + */ +#define USB_OTGFS_DIEPCTL0_MPS 0x00000003U +#define USB_OTGFS_DIEPCTL0_MPS_M (USB_OTGFS_DIEPCTL0_MPS_V << USB_OTGFS_DIEPCTL0_MPS_S) +#define USB_OTGFS_DIEPCTL0_MPS_V 0x00000003U +#define USB_OTGFS_DIEPCTL0_MPS_S 0 +/** USB_OTGFS_DIEPCTL0_USBACTEP : RO; bitpos: [15]; default: 1; + * USB Active Endpoint (USBActEP) + * + * This bit is always SET to 1, indicating that control endpoint 0 is always active in + * all configurations and interfaces. + */ +#define USB_OTGFS_DIEPCTL0_USBACTEP (BIT(15)) +#define USB_OTGFS_DIEPCTL0_USBACTEP_M (USB_OTGFS_DIEPCTL0_USBACTEP_V << USB_OTGFS_DIEPCTL0_USBACTEP_S) +#define USB_OTGFS_DIEPCTL0_USBACTEP_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_USBACTEP_S 15 +/** USB_OTGFS_DIEPCTL0_NAKSTS : RO; bitpos: [17]; default: 0; + * NAK Status (NAKSts) + * + * Indicates the following: + * - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status + * - 1'b1: The core is transmitting NAK handshakes on this endpoint. + * When this bit is set, either by the application or core, the core stops + * transmitting data, even If there is data available in the TxFIFO. + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + */ +#define USB_OTGFS_DIEPCTL0_NAKSTS (BIT(17)) +#define USB_OTGFS_DIEPCTL0_NAKSTS_M (USB_OTGFS_DIEPCTL0_NAKSTS_V << USB_OTGFS_DIEPCTL0_NAKSTS_S) +#define USB_OTGFS_DIEPCTL0_NAKSTS_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_NAKSTS_S 17 +/** USB_OTGFS_DIEPCTL0_EPTYPE : RO; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Hardcoded to 00 for control. + */ +#define USB_OTGFS_DIEPCTL0_EPTYPE 0x00000003U +#define USB_OTGFS_DIEPCTL0_EPTYPE_M (USB_OTGFS_DIEPCTL0_EPTYPE_V << USB_OTGFS_DIEPCTL0_EPTYPE_S) +#define USB_OTGFS_DIEPCTL0_EPTYPE_V 0x00000003U +#define USB_OTGFS_DIEPCTL0_EPTYPE_S 18 +/** USB_OTGFS_DIEPCTL0_STALL : R/W; bitpos: [21]; default: 0; + * STALL Handshake (Stall) + * + * The application can only set this bit, and the core clears it, when a + * SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic + * IN NAK, or Global OUT NAK is set along with this bit, the STALL + * bit takes priority. + */ +#define USB_OTGFS_DIEPCTL0_STALL (BIT(21)) +#define USB_OTGFS_DIEPCTL0_STALL_M (USB_OTGFS_DIEPCTL0_STALL_V << USB_OTGFS_DIEPCTL0_STALL_S) +#define USB_OTGFS_DIEPCTL0_STALL_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_STALL_S 21 +/** USB_OTGFS_DIEPCTL0_TXFNUM : R/W; bitpos: [25:22]; default: 0; + * TxFIFO Number (TxFNum) + * - For Shared FIFO operation, this value is always set to 0, indicating that control + * IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO. + * - For Dedicated FIFO operation, this value is set to the FIFO number that is + * assigned to IN Endpoint. + */ +#define USB_OTGFS_DIEPCTL0_TXFNUM 0x0000000FU +#define USB_OTGFS_DIEPCTL0_TXFNUM_M (USB_OTGFS_DIEPCTL0_TXFNUM_V << USB_OTGFS_DIEPCTL0_TXFNUM_S) +#define USB_OTGFS_DIEPCTL0_TXFNUM_V 0x0000000FU +#define USB_OTGFS_DIEPCTL0_TXFNUM_S 22 +/** USB_OTGFS_DIEPCTL0_CNAK : R/W; bitpos: [26]; default: 0; + * + * Clear NAK (CNAK) + * A write to this bit clears the NAK bit for the endpoint. + */ +#define USB_OTGFS_DIEPCTL0_CNAK (BIT(26)) +#define USB_OTGFS_DIEPCTL0_CNAK_M (USB_OTGFS_DIEPCTL0_CNAK_V << USB_OTGFS_DIEPCTL0_CNAK_S) +#define USB_OTGFS_DIEPCTL0_CNAK_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_CNAK_S 26 +/** USB_OTGFS_DIEPCTL0_SNAK : R/W; bitpos: [27]; default: 0; + * + * Set NAK (SNAK) + * A write to this bit sets the NAK bit for the endpoint. + * Using this bit, the application can control the transmission of NAK + * handshakes on an endpoint. The core can also set this bit for an + * endpoint after a SETUP packet is received on that endpoint. + */ +#define USB_OTGFS_DIEPCTL0_SNAK (BIT(27)) +#define USB_OTGFS_DIEPCTL0_SNAK_M (USB_OTGFS_DIEPCTL0_SNAK_V << USB_OTGFS_DIEPCTL0_SNAK_S) +#define USB_OTGFS_DIEPCTL0_SNAK_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_SNAK_S 27 +/** USB_OTGFS_DIEPCTL0_EPDIS : R/W; bitpos: [30]; default: 0; + * Endpoint Disable (EPDis) + * + * The application sets this bit to stop transmitting data on an endpoint, + * even before the transfer for that endpoint is complete. The application + * must wait for the Endpoint Disabled interrupt before treating the endpoint + * as disabled. The core clears this bit before setting the Endpoint Disabled + * Interrupt. The application must Set this bit only if Endpoint Enable is + * already set for this endpoint. + */ +#define USB_OTGFS_DIEPCTL0_EPDIS (BIT(30)) +#define USB_OTGFS_DIEPCTL0_EPDIS_M (USB_OTGFS_DIEPCTL0_EPDIS_V << USB_OTGFS_DIEPCTL0_EPDIS_S) +#define USB_OTGFS_DIEPCTL0_EPDIS_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_EPDIS_S 30 +/** USB_OTGFS_DIEPCTL0_EPENA : R/W; bitpos: [31]; default: 0; + * Endpoint Enable (EPEna) + * + * When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that + * the descriptor structure and data buffer with data ready to transmit is setup. + * + * When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) + * this bit indicates that data is ready to be transmitted on the endpoint. + * The core clears this bit before setting the following interrupts on this endpoint: + * - Endpoint Disabled + * - Transfer Completed + */ +#define USB_OTGFS_DIEPCTL0_EPENA (BIT(31)) +#define USB_OTGFS_DIEPCTL0_EPENA_M (USB_OTGFS_DIEPCTL0_EPENA_V << USB_OTGFS_DIEPCTL0_EPENA_S) +#define USB_OTGFS_DIEPCTL0_EPENA_V 0x00000001U +#define USB_OTGFS_DIEPCTL0_EPENA_S 31 + +/** USB_OTGFS_DIEPINT0_REG register + * Device IN Endpoint 0 Interrupt Register This register indicates the status of an + * endpoint with respect to USB- and AHB-related events. It is shown in the Interrupt + * Hierarchy figure in the databook. The application must read this register when the + * OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt + * register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the + * application can read this register, it must first read the Device All Endpoints + * Interrupt (DAINT) register to get the exact endpoint number for the Device + * Endpoint-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the DAINT and GINTSTS registers + */ +#define USB_OTGFS_DIEPINT0_REG(i) (DR_REG_USB_BASE(i) + 0x908) +/** USB_OTGFS_DIEPINT0_XFERCOMPL : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt (XferCompl) + * + * Applies to IN and OUT endpoints. + * - When Scatter/Gather DMA mode is enabled + * -- For IN endpoint this field indicates that the requested data from the descriptor + * is moved from external system memory to internal FIFO. + * -- For OUT endpoint this field indicates that the requested data from the internal + * FIFO is moved to external system memory. This interrupt is generated only when the + * corresponding endpoint descriptor is closed, and the IOC bit for the corresponding + * descriptor is set. + * - When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + */ +#define USB_OTGFS_DIEPINT0_XFERCOMPL (BIT(0)) +#define USB_OTGFS_DIEPINT0_XFERCOMPL_M (USB_OTGFS_DIEPINT0_XFERCOMPL_V << USB_OTGFS_DIEPINT0_XFERCOMPL_S) +#define USB_OTGFS_DIEPINT0_XFERCOMPL_V 0x00000001U +#define USB_OTGFS_DIEPINT0_XFERCOMPL_S 0 +/** USB_OTGFS_DIEPINT0_EPDISBLD : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt (EPDisbld) + * + * Applies to IN and OUT endpoints. + * + * This bit indicates that the endpoint is disabled per the application's request. + */ +#define USB_OTGFS_DIEPINT0_EPDISBLD (BIT(1)) +#define USB_OTGFS_DIEPINT0_EPDISBLD_M (USB_OTGFS_DIEPINT0_EPDISBLD_V << USB_OTGFS_DIEPINT0_EPDISBLD_S) +#define USB_OTGFS_DIEPINT0_EPDISBLD_V 0x00000001U +#define USB_OTGFS_DIEPINT0_EPDISBLD_S 1 +/** USB_OTGFS_DIEPINT0_AHBERR : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * Applies to IN and OUT endpoints. + * + * This is generated only in Internal DMA mode when there is an AHB error during an + * AHB read/write. The application can read the corresponding endpoint DMA address + * register to get the error address. + */ +#define USB_OTGFS_DIEPINT0_AHBERR (BIT(2)) +#define USB_OTGFS_DIEPINT0_AHBERR_M (USB_OTGFS_DIEPINT0_AHBERR_V << USB_OTGFS_DIEPINT0_AHBERR_S) +#define USB_OTGFS_DIEPINT0_AHBERR_V 0x00000001U +#define USB_OTGFS_DIEPINT0_AHBERR_S 2 +/** USB_OTGFS_DIEPINT0_TIMEOUT : R/W; bitpos: [3]; default: 0; + * Timeout Condition (TimeOUT) + * - In shared TX FIFO mode, applies to non-isochronous IN endpoints only. + * - In dedicated FIFO mode, applies only to Control IN endpoints. + * - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted. + * Indicates that the core has detected a timeout condition on the USB for the last IN + * token on this endpoint. + */ +#define USB_OTGFS_DIEPINT0_TIMEOUT (BIT(3)) +#define USB_OTGFS_DIEPINT0_TIMEOUT_M (USB_OTGFS_DIEPINT0_TIMEOUT_V << USB_OTGFS_DIEPINT0_TIMEOUT_S) +#define USB_OTGFS_DIEPINT0_TIMEOUT_V 0x00000001U +#define USB_OTGFS_DIEPINT0_TIMEOUT_S 3 +/** USB_OTGFS_DIEPINT0_INTKNTXFEMP : R/W; bitpos: [4]; default: 0; + * IN Token Received When TxFIFO is Empty (INTknTXFEmp) + * + * Applies to non-periodic IN endpoints only. + * + * Indicates that an IN token was received when the associated TxFIFO + * (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for + * which the IN token was received. + */ +#define USB_OTGFS_DIEPINT0_INTKNTXFEMP (BIT(4)) +#define USB_OTGFS_DIEPINT0_INTKNTXFEMP_M (USB_OTGFS_DIEPINT0_INTKNTXFEMP_V << USB_OTGFS_DIEPINT0_INTKNTXFEMP_S) +#define USB_OTGFS_DIEPINT0_INTKNTXFEMP_V 0x00000001U +#define USB_OTGFS_DIEPINT0_INTKNTXFEMP_S 4 +/** USB_OTGFS_DIEPINT0_INTKNEPMIS : R/W; bitpos: [5]; default: 0; + * IN Token Received with EP Mismatch (INTknEPMis) + * + * Applies to non-periodic IN endpoints only. + * + * Indicates that the data in the top of the non-periodic TxFIFO belongs to an + * endpoint other than the one for which the IN token was received. This interrupt is + * asserted on the endpoint for which the IN token was received. + */ +#define USB_OTGFS_DIEPINT0_INTKNEPMIS (BIT(5)) +#define USB_OTGFS_DIEPINT0_INTKNEPMIS_M (USB_OTGFS_DIEPINT0_INTKNEPMIS_V << USB_OTGFS_DIEPINT0_INTKNEPMIS_S) +#define USB_OTGFS_DIEPINT0_INTKNEPMIS_V 0x00000001U +#define USB_OTGFS_DIEPINT0_INTKNEPMIS_S 5 +/** USB_OTGFS_DIEPINT0_INEPNAKEFF : R/W; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective (INEPNakEff) + * + * Applies to periodic IN endpoints only. + * + * This bit can be cleared when the application clears the IN endpoint NAK by writing + * to DIEPCTLn.CNAK. + * + * This interrupt indicates that the core has sampled the NAK bit + * + * Set (either by the application or by the core). + * + * The interrupt indicates that the IN endpoint NAK bit Set by the application has + * taken effect in the core. + * + * This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL + * bit takes priority over a NAK bit. + */ +#define USB_OTGFS_DIEPINT0_INEPNAKEFF (BIT(6)) +#define USB_OTGFS_DIEPINT0_INEPNAKEFF_M (USB_OTGFS_DIEPINT0_INEPNAKEFF_V << USB_OTGFS_DIEPINT0_INEPNAKEFF_S) +#define USB_OTGFS_DIEPINT0_INEPNAKEFF_V 0x00000001U +#define USB_OTGFS_DIEPINT0_INEPNAKEFF_S 6 +/** USB_OTGFS_DIEPINT0_TXFEMP : RO; bitpos: [7]; default: 1; + * Transmit FIFO Empty (TxFEmp) + * + * This bit is valid only for IN Endpoints + * + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty. The half or completely empty status is determined by the TxFIFO + * Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + */ +#define USB_OTGFS_DIEPINT0_TXFEMP (BIT(7)) +#define USB_OTGFS_DIEPINT0_TXFEMP_M (USB_OTGFS_DIEPINT0_TXFEMP_V << USB_OTGFS_DIEPINT0_TXFEMP_S) +#define USB_OTGFS_DIEPINT0_TXFEMP_V 0x00000001U +#define USB_OTGFS_DIEPINT0_TXFEMP_S 7 +/** USB_OTGFS_DIEPINT0_TXFIFOUNDRN : R/W; bitpos: [8]; default: 0; + * Fifo Underrun (TxfifoUndrn) + * + * Applies to IN endpoints only. + * + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint. + */ +#define USB_OTGFS_DIEPINT0_TXFIFOUNDRN (BIT(8)) +#define USB_OTGFS_DIEPINT0_TXFIFOUNDRN_M (USB_OTGFS_DIEPINT0_TXFIFOUNDRN_V << USB_OTGFS_DIEPINT0_TXFIFOUNDRN_S) +#define USB_OTGFS_DIEPINT0_TXFIFOUNDRN_V 0x00000001U +#define USB_OTGFS_DIEPINT0_TXFIFOUNDRN_S 8 +/** USB_OTGFS_DIEPINT0_BNAINTR : R/W; bitpos: [9]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done. + */ +#define USB_OTGFS_DIEPINT0_BNAINTR (BIT(9)) +#define USB_OTGFS_DIEPINT0_BNAINTR_M (USB_OTGFS_DIEPINT0_BNAINTR_V << USB_OTGFS_DIEPINT0_BNAINTR_S) +#define USB_OTGFS_DIEPINT0_BNAINTR_V 0x00000001U +#define USB_OTGFS_DIEPINT0_BNAINTR_S 9 +/** USB_OTGFS_DIEPINT0_PKTDRPSTS : R/W; bitpos: [11]; default: 0; + * Packet Drop Status (PktDrpSts) + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an interrupt. + * + * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer + * interrupt feature is selected. + */ +#define USB_OTGFS_DIEPINT0_PKTDRPSTS (BIT(11)) +#define USB_OTGFS_DIEPINT0_PKTDRPSTS_M (USB_OTGFS_DIEPINT0_PKTDRPSTS_V << USB_OTGFS_DIEPINT0_PKTDRPSTS_S) +#define USB_OTGFS_DIEPINT0_PKTDRPSTS_V 0x00000001U +#define USB_OTGFS_DIEPINT0_PKTDRPSTS_S 11 +/** USB_OTGFS_DIEPINT0_BBLEERR : R/W; bitpos: [12]; default: 0; + * NAK Interrupt (BbleErr) + * + * The core generates this interrupt when babble is received for the endpoint. + */ +#define USB_OTGFS_DIEPINT0_BBLEERR (BIT(12)) +#define USB_OTGFS_DIEPINT0_BBLEERR_M (USB_OTGFS_DIEPINT0_BBLEERR_V << USB_OTGFS_DIEPINT0_BBLEERR_S) +#define USB_OTGFS_DIEPINT0_BBLEERR_V 0x00000001U +#define USB_OTGFS_DIEPINT0_BBLEERR_S 12 +/** USB_OTGFS_DIEPINT0_NAKINTRPT : R/W; bitpos: [13]; default: 0; + * NAK Interrupt (NAKInterrupt) + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. + * +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: OTG Control and Status Register */ +/** Type of otgfs_gotgctl register + * OTG Control and Status Register The OTG Control and Status register controls the + * behavior and reflects the status of the OTG function of the controller. + */ +typedef union { + struct { + /** otgfs_gotgctl_sesreqscs : RO; bitpos: [0]; default: 0; + * Mode: Device only + * Session Request Success (SesReqScs) + * The core sets this bit when a session request initiation is successful. + * - 1'b0: Session request failure + * - 1'b1: Session request success + */ + uint32_t otgfs_gotgctl_sesreqscs:1; + /** otgfs_gotgctl_sesreq : R/W; bitpos: [1]; default: 0; + * Mode: Device only + * Session Request (SesReq) + * The application sets this bit to initiate a session request on the USB. The + * application can clear this bit by writing a 0 when the Host Negotiation Success + * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. + * The core clears this bit when the HstNegSucStsChng bit is cleared. + * If you use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the + * session request, the application must wait until the VBUS discharges to 0.2 V, + * after the B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This + * discharge time varies between different PHYs and can be obtained from the PHY + * vendor. + * - 1'b0: No session request + * - 1'b1: Session request + */ + uint32_t otgfs_gotgctl_sesreq:1; + /** otgfs_gotgctl_vbvalidoven : R/W; bitpos: [2]; default: 0; + * Mode: Host only + * VBUS Valid Override Enable (VbvalidOvEn) + * This bit is used to enable/disable the software to override the Bvalid signal using + * the GOTGCTL.VbvalidOvVal. + * - 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL.VbvalidOvVal. + * - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the controller. + */ + uint32_t otgfs_gotgctl_vbvalidoven:1; + /** otgfs_gotgctl_vbvalidovval : R/W; bitpos: [3]; default: 0; + * Mode: Host only + * VBUS Valid OverrideValue (VbvalidOvVal) + * This bit is used to set Override value for vbusvalid signal when + * GOTGCTL.VbvalidOvEn is set. + * - 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1 + * - 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1 + */ + uint32_t otgfs_gotgctl_vbvalidovval:1; + /** otgfs_gotgctl_avalidoven : R/W; bitpos: [4]; default: 0; + * Mode: Host only + * A-Peripheral Session Valid Override Enable (AvalidOvEn) + * This bit is used to enable/disable the software to override the Avalid signal using + * the GOTGCTL.AvalidOvVal. + * - 1'b1: Internally Avalid received from the PHY is overridden with + * GOTGCTL.AvalidOvVal. + * - 1'b0: Override is disabled and avalid signal from the respective PHY selected is + * used internally by the core + */ + uint32_t otgfs_gotgctl_avalidoven:1; + /** otgfs_gotgctl_avalidovval : R/W; bitpos: [5]; default: 0; + * Mode: Host only + * A-Peripheral Session Valid OverrideValue (AvalidOvVal) + * This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is + * set. + * - 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + * - 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + */ + uint32_t otgfs_gotgctl_avalidovval:1; + /** otgfs_gotgctl_bvalidoven : R/W; bitpos: [6]; default: 0; + * Mode: Device only + * B-Peripheral Session Valid Override Value (BvalidOvEn) + * This bit is used to enable/disable the software to override the Bvalid signal using + * the GOTGCTL.BvalidOvVal. + * - 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL.BvalidOvVal. + * - 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the force + */ + uint32_t otgfs_gotgctl_bvalidoven:1; + /** otgfs_gotgctl_bvalidovval : R/W; bitpos: [7]; default: 0; + * Mode: Device only + * B-Peripheral Session Valid OverrideValue (BvalidOvVal) + * This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is + * set. + * - 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1 + * - 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1 + */ + uint32_t otgfs_gotgctl_bvalidovval:1; + /** otgfs_gotgctl_hstnegscs : RO; bitpos: [8]; default: 0; + * Mode: HNP-capable Device + * Host Negotiation Success (HstNegScs) + * The controller sets this bit when host negotiation is successful. The controller + * clears this bit when the HNP Request (HNPReq) bit in this register is set. + * - 1'b0: Host negotiation failure + * - 1'b1: Host negotiation success + */ + uint32_t otgfs_gotgctl_hstnegscs:1; + /** otgfs_gotgctl_hnpreq : R/W; bitpos: [9]; default: 0; + * Mode: HNP Capable OTG Device + * HNP Request (HNPReq) + * The application sets this bit to initiate an HNP request to the connected USB host. + * The application can clear this bit by writing a 0 when the Host Negotiation Success + * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. + * The controller clears this bit when the HstNegSucStsChng bit is cleared. + * - 1'b0: No HNP request + * - 1'b1: HNP request + */ + uint32_t otgfs_gotgctl_hnpreq:1; + /** otgfs_gotgctl_hstsethnpen : R/W; bitpos: [10]; default: 0; + * Mode: HNP Capable OTG Host + * Host Set HNP Enable (HstSetHNPEn) + * The application sets this bit when it has successfully enabled HNP (using the + * SetFeature.SetHNPEnable command) on the connected device. + * - 1'b0: Host Set HNP is not enabled + * - 1'b1: Host Set HNP is enabled + */ + uint32_t otgfs_gotgctl_hstsethnpen:1; + /** otgfs_gotgctl_devhnpen : R/W; bitpos: [11]; default: 0; + * Mode: HNP Capable OTG Device + * Device HNP Enabled (DevHNPEn) + * The application sets this bit when it successfully receives a + * SetFeature.SetHNPEnable command from the connected USB host. + * - 1'b0: HNP is not enabled in the application + * - 1'b1: HNP is enabled in the application + */ + uint32_t otgfs_gotgctl_devhnpen:1; + /** otgfs_gotgctl_ehen : R/W; bitpos: [12]; default: 0; + * Mode: SRP Capable Host + * Embedded Host Enable + * It is used to select between OTG A Device state Machine and Embedded Host state + * machine. + * - 1'b0: OTG A Device state machine is selected + * - 1'b1: Embedded Host State Machine is selected + * Note: + * This field is valid only in SRP-Capable OTG Mode (OTG_MODE=0,1). + */ + uint32_t otgfs_gotgctl_ehen:1; + uint32_t reserved_13:2; + /** otgfs_gotgctl_dbncefltrbypass : R/W; bitpos: [15]; default: 0; + * Mode: Host and Device + * Debounce Filter Bypass + * Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when + * enabled. + * - 1'b0: Disabled + * - 1'b1: Enabled + * + * + * Note: This register bit is valid only when debounce filters are present in core. + */ + uint32_t otgfs_gotgctl_dbncefltrbypass:1; + /** otgfs_gotgctl_conidsts : RO; bitpos: [16]; default: 1; + * Mode: Host and Device + * Connector ID Status (ConIDSts) + * Indicates the connector ID status on a connect event. + * - 1'b0: The core is in A-Device mode. + * - 1'b1: The core is in B-Device mode. + * + * Note: + * The reset value of this register field can be read only after the PHY clock is + * stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read + * the correct reset value which ever event is later. + * Reset: + * - 1'b0: in host only mode (OTG_MODE = 5 or 6) + * - 1'b1: in all other configurations + */ + uint32_t otgfs_gotgctl_conidsts:1; + /** otgfs_gotgctl_dbnctime : RO; bitpos: [17]; default: 0; + * Mode: Host only + * Long/Short Debounce Time (DbncTime) + * Indicates the debounce time of a detected connection. + * - 1'b0: Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + * - 1'b1: Short debounce time, used for soft connections (2.5 micro-sec) + */ + uint32_t otgfs_gotgctl_dbnctime:1; + /** otgfs_gotgctl_asesvld : RO; bitpos: [18]; default: 0; + * Mode: Host only + * A-Session Valid (ASesVld) + * Indicates the Host mode transceiver status. + * - 1'b0: A-session is not valid + * - 1'b1: A-session is valid + * Note: If you do not enabled OTG features (such as SRP and HNP), the read reset + * value will be 1. The vbus assigns the values internally for non-SRP or non-HNP + * configurations. + * In case of OTG_MODE=0, the reset value of this bit is 1'b0. + */ + uint32_t otgfs_gotgctl_asesvld:1; + /** otgfs_gotgctl_bsesvld : RO; bitpos: [19]; default: 0; + * Mode: Device only + * B-Session Valid (BSesVld) + * Indicates the Device mode transceiver status. + * - 1'b0: B-session is not valid. + * - 1'b1: B-session is valid. + * In OTG mode, you can use this bit to determine if the device is connected or + * disconnected. + * + * Note: + * - If you do not enable OTG features (such as SRP and HNP), the read reset value + * will be 1.The vbus assigns the values internally for non- SRP or non-HNP + * configurations. + * - In case of OTG_MODE=0, the reset value of this bit is 1'b0. + * - The reset value of this register field can be read only after the PHY clock is + * stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read + * the correct reset value which ever event is later. + */ + uint32_t otgfs_gotgctl_bsesvld:1; + /** otgfs_gotgctl_otgver : R/W; bitpos: [20]; default: 0; + * OTG Version (OTGVer) + * Indicates the OTG revision. + * - 1'b0: OTG Version 1.3. In this version the core supports Data line pulsing and + * VBus pulsing for SRP. + * - 1'b1: OTG Version 2.0. In this version the core supports only Data line pulsing + * for SRP. + */ + uint32_t otgfs_gotgctl_otgver:1; + /** otgfs_gotgctl_curmod : RO; bitpos: [21]; default: 0; + * Current Mode of Operation (CurMod) + * Mode: Host and Device + * Indicates the current mode. + * - 1'b0: Device mode + * - 1'b1: Host mode + * Reset: + * - 1'b1 in Host-only mode (OTG_MODE=5 or 6) + * - 1'b0 in all other configurations + * Note: The reset value of this register field can be read only after the PHY clock + * is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to + * read the correct reset value which ever event is later. + */ + uint32_t otgfs_gotgctl_curmod:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} usb_otgfs_gotgctl_reg_t; + + +/** Group: OTG Interrupt Register */ +/** Type of otgfs_gotgint register + * OTG Interrupt Register The application reads this register whenever there is an OTG + * interrupt and clears the bits in this register to clear the OTG interrupt. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** otgfs_gotgint_sesenddet : R/W; bitpos: [2]; default: 0; + * Mode: Host and Device + * Session End Detected (SesEndDet) + * The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit + * can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_sesenddet:1; + uint32_t reserved_3:5; + /** otgfs_gotgint_sesreqsucstschng : R/W; bitpos: [8]; default: 0; + * Mode: Host and Device + * Session Request Success Status Change (SesReqSucStsChng) + * The core sets this bit on the success or failure of a session request. The + * application must read the Session Request Success bit in the OTG Control and Status + * register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set + * only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_sesreqsucstschng:1; + /** otgfs_gotgint_hstnegsucstschng : R/W; bitpos: [9]; default: 0; + * Mode: Host and Device + * Host Negotiation Success Status Change (HstNegSucStsChng) + * The core sets this bit on the success or failure of a USB host negotiation request. + * The application must read the Host Negotiation Success bit of the OTG Control and + * Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can + * be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_hstnegsucstschng:1; + uint32_t reserved_10:7; + /** otgfs_gotgint_hstnegdet : R/W; bitpos: [17]; default: 0; + * Mode:Host and Device + * Host Negotiation Detected (HstNegDet) + * The core sets this bit when it detects a host negotiation request on the USB. This + * bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_hstnegdet:1; + /** otgfs_gotgint_adevtoutchg : R/W; bitpos: [18]; default: 0; + * Mode: Host and Device + * A-Device Timeout Change (ADevTOUTChg) + * The core sets this bit to indicate that the A-device has timed out while waiting + * for the B-device to connect.This bit can be set only by the core and the + * application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_adevtoutchg:1; + /** otgfs_gotgint_dbncedone : R/W; bitpos: [19]; default: 0; + * Mode: Host only + * Debounce Done (DbnceDone) + * The core sets this bit when the debounce is completed after the device connect. The + * application can start driving USB reset after seeing this interrupt. This bit is + * only valid when the HNP Capable or SRP Capable bit is SET in the Core USB + * Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit + * can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gotgint_dbncedone:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} usb_otgfs_gotgint_reg_t; + + +/** Group: AHB Configuration Register */ +/** Type of otgfs_gahbcfg register + * AHB Configuration Register This register can be used to configure the core after + * power-on or a change in mode. This register mainly contains AHB system-related + * configuration parameters. Do not change this register after the initial + * programming. The application must program this register before starting any + * transactions on either the AHB or the USB. + */ +typedef union { + struct { + /** otgfs_gahbcfg_glblintrmsk : R/W; bitpos: [0]; default: 0; + * Mode: Host and device + * Global Interrupt Mask (GlblIntrMsk) + * The application uses this bit to mask or unmask the interrupt line assertion to + * itself. Irrespective of this bit's setting, the interrupt status registers are + * updated by the controller. + * - 1'b0: Mask the interrupt assertion to the application. + * - 1'b1: Unmask the interrupt assertion to the application. + */ + uint32_t otgfs_gahbcfg_glblintrmsk:1; + /** otgfs_gahbcfg_hbstlen : R/W; bitpos: [4:1]; default: 0; + * Mode: Host and device + * Burst Length/Type (HBstLen) + * This field is used in both External and Internal DMA modes. In External DMA mode, + * these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper + * to interface the External DMA Controller interface to Synopsis DW_ahb_dmac or ARM + * PrimeCell. + * External DMA Mode defines the DMA burst length in terms of 32-bit words: + * - 4'b0000: 1 word + * - 4'b0001: 4 words + * - 4'b0010: 8 words + * - 4'b0011: 16 words + * - 4'b0100: 32 words + * - 4'b0101: 64 words + * - 4'b0110: 128 words + * - 4'b0111: 256 words + * - Others: Reserved + * Internal DMA Mode AHB Master burst type: + * - 4'b0000 Single + * - 4'b0001 INCR + * - 4'b0011 INCR4 + * - 4'b0101 INCR8 + * - 4'b0111 INCR16 + * - Others: Reserved + */ + uint32_t otgfs_gahbcfg_hbstlen:4; + /** otgfs_gahbcfg_dmaen : R/W; bitpos: [5]; default: 0; + * Mode: Host and device + * DMA Enable (DMAEn) + * + * This bit is always 0 when Slave-Only mode has been selected. + * + * Reset: 1'b0 + */ + uint32_t otgfs_gahbcfg_dmaen:1; + uint32_t reserved_6:1; + /** otgfs_gahbcfg_nptxfemplvl : R/W; bitpos: [7]; default: 0; + * Mode: Host and device + * Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + * This bit is used only in Slave mode. In host mode and with Shared FIFO with device + * mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the + * Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. + * With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit + * FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. + * Host mode and with Shared FIFO with device mode: + * - 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half + * empty + * - 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is + * completely empty + * Dedicated FIFO in device mode: + * - 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half + * empty + * - 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is + * completely empty + */ + uint32_t otgfs_gahbcfg_nptxfemplvl:1; + /** otgfs_gahbcfg_ptxfemplvl : R/W; bitpos: [8]; default: 0; + * Mode: Host only + * Periodic TxFIFO Empty Level (PTxFEmpLvl) + * Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt + * register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode. + * - 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty + * - 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely + * empty + */ + uint32_t otgfs_gahbcfg_ptxfemplvl:1; + uint32_t reserved_9:12; + /** otgfs_gahbcfg_remmemsupp : R/W; bitpos: [21]; default: 0; + * Mode: Host and Device + * Remote Memory Support (RemMemSupp) + * This bit is programmed to enable the functionality to wait for the system DMA Done + * Signal for the DMA Write Transfers. + * - GAHBCFG.RemMemSupp=1 + * The int_dma_req output signal is asserted when the DMA starts write transfer to the + * external memory. When the core is done with the Transfers it asserts int_dma_done + * signal to flag the completion of DMA writes from the controller. The core then + * waits for sys_dma_done signal from the system to proceed further and complete the + * Data Transfer corresponding to a particular Channel/Endpoint. + * - GAHBCFG.RemMemSupp=0 + * The int_dma_req and int_dma_done signals are not asserted and the core proceeds + * with the assertion of the XferComp interrupt as soon as the DMA write transfer is + * done at the Core Boundary and it does not wait for the sys_dma_done signal to + * complete the DATA transfers. + */ + uint32_t otgfs_gahbcfg_remmemsupp:1; + /** otgfs_gahbcfg_notialldmawrit : R/W; bitpos: [22]; default: 0; + * Mode: Host and Device + * Notify All DMA Write Transactions (NotiAllDmaWrit) + * This bit is programmed to enable the System DMA Done functionality for all the DMA + * write Transactions corresponding to the Channel/Endpoint. This bit is valid only + * when GAHBCFG.RemMemSupp is set to 1. + * - GAHBCFG.NotiAllDmaWrit = 1 + * The core asserts int_dma_req for all the DMA write transactions on the AHB + * interface along with int_dma_done, chep_last_transact and chep_number signal + * information. The core waits for sys_dma_done signal for all the DMA write + * transactions in order to complete the transfer of a particular Channel/Endpoint. + * - GAHBCFG.NotiAllDmaWrit = 0 + * The core asserts int_dma_req signal only for the last transaction of DMA write + * transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits + * for sys_dma_done signal only for that transaction of DMA write to complete the + * transfer of a particular Channel/Endpoint. + */ + uint32_t otgfs_gahbcfg_notialldmawrit:1; + /** otgfs_gahbcfg_ahbsingle : R/W; bitpos: [23]; default: 0; + * Mode: Host and Device + * AHB Single Support (AHBSingle) + * This bit when programmed supports Single transfers for the remaining data in a + * transfer when the core is operating in DMA mode. + * - 1'b0: The remaining data in the transfer is sent using INCR burst size. + * - 1'b1: The remaining data in the transfer is sent using Single burst size. + * Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR + * burst type. Enable this feature when the AHB Slave connected to the core does not + * support INCR burst (and when Split, and Retry transactions are not being used in + * the bus). + */ + uint32_t otgfs_gahbcfg_ahbsingle:1; + /** otgfs_gahbcfg_invdescendianess : R/W; bitpos: [24]; default: 0; + * Mode: Host and Device + * Invert Descriptor Endianness (InvDescEndianess) + * - 1'b0: Descriptor Endianness is same as AHB Master Endianness. + * - 1'b1: + * -- If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little + * Endian. + * -- If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big + * Endian. + */ + uint32_t otgfs_gahbcfg_invdescendianess:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} usb_otgfs_gahbcfg_reg_t; + + +/** Group: USB Configuration Register */ +/** Type of otgfs_gusbcfg register + * USB Configuration Register This register can be used to configure the core after + * power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY + * related configuration parameters. The application must program this register before + * starting any transactions on either the AHB or the USB. Do not make changes to this + * register after the initial programming. + */ +typedef union { + struct { + /** otgfs_gusbcfg_toutcal : R/W; bitpos: [2:0]; default: 0; + * Mode: Host and Device + * HS/FS Timeout Calibration (TOutCal) + * + * The number of PHY clocks that the application programs in this field is added to + * the high-speed/full-speed interpacket timeout duration in the core to account for + * any additional delays introduced by the PHY. This can be required, because the + * delay introduced by the PHY in generating the linestate condition can vary from one + * PHY to another. + * + * The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) + * bit times. The USB standard timeout value for full-speed operation is 16 to 18 + * (inclusive) bit times. The application must program this field based on the speed + * of enumeration. The number of bit times added per PHY clock are as follows: + * + * High-speed operation: + * - One 30-MHz PHY clock = 16 bit times + * - One 60-MHz PHY clock = 8 bit times + * Full-speed operation: + * - One 30-MHz PHY clock = 0.4 bit times + * - One 60-MHz PHY clock = 0.2 bit times + * - One 48-MHz PHY clock = 0.25 bit times + */ + uint32_t otgfs_gusbcfg_toutcal:3; + /** otgfs_gusbcfg_phyif : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * PHY Interface (PHYIf) + * The application uses this bit to configure the core to support a UTMI+ PHY with an + * 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode. + * - 1'b0: 8 bits + * - 1'b1: 16 bits + * This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit + * returns the value for the power-on interface selected during configuration. + */ + uint32_t otgfs_gusbcfg_phyif:1; + uint32_t reserved_4:1; + /** otgfs_gusbcfg_fsintf : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * Full-Speed Serial Interface Select (FSIntf) + * + * The application uses this bit to select either a unidirectional or bidirectional + * USB 1.1 full-speed serial transceiver interface. + * - 1'b0: 6-pin unidirectional full-speed serial interface + * - 1'b1: 3-pin bidirectional full-speed serial interface + * If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is + * always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the + * application can Set this bit to select between the 3- and 6-pin interfaces, and + * access is Read and Write. + * + * Note: For supporting the new 4-pin bi-directional interface, you need to select + * 6-pin unidirectional FS serial mode, and add an external control to convert it to a + * 4-pin interface. + */ + uint32_t otgfs_gusbcfg_fsintf:1; + /** otgfs_gusbcfg_physel : RO; bitpos: [6]; default: 1; + * PHYSel + * + * Mode: Host and Device + * + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel) + * The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a + * full-speed transceiver. + * - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY + * - 1'b1: USB 1.1 full-speed serial transceiver + * If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit + * is always 0, with Write Only access. + * If a high-speed PHY interface was not selected in, this bit is always 1, with Write + * Only access. + * If both interface types were selected (parameters have non-zero values), the + * application uses this bit to select which interface is active, and access is Read + * and Write. + */ + uint32_t otgfs_gusbcfg_physel:1; + uint32_t reserved_7:1; + /** otgfs_gusbcfg_srpcap : R/W; bitpos: [8]; default: 0; + * Mode: Host and Device + * SRP-Capable (SRPCap) + * The application uses this bit to control the controller's SRP capabilities. If the + * core operates as a non-SRP-capable B-device, it cannot request the connected + * A-device (host) to + * activate VBUS and start a session. + * - 1'b0: SRP capability is not enabled. + * - 1'b1: SRP capability is enabled. + * If SRP functionality is disabled by the software, the OTG signals on the PHY domain + * must be tied to the appropriate values. + */ + uint32_t otgfs_gusbcfg_srpcap:1; + /** otgfs_gusbcfg_hnpcap : R/W; bitpos: [9]; default: 0; + * Mode: Host and Device + * HNP-Capable (HNPCap) + * The application uses this bit to control the controller's HNP capabilities. + * - 1'b0: HNP capability is not enabled. + * - 1'b1: HNP capability is enabled. + * If HNP functionality is disabled by the software, the OTG signals on the PHY domain + * must be tied to the appropriate values. + */ + uint32_t otgfs_gusbcfg_hnpcap:1; + /** otgfs_gusbcfg_usbtrdtim : R/W; bitpos: [13:10]; default: 5; + * Mode: Device only + * USB Turnaround Time (USBTrdTim) + * Sets the turnaround time in PHY clocks. Specifies the response time for a MAC + * request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). + * This must be programmed to + * - 4'h5: When the MAC interface is 16-bit UTMI+ . + * - 4'h9: When the MAC interface is 8-bit UTMI+ . + * Note: The previous values are calculated for the minimum AHB frequency of 30 MHz. + * USB turnaround time is critical for certification where long cables and 5-Hubs are + * used. If you need the AHB to run at less than 30 MHz, and if USB turnaround time is + * not critical, these bits can be programmed to a larger value. + */ + uint32_t otgfs_gusbcfg_usbtrdtim:4; + uint32_t reserved_14:8; + /** otgfs_gusbcfg_termseldlpulse : RO; bitpos: [22]; default: 0; + * Mode: Device only + * TermSel DLine Pulsing Selection (TermSelDLPulse) + * This bit selects utmi_termselect to drive data line pulse during SRP. + * - 1'b0: Data line pulsing using utmi_txvalid (Default). + * - 1'b1: Data line pulsing using utmi_termsel. + */ + uint32_t otgfs_gusbcfg_termseldlpulse:1; + uint32_t reserved_23:3; + /** otgfs_gusbcfg_ic_usbcap : RO; bitpos: [26]; default: 0; + * Mode: Host and Device + * IC_USB-Capable (IC_USBCap) + * The application uses this bit to control the core's IC_USB capabilities. + * - 1'b0: IC_USB PHY Interface is not selected. + * - 1'b1: IC_USB PHY Interface is selected. + * This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0. + * The reset value depends on the configuration parameter OTG_SELECT_IC_USB when + * OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is + * read only. + */ + uint32_t otgfs_gusbcfg_ic_usbcap:1; + uint32_t reserved_27:1; + /** otgfs_gusbcfg_txenddelay : R/W; bitpos: [28]; default: 0; + * Mode: Device only + * Tx End Delay (TxEndDelay) + * Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as + * per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup. + * - 1'b0 : Normal Mode. + * - 1'b1 : Tx End delay. + */ + uint32_t otgfs_gusbcfg_txenddelay:1; + /** otgfs_gusbcfg_forcehstmode : R/W; bitpos: [29]; default: 0; + * Mode: Host and device + * Force Host Mode (ForceHstMode) + * Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig + * input pin. + * - 1'b0 : Normal Mode. + * - 1'b1 : Force Host Mode. + * After setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for 500 + * micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all + * other cases, this bit reads 0. + */ + uint32_t otgfs_gusbcfg_forcehstmode:1; + /** otgfs_gusbcfg_forcedevmode : R/W; bitpos: [30]; default: 0; + * Mode:Host and device + * Force Device Mode (ForceDevMode) + * Writing a 1 to this bit forces the controller to device mode irrespective of + * utmiotg_iddig input pin. + * - 1'b0 : Normal Mode. + * - 1'b1 : Force Device Mode. + * After setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for 500 + * micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all + * other cases, this bit reads 0. + */ + uint32_t otgfs_gusbcfg_forcedevmode:1; + /** otgfs_gusbcfg_corrupttxpkt : R/W; bitpos: [31]; default: 0; + * Mode: Host and device + * Corrupt Tx packet (CorruptTxPkt) + * This bit is for debug purposes only. Never Set this bit to 1. The application + * should always write 1'b0 to this bit. + */ + uint32_t otgfs_gusbcfg_corrupttxpkt:1; + }; + uint32_t val; +} usb_otgfs_gusbcfg_reg_t; + + +/** Group: Reset Register */ +/** Type of otgfs_grstctl register + * Reset Register The application uses this register to reset various hardware + * features inside the controller. + */ +typedef union { + struct { + /** otgfs_grstctl_csftrst : R/W; bitpos: [0]; default: 0; + * Mode: Host and Device + * Core Soft Reset (CSftRst) + * Resets the hclk and phy_clock domains as follows: + * - Clears the interrupts and all the CSR registers except the following register + * bits: + * -- PCGCCTL.RstPdwnModule + * -- PCGCCTL.GateHclk + * -- PCGCCTL.PwrClmp + * -- PCGCCTL.StopPPhyLPwrClkSelclk + * -- GUSBCFG.ForceDevMode + * -- GUSBCFG.ForceHstMode + * -- GUSBCFG.PhyLPwrClkSel + * -- GUSBCFG.DDRSel + * -- GUSBCFG.PHYSel + * -- GUSBCFG.FSIntf + * -- GUSBCFG.ULPI_UTMI_Sel + * -- GUSBCFG.TxEndDelay + * -- GUSBCFG.TermSelDLPulse + * -- GUSBCFG.ULPIClkSusM + * -- GUSBCFG.ULPIAutoRes + * -- GUSBCFG.ULPIFsLs + * -- GGPIO + * -- GPWRDN + * -- GADPCTL + * -- HCFG.FSLSPclkSel + * -- DCFG.DevSpd + * -- DCTL.SftDiscon + * - All module state machines + * - All module state machines (except the AHB Slave Unit) are reset to the IDLE + * state, and all the transmit FIFOs and the receive FIFO are flushed. + * - Any transactions on the AHB Master are terminated as soon as possible, after + * gracefully completing the last data phase of an AHB transfer. Any transactions on + * the USB are terminated immediately. + * - When Hibernation or ADP feature is enabled, the PMU module is not reset by the + * Core Soft Reset. + * The application can write to this bit any time it wants to reset the core. This is + * a self-clearing bit and the core clears this bit after + * all the necessary logic is reset in the core, which can take several clocks, + * depending on the current state of the core. Once this bit is cleared software must + * wait at least 3 PHY clocks before doing any access to the PHY domain + * (synchronization delay). Software must also must check that bit 31 of this register + * is 1 (AHB Master is IDLE) before starting any operation. + * + * Typically software reset is used during software development and also when you + * dynamically change the PHY selection bits in the USB configuration registers listed + * above. When you change the PHY, the corresponding clock for the PHY is selected and + * used in the PHY domain. Once a new clock is selected, the PHY domain has to be + * reset for proper operation. + */ + uint32_t otgfs_grstctl_csftrst:1; + /** otgfs_grstctl_piufssftrst : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + * + * Resets the PIU FS Dedicated Controller + * All module state machines in FS Dedicated Controller of PIU are reset to the IDLE + * state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors + * like Loss of activity or Babble Error resulting in the PHY remaining in RX state + * for more than one frame boundary. + * This is a self clearing bit and core clears this bit after all the necessary logic + * is reset in the core. + */ + uint32_t otgfs_grstctl_piufssftrst:1; + /** otgfs_grstctl_frmcntrrst : R/W; bitpos: [2]; default: 0; + * Mode: Host only + * Host Frame Counter Reset (FrmCntrRst) + * The application writes this bit to reset the (micro)Frame number counter inside the + * core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the + * core has a (micro)Frame number of 0. + * When application writes 1 to the bit, it might not be able to read back the value + * as it will get cleared by the core in a few clock cycles. + */ + uint32_t otgfs_grstctl_frmcntrrst:1; + uint32_t reserved_3:1; + /** otgfs_grstctl_rxfflsh : R/W; bitpos: [4]; default: 0; + * Mode: Host and Device + * RxFIFO Flush (RxFFlsh) + * The application can flush the entire RxFIFO using this bit, but must first ensure + * that the core is not in the middle of a transaction. + * The application must only write to this bit after checking that the controller is + * neither reading from the RxFIFO nor writing to the RxFIFO. + * + * The application must wait until the bit is cleared before performing any other + * operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear. + */ + uint32_t otgfs_grstctl_rxfflsh:1; + /** otgfs_grstctl_txfflsh : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * TxFIFO Flush (TxFFlsh) + * This bit selectively flushes a single or all transmit FIFOs, but cannot do so If + * the core is in the midst of a transaction. + * The application must write this bit only after checking that the core is neither + * writing to the TxFIFO nor reading from the TxFIFO. + * Verify using these registers: + * - ReadNAK Effective Interrupt ensures the core is not reading from the FIFO + * - WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO. + * Flushing is normally recommended when FIFOs are reconfigured or when switching + * between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also + * recommended during device endpoint disable. The application must wait until the + * core clears this bit before performing any operations. This bit takes eight clocks + * to clear, using the slower clock of phy_clk or hclk. + */ + uint32_t otgfs_grstctl_txfflsh:1; + /** otgfs_grstctl_txfnum : R/W; bitpos: [10:6]; default: 0; + * Mode: Host and Device + * TxFIFO Number (TxFNum) + * This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field + * must not be changed until the core clears the TxFIFO Flush bit. + * - 5'h0: + * -- Non-periodic TxFIFO flush in Host mode + * -- Non-periodic TxFIFO flush in device mode when in shared FIFO operation + * -- Tx FIFO 0 flush in device mode when in dedicated FIFO mode + * - 5'h1: + * -- Periodic TxFIFO flush in Host mode + * -- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation + * -- TXFIFO 1 flush in device mode when in dedicated FIFO mode + * - 5'h2: + * -- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation + * -- TXFIFO 2 flush in device mode when in dedicated FIFO mode + * ... + * - 5'hF + * -- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation + * -- TXFIFO 15 flush in device mode when in dedicated FIFO mode + * - 5'h10: Flush all the transmit FIFOs in device or host mode + */ + uint32_t otgfs_grstctl_txfnum:5; + uint32_t reserved_11:19; + /** otgfs_grstctl_dmareq : RO; bitpos: [30]; default: 0; + * Mode: Host and Device + * DMA Request Signal (DMAReq) + * Indicates that the DMA request is in progress. Used for debug. + */ + uint32_t otgfs_grstctl_dmareq:1; + /** otgfs_grstctl_ahbidle : RO; bitpos: [31]; default: 1; + * Mode: Host and Device + * AHB Master Idle (AHBIdle) + * Indicates that the AHB Master State Machine is in the IDLE condition. + */ + uint32_t otgfs_grstctl_ahbidle:1; + }; + uint32_t val; +} usb_otgfs_grstctl_reg_t; + + +/** Group: Interrupt Register */ +/** Type of otgfs_gintsts register + * Interrupt Register This register interrupts the application for system-level + * events in the current mode (Device mode or Host mode). Some of the bits in this + * register are valid only in Host mode, while others are valid in Device mode only. + * This register also indicates the current mode. To clear the interrupt status bits + * of type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status + * interrupts are read only; once software reads from or writes to the FIFO while + * servicing these interrupts, FIFO interrupt conditions are cleared automatically. + * The application must clear the GINTSTS register at initialization before unmasking + * the interrupt bit to avoid any interrupts generated prior to initialization. Note: + * Read the reset value of GINTSTS.CurMod only after the following conditions: - If + * IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER + * is enabled, read only after the filter timer expires. + */ +typedef union { + struct { + /** otgfs_gintsts_curmod : RO; bitpos: [0]; default: 0; + * Mode: Host and Device + * Current Mode of Operation (CurMod) + * Indicates the current mode. + * - 1'b0: Device mode + * - 1'b1: Host mode + * + * + * Note: The reset value of this register field can be read only after the PHY clock + * is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to + * read the correct reset value which ever event is later. + */ + uint32_t otgfs_gintsts_curmod:1; + /** otgfs_gintsts_modemis : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * Mode Mismatch Interrupt (ModeMis) + * The core sets this bit when the application is trying to access: + * - A Host mode register, when the controller is operating in Device mode + * - A Device mode register, when the controller is operating in Host mode + * The register access is completed on the AHB with an OKAY response, but is ignored + * by the controller internally and does not affect the operation of the controller. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_gintsts_modemis:1; + /** otgfs_gintsts_otgint : RO; bitpos: [2]; default: 0; + * Mode: Host and Device + * OTG Interrupt (OTGInt) + * The controller sets this bit to indicate an OTG protocol event. The application + * must read the OTG Interrupt Status (GOTGINT) register to determine the exact event + * that caused this interrupt. The application must clear the appropriate status bit + * in the GOTGINT register to clear this bit. + */ + uint32_t otgfs_gintsts_otgint:1; + /** otgfs_gintsts_sof : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * Start of (micro)Frame (Sof) + * + * In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), + * or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to + * this bit to clear the interrupt. + * + * In Device mode, the controller sets this bit to indicate that an SOF token has been + * received on the USB. The application can read the Device Status register to get the + * current (micro)Frame number. This interrupt is seen only when the core is operating + * at either HS or FS. This bit can be set only by the core and the application must + * write 1 to clear it. + * + * Note: This register may return 1'b1 if read immediately after power-on reset. + * If the register bit reads 1'b1 immediately after power-on reset, it does not + * indicate that an SOF has been sent (in case of host mode) or SOF has been received + * (in case of device mode). + * The read value of this interrupt is valid only after a valid connection between + * host and device is established. If the bit is set after power on reset the + * application can clear the bit. + */ + uint32_t otgfs_gintsts_sof:1; + /** otgfs_gintsts_rxflvl : RO; bitpos: [4]; default: 0; + * Mode: Host and Device + * RxFIFO Non-Empty (RxFLvl) + * + * Indicates that there is at least one packet pending to be read from the RxFIFO. + */ + uint32_t otgfs_gintsts_rxflvl:1; + /** otgfs_gintsts_nptxfemp : RO; bitpos: [5]; default: 1; + * Mode: Host and Device + * Non-periodic TxFIFO Empty (NPTxFEmp) + * This interrupt is asserted when the Non-periodic TxFIFO is either half or + * completely empty, and there is space for at least one Entry to be written to the + * Non-periodic Transmit Request Queue. The half or completely empty status is + * determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration + * register (GAHBCFG.NPTxFEmpLvl). + * In host mode, the application can use GINTSTS.NPTxFEmp with the OTG_EN_DED_TX_FIFO + * parameter set to either 1 or 0. + * In device mode, the application uses GINTSTS.NPTxFEmp when OTG_EN_DED_TX_FIFO=0. + * When OTG_EN_DED_TX_FIFO=1, the application uses DIEPINTn.TxFEmp. + */ + uint32_t otgfs_gintsts_nptxfemp:1; + /** otgfs_gintsts_ginnakeff : RO; bitpos: [6]; default: 0; + * Mode: Device only + * Global IN Non-periodic NAK Effective (GINNakEff) + * Indicates that the Set Global Non-periodic IN NAK bit in the Device Control + * register (DCTL.SGNPInNak) set by the application, has taken effect in the core. + * That is, the core has sampled the Global IN NAK bit Set by the application. This + * bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the + * Device Control register (DCTL.CGNPInNak). This interrupt does not necessarily mean + * that a NAK handshake + * is sent out on the USB. The STALL bit takes precedence over the NAK bit. + */ + uint32_t otgfs_gintsts_ginnakeff:1; + /** otgfs_gintsts_goutnakeff : RO; bitpos: [7]; default: 0; + * Mode: Device only + * Global OUT NAK Effective (GOUTNakEff) + * Indicates that the Set Global OUT NAK bit in the Device Control register + * (DCTL.SGOUTNak), Set by the application, has taken effect in the core. This bit can + * be cleared by writing the Clear Global OUT NAK bit in the Device Control register + * (DCTL.CGOUTNak). + */ + uint32_t otgfs_gintsts_goutnakeff:1; + uint32_t reserved_8:2; + /** otgfs_gintsts_erlysusp : R/W; bitpos: [10]; default: 0; + * Mode: Device only + * Early Suspend (ErlySusp) + * The controller sets this bit to indicate that an Idle state has been detected on + * the USB for 3 ms. + */ + uint32_t otgfs_gintsts_erlysusp:1; + /** otgfs_gintsts_usbsusp : R/W; bitpos: [11]; default: 0; + * Mode: Device only + * USB Suspend (USBSusp) + * The controller sets this bit to indicate that a suspend was detected on the USB. + * The controller enters the Suspended state when there is no activity on the + * linestate signal for an extended period of time. + */ + uint32_t otgfs_gintsts_usbsusp:1; + /** otgfs_gintsts_usbrst : R/W; bitpos: [12]; default: 0; + * Mode: Device only + * USB Reset (USBRst) + * The controller sets this bit to indicate that a reset is detected on the USB. + */ + uint32_t otgfs_gintsts_usbrst:1; + /** otgfs_gintsts_enumdone : R/W; bitpos: [13]; default: 0; + * Mode: Device only + * Enumeration Done (EnumDone) + * The core sets this bit to indicate that speed enumeration is complete. The + * application must read the Device Status (DSTS) register to obtain the enumerated + * speed. + */ + uint32_t otgfs_gintsts_enumdone:1; + /** otgfs_gintsts_isooutdrop : R/W; bitpos: [14]; default: 0; + * Mode: Device only + * Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + * The controller sets this bit when it fails to write an isochronous OUT packet into + * the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum + * packet size packet for the isochronous OUT endpoint. + */ + uint32_t otgfs_gintsts_isooutdrop:1; + /** otgfs_gintsts_eopf : R/W; bitpos: [15]; default: 0; + * Mode: Device only + * End of Periodic Frame Interrupt (EOPF) + * Indicates that the period specified in the Periodic Frame Interval field of the + * Device Configuration register (DCFG.PerFrInt) has been reached in the current + * microframe. + */ + uint32_t otgfs_gintsts_eopf:1; + uint32_t reserved_16:1; + /** otgfs_gintsts_epmis : R/W; bitpos: [17]; default: 0; + * Mode: Device only + * Endpoint Mismatch Interrupt (EPMis) + * Note: This interrupt is valid only in shared FIFO operation. + * Indicates that an IN token has been received for a non-periodic endpoint, but the + * data for another endpoint is present in the top of the Non-periodic Transmit FIFO + * and the IN endpoint mismatch count programmed by the application has expired. + */ + uint32_t otgfs_gintsts_epmis:1; + /** otgfs_gintsts_iepint : RO; bitpos: [18]; default: 0; + * Mode: Device only + * IN Endpoints Interrupt (IEPInt) + * The core sets this bit to indicate that an interrupt is pending on one of the IN + * endpoints of the core (in Device mode). The application must read the Device All + * Endpoints Interrupt (DAINT) register to determine the exact number of the IN + * endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the + * exact cause of the interrupt. The application must clear the appropriate status bit + * in the corresponding DIEPINTn register to + * clear this bit. + */ + uint32_t otgfs_gintsts_iepint:1; + /** otgfs_gintsts_oepint : RO; bitpos: [19]; default: 0; + * Mode: Device only + * OUT Endpoints Interrupt (OEPInt) + * The controller sets this bit to indicate that an interrupt is pending on one of the + * OUT endpoints of the core (in Device mode). The application must read the Device + * All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT + * endpoint on which the interrupt occurred, and then read the corresponding Device + * OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the + * interrupt. The application must + * clear the appropriate status bit in the corresponding DOEPINTn register to clear + * this bit. + */ + uint32_t otgfs_gintsts_oepint:1; + /** otgfs_gintsts_incompisoin : R/W; bitpos: [20]; default: 0; + * Mode: Device only + * Incomplete Isochronous IN Transfer (incompISOIN) + * The core sets this interrupt to indicate that there is at least one isochronous IN + * endpoint on which the transfer is not completed in the current microframe. This + * interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in + * this register. + * Note: This interrupt is not asserted in Scatter/Gather DMA mode. + */ + uint32_t otgfs_gintsts_incompisoin:1; + /** otgfs_gintsts_incomplp : R/W; bitpos: [21]; default: 0; + * Incomplete Periodic Transfer (incomplP) + * Mode: Host only + * In Host mode, the core sets this interrupt bit when there are incomplete periodic + * transactions still pending which are scheduled for the current microframe. + * Incomplete Isochronous OUT Transfer (incompISOOUT) + * Mode: Device only + * The Device mode, the core sets this interrupt to indicate that there is at least + * one isochronous OUT endpoint on which the transfer is not completed in the current + * microframe. This interrupt is asserted along with the End of Periodic Frame + * Interrupt (EOPF) bit in this register. + */ + uint32_t otgfs_gintsts_incomplp:1; + /** otgfs_gintsts_fetsusp : R/W; bitpos: [22]; default: 0; + * Mode: Device only + * Data Fetch Suspended (FetSusp) + * This interrupt is valid only in DMA mode. This interrupt indicates that the core + * has stopped fetching data. For IN endpoints due to the unavailability of TxFIFO + * space or Request Queue space. This interrupt is used by the application for an + * endpoint mismatch algorithm. + * + * For example, after detecting an endpoint mismatch, the application: + * - Sets a Global non-periodic IN NAK handshake + * - Disables IN endpoints + * - Flushes the FIFO + * - Determines the token sequence from the IN Token Sequence Learning Queue + * - Re-enables the endpoints + * - Clears the Global non-periodic IN NAK handshake + * If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for + * the IN endpoint, and the IN token is received. The core generates an 'IN token + * received when FIFO empty' interrupt. The DWC_otg then sends the host a NAK + * response. To avoid this scenario, the application can check the GINTSTS.FetSusp + * interrupt, which ensures that the FIFO is full before clearing a Global NAK + * handshake. + * + * Alternatively, the application can mask the IN token received when FIFO empty + * interrupt when clearing a Global IN NAK handshake. + */ + uint32_t otgfs_gintsts_fetsusp:1; + /** otgfs_gintsts_resetdet : R/W; bitpos: [23]; default: 0; + * Mode: Device only + * Reset detected Interrupt (ResetDet) + * In Device mode, this interrupt is asserted when a reset is detected on the USB in + * partial power-down mode when the device is in Suspend. + * + * In Host mode, this interrupt is not asserted. + */ + uint32_t otgfs_gintsts_resetdet:1; + /** otgfs_gintsts_prtint : RO; bitpos: [24]; default: 0; + * Mode: Host only + * Host Port Interrupt (PrtInt) + * The core sets this bit to indicate a change in port status of one of the controller + * ports in Host mode. The application must read the Host Port Control and Status + * (HPRT) register to determine the exact event that caused this interrupt. The + * application must clear the appropriate status bit in the Host Port + * Control and Status register to clear this bit. + */ + uint32_t otgfs_gintsts_prtint:1; + /** otgfs_gintsts_hchint : RO; bitpos: [25]; default: 0; + * Mode: Host only + * Host Channels Interrupt (HChInt) + * The core sets this bit to indicate that an interrupt is pending on one of the + * channels of the core (in Host mode). The application must read the Host All + * Channels Interrupt (HAINT) register to determine the exact number of the channel on + * which the interrupt occurred, and Then read the corresponding Host + * Channel-n Interrupt (HCINTn) register to determine the exact cause of the + * interrupt. The application must clear the appropriate status bit in the HCINTn + * register to clear this bit. + */ + uint32_t otgfs_gintsts_hchint:1; + /** otgfs_gintsts_ptxfemp : RO; bitpos: [26]; default: 1; + * Mode: Host only + * Periodic TxFIFO Empty (PTxFEmp) + * This interrupt is asserted when the Periodic Transmit FIFO is either half or + * completely empty and there is space for at least one entry to be written in the + * Periodic Request Queue. The half or completely empty status is determined by the + * Periodic TxFIFO Empty Level bit in the Core AHB Configuration register + * (GAHBCFG.PTxFEmpLvl). + */ + uint32_t otgfs_gintsts_ptxfemp:1; + uint32_t reserved_27:1; + /** otgfs_gintsts_conidstschng : R/W; bitpos: [28]; default: 0; + * Mode: Host and Device + * Connector ID Status Change (ConIDStsChng) + * The core sets this bit when there is a change in connector ID status. + */ + uint32_t otgfs_gintsts_conidstschng:1; + /** otgfs_gintsts_disconnint : R/W; bitpos: [29]; default: 0; + * Mode: Host only + * Disconnect Detected Interrupt (DisconnInt) + * Asserted when a device disconnect is detected. + */ + uint32_t otgfs_gintsts_disconnint:1; + /** otgfs_gintsts_sessreqint : R/W; bitpos: [30]; default: 0; + * Mode: Host and Device + * Session Request/New Session Detected Interrupt (SessReqInt) + * In Host mode, this interrupt is asserted when a session request is detected from + * the device. In Host mode, this interrupt is asserted when a session request is + * detected from the device. + * In Device mode, this interrupt is asserted when the utmisrp_bvalid signal goes high. + * For more information on how to use this interrupt, see 'Partial Power-Down and + * Clock Gating Programming Model' in the Programming Guide. + */ + uint32_t otgfs_gintsts_sessreqint:1; + /** otgfs_gintsts_wkupint : R/W; bitpos: [31]; default: 0; + * Mode: Host and Device + * Resume/Remote Wakeup Detected Interrupt (WkUpInt) + * Wakeup Interrupt during Suspend(L2) or LPM(L1) state. + * - During Suspend(L2): + * -- Device Mode: This interrupt is asserted only when Host Initiated Resume is + * detected on USB. + * -- Host Mode: This interrupt is asserted only when Device Initiated Remote Wakeup + * is detected on USB. + * For more information, see 'Partial Power-Down and Clock Gating Programming Model' + * in the Programming Guide. + * - During LPM(L1): + * -- Device Mode: This interrupt is asserted for either Host Initiated Resume or + * Device Initiated Remote Wakeup on USB. + * -- Host Mode: This interrupt is asserted for either Host Initiated Resume or Device + * Initiated Remote Wakeup on USB. + * For more information, see 'LPM Entry and Exit Programming Model' in the Programming + * Guide. + */ + uint32_t otgfs_gintsts_wkupint:1; + }; + uint32_t val; +} usb_otgfs_gintsts_reg_t; + + +/** Group: Interrupt Mask Register */ +/** Type of otgfs_gintmsk register + * Interrupt Mask Register This register works with the Interrupt Register (GINTSTS) + * to interrupt the application. When an interrupt bit is masked, the interrupt + * associated with that bit is not generated. However, the GINTSTS register bit + * corresponding to that interrupt is still set. Note: The fields of this register + * change depending on host or device mode. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** otgfs_gintmsk_modemismsk : R/W; bitpos: [1]; default: 0; + * Mode: Host and Device + * Mode Mismatch Interrupt Mask (ModeMisMsk) + */ + uint32_t otgfs_gintmsk_modemismsk:1; + /** otgfs_gintmsk_otgintmsk : R/W; bitpos: [2]; default: 0; + * Mode: Host and Device + * OTG Interrupt Mask (OTGIntMsk) + */ + uint32_t otgfs_gintmsk_otgintmsk:1; + /** otgfs_gintmsk_sofmsk : R/W; bitpos: [3]; default: 0; + * Mode: Host and Device + * Start of (micro)Frame Mask (SofMsk) + */ + uint32_t otgfs_gintmsk_sofmsk:1; + /** otgfs_gintmsk_rxflvlmsk : R/W; bitpos: [4]; default: 0; + * Mode: Host and Device + * Receive FIFO Non-Empty Mask (RxFLvlMsk) + */ + uint32_t otgfs_gintmsk_rxflvlmsk:1; + /** otgfs_gintmsk_nptxfempmsk : R/W; bitpos: [5]; default: 0; + * Mode: Host and Device + * Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + */ + uint32_t otgfs_gintmsk_nptxfempmsk:1; + /** otgfs_gintmsk_ginnakeffmsk : R/W; bitpos: [6]; default: 0; + * Mode: Device only, + * Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + */ + uint32_t otgfs_gintmsk_ginnakeffmsk:1; + /** otgfs_gintmsk_goutnakeffmsk : R/W; bitpos: [7]; default: 0; + * Mode: Device only + * Global OUT NAK Effective Mask (GOUTNakEffMsk) + */ + uint32_t otgfs_gintmsk_goutnakeffmsk:1; + uint32_t reserved_8:2; + /** otgfs_gintmsk_erlysuspmsk : R/W; bitpos: [10]; default: 0; + * Mode: Device only + * Early Suspend Mask (ErlySuspMsk) + */ + uint32_t otgfs_gintmsk_erlysuspmsk:1; + /** otgfs_gintmsk_usbsuspmsk : R/W; bitpos: [11]; default: 0; + * Mode: Device only + * USB Suspend Mask (USBSuspMsk) + */ + uint32_t otgfs_gintmsk_usbsuspmsk:1; + /** otgfs_gintmsk_usbrstmsk : R/W; bitpos: [12]; default: 0; + * Mode: Device only + * USB Reset Mask (USBRstMsk) + */ + uint32_t otgfs_gintmsk_usbrstmsk:1; + /** otgfs_gintmsk_enumdonemsk : R/W; bitpos: [13]; default: 0; + * Mode: Device only + * Enumeration Done Mask (EnumDoneMsk) + */ + uint32_t otgfs_gintmsk_enumdonemsk:1; + /** otgfs_gintmsk_isooutdropmsk : R/W; bitpos: [14]; default: 0; + * Mode: Device only + * Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + */ + uint32_t otgfs_gintmsk_isooutdropmsk:1; + /** otgfs_gintmsk_eopfmsk : R/W; bitpos: [15]; default: 0; + * Mode: Device only + * End of Periodic Frame Interrupt Mask (EOPFMsk) + */ + uint32_t otgfs_gintmsk_eopfmsk:1; + uint32_t reserved_16:1; + /** otgfs_gintmsk_epmismsk : R/W; bitpos: [17]; default: 0; + * Mode: Device only + * Endpoint Mismatch Interrupt Mask (EPMisMsk) + */ + uint32_t otgfs_gintmsk_epmismsk:1; + /** otgfs_gintmsk_iepintmsk : R/W; bitpos: [18]; default: 0; + * Mode: Device only + * IN Endpoints Interrupt Mask (IEPIntMsk) + */ + uint32_t otgfs_gintmsk_iepintmsk:1; + /** otgfs_gintmsk_oepintmsk : R/W; bitpos: [19]; default: 0; + * Mode: Device only + * OUT Endpoints Interrupt Mask (OEPIntMsk) + */ + uint32_t otgfs_gintmsk_oepintmsk:1; + uint32_t reserved_20:1; + /** otgfs_gintmsk_incomplpmsk : R/W; bitpos: [21]; default: 0; + * Incomplete Periodic Transfer Mask (incomplPMsk) + * Mode: Host only + * Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk) + * Mode: Device only + */ + uint32_t otgfs_gintmsk_incomplpmsk:1; + /** otgfs_gintmsk_fetsuspmsk : R/W; bitpos: [22]; default: 0; + * Mode: Device only + * Data Fetch Suspended Mask (FetSuspMsk) + */ + uint32_t otgfs_gintmsk_fetsuspmsk:1; + /** otgfs_gintmsk_resetdetmsk : R/W; bitpos: [23]; default: 0; + * Mode: Device only + * Reset detected Interrupt Mask (ResetDetMsk) + */ + uint32_t otgfs_gintmsk_resetdetmsk:1; + /** otgfs_gintmsk_prtintmsk : R/W; bitpos: [24]; default: 0; + * Mode: Host only + * Host Port Interrupt Mask (PrtIntMsk) + */ + uint32_t otgfs_gintmsk_prtintmsk:1; + /** otgfs_gintmsk_hchintmsk : R/W; bitpos: [25]; default: 0; + * Mode: Host only + * Host Channels Interrupt Mask (HChIntMsk) + */ + uint32_t otgfs_gintmsk_hchintmsk:1; + /** otgfs_gintmsk_ptxfempmsk : R/W; bitpos: [26]; default: 0; + * Mode: Host only + * Periodic TxFIFO Empty Mask (PTxFEmpMsk) + */ + uint32_t otgfs_gintmsk_ptxfempmsk:1; + uint32_t reserved_27:1; + /** otgfs_gintmsk_conidstschngmsk : R/W; bitpos: [28]; default: 0; + * Mode: Host and Device + * Connector ID Status Change Mask (ConIDStsChngMsk) + */ + uint32_t otgfs_gintmsk_conidstschngmsk:1; + /** otgfs_gintmsk_disconnintmsk : R/W; bitpos: [29]; default: 0; + * Mode: Host and Device + * Disconnect Detected Interrupt Mask (DisconnIntMsk) + */ + uint32_t otgfs_gintmsk_disconnintmsk:1; + /** otgfs_gintmsk_sessreqintmsk : R/W; bitpos: [30]; default: 0; + * Mode: Host and Device + * Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + */ + uint32_t otgfs_gintmsk_sessreqintmsk:1; + /** otgfs_gintmsk_wkupintmsk : R/W; bitpos: [31]; default: 0; + * Mode: Host and Device + * Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + * The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in + * suspend state. + */ + uint32_t otgfs_gintmsk_wkupintmsk:1; + }; + uint32_t val; +} usb_otgfs_gintmsk_reg_t; + + +/** Group: Receive Status Debug Read Register */ +/** Type of otgfs_grxstsr register + * Receive Status Debug Read Register A read to the Receive Status Debug Read register + * returns the contents of the top of the Receive FIFO. The receive status contents + * must be interpreted differently in Host and Device modes. The core ignores the + * receive status read when the receive FIFO is empty and returns a value of + * 32'h0000_0000. Note: - Use of these fields vary based on whether the core is + * functioning as a host or a device. - Do not read this register's reset value + * before configuring the core because the read value is 'X' in the simulation. + */ +typedef union { + struct { + /** otgfs_grxstsr_chnum : RO; bitpos: [3:0]; default: 0; + * Channel Number (ChNum) + * Mode: Host only + * Indicates the channel number to which the current received packet belongs. + * Endpoint Number (EPNum) + * Mode: Device only + * Indicates the endpoint number to which the current received packet belongs. + */ + uint32_t otgfs_grxstsr_chnum:4; + /** otgfs_grxstsr_bcnt : RO; bitpos: [14:4]; default: 0; + * Byte Count (BCnt) + * + * In host mode, indicates the byte count of the received IN data packet. + * + * In device mode, indicates the byte count of the received data packet. + */ + uint32_t otgfs_grxstsr_bcnt:11; + /** otgfs_grxstsr_dpid : RO; bitpos: [16:15]; default: 0; + * Data PID (DPID) + * + * In host mode, indicates the Data PID of the received packet. In device mode, + * indicates the Data PID of the received OUT data packet. + * - 2'b00: DATA0 + * - 2'b10: DATA1 + * - 2'b01: DATA2 + * - 2'b11: MDATA + * Reset: 2'h0 + */ + uint32_t otgfs_grxstsr_dpid:2; + /** otgfs_grxstsr_pktsts : RO; bitpos: [20:17]; default: 0; + * Packet Status (PktSts) indicates the status of the received packet. + * In host mode, + * - 4'b0010: IN data packet received + * - 4'b0011: IN transfer completed (triggers an interrupt) + * - 4'b0101: Data toggle error (triggers an interrupt) + * - 4'b0111: Channel halted (triggers an interrupt) + * - Others: Reserved + * Reset:4'b0 + * + * In device mode, + * - 4'b0001: Global OUT NAK (triggers an interrupt) + * - 4'b0010: OUT data packet received + * - 4'b0011: OUT transfer completed (triggers an interrupt) + * - 4'b0100: SETUP transaction completed (triggers an interrupt) + * - 4'b0110: SETUP data packet received + * - Others: Reserved + * Reset:4'h0 + */ + uint32_t otgfs_grxstsr_pktsts:4; + /** otgfs_grxstsr_fn : RO; bitpos: [24:21]; default: 0; + * Mode: Device only + * Frame Number (FN) + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported. + */ + uint32_t otgfs_grxstsr_fn:4; + uint32_t reserved_25:7; + }; + uint32_t val; +} usb_otgfs_grxstsr_reg_t; + + +/** Group: Receive Status Read/Pop Register */ +/** Type of otgfs_grxstsp register + * Receive Status Read/Pop Register A read to the Receive Status Read and Pop register + * returns the contents of the top of the Receive FIFO and additionally pops the top + * data entry out of the RxFIFO. The receive status contents must be interpreted + * differently in Host and Device modes. The core ignores the receive status pop/read + * when the receive FIFO is empty and returns a value of 32'h0000_0000. The + * application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty + * bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Note: - Use of + * these fields vary based on whether the core is functioning as a host or a device. + * - Do not read this register's reset value before configuring the core because the + * read value is 'X' in the simulation. + */ +typedef union { + struct { + /** otgfs_grxstsp_chnum : RO; bitpos: [3:0]; default: 0; + * Channel Number (ChNum) + * Mode: Host only + * Indicates the channel number to which the current received packet belongs. + * Endpoint Number (EPNum) + * Mode: Device only + * Indicates the endpoint number to which the current received packet belongs. + */ + uint32_t otgfs_grxstsp_chnum:4; + /** otgfs_grxstsp_bcnt : RO; bitpos: [14:4]; default: 0; + * Byte Count (BCnt) + * + * In host mode, indicates the byte count of the received IN data packet. + * + * In device mode, indicates the byte count of the received data packet. + */ + uint32_t otgfs_grxstsp_bcnt:11; + /** otgfs_grxstsp_dpid : RO; bitpos: [16:15]; default: 0; + * Data PID (DPID) + * + * In host mode, indicates the Data PID of the received packet. In device mode, + * indicates the Data PID of the received OUT data packet. + * - 2'b00: DATA0 + * - 2'b10: DATA1 + * - 2'b01: DATA2 + * - 2'b11: MDATA + * Reset: 2'h0 + */ + uint32_t otgfs_grxstsp_dpid:2; + /** otgfs_grxstsp_pktsts : RO; bitpos: [20:17]; default: 0; + * Packet Status (PktSts) indicates the status of the received packet. + * In host mode, + * - 4'b0010: IN data packet received + * - 4'b0011: IN transfer completed (triggers an interrupt) + * - 4'b0101: Data toggle error (triggers an interrupt) + * - 4'b0111: Channel halted (triggers an interrupt) + * - Others: Reserved + * Reset:4'b0 + * + * In device mode, + * - 4'b0001: Global OUT NAK (triggers an interrupt) + * - 4'b0010: OUT data packet received + * - 4'b0011: OUT transfer completed (triggers an interrupt) + * - 4'b0100: SETUP transaction completed (triggers an interrupt) + * - 4'b0110: SETUP data packet received + * - Others: Reserved + * Reset:4'h0 + */ + uint32_t otgfs_grxstsp_pktsts:4; + /** otgfs_grxstsp_fn : RO; bitpos: [24:21]; default: 0; + * Mode: Device only + * Frame Number (FN) + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported. + */ + uint32_t otgfs_grxstsp_fn:4; + uint32_t reserved_25:7; + }; + uint32_t val; +} usb_otgfs_grxstsp_reg_t; + + +/** Group: Receive FIFO Size Register */ +/** Type of otgfs_grxfsiz register + * Receive FIFO Size Register The application can program the RAM size that must be + * allocated to the RxFIFO. + */ +typedef union { + struct { + /** otgfs_grxfsiz_rxfdep : R/W; bitpos: [8:0]; default: 256; + * Mode: Host and Device + * RxFIFO Depth (RxFDep) + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * The power-on reset value of this register is specified as the Largest Rx Data FIFO + * Depth during configuration. + * If Enable Dynamic FIFO Sizing is selected in coreConsultant, these flops are + * optimized, and reads return the power-on value. + * If Enable Dynamic FIFO Sizing is selected in coreConsultant, you can write a new + * value in this field. Programmed values must not exceed the power-on value. + */ + uint32_t otgfs_grxfsiz_rxfdep:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} usb_otgfs_grxfsiz_reg_t; + + +/** Group: Non-periodic Transmit FIFO Size Register */ +/** Type of otgfs_gnptxfsiz register + * Non-periodic Transmit FIFO Size Register The application can program the RAM size + * and the memory start address for the Non-periodic TxFIFO Note: The fields of this + * register change depending on host or device mode. + */ +typedef union { + struct { + /** otgfs_gnptxfsiz_nptxfstaddr : R/W; bitpos: [8:0]; default: 256; + * Non-periodic Transmit RAM Start Address (NPTxFStAddr) + * For host mode, this field is always valid. + * This field contains the memory start address for Non-periodic Transmit FIFO RAM. + * - This field is determined during coreConsultant configuration by Enable Dynamic + * FIFO Sizing? (OTG_DFIFO_DYNAMIC):OTG_DFIFO_DYNAMIC = 0 + * These flops are optimized, and reads return the power-on value. + * - OTG_DFIFO_DYNAMIC = 1 The application can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + * Programmed values must not exceed the power-on value set in coreConsultant. + * The power-on reset value of this field is specified during coreConsultant + * configuration by Largest Rx Data FIFO Depth (parameter OTG_RX_DFIFO_DEPTH). + */ + uint32_t otgfs_gnptxfsiz_nptxfstaddr:9; + uint32_t reserved_9:7; + /** otgfs_gnptxfsiz_nptxfdep : R/W; bitpos: [24:16]; default: 256; + * Mode: Host only + * Non-periodic TxFIFO Depth (NPTxFDep) + * For host mode, this field is always valid. + * For device mode, this field is valid only when OTG_EN_DED_TX_FIFO=0. + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * This attribute of field is determined during coreConsultant configuration by Enable + * Dynamic FIFO Sizing? (OTG_DFIFO_DYNAMIC): + * - OTG_DFIFO_DYNAMIC = 0: These flops are optimized, and reads return the power-on + * value. + * - OTG_DFIFO_DYNAMIC = 1: The application can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + * The power-on reset value of this field is specified during coreConsultant + * configuration as Largest IN Endpoint FIFO 0 Depth (parameter + * OTG_TX_DINEP_DFIFO_DEPTH_0). + */ + uint32_t otgfs_gnptxfsiz_nptxfdep:9; + uint32_t reserved_25:7; + }; + uint32_t val; +} usb_otgfs_gnptxfsiz_reg_t; + + +/** Group: Non-periodic Transmit FIFO/Queue Status Register */ +/** Type of otgfs_gnptxsts register + * Non-periodic Transmit FIFO/Queue Status Register In Device mode, this register is + * valid only in Shared FIFO operation. This read-only register contains the free + * space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request + * Queue. + */ +typedef union { + struct { + /** otgfs_gnptxsts_nptxfspcavail : RO; bitpos: [15:0]; default: 256; + * Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + * Indicates the amount of free space available in the Non-periodic TxFIFO. + * Values are in terms of 32-bit words. + * - 16'h0: Non-periodic TxFIFO is full + * - 16'h1: 1 word available + * - 16'h2: 2 words available + * - 16'hn: n words available (where 0 <= n <= 32,768) + * - 16'h8000: 32,768 words available + * - Others: Reserved + * Reset: Configurable + */ + uint32_t otgfs_gnptxsts_nptxfspcavail:16; + /** otgfs_gnptxsts_nptxqspcavail : RO; bitpos: [23:16]; default: 4; + * Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + * Indicates the amount of free space available in the Non-periodic Transmit Request + * Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only + * IN requests. + * - 8'h0: Non-periodic Transmit Request Queue is full + * - 8'h1: 1 location available + * - 8'h2: 2 locations available + * - n: n locations available (0 <= n <= 8) + * - Others: Reserved + * Reset: Configurable + */ + uint32_t otgfs_gnptxsts_nptxqspcavail:8; + /** otgfs_gnptxsts_nptxqtop : RO; bitpos: [30:24]; default: 0; + * Top of the Non-periodic Transmit Request Queue (NPTxQTop) + * Entry in the Non-periodic Tx Request Queue that is currently being processed by the + * MAC. + * + * - Bits [30:27]: Channel/endpoint number + * - Bits [26:25]: + * - 2'b00: IN/OUT token + * -- 2'b01: Zero-length transmit packet (device IN/host OUT) + * -- 2'b10: PING/CSPLIT token + * -- 2'b11: Channel halt command + * - Bit [24]: Terminate (last Entry for selected channel/endpoint) + * Reset: 7'h0 + */ + uint32_t otgfs_gnptxsts_nptxqtop:7; + uint32_t reserved_31:1; + }; + uint32_t val; +} usb_otgfs_gnptxsts_reg_t; + + +/** Group: Synopsis ID Register */ +/** Type of otgfs_gsnpsid register + * Synopsis ID Register This read-only register contains the release number of the + * core being used. + */ +typedef union { + struct { + /** otgfs_gsnpsid_synopsysid : RO; bitpos: [31:0]; default: 1330921482; + * Release number of the controller being used currently. + */ + uint32_t otgfs_gsnpsid_synopsysid:32; + }; + uint32_t val; +} usb_otgfs_gsnpsid_reg_t; + + +/** Group: User Hardware Configuration 1 Register */ +/** Type of otgfs_ghwcfg1 register + * User Hardware Configuration 1 Register This register contains the logical endpoint + * direction(s) selected using coreConsultant. + */ +typedef union { + struct { + /** otgfs_ghwcfg1_epdir : RO; bitpos: [31:0]; default: 0; + * This 32-bit field uses two bits per + * endpoint to determine the endpoint direction. + * + * Endpoint + * - Bits [31:30]: Endpoint 15 direction + * - Bits [29:28]: Endpoint 14 direction + * ... + * - Bits [3:2]: Endpoint 1 direction + * - Bits[1:0]: Endpoint 0 direction (always BIDIR) + * Direction + * - 2'b00: BIDIR (IN and OUT) endpoint + * - 2'b01: IN endpoint + * - 2'b10: OUT endpoint + * - 2'b11: Reserved + * Note: This field is configured using the OTG_EP_DIR_1(n) parameter. + */ + uint32_t otgfs_ghwcfg1_epdir:32; + }; + uint32_t val; +} usb_otgfs_ghwcfg1_reg_t; + + +/** Group: User Hardware Configuration 2 Register */ +/** Type of otgfs_ghwcfg2 register + * User Hardware Configuration 2 Register This register contains configuration + * options selected using coreConsultant. + */ +typedef union { + struct { + /** otgfs_ghwcfg2_otgmode : RO; bitpos: [2:0]; default: 0; + * Mode of Operation (OtgMode) + * - 3'b000: HNP- and SRP-Capable OTG (Host & Device) + * - 3'b001: SRP-Capable OTG (Host & Device) + * - 3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device) + * - 3'b011: SRP-Capable Device + * - 3'b100: Non-OTG Device + * - 3'b101: SRP-Capable Host + * - 3'b110: Non-OTG Host + * - Others: Reserved + * Note: This field is configured using the OTG_MODE parameter. + */ + uint32_t otgfs_ghwcfg2_otgmode:3; + /** otgfs_ghwcfg2_otgarch : RO; bitpos: [4:3]; default: 2; + * Architecture (OtgArch) + * - 2'b00: Slave-Only + * - 2'b01: External DMA + * - 2'b10: Internal DMA + * - Others: Reserved + * Note: This field is configured using the OTG_ARCHITECTURE parameter. + */ + uint32_t otgfs_ghwcfg2_otgarch:2; + /** otgfs_ghwcfg2_singpnt : RO; bitpos: [5]; default: 1; + * Point-to-Point (SingPnt) + * - 1'b0: Multi-point application (hub and split support) + * - 1'b1: Single-point application (no hub and split support) + * Note: This field is configured using the OTG_SINGLE_POINT parameter. + */ + uint32_t otgfs_ghwcfg2_singpnt:1; + /** otgfs_ghwcfg2_hsphytype : RO; bitpos: [7:6]; default: 0; + * High-Speed PHY Interface Type (HSPhyType) + * - 2'b00: High-Speed interface not supported + * - 2'b01: UTMI+ + * - 2'b10: ULPI + * - 2'b11: UTMI+ and ULPI + * Note: This field is configured using the OTG_HSPHY_INTERFACE parameter. + */ + uint32_t otgfs_ghwcfg2_hsphytype:2; + /** otgfs_ghwcfg2_fsphytype : RO; bitpos: [9:8]; default: 1; + * Full-Speed PHY Interface Type (FSPhyType) + * - 2'b00: Full-speed interface not supported + * - 2'b01: Dedicated full-speed interface + * - 2'b10: FS pins shared with UTMI+ pins + * - 2'b11: FS pins shared with ULPI pins + * Note: This field is configured using the OTG_FSPHY_INTERFACE parameter. + */ + uint32_t otgfs_ghwcfg2_fsphytype:2; + /** otgfs_ghwcfg2_numdeveps : RO; bitpos: [13:10]; default: 6; + * Number of Device Endpoints (NumDevEps) + * + * Indicates the number of device endpoints supported by the core in Device mode. + * + * The range of this field is 0-15. + * + * Note: This field is configured using the OTG_NUM_EPS parameter. + */ + uint32_t otgfs_ghwcfg2_numdeveps:4; + /** otgfs_ghwcfg2_numhstchnl : RO; bitpos: [17:14]; default: 7; + * Number of Host Channels (NumHstChnl) + * Indicates the number of host channels supported by the core in Host mode. The range + * of this field is 0-15: 0 specifies 1 channel, 15 specifies 16 channels. + * + * Note: This field is configured using the OTG_NUM_HOST_CHAN parameter. + */ + uint32_t otgfs_ghwcfg2_numhstchnl:4; + /** otgfs_ghwcfg2_periosupport : RO; bitpos: [18]; default: 1; + * Periodic OUT Channels Supported in Host Mode (PerioSupport) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_EN_PERIO_HOST parameter. + */ + uint32_t otgfs_ghwcfg2_periosupport:1; + /** otgfs_ghwcfg2_dynfifosizing : RO; bitpos: [19]; default: 1; + * Dynamic FIFO Sizing Enabled (DynFifoSizing) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_DFIFO_DYNAMIC parameter. + */ + uint32_t otgfs_ghwcfg2_dynfifosizing:1; + /** otgfs_ghwcfg2_multiprocintrpt : RO; bitpos: [20]; default: 0; + * Multi Processor Interrupt Enabled (MultiProcIntrpt) + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_MULTI_PROC_INTRPT parameter. + */ + uint32_t otgfs_ghwcfg2_multiprocintrpt:1; + uint32_t reserved_21:1; + /** otgfs_ghwcfg2_nptxqdepth : RO; bitpos: [23:22]; default: 1; + * Non-periodic Request Queue Depth (NPTxQDepth) + * - 2'b00: 2 + * - 2'b01: 4 + * - 2'b10: 8 + * - Others: Reserved + * Note: This field is configured using the OTG_NPERIO_TX_QUEUE_DEPTH parameter. + */ + uint32_t otgfs_ghwcfg2_nptxqdepth:2; + /** otgfs_ghwcfg2_ptxqdepth : RO; bitpos: [25:24]; default: 2; + * Host Mode Periodic Request Queue Depth (PTxQDepth) + * - 2'b00: 2 + * - 2'b01: 4 + * - 2'b10: 8 + * - 2'b11:16 + * Note: This field is configured using the OTG_PERIO_TX_QUEUE_DEPTH parameter. + */ + uint32_t otgfs_ghwcfg2_ptxqdepth:2; + /** otgfs_ghwcfg2_tknqdepth : RO; bitpos: [30:26]; default: 8; + * Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + * Range: 0-30 + * + * Note: This field is configured using the OTG_TOKEN_QUEUE_DEPTH parameter. + */ + uint32_t otgfs_ghwcfg2_tknqdepth:5; + uint32_t reserved_31:1; + }; + uint32_t val; +} usb_otgfs_ghwcfg2_reg_t; + + +/** Group: User Hardware Configuration 3 Register */ +/** Type of otgfs_ghwcfg3 register + * User Hardware Configuration 3 Register + */ +typedef union { + struct { + /** otgfs_ghwcfg3_xfersizewidth : RO; bitpos: [3:0]; default: 5; + * Width of Transfer Size Counters (XferSizeWidth) + * - 4'b0000: 11 bits + * - 4'b0001: 12 bits + * ... + * - 4'b1000: 19 bits + * - Others: Reserved + * Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter. + */ + uint32_t otgfs_ghwcfg3_xfersizewidth:4; + /** otgfs_ghwcfg3_pktsizewidth : RO; bitpos: [6:4]; default: 3; + * Width of Packet Size Counters (PktSizeWidth) + * - 3'b000: 4 bits + * - 3'b001: 5 bits + * - 3'b010: 6 bits + * - 3'b011: 7 bits + * - 3'b100: 8 bits + * - 3'b101: 9 bits + * - 3'b110: 10 bits + * - Others: Reserved + * Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter. + */ + uint32_t otgfs_ghwcfg3_pktsizewidth:3; + /** otgfs_ghwcfg3_otgen : RO; bitpos: [7]; default: 1; + * OTG Function Enabled (OtgEn) + * + * The application uses this bit to indicate the OTG capabilities of the controller . + * - 1'b0: Not OTG capable + * - 1'b1: OTG Capable + * Note: This field is configured using the OTG_MODE parameter. + */ + uint32_t otgfs_ghwcfg3_otgen:1; + /** otgfs_ghwcfg3_i2cintsel : RO; bitpos: [8]; default: 0; + * I2C Selection (I2CIntSel) + * - 1'b0: I2C Interface is not available on the controller. + * - 1'b1: I2C Interface is available on the controller. + * Note: This field is configured using the OTG_I2C_INTERFACE parameter. + */ + uint32_t otgfs_ghwcfg3_i2cintsel:1; + /** otgfs_ghwcfg3_vndctlsupt : RO; bitpos: [9]; default: 0; + * Vendor Control Interface Support (VndctlSupt) + * + * - 1'b0: Vendor Control Interface is not available on the core. + * - 1'b1: Vendor Control Interface is available. + * Note: This field is configured using the OTG_VENDOR_CTL_INTERFACE parameter. + */ + uint32_t otgfs_ghwcfg3_vndctlsupt:1; + /** otgfs_ghwcfg3_optfeature : RO; bitpos: [10]; default: 1; + * Optional Features Removed (OptFeature) + * Indicates whether the User ID register, GPIO interface ports, and SOF toggle and + * counter ports were removed for gate count optimization by enabling Remove Optional + * Features. + * - 1'b0: No + * - 1'b1: Yes + * Note: This field is configured using the OTG_RM_OPT_FEATURES parameter. + */ + uint32_t otgfs_ghwcfg3_optfeature:1; + /** otgfs_ghwcfg3_rsttype : RO; bitpos: [11]; default: 0; + * Reset Style for Clocked always Blocks in RTL (RstType) + * - 1'b0: Asynchronous reset is used in the controller + * - 1'b1: Synchronous reset is used in the controller + * Note: This field is configured using the OTG_SYNC_RESET_TYPE parameter. + */ + uint32_t otgfs_ghwcfg3_rsttype:1; + /** otgfs_ghwcfg3_adpsupport : RO; bitpos: [12]; default: 0; + * This bit indicates whether ADP logic is present within or external to the controller + * - 0: No ADP logic present with the controller + * - 1: ADP logic is present along with the controller. + */ + uint32_t otgfs_ghwcfg3_adpsupport:1; + /** otgfs_ghwcfg3_hsicmode : RO; bitpos: [13]; default: 0; + * HSIC mode specified for Mode of Operation + * Value Range: 0 - 1 + * - 1: HSIC-capable with shared UTMI PHY interface + * - 0: Non-HSIC-capable + */ + uint32_t otgfs_ghwcfg3_hsicmode:1; + /** otgfs_ghwcfg3_bcsupport : RO; bitpos: [14]; default: 0; + * This bit indicates the controller support for Battery Charger. + * - 0 - No Battery Charger Support + * - 1 - Battery Charger support present + */ + uint32_t otgfs_ghwcfg3_bcsupport:1; + /** otgfs_ghwcfg3_lpmmode : RO; bitpos: [15]; default: 0; + * LPM mode specified for Mode of Operation. + */ + uint32_t otgfs_ghwcfg3_lpmmode:1; + /** otgfs_ghwcfg3_dfifodepth : RO; bitpos: [31:16]; default: 200; + * DFIFO Depth (DfifoDepth - EP_LOC_CNT) + * + * This value is in terms of 32-bit words. + * - Minimum value is 32 + * - Maximum value is 32,768 + * Note: This field is configured using the OTG_DFIFO_DEPTH parameter. For more + * information on EP_LOC_CNT, see the Endpoint Information Controller (EPINFO_CTL) + * section. + */ + uint32_t otgfs_ghwcfg3_dfifodepth:16; + }; + uint32_t val; +} usb_otgfs_ghwcfg3_reg_t; + + +/** Group: User Hardware Configuration 4 Register */ +/** Type of otgfs_ghwcfg4 register + * User Hardware Configuration 4 Register Note Bit [31] is available only when + * Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this + * field is reserved. + */ +typedef union { + struct { + /** otgfs_ghwcfg4_numdevperioeps : RO; bitpos: [3:0]; default: 0; + * Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + * + * Range: 0-15 + */ + uint32_t otgfs_ghwcfg4_numdevperioeps:4; + /** otgfs_ghwcfg4_partialpwrdn : RO; bitpos: [4]; default: 1; + * Enable Partial Power Down (PartialPwrDn) + * - 1'b0: Partial Power Down Not Enabled + * - 1'b1: Partial Power Down Enabled + */ + uint32_t otgfs_ghwcfg4_partialpwrdn:1; + /** otgfs_ghwcfg4_ahbfreq : RO; bitpos: [5]; default: 1; + * Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + * - 1'b0: No + * - 1'b1: Yes + */ + uint32_t otgfs_ghwcfg4_ahbfreq:1; + /** otgfs_ghwcfg4_hibernation : RO; bitpos: [6]; default: 0; + * Enable Hibernation (Hibernation) + * - 1'b0: Hibernation feature not enabled + * - 1'b1: Hibernation feature enabled + */ + uint32_t otgfs_ghwcfg4_hibernation:1; + /** otgfs_ghwcfg4_extendedhibernation : RO; bitpos: [7]; default: 0; + * Enable Hibernation + * - 1'b0: Extended Hibernation feature not enabled + * - 1'b1: Extended Hibernation feature enabled + */ + uint32_t otgfs_ghwcfg4_extendedhibernation:1; + uint32_t reserved_8:4; + /** otgfs_ghwcfg4_acgsupt : RO; bitpos: [12]; default: 0; + * Active Clock Gating Support + * + * This bit indicates that the controller supports the Dynamic (Switching) Power + * Reduction during periods + * when there is no USB and AHB Traffic. + * - 1'b0: Active Clock Gating is not enabled. + * - 1'b1: Active Clock Gating Enabled. + */ + uint32_t otgfs_ghwcfg4_acgsupt:1; + /** otgfs_ghwcfg4_enhancedlpmsupt : RO; bitpos: [13]; default: 1; + * Enhanced LPM Support (EnhancedLPMSupt) + * + * This bit indicates that the controller supports the following behavior: + * L1 Entry Behavior based on FIFO Status + * - TX FIFO + * - Accept L1 Request even if ISOC OUT TX FIFO is not empty. + * - Reject L1 Request if Non-Periodic TX FIFO is not empty. + * - Ensure application can flush the TX FIFO while the Controller is in L1. + * - RX FIFO + * - Accept L1 Request even if RX FIFO (common to Periodic and Non-Periodic) is not + * empty. + * - Accept L1 Request but delay SLEEPM assertion until RX SINK Buffer is empty. + * + * Prevent L1 Entry if a Control Transfer is in progress on any Control Endpoint. + * Ability to Flush TxFIFO even if PHY Clock is gated. + * + */ + uint32_t otgfs_ghwcfg4_enhancedlpmsupt:1; + /** otgfs_ghwcfg4_phydatawidth : RO; bitpos: [15:14]; default: 2; + * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + * (PhyDataWidth)When a ULPI PHY is used, an internal wrapper converts ULPI to + * UTMI+. + * - 2'b00: 8 bits + * - 2'b01: 16 bits + * - 2'b10: 8/16 bits, software selectable + * - Others: Reserved + */ + uint32_t otgfs_ghwcfg4_phydatawidth:2; + /** otgfs_ghwcfg4_numctleps : RO; bitpos: [19:16]; default: 0; + * Number of Device Mode Control Endpoints in Addition to + * Endpoint 0 (NumCtlEps) + * Range: 0-15 + */ + uint32_t otgfs_ghwcfg4_numctleps:4; + /** otgfs_ghwcfg4_iddgfltr : RO; bitpos: [20]; default: 1; + * IDDIG Filter Enable (IddgFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ + uint32_t otgfs_ghwcfg4_iddgfltr:1; + /** otgfs_ghwcfg4_vbusvalidfltr : RO; bitpos: [21]; default: 1; + * VBUS Valid Filter Enabled (VBusValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ + uint32_t otgfs_ghwcfg4_vbusvalidfltr:1; + /** otgfs_ghwcfg4_avalidfltr : RO; bitpos: [22]; default: 1; + * a_valid Filter Enabled (AValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ + uint32_t otgfs_ghwcfg4_avalidfltr:1; + /** otgfs_ghwcfg4_bvalidfltr : RO; bitpos: [23]; default: 1; + * b_valid Filter Enabled (BValidFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ + uint32_t otgfs_ghwcfg4_bvalidfltr:1; + /** otgfs_ghwcfg4_sessendfltr : RO; bitpos: [24]; default: 1; + * session_end Filter Enabled (SessEndFltr) + * - 1'b0: No filter + * - 1'b1: Filter + */ + uint32_t otgfs_ghwcfg4_sessendfltr:1; + /** otgfs_ghwcfg4_dedfifomode : RO; bitpos: [25]; default: 1; + * Enable Dedicated Transmit FIFO for device IN Endpoints + * (DedFifoMode) + * - 1'b0 : Dedicated Transmit FIFO Operation not enabled. + * - 1'b1 : Dedicated Transmit FIFO Operation enabled. + */ + uint32_t otgfs_ghwcfg4_dedfifomode:1; + /** otgfs_ghwcfg4_ineps : RO; bitpos: [29:26]; default: 4; + * Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + * - 0: 1 IN Endpoint + * - 1: 2 IN Endpoints + * .... + * - 15: 16 IN Endpoints + */ + uint32_t otgfs_ghwcfg4_ineps:4; + /** otgfs_ghwcfg4_descdmaenabled : RO; bitpos: [30]; default: 1; + * Scatter/Gather DMA configuration + * - 1'b0: Non-Scatter/Gather DMA configuration + * - 1'b1: Scatter/Gather DMA configuration + */ + uint32_t otgfs_ghwcfg4_descdmaenabled:1; + /** otgfs_ghwcfg4_descdma : RO; bitpos: [31]; default: 1; + * Scatter/Gather DMA configuration + * - 1'b0: Non Dynamic configuration + * - 1'b1: Dynamic configuration + * Note: This field is configured using the OTG_EN_DESC_DMA parameter. + */ + uint32_t otgfs_ghwcfg4_descdma:1; + }; + uint32_t val; +} usb_otgfs_ghwcfg4_reg_t; + + +/** Group: Global DFIFO Configuration Register */ +/** Type of otgfs_gdfifocfg register + * Global DFIFO Configuration Register + */ +typedef union { + struct { + /** otgfs_gdfifocfg_gdfifocfg : R/W; bitpos: [15:0]; default: 256; + * GDFIFOCfg + * + * This field is for dynamic programming of the DFIFO Size. This value takes effect + * only when the application programs a non zero value to this register. The value + * programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The + * core does not have any corrective logic if the FIFO sizes are programmed + * incorrectly. + */ + uint32_t otgfs_gdfifocfg_gdfifocfg:16; + /** otgfs_gdfifocfg_epinfobaseaddr : R/W; bitpos: [31:16]; default: 200; + * EPInfoBaseAddr + * + * This field provides the start address of the EP info controller. + */ + uint32_t otgfs_gdfifocfg_epinfobaseaddr:16; + }; + uint32_t val; +} usb_otgfs_gdfifocfg_reg_t; + + +/** Group: Host Periodic Transmit FIFO Size Register */ +/** Type of otgfs_hptxfsiz register + * Host Periodic Transmit FIFO Size Register This register holds the size and the + * memory start address of the Periodic TxFIFO. Note: Read the reset value of this + * register only after the following conditions: - If IDDIG_FILTER is disabled, read + * only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the + * filter timer expires. + */ +typedef union { + struct { + /** otgfs_hptxfsiz_ptxfstaddr : R/W; bitpos: [9:0]; default: 512; + * Host Periodic TxFIFO Start Address (PTxFStAddr) + * + * The power-on reset value of this register is the sum of the Largest Rx Data FIFO + * Depth and Largest Non-periodic Tx Data FIFO Depth.These parameters are: + * + * In shared FIFO operation: + * - OTG_RX_DFIFO_DEPTH + OTG_TX_NPERIO_DFIFO_DEPTH + * + * In dedicated FIFO mode: + * - OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH If Enable Dynamic FIFO Sizing? + * was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are + * optimized, and reads return the power-on value. If Enable Dynamic FIFO Sizing? was + * selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new + * value in this field. + * + * Programmed values must not exceed the power-on value set in coreConsultant. + */ + uint32_t otgfs_hptxfsiz_ptxfstaddr:10; + uint32_t reserved_10:6; + /** otgfs_hptxfsiz_ptxfsize : R/W; bitpos: [24:16]; default: 256; + * Host Periodic TxFIFO Depth (PTxFSize) + * + * This value is in terms of 32-bit words. + * - Minimum value is 16 + * - Maximum value is 32,768 + * The power-on reset value of this register is specified as the Largest Host Mode + * Periodic Tx Data FIFO Depth. + * - If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter + * OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on + * value. + * - If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter + * OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. + * Programmed values must not exceed the power-on value set in coreConsultant. + */ + uint32_t otgfs_hptxfsiz_ptxfsize:9; + uint32_t reserved_25:7; + }; + uint32_t val; +} usb_otgfs_hptxfsiz_reg_t; + + +/** Group: Device IN Endpoint Transmit FIFO Size Register $i */ +/** Type of otgfs_dieptxf1 register + * Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in + * dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start + * address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data + * for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 + * to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and + * memory start address. + */ +typedef union { + struct { + /** otgfs_dieptxf1_inepntxfstaddr : R/W; bitpos: [9:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * + * This field contains the memory start address for IN endpoint Transmit FIFOn (0 Slave mode + * - GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid + * - GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode + * - GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode + */ + uint32_t otgfs_hcfg_descdma:1; + /** otgfs_hcfg_frlisten : R/W; bitpos: [25:24]; default: 0; + * Frame List Entries(FrListEn) + * + * The value in the register specifies the number of entries in the Frame list. + * This field is valid only in Scatter/Gather DMA mode. + * - 2'b00: 8 Entries + * - 2'b01: 16 Entries + * - 2'b10: 32 Entries + * - 2'b11: 64 Entries + */ + uint32_t otgfs_hcfg_frlisten:2; + /** otgfs_hcfg_perschedena : R/W; bitpos: [26]; default: 0; + * Enable Periodic Scheduling (PerSchedEna): + * + * Applicable in host DDMA mode only. + * Enables periodic scheduling within the core. Initially, the bit is reset. + * The core will not process any periodic channels. + * + * As soon as this bit is set, + * the core will get ready to start scheduling periodic channels and + * sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core + * has enabled periodic scheduling. Once HCFG.PerSchedEna is set, + * the application is not supposed to again reset the bit unless HCFG.PerSchedStat + * is set. + * + * As soon as this bit is reset, the core will get ready to + * stop scheduling periodic channels and resets HCFG.PerSchedStat. + */ + uint32_t otgfs_hcfg_perschedena:1; + uint32_t reserved_27:4; + /** otgfs_hcfg_modechtimen : R/W; bitpos: [31]; default: 0; + * Mode Change Ready Timer Enable (ModeChTimEn) + * + * This bit is used to enable/disable the Host core to wait 200 PHY clock cycles at + * the end of Resume to change the opmode signal to the PHY to 00 + * after Suspend or LPM. + * - 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 + * at the end of resume to the change the opmode from 2'b10 to 2'b00 + * - 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to + * change the opmode from 2'b10 to 2'b00. + */ + uint32_t otgfs_hcfg_modechtimen:1; + }; + uint32_t val; +} usb_otgfs_hcfg_reg_t; + + +/** Group: Host Frame Interval Register */ +/** Type of otgfs_hfir register + * Host Frame Interval Register + */ +typedef union { + struct { + /** otgfs_hfir_frint : R/W; bitpos: [15:0]; default: 60000; + * Frame Interval (FrInt) + * + * The value that the application programs to this field specifies + * the interval between two consecutive SOFs (FS) or micro- + * SOFs (HS) or Keep-Alive tokens (HS). This field contains the + * number of PHY clocks that constitute the required frame + * interval. The Default value set in this field is for FS operation + * when the PHY clock frequency is 60 MHz. The application can + * write a value to this register only after the Port Enable bit of the + * Host Port Control and Status register (HPRT.PrtEnaPort) has + * been Set. If no value is programmed, the core calculates the + * value based on the PHY clock specified in the FS/LS PHY + * Clock Select field of the Host Configuration register + * (HCFG.FSLSPclkSel). Do not change the value of this field + * after the initial configuration. + * - 125 s * (PHY clock frequency for HS) + * - 1 ms * (PHY clock frequency for FS/LS) + */ + uint32_t otgfs_hfir_frint:16; + /** otgfs_hfir_hfirrldctrl : R/W; bitpos: [16]; default: 0; + * Reload Control (HFIRRldCtrl) + * + * This bit allows dynamic reloading of the HFIR register during run time. + * - 1'b0 : The HFIR cannot be reloaded dynamically + * - 1'b1: the HFIR can be dynamically reloaded during runtime. + * This bit needs to be programmed during initial configuration and its value should + * not be changed during runtime. + */ + uint32_t otgfs_hfir_hfirrldctrl:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} usb_otgfs_hfir_reg_t; + + +/** Group: Host Frame Number/Frame Time Remaining Register */ +/** Type of otgfs_hfnum register + * Host Frame Number/Frame Time Remaining Register This register indicates the + * current frame number. It also indicates the time remaining (in terms of the number + * of PHY clocks) in the current (micro)frame. Note: Read the reset value of this + * register only after the following conditions: - If IDDIG_FILTER is disabled, read + * only when the PHY clock is stable. - If IDDIG_FILTER is enabled, read only after + * the filter timer expires. + */ +typedef union { + struct { + /** otgfs_hfnum_frnum : RO; bitpos: [15:0]; default: 16383; + * Frame Number (FrNum) + * + * This field increments when a new SOF is transmitted on the + * USB, and is reset to 0 when it reaches 16'h3FFF. + */ + uint32_t otgfs_hfnum_frnum:16; + /** otgfs_hfnum_frrem : RO; bitpos: [31:16]; default: 0; + * Frame Time Remaining (FrRem) + * + * Indicates the amount of time remaining in the current + * microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This + * field decrements on each PHY clock. When it reaches zero, this + * field is reloaded with the value in the Frame Interval register and + * a new SOF is transmitted on the USB. + */ + uint32_t otgfs_hfnum_frrem:16; + }; + uint32_t val; +} usb_otgfs_hfnum_reg_t; + + +/** Group: Host Periodic Transmit FIFO/Queue Status Register */ +/** Type of otgfs_hptxsts register + * Host Periodic Transmit FIFO/Queue Status Register + */ +typedef union { + struct { + /** otgfs_hptxsts_ptxfspcavail : RO; bitpos: [15:0]; default: 256; + * Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) + * + * Indicates the number of free locations available to be written to in the Periodic + * TxFIFO. + * + * Values are in terms of 32-bit words + * - 16'h0 : Periodic TxFIFO is full + * - 16'h1 : 1 word available + * - 16'h2 : 2 words available + * - 16'hn : n words available (where 0 n 32,768) + * - 16'h8000 : 32,768 words + * - Others : Reserved + */ + uint32_t otgfs_hptxsts_ptxfspcavail:16; + /** otgfs_hptxsts_ptxqspcavail : RO; bitpos: [23:16]; default: 8; + * Periodic Transmit Request Queue Space Available (PTxQSpcAvail) + * + * Indicates the number of free locations available to be written in the Periodic + * Transmit Request Queue. This queue holds both IN and OUT requests. + * - 8'h0: Periodic Transmit Request Queue is full + * - 8'h1: 1 location available + * - 8'h2: 2 locations available + * - n: n locations available (0 <= n <= 16) + * - Others: Reserved + */ + uint32_t otgfs_hptxsts_ptxqspcavail:8; + /** otgfs_hptxsts_ptxqtop : RO; bitpos: [31:24]; default: 0; + * Top of the Periodic Transmit Request Queue (PTxQTop) + * + * This indicates the Entry in the Periodic Tx Request Queue that is + * currently being processes by the MAC. + * + * This register is used for debugging. + * - Bit [31]: Odd/Even (micro)Frame + * -- 1'b0: send in even (micro)Frame + * -- 1'b1: send in odd (micro)Frame + * - Bits [30:27]: Channel/endpoint number + * - Bits [26:25]: Type + * -- 2'b00: IN/OUT + * -- 2'b01: Zero-length packet + * -- 2'b10: CSPLIT + * -- 2'b11: Disable channel command + * - Bit [24]: Terminate (last Entry for the selected channel/endpoint) + */ + uint32_t otgfs_hptxsts_ptxqtop:8; + }; + uint32_t val; +} usb_otgfs_hptxsts_reg_t; + + +/** Group: Host All Channels Interrupt Register */ +/** Type of otgfs_haint register + * Host All Channels Interrupt Register When a significant event occurs on a channel, + * the Host All Channels Interrupt register interrupts the application using the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is + * shown in the Interrupt Hierarchy figure in the databook. There is one interrupt bit + * per channel, up to a maximum of 16 bits. Bits in this register are set and cleared + * when the application sets and clears bits in the corresponding Host Channel-n + * Interrupt register. + */ +typedef union { + struct { + /** otgfs_haint_haint : RO; bitpos: [7:0]; default: 0; + * + * Channel Interrupt for channel no. + */ + uint32_t otgfs_haint_haint:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_otgfs_haint_reg_t; + + +/** Group: Host All Channels Interrupt Mask Register */ +/** Type of otgfs_haintmsk register + * Host All Channels Interrupt Mask Register The Host All Channel Interrupt Mask + * register works with the Host All Channel Interrupt register to interrupt the + * application when an event occurs on a channel. There is one interrupt mask bit per + * channel, up to a maximum of 16 bits. + */ +typedef union { + struct { + /** otgfs_haintmsk_haintmsk : R/W; bitpos: [7:0]; default: 0; + * Channel Interrupt Mask (HAINTMsk) + * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 + */ + uint32_t otgfs_haintmsk_haintmsk:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_otgfs_haintmsk_reg_t; + + +/** Group: Host Frame List Base Address Register */ +/** Type of otgfs_hflbaddr register + * Host Frame List Base Address Register This register is present only in case of + * Scatter/Gather DMA. It is implemented as flops. This register holds the starting + * address of the Frame list information. + */ +typedef union { + struct { + /** otgfs_hflbaddr_hflbaddr : R/W; bitpos: [31:0]; default: 0; + * The starting address of the Frame list. + * This register is used only for Isochronous and Interrupt Channels. + */ + uint32_t otgfs_hflbaddr_hflbaddr:32; + }; + uint32_t val; +} usb_otgfs_hflbaddr_reg_t; + + +/** Group: Host Port Control and Status Register */ +/** Type of otgfs_hprt register + * Host Port Control and Status Register This register is available only in Host + * mode. Currently, the OTG Host supports only one port. A single register holds USB + * port-related information such as USB reset, enable, suspend, resume, connect + * status, and test mode for each port. It is shown in the Interrupt Hierarchy figure + * in the databook. The R_SS_WC bits in this register can trigger an interrupt to the + * application through the Host Port Interrupt bit of the Core Interrupt register + * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and + * clear the bit that caused the interrupt. For the R_SS_WC bits, the application must + * write a 1 to the bit to clear the interrupt. + */ +typedef union { + struct { + /** otgfs_hprt_prtconnsts : RO; bitpos: [0]; default: 0; + * Port Connect Status (PrtConnSts) + * - 0: No device is attached to the port. + * - 1: A device is attached to the port. + */ + uint32_t otgfs_hprt_prtconnsts:1; + /** otgfs_hprt_prtconndet : R/W; bitpos: [1]; default: 0; + * Port Connect Detected (PrtConnDet) + * + * The core sets this bit when a device connection is detected + * to trigger an interrupt to the application using the Host Port + * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set + * only by the core and the application should write 1 to clear it.The application + * must write a 1 to this bit to clear the + * interrupt. + */ + uint32_t otgfs_hprt_prtconndet:1; + /** otgfs_hprt_prtena : R/W; bitpos: [2]; default: 0; + * Port Enable (PrtEna) + * + * A port is enabled only by the core after a reset sequence, + * and is disabled by an overcurrent condition, a disconnect + * condition, or by the application clearing this bit. The + * application cannot Set this bit by a register write. It can only + * clear it to disable the port by writing 1. This bit does not trigger any + * interrupt to the application. + * - 1'b0: Port disabled + * - 1'b1: Port enabled + */ + uint32_t otgfs_hprt_prtena:1; + /** otgfs_hprt_prtenchng : R/W; bitpos: [3]; default: 0; + * Port Enable/Disable Change (PrtEnChng) + * + * The core sets this bit when the status of the Port Enable bit [2] of this register + * changes.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hprt_prtenchng:1; + /** otgfs_hprt_prtovrcurract : RO; bitpos: [4]; default: 0; + * Port Overcurrent Active (PrtOvrCurrAct) + * + * Indicates the overcurrent condition of the port. + * - 1'b0: No overcurrent condition + * - 1'b1: Overcurrent condition + */ + uint32_t otgfs_hprt_prtovrcurract:1; + /** otgfs_hprt_prtovrcurrchng : R/W; bitpos: [5]; default: 0; + * Port Overcurrent Change (PrtOvrCurrChng) + * + * The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) + * in this register changes.This bit can be set only by the core and the application + * should write 1 to clear it + */ + uint32_t otgfs_hprt_prtovrcurrchng:1; + /** otgfs_hprt_prtres : R/W; bitpos: [6]; default: 0; + * Port Resume (PrtRes) + * + * The application sets this bit to drive resume signaling on the + * port. The core continues to drive the resume signal until the + * application clears this bit. + * + * If the core detects a USB remote wakeup sequence, as + * indicated by the Port Resume/Remote Wakeup Detected + * Interrupt bit of the Core Interrupt register + * (GINTSTS.WkUpInt), the core starts driving resume + * signaling without application intervention and clears this bit + * when it detects a disconnect condition. The read value of + * this bit indicates whether the core is currently driving + * resume signaling. + * - 1'b0: No resume driven + * - 1'b1: Resume driven + * When LPM is enabled, In L1 state the behavior of this bit is as follows: + * The application sets this bit to drive resume signaling on the port. + * The core continues to drive the resume signal until a pre-determined time + * specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote + * wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected + * Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), + * the core starts driving resume signaling without application intervention + * and clears this bit at the end of resume.This bit can be set by both core or + * application + * and also cleared by core or application. This bit is cleared by the core even if + * there is + * no device connected to the Host. + */ + uint32_t otgfs_hprt_prtres:1; + /** otgfs_hprt_prtsusp : R/W; bitpos: [7]; default: 0; + * Port Suspend (PrtSusp) + * + * The application sets this bit to put this port in Suspend + * mode. The core only stops sending SOFs when this is Set. + * To stop the PHY clock, the application must Set the Port + * Clock Stop bit, which asserts the suspend input pin of the + * PHY. + * + * The read value of this bit reflects the current suspend status + * of the port. This bit is cleared by the core after a remote + * wakeup signal is detected or the application sets the Port + * Reset bit or Port Resume bit in this register or the + * Resume/Remote Wakeup Detected Interrupt bit or + * Disconnect Detected Interrupt bit in the Core Interrupt + * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, + * respectively).This bit is cleared by the core even if there is + * no device connected to the Host. + * - 1'b0: Port not in Suspend mode + * - 1'b1: Port in Suspend mode + */ + uint32_t otgfs_hprt_prtsusp:1; + /** otgfs_hprt_prtrst : R/W; bitpos: [8]; default: 0; + * Port Reset (PrtRst) + * + * When the application sets this bit, a reset sequence is + * started on this port. The application must time the reset + * period and clear this bit after the reset sequence is + * complete. + * - 1'b0: Port not in reset + * - 1'b1: Port in reset + * The application must leave this bit set for at least a + * minimum duration mentioned below to start a reset on the + * port. The application can leave it set for another 10 ms in + * addition to the required minimum duration, before clearing + * the bit, even though there is no maximum limit Set by the + * USB standard.This bit is cleared by the core even if there is + * no device connected to the Host. + * - High speed: 50 ms + * - Full speed/Low speed: 10 ms + */ + uint32_t otgfs_hprt_prtrst:1; + uint32_t reserved_9:1; + /** otgfs_hprt_prtlnsts : RO; bitpos: [11:10]; default: 0; + * Port Line Status (PrtLnSts) + * + * Indicates the current logic level USB data lines + * - Bit [10]: Logic level of D+ + * - Bit [11]: Logic level of D- + */ + uint32_t otgfs_hprt_prtlnsts:2; + /** otgfs_hprt_prtpwr : R/W; bitpos: [12]; default: 0; + * Port Power (PrtPwr) + * + * The application uses this field to control power to this port (write 1'b1 to set to + * 1'b1 + * and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current + * condition. + * - 1'b0: Power off + * - 1'b1: Power on + * + * Note: This bit is interface independent. The application needs to program this bit + * for all interfaces as described in the host programming flow in the Programming + * Guide. + */ + uint32_t otgfs_hprt_prtpwr:1; + /** otgfs_hprt_prttstctl : R/W; bitpos: [16:13]; default: 0; + * Port Test Control (PrtTstCtl) + * + * The application writes a nonzero value to this field to put the port into a Test + * mode, and the corresponding pattern is signaled on the port. + * - 4'b0000: Test mode disabled + * - 4'b0001: Test_J mode + * - 4'b0010: Test_K mode + * - 4'b0011: Test_SE0_NAK mode + * - 4'b0100: Test_Packet mode + * - 4'b0101: Test_Force_Enable + * - Others: Reserved + * + * To move the DWC_otg controller to test mode, you must set this field. Complete the + * following steps to move the DWC_otg core to test mode: + * - 1. Power on the core. + * - 2. Load the DWC_otg driver. + * - 3. Connect an HS device and enumerate to HS mode. + * - 4. Access the HPRT register to send test packets. + * - 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core + * continues sending out test packets. + * - 6. Test the eye diagram. + */ + uint32_t otgfs_hprt_prttstctl:4; + /** otgfs_hprt_prtspd : RO; bitpos: [18:17]; default: 0; + * Port Speed (PrtSpd) + * + * Indicates the speed of the device attached to this port. + * - 2'b00: High speed + * - 2'b01: Full speed + * - 2'b10: Low speed + * - 2'b11: Reserved + */ + uint32_t otgfs_hprt_prtspd:2; + uint32_t reserved_19:13; + }; + uint32_t val; +} usb_otgfs_hprt_reg_t; + + +/** Group: Host Channel 0 Characteristics Register */ +/** Type of otgfs_hcchar0 register + * Host Channel 0 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar0_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar0_mps:11; + /** otgfs_hcchar0_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar0_epnum:4; + /** otgfs_hcchar0_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar0_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar0_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar0_lspddev:1; + /** otgfs_hcchar0_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar0_eptype:2; + /** otgfs_hcchar0_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar0_ec:2; + /** otgfs_hcchar0_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar0_devaddr:7; + /** otgfs_hcchar0_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar0_oddfrm:1; + /** otgfs_hcchar0_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar0_chdis:1; + /** otgfs_hcchar0_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar0_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar0_reg_t; + + +/** Group: "Host Channel $i Interrupt Register" */ +/** Type of otgfs_hcint0 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint0_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint0_xfercompl:1; + /** otgfs_hcint0_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint0_chhltd:1; + /** otgfs_hcint0_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint0_ahberr:1; + /** otgfs_hcint0_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint0_stall:1; + /** otgfs_hcint0_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint0_nak:1; + /** otgfs_hcint0_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint0_ack:1; + /** otgfs_hcint0_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint0_nyet:1; + /** otgfs_hcint0_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint0_xacterr:1; + /** otgfs_hcint0_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint0_bblerr:1; + /** otgfs_hcint0_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint0_frmovrun:1; + /** otgfs_hcint0_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint0_datatglerr:1; + /** otgfs_hcint0_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint0_bnaintr:1; + /** otgfs_hcint0_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint0_xcs_xact_err:1; + /** otgfs_hcint0_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint0_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint0_reg_t; + +/** Type of otgfs_hcint1 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint1_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint1_xfercompl:1; + /** otgfs_hcint1_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint1_chhltd:1; + /** otgfs_hcint1_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint1_ahberr:1; + /** otgfs_hcint1_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint1_stall:1; + /** otgfs_hcint1_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint1_nak:1; + /** otgfs_hcint1_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint1_ack:1; + /** otgfs_hcint1_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint1_nyet:1; + /** otgfs_hcint1_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint1_xacterr:1; + /** otgfs_hcint1_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint1_bblerr:1; + /** otgfs_hcint1_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint1_frmovrun:1; + /** otgfs_hcint1_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint1_datatglerr:1; + /** otgfs_hcint1_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint1_bnaintr:1; + /** otgfs_hcint1_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint1_xcs_xact_err:1; + /** otgfs_hcint1_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint1_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint1_reg_t; + +/** Type of otgfs_hcint2 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint2_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint2_xfercompl:1; + /** otgfs_hcint2_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint2_chhltd:1; + /** otgfs_hcint2_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint2_ahberr:1; + /** otgfs_hcint2_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint2_stall:1; + /** otgfs_hcint2_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint2_nak:1; + /** otgfs_hcint2_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint2_ack:1; + /** otgfs_hcint2_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint2_nyet:1; + /** otgfs_hcint2_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint2_xacterr:1; + /** otgfs_hcint2_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint2_bblerr:1; + /** otgfs_hcint2_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint2_frmovrun:1; + /** otgfs_hcint2_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint2_datatglerr:1; + /** otgfs_hcint2_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint2_bnaintr:1; + /** otgfs_hcint2_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint2_xcs_xact_err:1; + /** otgfs_hcint2_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint2_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint2_reg_t; + +/** Type of otgfs_hcint3 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint3_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint3_xfercompl:1; + /** otgfs_hcint3_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint3_chhltd:1; + /** otgfs_hcint3_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint3_ahberr:1; + /** otgfs_hcint3_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint3_stall:1; + /** otgfs_hcint3_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint3_nak:1; + /** otgfs_hcint3_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint3_ack:1; + /** otgfs_hcint3_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint3_nyet:1; + /** otgfs_hcint3_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint3_xacterr:1; + /** otgfs_hcint3_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint3_bblerr:1; + /** otgfs_hcint3_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint3_frmovrun:1; + /** otgfs_hcint3_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint3_datatglerr:1; + /** otgfs_hcint3_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint3_bnaintr:1; + /** otgfs_hcint3_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint3_xcs_xact_err:1; + /** otgfs_hcint3_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint3_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint3_reg_t; + +/** Type of otgfs_hcint4 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint4_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint4_xfercompl:1; + /** otgfs_hcint4_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint4_chhltd:1; + /** otgfs_hcint4_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint4_ahberr:1; + /** otgfs_hcint4_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint4_stall:1; + /** otgfs_hcint4_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint4_nak:1; + /** otgfs_hcint4_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint4_ack:1; + /** otgfs_hcint4_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint4_nyet:1; + /** otgfs_hcint4_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint4_xacterr:1; + /** otgfs_hcint4_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint4_bblerr:1; + /** otgfs_hcint4_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint4_frmovrun:1; + /** otgfs_hcint4_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint4_datatglerr:1; + /** otgfs_hcint4_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint4_bnaintr:1; + /** otgfs_hcint4_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint4_xcs_xact_err:1; + /** otgfs_hcint4_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint4_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint4_reg_t; + +/** Type of otgfs_hcint5 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint5_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint5_xfercompl:1; + /** otgfs_hcint5_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint5_chhltd:1; + /** otgfs_hcint5_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint5_ahberr:1; + /** otgfs_hcint5_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint5_stall:1; + /** otgfs_hcint5_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint5_nak:1; + /** otgfs_hcint5_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint5_ack:1; + /** otgfs_hcint5_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint5_nyet:1; + /** otgfs_hcint5_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint5_xacterr:1; + /** otgfs_hcint5_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint5_bblerr:1; + /** otgfs_hcint5_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint5_frmovrun:1; + /** otgfs_hcint5_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint5_datatglerr:1; + /** otgfs_hcint5_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint5_bnaintr:1; + /** otgfs_hcint5_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint5_xcs_xact_err:1; + /** otgfs_hcint5_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint5_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint5_reg_t; + +/** Type of otgfs_hcint6 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint6_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint6_xfercompl:1; + /** otgfs_hcint6_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint6_chhltd:1; + /** otgfs_hcint6_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint6_ahberr:1; + /** otgfs_hcint6_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint6_stall:1; + /** otgfs_hcint6_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint6_nak:1; + /** otgfs_hcint6_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint6_ack:1; + /** otgfs_hcint6_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint6_nyet:1; + /** otgfs_hcint6_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint6_xacterr:1; + /** otgfs_hcint6_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint6_bblerr:1; + /** otgfs_hcint6_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint6_frmovrun:1; + /** otgfs_hcint6_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint6_datatglerr:1; + /** otgfs_hcint6_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint6_bnaintr:1; + /** otgfs_hcint6_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint6_xcs_xact_err:1; + /** otgfs_hcint6_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint6_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint6_reg_t; + +/** Type of otgfs_hcint7 register + * Host Channel $i Interrupt Register This register indicates the status of a channel + * with respect to USB- and AHB-related events. It is shown in the Interrupt Hierarchy + * figure in the databook. The application must read this register when the Host + * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. + * Before the application can read this register, it must first read the Host All + * Channels Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS registers. + */ +typedef union { + struct { + /** otgfs_hcint7_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed (XferCompl) + * + * Transfer completed normally without any errors.This bit can be set only by the core + * and the application should write 1 to clear it. + * - For Scatter/Gather DMA mode, it indicates that current descriptor processing got + * completed with IOC bit set in its descriptor. + * - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally + * without any errors. + */ + uint32_t otgfs_hcint7_xfercompl:1; + /** otgfs_hcint7_chhltd : R/W; bitpos: [1]; default: 0; + * Channel Halted (ChHltd) + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. + * + * In Scatter/gather DMA mode, this indicates that transfer completed due to any of + * the following + * - EOL being set in descriptor + * - AHB error + * - Excessive transaction errors + * - Babble + * - Stall + */ + uint32_t otgfs_hcint7_chhltd:1; + /** otgfs_hcint7_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * This is generated only in Internal DMA mode when there is an AHB error during AHB + * read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + */ + uint32_t otgfs_hcint7_ahberr:1; + /** otgfs_hcint7_stall : R/W; bitpos: [3]; default: 0; + * STALL Response Received Interrupt (STALL) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint7_stall:1; + /** otgfs_hcint7_nak : R/W; bitpos: [4]; default: 0; + * NAK Response Received Interrupt (NAK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint7_nak:1; + /** otgfs_hcint7_ack : R/W; bitpos: [5]; default: 0; + * ACK Response Received/Transmitted Interrupt (ACK) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint7_ack:1; + /** otgfs_hcint7_nyet : R/W; bitpos: [6]; default: 0; + * NYET Response Received Interrupt (NYET) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint7_nyet:1; + /** otgfs_hcint7_xacterr : R/W; bitpos: [7]; default: 0; + * Transaction Error (XactErr) + * + * Indicates one of the following errors occurred on the USB. + * - CRC check failure + * - Timeout + * - Bit stuff error + * - False EOP + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + */ + uint32_t otgfs_hcint7_xacterr:1; + /** otgfs_hcint7_bblerr : R/W; bitpos: [8]; default: 0; + * Babble Error (BblErr) + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear it. + */ + uint32_t otgfs_hcint7_bblerr:1; + /** otgfs_hcint7_frmovrun : R/W; bitpos: [9]; default: 0; + * Frame Overrun (FrmOvrun). + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. This bit can be set only by the core and the application should write + * 1 to clear + * it. + */ + uint32_t otgfs_hcint7_frmovrun:1; + /** otgfs_hcint7_datatglerr : R/W; bitpos: [10]; default: 0; + * + * Data Toggle Error (DataTglErr).This bit can be set only by the core and the + * application should write 1 to clear + * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked + * in the core. + */ + uint32_t otgfs_hcint7_datatglerr:1; + /** otgfs_hcint7_bnaintr : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * The core generates this interrupt when the descriptor accessed + * is not ready for the Core to process. BNA will not be generated + * for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint7_bnaintr:1; + /** otgfs_hcint7_xcs_xact_err : R/W; bitpos: [12]; default: 0; + * Excessive Transaction Error (XCS_XACT_ERR) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will + * not be generated for Isochronous channels. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint7_xcs_xact_err:1; + /** otgfs_hcint7_desc_lst_rollintr : R/W; bitpos: [13]; default: 0; + * Descriptor rollover interrupt (DESC_LST_ROLLIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this + * bit + * when the corresponding channel's descriptor list rolls over. + * For non Scatter/Gather DMA mode, this bit is reserved. + */ + uint32_t otgfs_hcint7_desc_lst_rollintr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcint7_reg_t; + + +/** Group: "Host Channel $i Interrupt Mask Register" */ +/** Type of otgfs_hcintmsk0 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk0_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk0_xfercomplmsk:1; + /** otgfs_hcintmsk0_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk0_chhltdmsk:1; + /** otgfs_hcintmsk0_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk0_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk0_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk0_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk0_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk0_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk0_reg_t; + +/** Type of otgfs_hcintmsk1 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk1_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk1_xfercomplmsk:1; + /** otgfs_hcintmsk1_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk1_chhltdmsk:1; + /** otgfs_hcintmsk1_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk1_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk1_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk1_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk1_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk1_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk1_reg_t; + +/** Type of otgfs_hcintmsk2 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk2_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk2_xfercomplmsk:1; + /** otgfs_hcintmsk2_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk2_chhltdmsk:1; + /** otgfs_hcintmsk2_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk2_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk2_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk2_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk2_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk2_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk2_reg_t; + +/** Type of otgfs_hcintmsk3 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk3_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk3_xfercomplmsk:1; + /** otgfs_hcintmsk3_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk3_chhltdmsk:1; + /** otgfs_hcintmsk3_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk3_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk3_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk3_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk3_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk3_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk3_reg_t; + +/** Type of otgfs_hcintmsk4 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk4_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk4_xfercomplmsk:1; + /** otgfs_hcintmsk4_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk4_chhltdmsk:1; + /** otgfs_hcintmsk4_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk4_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk4_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk4_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk4_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk4_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk4_reg_t; + +/** Type of otgfs_hcintmsk5 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk5_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk5_xfercomplmsk:1; + /** otgfs_hcintmsk5_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk5_chhltdmsk:1; + /** otgfs_hcintmsk5_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk5_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk5_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk5_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk5_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk5_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk5_reg_t; + +/** Type of otgfs_hcintmsk6 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk6_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk6_xfercomplmsk:1; + /** otgfs_hcintmsk6_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk6_chhltdmsk:1; + /** otgfs_hcintmsk6_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk6_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk6_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk6_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk6_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk6_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk6_reg_t; + +/** Type of otgfs_hcintmsk7 register + * Host Channel $i Interrupt Mask Register This register reflects the mask for each + * channel status described in the previous section. + */ +typedef union { + struct { + /** otgfs_hcintmsk7_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * + * Transfer Completed Mask (XferComplMsk) + */ + uint32_t otgfs_hcintmsk7_xfercomplmsk:1; + /** otgfs_hcintmsk7_chhltdmsk : R/W; bitpos: [1]; default: 0; + * + * Channel Halted Mask (ChHltdMsk) + */ + uint32_t otgfs_hcintmsk7_chhltdmsk:1; + /** otgfs_hcintmsk7_ahberrmsk : R/W; bitpos: [2]; default: 0; + * + * AHB Error Mask (AHBErrMsk) + * In scatter/gather DMA mode for host, + * interrupts will not be generated due to the corresponding bits set in + * HCINTn. + */ + uint32_t otgfs_hcintmsk7_ahberrmsk:1; + uint32_t reserved_3:8; + /** otgfs_hcintmsk7_bnaintrmsk : R/W; bitpos: [11]; default: 0; + * + * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk7_bnaintrmsk:1; + uint32_t reserved_12:1; + /** otgfs_hcintmsk7_desc_lst_rollintrmsk : R/W; bitpos: [13]; default: 0; + * + * Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk) + * This bit is valid only when Scatter/Gather DMA mode is enabled. + */ + uint32_t otgfs_hcintmsk7_desc_lst_rollintrmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_hcintmsk7_reg_t; + + +/** Group: Host Channel 0 Transfer Size Register */ +/** Type of otgfs_hctsiz0 register + * Host Channel 0 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz0_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz0_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz0_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz0_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz0_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz0_pid:2; + /** otgfs_hctsiz0_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz0_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz0_reg_t; + + +/** Group: "Host Channel $i DMA Address Register" */ +/** Type of otgfs_hcdma0 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma0_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma0_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma0_reg_t; + +/** Type of otgfs_hcdma1 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma1_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma1_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma1_reg_t; + +/** Type of otgfs_hcdma2 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma2_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma2_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma2_reg_t; + +/** Type of otgfs_hcdma3 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma3_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma3_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma3_reg_t; + +/** Type of otgfs_hcdma4 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma4_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma4_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma4_reg_t; + +/** Type of otgfs_hcdma5 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma5_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma5_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma5_reg_t; + +/** Type of otgfs_hcdma6 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma6_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma6_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma6_reg_t; + +/** Type of otgfs_hcdma7 register + * Host Channel $i DMA Address Register This register is used by the OTG host in the + * internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. + * The starting DMA address must be DWORD-aligned. + */ +typedef union { + struct { + /** otgfs_hcdma7_dmaaddr : R/W; bitpos: [31:0]; default: 0; + * In Buffer DMA Mode: + * + * [31:0]: DMA Address (DMAAddr) + * + * This field holds the start address in the external memory from which the data for + * the endpoint must be fetched or to which it must be stored. This register is + * incremented on every AHB transaction. + * + * Reset: X if not programmed as the register is in SPRAM. + * + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * + * [31:9]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the start address of the 512 bytes page. The first descriptor in + * the list should be located in this address. The first descriptor may be or may not + * be ready. The core starts processing the list from the CTD value. + * + * [8:3]: Current Transfer Desc(CTD) + * + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * - 0 - 1 descriptor. + * - 63 - 64 descriptors. + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. For example, if the application enables + * the channel after programming CTD=5, then the core will start processing the sixth + * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to + * DMAAddr. + * + * Reset: 6'h0 + * + * [2:0]: Reserved + * + * In Scatter-Gather DMA (DescDMA) Mode for Isochronous: + * + * [31:N]: DMA Address (DMAAddr) + * + * The start address must be 512-bytes aligned. + * + * This field holds the address of the 2*(nTD+1) bytes of locations in which the + * isochronous descriptors are present where N is based on nTD as follows: + * - [31:N]: Base Address + * - [N-1:3]: Offset + * - [2:0]: 000 + * For HS ISOC, if nTD is, + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * - 127, N=10 + * - 255, N=11 + * For FS ISOC, if nTD is, + * - 1, N=4 + * - 3, N=5 + * - 7, N=6 + * - 15, N=7 + * - 31, N=8 + * - 63, N=9 + * [N-1:3]: Current Transfer Desc(CTD) + * + * CTD for isochronous is based on the current frame/(micro)frame value. Need to be + * set to zero by application. + * + * Reset: (N+1:3)'h0 + * + * [2:0]: Reserved + */ + uint32_t otgfs_hcdma7_dmaaddr:32; + }; + uint32_t val; +} usb_otgfs_hcdma7_reg_t; + + +/** Group: "Host Channel $i DMA Buffer Address Register" */ +/** Type of otgfs_hcdmab0 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab0_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab0_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab0_reg_t; + +/** Type of otgfs_hcdmab1 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab1_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab1_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab1_reg_t; + +/** Type of otgfs_hcdmab2 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab2_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab2_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab2_reg_t; + +/** Type of otgfs_hcdmab3 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab3_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab3_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab3_reg_t; + +/** Type of otgfs_hcdmab4 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab4_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab4_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab4_reg_t; + +/** Type of otgfs_hcdmab5 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab5_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab5_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab5_reg_t; + +/** Type of otgfs_hcdmab6 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab6_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab6_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab6_reg_t; + +/** Type of otgfs_hcdmab7 register + * Host Channel $i DMA Buffer Address Register This register is present only in case + * of Scatter/Gather DMA. It is implemented in RAM instead of flop-based + * implementation. This register holds the current buffer address. + */ +typedef union { + struct { + /** otgfs_hcdmab7_hcdmab : RO; bitpos: [31:0]; default: 0; + * Holds the current buffer address. + * This register is updated as and when the data transfer for the corresponding end + * point + * is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise + * this + * field is reserved. + */ + uint32_t otgfs_hcdmab7_hcdmab:32; + }; + uint32_t val; +} usb_otgfs_hcdmab7_reg_t; + + +/** Group: Host Channel 1 Characteristics Register */ +/** Type of otgfs_hcchar1 register + * Host Channel 1 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar1_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar1_mps:11; + /** otgfs_hcchar1_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar1_epnum:4; + /** otgfs_hcchar1_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar1_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar1_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar1_lspddev:1; + /** otgfs_hcchar1_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar1_eptype:2; + /** otgfs_hcchar1_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar1_ec:2; + /** otgfs_hcchar1_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar1_devaddr:7; + /** otgfs_hcchar1_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar1_oddfrm:1; + /** otgfs_hcchar1_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar1_chdis:1; + /** otgfs_hcchar1_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar1_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar1_reg_t; + + +/** Group: Host Channel 1 Transfer Size Register */ +/** Type of otgfs_hctsiz1 register + * Host Channel 1 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz1_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz1_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz1_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz1_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz1_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz1_pid:2; + /** otgfs_hctsiz1_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz1_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz1_reg_t; + + +/** Group: Host Channel 2 Characteristics Register */ +/** Type of otgfs_hcchar2 register + * Host Channel 2 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar2_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar2_mps:11; + /** otgfs_hcchar2_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar2_epnum:4; + /** otgfs_hcchar2_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar2_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar2_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar2_lspddev:1; + /** otgfs_hcchar2_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar2_eptype:2; + /** otgfs_hcchar2_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar2_ec:2; + /** otgfs_hcchar2_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar2_devaddr:7; + /** otgfs_hcchar2_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar2_oddfrm:1; + /** otgfs_hcchar2_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar2_chdis:1; + /** otgfs_hcchar2_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar2_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar2_reg_t; + + +/** Group: Host Channel 2 Transfer Size Register */ +/** Type of otgfs_hctsiz2 register + * Host Channel 2 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz2_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz2_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz2_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz2_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz2_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz2_pid:2; + /** otgfs_hctsiz2_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz2_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz2_reg_t; + + +/** Group: Host Channel 3 Characteristics Register */ +/** Type of otgfs_hcchar3 register + * Host Channel 3 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar3_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar3_mps:11; + /** otgfs_hcchar3_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar3_epnum:4; + /** otgfs_hcchar3_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar3_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar3_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar3_lspddev:1; + /** otgfs_hcchar3_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar3_eptype:2; + /** otgfs_hcchar3_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar3_ec:2; + /** otgfs_hcchar3_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar3_devaddr:7; + /** otgfs_hcchar3_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar3_oddfrm:1; + /** otgfs_hcchar3_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar3_chdis:1; + /** otgfs_hcchar3_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar3_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar3_reg_t; + + +/** Group: Host Channel 3 Transfer Size Register */ +/** Type of otgfs_hctsiz3 register + * Host Channel 3 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz3_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz3_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz3_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz3_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz3_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz3_pid:2; + /** otgfs_hctsiz3_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz3_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz3_reg_t; + + +/** Group: Host Channel 4 Characteristics Register */ +/** Type of otgfs_hcchar4 register + * Host Channel 4 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar4_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar4_mps:11; + /** otgfs_hcchar4_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar4_epnum:4; + /** otgfs_hcchar4_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar4_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar4_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar4_lspddev:1; + /** otgfs_hcchar4_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar4_eptype:2; + /** otgfs_hcchar4_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar4_ec:2; + /** otgfs_hcchar4_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar4_devaddr:7; + /** otgfs_hcchar4_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar4_oddfrm:1; + /** otgfs_hcchar4_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar4_chdis:1; + /** otgfs_hcchar4_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar4_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar4_reg_t; + + +/** Group: Host Channel 4 Transfer Size Register */ +/** Type of otgfs_hctsiz4 register + * Host Channel 4 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz4_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz4_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz4_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz4_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz4_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz4_pid:2; + /** otgfs_hctsiz4_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz4_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz4_reg_t; + + +/** Group: Host Channel 5 Characteristics Register */ +/** Type of otgfs_hcchar5 register + * Host Channel 5 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar5_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar5_mps:11; + /** otgfs_hcchar5_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar5_epnum:4; + /** otgfs_hcchar5_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar5_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar5_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar5_lspddev:1; + /** otgfs_hcchar5_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar5_eptype:2; + /** otgfs_hcchar5_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar5_ec:2; + /** otgfs_hcchar5_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar5_devaddr:7; + /** otgfs_hcchar5_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar5_oddfrm:1; + /** otgfs_hcchar5_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar5_chdis:1; + /** otgfs_hcchar5_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar5_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar5_reg_t; + + +/** Group: Host Channel 5 Transfer Size Register */ +/** Type of otgfs_hctsiz5 register + * Host Channel 5 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz5_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz5_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz5_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz5_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz5_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz5_pid:2; + /** otgfs_hctsiz5_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz5_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz5_reg_t; + + +/** Group: Host Channel 6 Characteristics Register */ +/** Type of otgfs_hcchar6 register + * Host Channel 6 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar6_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar6_mps:11; + /** otgfs_hcchar6_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar6_epnum:4; + /** otgfs_hcchar6_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar6_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar6_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar6_lspddev:1; + /** otgfs_hcchar6_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar6_eptype:2; + /** otgfs_hcchar6_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar6_ec:2; + /** otgfs_hcchar6_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar6_devaddr:7; + /** otgfs_hcchar6_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar6_oddfrm:1; + /** otgfs_hcchar6_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar6_chdis:1; + /** otgfs_hcchar6_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar6_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar6_reg_t; + + +/** Group: Host Channel 6 Transfer Size Register */ +/** Type of otgfs_hctsiz6 register + * Host Channel 6 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz6_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz6_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz6_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz6_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz6_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz6_pid:2; + /** otgfs_hctsiz6_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz6_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz6_reg_t; + + +/** Group: Host Channel 7 Characteristics Register */ +/** Type of otgfs_hcchar7 register + * Host Channel 7 Characteristics Register + */ +typedef union { + struct { + /** otgfs_hcchar7_mps : R/W; bitpos: [10:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Indicates the maximum packet size of the associated endpoint. + */ + uint32_t otgfs_hcchar7_mps:11; + /** otgfs_hcchar7_epnum : R/W; bitpos: [14:11]; default: 0; + * Endpoint Number (EPNum) + * + * Indicates the endpoint number on the device serving as the data source or sink. + */ + uint32_t otgfs_hcchar7_epnum:4; + /** otgfs_hcchar7_epdir : R/W; bitpos: [15]; default: 0; + * Endpoint Direction (EPDir) + * + * Indicates whether the transaction is IN or OUT. + * - 1'b0: OUT + * - 1'b1: IN + */ + uint32_t otgfs_hcchar7_epdir:1; + uint32_t reserved_16:1; + /** otgfs_hcchar7_lspddev : R/W; bitpos: [17]; default: 0; + * Low-Speed Device (LSpdDev) + * + * This field is Set by the application to indicate that this channel is communicating + * to a low-speed device. + * + * The application must program this bit when a low speed device is connected to the + * host through an FS HUB. The DWC_otg Host core uses this field to drive the + * XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub. + * + * Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is + * set by the application software. + */ + uint32_t otgfs_hcchar7_lspddev:1; + /** otgfs_hcchar7_eptype : R/W; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Indicates the transfer type selected. + * - 2'b00: Control + * - 2'b01: Isochronous + * - 2'b10: Bulk + * - 2'b11: Interrupt + */ + uint32_t otgfs_hcchar7_eptype:2; + /** otgfs_hcchar7_ec : R/W; bitpos: [21:20]; default: 0; + * Multi Count (MC) / Error Count (EC) + * + * When the Split Enable bit of the Host Channel-n Split Control + * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to + * the host the number of transactions that must be executed per + * microframe for this periodic endpoint. For non periodic transfers, + * this field is used only in DMA mode, and specifies the number + * packets to be fetched for this channel before the internal DMA + * engine changes arbitration. + * - 2'b00: Reserved This field yields undefined results. + * - 2'b01: 1 transaction + * - 2'b10: 2 transactions to be issued for this endpoint per microframe + * - 2'b11: 3 transactions to be issued for this endpoint per microframe + * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the + * number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at + * least 2'b01. + */ + uint32_t otgfs_hcchar7_ec:2; + /** otgfs_hcchar7_devaddr : R/W; bitpos: [28:22]; default: 0; + * Device Address (DevAddr) + * + * This field selects the specific device serving as the data source + * or sink. + */ + uint32_t otgfs_hcchar7_devaddr:7; + /** otgfs_hcchar7_oddfrm : R/W; bitpos: [29]; default: 0; + * Odd Frame (OddFrm) + * + * This field is set (reset) by the application to indicate that the OTG host must + * perform + * a transfer in an odd (micro)Frame. This field is applicable for only periodic + * (isochronous and interrupt) transactions. + * - 1'b0: Even (micro)Frame + * - 1'b1: Odd (micro)Frame + */ + uint32_t otgfs_hcchar7_oddfrm:1; + /** otgfs_hcchar7_chdis : R/W; bitpos: [30]; default: 0; + * Channel Disable (ChDis) + * + * The application sets this bit to stop transmitting/receiving data + * on a channel, even before the transfer for that channel is + * complete. The application must wait for the Channel Disabled + * interrupt before treating the channel as disabled. + */ + uint32_t otgfs_hcchar7_chdis:1; + /** otgfs_hcchar7_chena : R/W; bitpos: [31]; default: 0; + * Channel Enable (ChEna) + * + * When Scatter/Gather mode is enabled + * - 1'b0: Indicates that the descriptor structure is not yet ready. + * - 1'b1: Indicates that the descriptor structure and data buffer with data + * is setup and this channel can access the descriptor. + * When Scatter/Gather mode is disabled + * + * This field is set by the application and cleared by the OTG host. + * - 1'b0: Channel disabled + * - 1'b1: Channel enabled + */ + uint32_t otgfs_hcchar7_chena:1; + }; + uint32_t val; +} usb_otgfs_hcchar7_reg_t; + + +/** Group: Host Channel 7 Transfer Size Register */ +/** Type of otgfs_hctsiz7 register + * Host Channel 7 Transfer Size Register + */ +typedef union { + struct { + /** otgfs_hctsiz7_xfersize : R/W; bitpos: [15:0]; default: 0; + * Transfer Size (XferSize) + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. + * + * For an IN, this field is the buffer size that the application has Reserved for the + * transfer. The application is expected to program this field as an integer multiple + * of the maximum packet size for IN transactions (periodic and non-periodic). + * + * The width of this counter is specified as Width of Transfer Size Counters during + * coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz7_xfersize:16; + uint32_t reserved_16:3; + /** otgfs_hctsiz7_pktcnt : R/W; bitpos: [25:19]; default: 0; + * Packet Count (PktCnt) + * + * This field is programmed by the application with the expected number of packets to + * be transmitted (OUT) or received (IN). + * + * The host decrements this count on every successful transmission or reception of an + * OUT/IN packet. Once this count reaches zero, the application is interrupted to + * indicate normal completion. + * + * The width of this counter is specified as Width of Packet Counters during + * coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH). + */ + uint32_t otgfs_hctsiz7_pktcnt:7; + uint32_t reserved_26:3; + /** otgfs_hctsiz7_pid : R/W; bitpos: [30:29]; default: 0; + * PID (Pid) + * + * The application programs this field with the type of PID to use for the initial + * transaction. The host maintains this field for the rest of the transfer. + * - 2'b00: DATA0 + * - 2'b01: DATA2 + * - 2'b10: DATA1 + * - 2'b11: MDATA (non-control)/SETUP (control) + */ + uint32_t otgfs_hctsiz7_pid:2; + /** otgfs_hctsiz7_dopng : R/W; bitpos: [31]; default: 0; + * Do Ping (DoPng) + * + * This bit is used only for OUT transfers. + * Setting this field to 1 directs the host to do PING protocol. + * + * Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers + * it disables the channel. + */ + uint32_t otgfs_hctsiz7_dopng:1; + }; + uint32_t val; +} usb_otgfs_hctsiz7_reg_t; + + +/** Group: Device Configuration Register */ +/** Type of otgfs_dcfg register + * Device Configuration Register This register configures the core in Device mode + * after power-on or after certain control commands or enumeration. Do not make + * changes to this register after initial programming. + */ +typedef union { + struct { + /** otgfs_dcfg_devspd : R/W; bitpos: [1:0]; default: 0; + * Device Speed (DevSpd) + * + * Indicates the speed at which the application requires the core to + * enumerate, or the maximum speed the application can support. + * However, the actual bus speed is determined only after the connect + * sequence is completed, and is based on the speed of the USB + * host to which the core is connected. + */ + uint32_t otgfs_dcfg_devspd:2; + /** otgfs_dcfg_nzstsouthshk : R/W; bitpos: [2]; default: 0; + * Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + * + * The application can use this field to select the handshake the core sends on + * receiving a nonzero-length data packet during the OUT transaction of a control + * transfer's Status stage. + * - 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do + * not send the received OUT packet to the application. + * - 1'b0: Send the received OUT packet to the application (zerolength or + * nonzero-length) and send a handshake based on the NAK and STALL bits for the + * endpoint in the Device Endpoint Control register. + */ + uint32_t otgfs_dcfg_nzstsouthshk:1; + /** otgfs_dcfg_ena32khzsusp : R/W; bitpos: [3]; default: 0; + * Enable 32 KHz Suspend mode (Ena32KHzSusp) + * + * This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs + * to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock + * during Suspend must be switched from 48 MHz to 32 KHz. + */ + uint32_t otgfs_dcfg_ena32khzsusp:1; + /** otgfs_dcfg_devaddr : R/W; bitpos: [10:4]; default: 0; + * Device Address (DevAddr) + * + * The application must program this field after every SetAddress control command. + */ + uint32_t otgfs_dcfg_devaddr:7; + /** otgfs_dcfg_perfrint : R/W; bitpos: [12:11]; default: 0; + * Periodic Frame Interval (PerFrInt) + * + * Indicates the time within a (micro)Frame at which the application + * must be notified using the End Of Periodic Frame Interrupt. This + * can be used to determine If all the isochronous traffic for that + * (micro)Frame is complete. + * - 2'b00: 80% of the (micro)Frame interval + * - 2'b01: 85% of the (micro)Frame interval + * - 2'b10: 90% of the (micro)Frame interval + * - 2'b11: 95% of the (micro)Frame interval + */ + uint32_t otgfs_dcfg_perfrint:2; + /** otgfs_dcfg_endevoutnak : R/W; bitpos: [13]; default: 0; + * Enable Device OUT NAK (EnDevOutNak) + * + * This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed + * for Device mode Descriptor DMA + * - 1'b0 : The core does not set NAK after Bulk OUT transfer complete + * - 1'b1 : The core sets NAK after Bulk OUT transfer complete + * It bit is one time programmable after reset like any other DCFG register bits. + */ + uint32_t otgfs_dcfg_endevoutnak:1; + /** otgfs_dcfg_xcvrdly : R/W; bitpos: [14]; default: 0; + * XCVRDLY + * + * Enables or disables delay between xcvr_sel and txvalid during device chirp + */ + uint32_t otgfs_dcfg_xcvrdly:1; + /** otgfs_dcfg_erraticintmsk : R/W; bitpos: [15]; default: 0; + * Erratic Error Interrupt Mask + */ + uint32_t otgfs_dcfg_erraticintmsk:1; + uint32_t reserved_16:7; + /** otgfs_dcfg_descdma : R/W; bitpos: [23]; default: 0; + * Enable Scatter/gather DMA in device mode (DescDMA). + * + * When the Scatter/Gather DMA option selected during configuration of the RTL, the + * application can Set this bit during initialization to enable the Scatter/Gather DMA + * operation. + * + * Note: This bit must be modified only once after a reset. The following combinations + * are available for programming: + * - GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode + * - GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid + * - GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA mode + * - GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode + */ + uint32_t otgfs_dcfg_descdma:1; + /** otgfs_dcfg_perschintvl : R/W; bitpos: [25:24]; default: 0; + * Periodic Scheduling Interval (PerSchIntvl) + * + * PerSchIntvl must be programmed for Scatter/Gather DMA mode. + * + * This field specifies the amount of time the Internal + * DMA engine must allocate for fetching periodic IN endpoint data. + * Based on the number of periodic endpoints, this value must be + * specified as 25,50 or 75% of (micro)Frame. + * - When any periodic endpoints are active, the internal DMA engine allocates the + * specified amount of time in fetching periodic IN endpoint data . + * - When no periodic endpoints are active, Then the internal DMA engine services + * non-periodic endpoints, ignoring this field. + * - After the specified time within a (micro)Frame, the DMA switches to fetching for + * non-periodic endpoints. + * -- 2'b00: 25% of (micro)Frame. + * -- 2'b01: 50% of (micro)Frame. + * -- 2'b10: 75% of (micro)Frame. + * -- 2'b11: Reserved. + * Reset: 2'b00 + */ + uint32_t otgfs_dcfg_perschintvl:2; + /** otgfs_dcfg_resvalid : R/W; bitpos: [31:26]; default: 2; + * Resume Validation Period (ResValid) + * + * This field is effective only when DCFG.Ena32KHzSusp is set. + * It controls the resume period when the core resumes from + * suspend. The core counts for ResValid number of clock cycles + * to detect a valid resume when this bit is set + */ + uint32_t otgfs_dcfg_resvalid:6; + }; + uint32_t val; +} usb_otgfs_dcfg_reg_t; + + +/** Group: Device Control Register */ +/** Type of otgfs_dctl register + * Device Control Register + */ +typedef union { + struct { + /** otgfs_dctl_rmtwkupsig : R/W; bitpos: [0]; default: 0; + * Remote Wakeup Signaling (RmtWkUpSig) + * + * When the application sets this bit, the core initiates remote + * signaling to wake up the USB host. The application must Set this + * bit to instruct the core to exit the Suspend state. As specified in + * the USB 2.0 specification, the application must clear this bit + * 1-15 ms after setting it. + * + * + * If LPM is enabled and the core is in the L1 (Sleep) state, when the application + * sets this bit, the core initiates L1 remote signaling to wake up the USB host. The + * application must set this bit to instruct the core to exit the Sleep state. As + * specified in the LPM specification, the hardware automatically clears this bit 50 + * microseconds (TL1DevDrvResume) after being set by the application. The application + * must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is + * zero. + */ + uint32_t otgfs_dctl_rmtwkupsig:1; + /** otgfs_dctl_sftdiscon : R/W; bitpos: [1]; default: 1; + * Soft Disconnect (SftDiscon) + * + * The application uses this bit to signal the controller to do a soft disconnect. As + * long as this bit is Set, the host does not see that the device is connected, and + * the device does not receive + * signals on the USB. The core stays in the disconnected state until the application + * clears this bit. + * - 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the + * core drives the phy_opmode_o signal on the + * UTMI+ to 2'b00, which generates a device connect event to the USB host. When the + * device is reconnected, the USB host restarts device enumeration. + * - 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which + * generates a device disconnect event to the USB host. + * The following is the minimum duration under various conditions for which this bit + * must be set for the USB host to detect a device disconnect. To accommodate clock + * jitter, it is + * recommended that the application adds some extra delay to the specified minimum + * duration. + * + * For high speed, if the device state is, + * - Suspended, the minimum duration is 1ms + 2.5us + * - Idle, the minimum duration is 3ms + 2.5us + * - Not Idle or Suspended (performing transactions), the minimum duration 125 us + * For full speed/low speed, if the device state is, + * - Suspended, the minimum duration is 1ms + 2.5us + * - Idle, the minimum duration is 2.5us + * - Not Idle or Suspended (performing transactions), the minimum duration 125 us + * Note: + * - This bit can be also used for ULPI/FS Serial interfaces. + * - This bit is not impacted by a soft reset. + */ + uint32_t otgfs_dctl_sftdiscon:1; + /** otgfs_dctl_gnpinnaksts : RO; bitpos: [2]; default: 0; + * Global Non-periodic IN NAK Status (GNPINNakSts) + * - 1'b0: A handshake is sent out based on the data availability in the transmit FIFO. + * - 1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective + * of the data availability in the transmit FIFO. + */ + uint32_t otgfs_dctl_gnpinnaksts:1; + /** otgfs_dctl_goutnaksts : RO; bitpos: [3]; default: 0; + * Global OUT NAK Status (GOUTNakSts) + * - 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit + * settings. + * - 1'b1: No data is written to the RxFIFO, irrespective of space availability. Sends + * a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT + * packets are dropped. + */ + uint32_t otgfs_dctl_goutnaksts:1; + /** otgfs_dctl_tstctl : R/W; bitpos: [6:4]; default: 0; + * Test Control (TstCtl) + * - 3'b000: Test mode disabled + * - 3'b001: Test_J mode + * - 3'b010: Test_K mode + * - 3'b011: Test_SE0_NAK mode + * - 3'b100: Test_Packet mode + * - 3'b101: Test_Force_Enable + * - Others: Reserved + */ + uint32_t otgfs_dctl_tstctl:3; + /** otgfs_dctl_sgnpinnak : R/W; bitpos: [7]; default: 0; + * Set Global Non-periodic IN NAK (SGNPInNak) + * + * A write to this field sets the Global Non-periodic IN NAK.The application uses this + * bit to send a NAK handshake on all non-periodic IN endpoints. + * The core can also Set this bit when a timeout condition is detected on a + * non-periodic endpoint in shared FIFO operation. + * The application must Set this bit only after making sure that the Global IN NAK + * Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared + */ + uint32_t otgfs_dctl_sgnpinnak:1; + /** otgfs_dctl_cgnpinnak : R/W; bitpos: [8]; default: 0; + * Clear Global Non-periodic IN NAK (CGNPInNak) + * + * A write to this field clears the Global Non-periodic IN NAK. + */ + uint32_t otgfs_dctl_cgnpinnak:1; + /** otgfs_dctl_sgoutnak : R/W; bitpos: [9]; default: 0; + * Set Global OUT NAK (SGOUTNak) + * + * A write to this field sets the Global OUT NAK. The application uses this bit to + * send a NAK handshake on all OUT endpoints. + * The application must set the this bit only after making sure that the Global OUT + * NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. + */ + uint32_t otgfs_dctl_sgoutnak:1; + /** otgfs_dctl_cgoutnak : R/W; bitpos: [10]; default: 0; + * Clear Global OUT NAK (CGOUTNak) + * + * A write to this field clears the Global OUT NAK. + */ + uint32_t otgfs_dctl_cgoutnak:1; + /** otgfs_dctl_pwronprgdone : R/W; bitpos: [11]; default: 0; + * Power-On Programming Done (PWROnPrgDone) + * + * The application uses this bit to indicate that register programming is completed + * after a wake-up from Power Down mode. + */ + uint32_t otgfs_dctl_pwronprgdone:1; + uint32_t reserved_12:1; + /** otgfs_dctl_gmc : R/W; bitpos: [14:13]; default: 0; + * Global Multi Count (GMC) + * + * GMC must be programmed only once after initialization. + * Applicable only for Scatter/Gather DMA mode. This indicates the number of packets + * to be serviced for that end point before moving to the next end point. It is only + * for non-periodic endpoints. + * - 2'b00: Invalid. + * - 2'b01: 1 packet. + * - 2'b10: 2 packets. + * - 2'b11: 3 packets. + * The value of this field automatically changes to 2'h1 when DCFG.DescDMA is set to + * 1. When Scatter/Gather DMA mode is disabled, this field is reserved. and reads + * 2'b00. + */ + uint32_t otgfs_dctl_gmc:2; + /** otgfs_dctl_ignrfrmnum : R/W; bitpos: [15]; default: 0; + * Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + * + * This field is also used to control the Periodic Transfer Interrupt (PTI) feature. + * + * Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold + * mode. + * + * Slave Mode (GAHBCFG.DMAEn=0): + * + * This bit is not valid in Slave mode and should not be programmed to 1. + * + * Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1): + * + * Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to + * High Speed, High bandwidth transfers. + * + * When this bit is enabled, there must be only one packet per descriptor. + * - 0: The core transmits the packets only in the frame number in which they are + * intended to be transmitted. + * - 1: The core ignores the frame number, sending packets immediately as the packets + * are ready. + * In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed + * when a ISOC IN token is received for an elapsed frame. + * + * Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode + * (GAHBCFG.DMAEn=1,DCFG.DescDMA=0): + * + * When Scatter/Gather DMA mode is disabled, this field is used by the application to + * enable Periodic Transfer Interrupt (PTI) Mode. + * + * The application can program Periodic Endpoint transfers for multiple (micro)Frames. + * - 0: Periodic Transfer Interrupt feature is disabled, application needs to program + * transfers for periodic endpoints every (micro)Frame + * - 1: Periodic Transfer Interrupt feature is enabled, application can program + * transfers for multiple (micro)Frames for periodic endpoints. + * In the PTI mode, the application will receive Transfer Complete Interrupt after + * transfers for multiple (micro)Frames are completed. + */ + uint32_t otgfs_dctl_ignrfrmnum:1; + /** otgfs_dctl_nakonbble : R/W; bitpos: [16]; default: 0; + * NAK on Babble Error (NakOnBble) + * + * Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for + * the endpoint on which babble is received. + */ + uint32_t otgfs_dctl_nakonbble:1; + /** otgfs_dctl_encontonbna : R/W; bitpos: [17]; default: 0; + * Enable Continue on BNA (EnContOnBNA) + * + * This bit enables the core to continue on BNA for Bulk OUT endpoints. + * With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA + * interrupt + * the core starts processing the descriptor that caused the BNA interrupt after + * the endpoint re-enables the endpoint. + * - 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the + * endpoint is re-enabled by the application,the core starts processing from the + * DOEPDMA descriptor. + * - 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the + * endpoint is re-enabled by the application, the core starts processing from the + * descriptor that received the BNA interrupt. + * + * This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable + * after reset bit like any other DCTL register bits. + */ + uint32_t otgfs_dctl_encontonbna:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} usb_otgfs_dctl_reg_t; + + +/** Group: Device Status Register */ +/** Type of otgfs_dsts register + * Device Status Register This register indicates the status of the core with respect + * to USB-related events. It must be read on interrupts from Device All Interrupts + * (DAINT) register. + */ +typedef union { + struct { + /** otgfs_dsts_suspsts : RO; bitpos: [0]; default: 0; + * Suspend Status (SuspSts) + * + * In Device mode, this bit is set as long as a Suspend condition is + * detected on the USB. The core enters the Suspend state + * when there is no activity on the phy_line_state_i signal for an + * extended period of time. The core comes out of the suspend under the following + * conditions : + * - If there is any activity on the phy_line_state_i signal, or + * - If the application writes to the Remote Wakeup Signaling bit in the Device + * Control register (DCTL.RmtWkUpSig). + * When the core comes out of the suspend, this bit is set to 1'b0. + */ + uint32_t otgfs_dsts_suspsts:1; + /** otgfs_dsts_enumspd : RO; bitpos: [2:1]; default: 1; + * Enumerated Speed (EnumSpd) + * + * Indicates the speed at which the controller has come up + * after speed detection through a connect or reset sequence. + * - 2'b00: High speed (PHY clock is running at 30 or 60 MHz) + * - 2'b01: Full speed (PHY clock is running at 30 or 60 MHz) + * - 2'b10: Low speed (PHY clock is running at 6 MHz) + * - 2'b11: Full speed (PHY clock is running at 48 MHz) + * Low speed is not supported for devices using a UTMI+ PHY. + */ + uint32_t otgfs_dsts_enumspd:2; + /** otgfs_dsts_errticerr : RO; bitpos: [3]; default: 0; + * Erratic Error (ErrticErr) + * + * The core sets this bit to report any erratic errors + * (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at + * least 2 ms, due to PHY error) seen on the UTMI+. + * Due to erratic errors, the DWC_otg core goes into Suspended + * state and an interrupt is generated to the application with Early + * Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). + * If the early suspend is asserted due to an erratic error, the + * application can only perform a soft disconnect recover. + */ + uint32_t otgfs_dsts_errticerr:1; + uint32_t reserved_4:4; + /** otgfs_dsts_soffn : RO; bitpos: [21:8]; default: 0; + * Frame or Microframe Number of the Received SOF (SOFFN) + * + * When the core is operating at high speed, this field contains a microframe number. + * When the core is operating at full or low speed, this field contains a Frame number. + * + * Note: This register may return a non-zero value if read immediately after power-on + * reset. + * In case the register bit reads non-zero immediately after power-on reset, it does + * not + * indicate that SOF has been received from the host. The read value of this interrupt + * is + * valid only after a valid connection between host and device is established. + */ + uint32_t otgfs_dsts_soffn:14; + /** otgfs_dsts_devlnsts : RO; bitpos: [23:22]; default: 0; + * Device Line Status (DevLnSts) + * + * Indicates the current logic level USB data lines + * - DevLnSts[1]: Logic level of D+ + * - DevLnSts[0]: Logic level of D- + */ + uint32_t otgfs_dsts_devlnsts:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_otgfs_dsts_reg_t; + + +/** Group: Device IN Endpoint Common Interrupt Mask Register */ +/** Type of otgfs_diepmsk register + * Device IN Endpoint Common Interrupt Mask Register This register works with each of + * the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate + * an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in + * the DIEPINTn register can be masked by writing to the corresponding bit in this + * register. Status bits are masked by default. + */ +typedef union { + struct { + /** otgfs_diepmsk_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt Mask (XferComplMsk) + */ + uint32_t otgfs_diepmsk_xfercomplmsk:1; + /** otgfs_diepmsk_epdisbldmsk : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt Mask (EPDisbldMsk) + */ + uint32_t otgfs_diepmsk_epdisbldmsk:1; + /** otgfs_diepmsk_ahberrmsk : R/W; bitpos: [2]; default: 0; + * AHB Error Mask (AHBErrMsk) + */ + uint32_t otgfs_diepmsk_ahberrmsk:1; + /** otgfs_diepmsk_timeoutmsk : R/W; bitpos: [3]; default: 0; + * Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + */ + uint32_t otgfs_diepmsk_timeoutmsk:1; + /** otgfs_diepmsk_intkntxfempmsk : R/W; bitpos: [4]; default: 0; + * IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + */ + uint32_t otgfs_diepmsk_intkntxfempmsk:1; + /** otgfs_diepmsk_intknepmismsk : R/W; bitpos: [5]; default: 0; + * IN Token received with EP Mismatch Mask (INTknEPMisMsk) + */ + uint32_t otgfs_diepmsk_intknepmismsk:1; + /** otgfs_diepmsk_inepnakeffmsk : R/W; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective Mask (INEPNakEffMsk) + */ + uint32_t otgfs_diepmsk_inepnakeffmsk:1; + uint32_t reserved_7:1; + /** otgfs_diepmsk_txfifoundrnmsk : R/W; bitpos: [8]; default: 0; + * Fifo Underrun Mask (TxfifoUndrnMsk) + */ + uint32_t otgfs_diepmsk_txfifoundrnmsk:1; + /** otgfs_diepmsk_bnainintrmsk : R/W; bitpos: [9]; default: 0; + * BNA interrupt Mask (BNAInIntrMsk) + */ + uint32_t otgfs_diepmsk_bnainintrmsk:1; + uint32_t reserved_10:3; + /** otgfs_diepmsk_nakmsk : R/W; bitpos: [13]; default: 0; + * NAK interrupt Mask (NAKMsk) + */ + uint32_t otgfs_diepmsk_nakmsk:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} usb_otgfs_diepmsk_reg_t; + + +/** Group: Device OUT Endpoint Common Interrupt Mask Register */ +/** Type of otgfs_doepmsk register + * Device OUT Endpoint Common Interrupt Mask Register This register works with each + * of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to + * generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific + * status in the DOEPINTn register can be masked by writing into the corresponding bit + * in this register. Status bits are masked by default. + */ +typedef union { + struct { + /** otgfs_doepmsk_xfercomplmsk : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt Mask (XferComplMsk) + */ + uint32_t otgfs_doepmsk_xfercomplmsk:1; + /** otgfs_doepmsk_epdisbldmsk : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt Mask (EPDisbldMsk) + */ + uint32_t otgfs_doepmsk_epdisbldmsk:1; + /** otgfs_doepmsk_ahberrmsk : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErrMsk) + */ + uint32_t otgfs_doepmsk_ahberrmsk:1; + /** otgfs_doepmsk_setupmsk : R/W; bitpos: [3]; default: 0; + * SETUP Phase Done Mask (SetUPMsk) + * + * Applies to control endpoints only. + */ + uint32_t otgfs_doepmsk_setupmsk:1; + /** otgfs_doepmsk_outtknepdismsk : R/W; bitpos: [4]; default: 0; + * OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + * + * Applies to control OUT endpoints only. + */ + uint32_t otgfs_doepmsk_outtknepdismsk:1; + /** otgfs_doepmsk_stsphsercvdmsk : R/W; bitpos: [5]; default: 0; + * Status Phase Received Mask (StsPhseRcvdMsk) + * + * Applies to control OUT endpoints only. + */ + uint32_t otgfs_doepmsk_stsphsercvdmsk:1; + /** otgfs_doepmsk_back2backsetup : R/W; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + * + * Applies to control OUT endpoints only. + */ + uint32_t otgfs_doepmsk_back2backsetup:1; + uint32_t reserved_7:1; + /** otgfs_doepmsk_outpkterrmsk : R/W; bitpos: [8]; default: 0; + * OUT Packet Error Mask (OutPktErrMsk) + */ + uint32_t otgfs_doepmsk_outpkterrmsk:1; + /** otgfs_doepmsk_bnaoutintrmsk : R/W; bitpos: [9]; default: 0; + * BNA interrupt Mask (BnaOutIntrMsk) + */ + uint32_t otgfs_doepmsk_bnaoutintrmsk:1; + uint32_t reserved_10:2; + /** otgfs_doepmsk_bbleerrmsk : R/W; bitpos: [12]; default: 0; + * Babble Error interrupt Mask (BbleErrMsk) + */ + uint32_t otgfs_doepmsk_bbleerrmsk:1; + /** otgfs_doepmsk_nakmsk : R/W; bitpos: [13]; default: 0; + * NAK interrupt Mask (NAKMsk) + */ + uint32_t otgfs_doepmsk_nakmsk:1; + /** otgfs_doepmsk_nyetmsk : R/W; bitpos: [14]; default: 0; + * NYET interrupt Mask (NYETMsk) + */ + uint32_t otgfs_doepmsk_nyetmsk:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} usb_otgfs_doepmsk_reg_t; + + +/** Group: Device All Endpoints Interrupt Register */ +/** Type of otgfs_daint register + * Device All Endpoints Interrupt Register When a significant event occurs on an + * endpoint, a Device All Endpoints Interrupt register interrupts the application + * using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit + * of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). + * This is shown in Figure 5-2. There is one interrupt bit per endpoint, up to a + * maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a + * bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits + * in this register are set and cleared when the application sets and clears bits in + * the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). + */ +typedef union { + struct { + /** otgfs_daint_inepint0 : RO; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt Bit + */ + uint32_t otgfs_daint_inepint0:1; + /** otgfs_daint_inepint1 : RO; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt Bit + */ + uint32_t otgfs_daint_inepint1:1; + /** otgfs_daint_inepint2 : RO; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt Bit + */ + uint32_t otgfs_daint_inepint2:1; + /** otgfs_daint_inepint3 : RO; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt Bit + */ + uint32_t otgfs_daint_inepint3:1; + /** otgfs_daint_inepint4 : RO; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt Bit + */ + uint32_t otgfs_daint_inepint4:1; + /** otgfs_daint_inepint5 : RO; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt Bit + */ + uint32_t otgfs_daint_inepint5:1; + /** otgfs_daint_inepint6 : RO; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt Bit + */ + uint32_t otgfs_daint_inepint6:1; + uint32_t reserved_7:9; + /** otgfs_daint_outepint0 : RO; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt Bit + */ + uint32_t otgfs_daint_outepint0:1; + /** otgfs_daint_outepint1 : RO; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt Bit + */ + uint32_t otgfs_daint_outepint1:1; + /** otgfs_daint_outepint2 : RO; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt Bit + */ + uint32_t otgfs_daint_outepint2:1; + /** otgfs_daint_outepint3 : RO; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt Bit + */ + uint32_t otgfs_daint_outepint3:1; + /** otgfs_daint_outepint4 : RO; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt Bit + */ + uint32_t otgfs_daint_outepint4:1; + /** otgfs_daint_outepint5 : RO; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt Bit + */ + uint32_t otgfs_daint_outepint5:1; + /** otgfs_daint_outepint6 : RO; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt Bit + */ + uint32_t otgfs_daint_outepint6:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_otgfs_daint_reg_t; + + +/** Group: Device All Endpoints Interrupt Mask Register */ +/** Type of otgfs_daintmsk register + * Device All Endpoints Interrupt Mask Register The Device Endpoint Interrupt Mask + * register works with the Device Endpoint Interrupt register to interrupt the + * application when an event occurs on a device endpoint. However, the Device All + * Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still + * set. + */ +typedef union { + struct { + /** otgfs_daintmsk_inepmsk0 : R/W; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk0:1; + /** otgfs_daintmsk_inepmsk1 : R/W; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk1:1; + /** otgfs_daintmsk_inepmsk2 : R/W; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk2:1; + /** otgfs_daintmsk_inepmsk3 : R/W; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk3:1; + /** otgfs_daintmsk_inepmsk4 : R/W; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk4:1; + /** otgfs_daintmsk_inepmsk5 : R/W; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk5:1; + /** otgfs_daintmsk_inepmsk6 : R/W; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_inepmsk6:1; + uint32_t reserved_7:9; + /** otgfs_daintmsk_outepmsk0 : R/W; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk0:1; + /** otgfs_daintmsk_outepmsk1 : R/W; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk1:1; + /** otgfs_daintmsk_outepmsk2 : R/W; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk2:1; + /** otgfs_daintmsk_outepmsk3 : R/W; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk3:1; + /** otgfs_daintmsk_outepmsk4 : R/W; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk4:1; + /** otgfs_daintmsk_outepmsk5 : R/W; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk5:1; + /** otgfs_daintmsk_outepmsk6 : R/W; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt mask Bit + */ + uint32_t otgfs_daintmsk_outepmsk6:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_otgfs_daintmsk_reg_t; + + +/** Group: Device VBUS Discharge Time Register */ +/** Type of otgfs_dvbusdis register + * Device VBUS Discharge Time Register This register specifies the VBUS discharge + * time after VBUS pulsing during SRP. + */ +typedef union { + struct { + /** otgfs_dvbusdis_dvbusdis : R/W; bitpos: [15:0]; default: 6103; + * Device VBUS Discharge Time (DVBUSDis) + * + * Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals + * (VBUS discharge time in PHY clocks) / 1, 024. + * + * The value you use depends whether the PHY is operating at 30MHz (16-bit data width) + * or 60 MHz (8-bit data width). + * + * Depending on your VBUS load, this value can need adjustment. + */ + uint32_t otgfs_dvbusdis_dvbusdis:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_otgfs_dvbusdis_reg_t; + + +/** Group: Device VBUS Pulsing Time Register */ +/** Type of otgfs_dvbuspulse register + * Device VBUS Pulsing Time Register + */ +typedef union { + struct { + /** otgfs_dvbuspulse_dvbuspulse : R/W; bitpos: [11:0]; default: 1464; + * Device VBUS Pulsing Time (DVBUSPulse) + * + * Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in + * PHY clocks) / 1, 024 + * + * The value you use depends whether the PHY is operating at 30MHz (16-bit data width) + * or 60 MHz (8-bit data width). + */ + uint32_t otgfs_dvbuspulse_dvbuspulse:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} usb_otgfs_dvbuspulse_reg_t; + + +/** Group: Device Threshold Control Register */ +/** Type of otgfs_dthrctl register + * Device Threshold Control Register + */ +typedef union { + struct { + /** otgfs_dthrctl_nonisothren : R/W; bitpos: [0]; default: 0; + * Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + * + * When this bit is Set, the core enables thresholding for Non Isochronous IN + * endpoints. + */ + uint32_t otgfs_dthrctl_nonisothren:1; + /** otgfs_dthrctl_isothren : R/W; bitpos: [1]; default: 0; + * + * ISO IN Endpoints Threshold Enable. (ISOThrEn) + * + * When this bit is Set, the core enables thresholding for isochronous IN + * endpoints. + */ + uint32_t otgfs_dthrctl_isothren:1; + /** otgfs_dthrctl_txthrlen : R/W; bitpos: [10:2]; default: 8; + * Transmit Threshold Length (TxThrLen) + * + * This field specifies Transmit thresholding size in DWORDS. This also forms + * the MAC threshold and specifies the amount of data in bytes to be in the + * corresponding endpoint transmit FIFO, before the core can start transmit + * on the USB. The threshold length has to be at least eight DWORDS when the + * value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the + * application needs to ensure that the AHB Threshold value does not go below + * the recommended eight DWORD. This field controls both isochronous and + * non-isochronous IN endpoint thresholds. The recommended value for ThrLen + * is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen). + * + * Note: + * - When OTG_ARCHITECTURE=0, the reset value of this register field is 0. + * - When OTG_ARCHITECTURE=2, the reset value of this register field is 8. + */ + uint32_t otgfs_dthrctl_txthrlen:9; + /** otgfs_dthrctl_ahbthrratio : R/W; bitpos: [12:11]; default: 0; + * AHB Threshold Ratio (AHBThrRatio) + * + * These bits define the ratio between the AHB threshold and the MAC threshold for the + * transmit path only. The AHB threshold always remains less than or equal to the USB + * threshold, because this does not increase overhead. Both the AHB and the MAC + * threshold must be DWORD-aligned. The application needs to program TxThrLen and the + * AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold + * value is not DWORD aligned, the core might not behave correctly. When programming + * the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB + * threshold value does not go below 8 DWORDS to meet the USB turnaround time + * requirements. + * - 2'b00: AHB threshold = MAC threshold + * - 2'b01: AHB threshold = MAC threshold / 2 + * - 2'b10: AHB threshold = MAC threshold / 4 + * - 2'b11: AHB threshold = MAC threshold / 8 + */ + uint32_t otgfs_dthrctl_ahbthrratio:2; + uint32_t reserved_13:3; + /** otgfs_dthrctl_rxthren : R/W; bitpos: [16]; default: 0; + * Receive Threshold Enable (RxThrEn) + * + * When this bit is set, the core enables thresholding in the receive direction. + * + * Note: We recommends that you do not enable RxThrEn, because it may cause issues in + * the RxFIFO especially during error conditions such as RxError and Babble. + */ + uint32_t otgfs_dthrctl_rxthren:1; + /** otgfs_dthrctl_rxthrlen : R/W; bitpos: [25:17]; default: 8; + * Receive Threshold Length (RxThrLen) + * + * This field specifies Receive thresholding size in DWORDS. + * This field also specifies the amount of data received on the USB before the core + * can start transmitting on the AHB. + * The threshold length has to be at least eight DWORDS. + * The recommended value for ThrLen is to be the same as the programmed + * AHB Burst Length (GAHBCFG.HBstLen). + */ + uint32_t otgfs_dthrctl_rxthrlen:9; + uint32_t reserved_26:1; + /** otgfs_dthrctl_arbprken : R/W; bitpos: [27]; default: 1; + * Arbiter Parking Enable (ArbPrkEn) + * + * This bit controls internal DMA arbiter parking for IN endpoints. If thresholding is + * enabled and this bit is set to one, then the arbiter parks on the IN endpoint for + * which there is a token received on the USB. This is done to avoid getting into + * underrun conditions. By default, arbiter parking is enabled. + */ + uint32_t otgfs_dthrctl_arbprken:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} usb_otgfs_dthrctl_reg_t; + + +/** Group: Device IN Endpoint FIFO Empty Interrupt Mask Register */ +/** Type of otgfs_diepempmsk register + * Device IN Endpoint FIFO Empty Interrupt Mask Register This register is valid only + * in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to + * control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp). + */ +typedef union { + struct { + /** otgfs_diepempmsk_ineptxfempmsk : R/W; bitpos: [15:0]; default: 0; + * IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + * + * These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint: + * + * Bit 0 for IN EP 0, bit 15 for IN EP 15 + */ + uint32_t otgfs_diepempmsk_ineptxfempmsk:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_otgfs_diepempmsk_reg_t; + + +/** Group: Device Control IN Endpoint 0 Control Register */ +/** Type of otgfs_diepctl0 register + * Device Control IN Endpoint 0 Control Register + */ +typedef union { + struct { + /** otgfs_diepctl0_mps : R/W; bitpos: [1:0]; default: 0; + * Maximum Packet Size (MPS) + * + * Applies to IN and OUT endpoints. + * + * The application must program this field with the maximum packet size for the + * current logical endpoint. + * - 2'b00: 64 bytes + * - 2'b01: 32 bytes + * - 2'b10: 16 bytes + * - 2'b11: 8 bytes + */ + uint32_t otgfs_diepctl0_mps:2; + uint32_t reserved_2:13; + /** otgfs_diepctl0_usbactep : RO; bitpos: [15]; default: 1; + * USB Active Endpoint (USBActEP) + * + * This bit is always SET to 1, indicating that control endpoint 0 is always active in + * all configurations and interfaces. + */ + uint32_t otgfs_diepctl0_usbactep:1; + uint32_t reserved_16:1; + /** otgfs_diepctl0_naksts : RO; bitpos: [17]; default: 0; + * NAK Status (NAKSts) + * + * Indicates the following: + * - 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status + * - 1'b1: The core is transmitting NAK handshakes on this endpoint. + * When this bit is set, either by the application or core, the core stops + * transmitting data, even If there is data available in the TxFIFO. + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + */ + uint32_t otgfs_diepctl0_naksts:1; + /** otgfs_diepctl0_eptype : RO; bitpos: [19:18]; default: 0; + * Endpoint Type (EPType) + * + * Hardcoded to 00 for control. + */ + uint32_t otgfs_diepctl0_eptype:2; + uint32_t reserved_20:1; + /** otgfs_diepctl0_stall : R/W; bitpos: [21]; default: 0; + * STALL Handshake (Stall) + * + * The application can only set this bit, and the core clears it, when a + * SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic + * IN NAK, or Global OUT NAK is set along with this bit, the STALL + * bit takes priority. + */ + uint32_t otgfs_diepctl0_stall:1; + /** otgfs_diepctl0_txfnum : R/W; bitpos: [25:22]; default: 0; + * TxFIFO Number (TxFNum) + * - For Shared FIFO operation, this value is always set to 0, indicating that control + * IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO. + * - For Dedicated FIFO operation, this value is set to the FIFO number that is + * assigned to IN Endpoint. + */ + uint32_t otgfs_diepctl0_txfnum:4; + /** otgfs_diepctl0_cnak : R/W; bitpos: [26]; default: 0; + * + * Clear NAK (CNAK) + * A write to this bit clears the NAK bit for the endpoint. + */ + uint32_t otgfs_diepctl0_cnak:1; + /** otgfs_diepctl0_snak : R/W; bitpos: [27]; default: 0; + * + * Set NAK (SNAK) + * A write to this bit sets the NAK bit for the endpoint. + * Using this bit, the application can control the transmission of NAK + * handshakes on an endpoint. The core can also set this bit for an + * endpoint after a SETUP packet is received on that endpoint. + */ + uint32_t otgfs_diepctl0_snak:1; + uint32_t reserved_28:2; + /** otgfs_diepctl0_epdis : R/W; bitpos: [30]; default: 0; + * Endpoint Disable (EPDis) + * + * The application sets this bit to stop transmitting data on an endpoint, + * even before the transfer for that endpoint is complete. The application + * must wait for the Endpoint Disabled interrupt before treating the endpoint + * as disabled. The core clears this bit before setting the Endpoint Disabled + * Interrupt. The application must Set this bit only if Endpoint Enable is + * already set for this endpoint. + */ + uint32_t otgfs_diepctl0_epdis:1; + /** otgfs_diepctl0_epena : R/W; bitpos: [31]; default: 0; + * Endpoint Enable (EPEna) + * + * When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that + * the descriptor structure and data buffer with data ready to transmit is setup. + * + * When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) + * this bit indicates that data is ready to be transmitted on the endpoint. + * The core clears this bit before setting the following interrupts on this endpoint: + * - Endpoint Disabled + * - Transfer Completed + */ + uint32_t otgfs_diepctl0_epena:1; + }; + uint32_t val; +} usb_otgfs_diepctl0_reg_t; + + +/** Group: Device IN Endpoint 0 Interrupt Register */ +/** Type of otgfs_diepint0 register + * Device IN Endpoint 0 Interrupt Register This register indicates the status of an + * endpoint with respect to USB- and AHB-related events. It is shown in the Interrupt + * Hierarchy figure in the databook. The application must read this register when the + * OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt + * register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the + * application can read this register, it must first read the Device All Endpoints + * Interrupt (DAINT) register to get the exact endpoint number for the Device + * Endpoint-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the DAINT and GINTSTS registers + */ +typedef union { + struct { + /** otgfs_diepint0_xfercompl : R/W; bitpos: [0]; default: 0; + * Transfer Completed Interrupt (XferCompl) + * + * Applies to IN and OUT endpoints. + * - When Scatter/Gather DMA mode is enabled + * -- For IN endpoint this field indicates that the requested data from the descriptor + * is moved from external system memory to internal FIFO. + * -- For OUT endpoint this field indicates that the requested data from the internal + * FIFO is moved to external system memory. This interrupt is generated only when the + * corresponding endpoint descriptor is closed, and the IOC bit for the corresponding + * descriptor is set. + * - When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this endpoint. + */ + uint32_t otgfs_diepint0_xfercompl:1; + /** otgfs_diepint0_epdisbld : R/W; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt (EPDisbld) + * + * Applies to IN and OUT endpoints. + * + * This bit indicates that the endpoint is disabled per the application's request. + */ + uint32_t otgfs_diepint0_epdisbld:1; + /** otgfs_diepint0_ahberr : R/W; bitpos: [2]; default: 0; + * AHB Error (AHBErr) + * + * Applies to IN and OUT endpoints. + * + * This is generated only in Internal DMA mode when there is an AHB error during an + * AHB read/write. The application can read the corresponding endpoint DMA address + * register to get the error address. + */ + uint32_t otgfs_diepint0_ahberr:1; + /** otgfs_diepint0_timeout : R/W; bitpos: [3]; default: 0; + * Timeout Condition (TimeOUT) + * - In shared TX FIFO mode, applies to non-isochronous IN endpoints only. + * - In dedicated FIFO mode, applies only to Control IN endpoints. + * - In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted. + * Indicates that the core has detected a timeout condition on the USB for the last IN + * token on this endpoint. + */ + uint32_t otgfs_diepint0_timeout:1; + /** otgfs_diepint0_intkntxfemp : R/W; bitpos: [4]; default: 0; + * IN Token Received When TxFIFO is Empty (INTknTXFEmp) + * + * Applies to non-periodic IN endpoints only. + * + * Indicates that an IN token was received when the associated TxFIFO + * (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for + * which the IN token was received. + */ + uint32_t otgfs_diepint0_intkntxfemp:1; + /** otgfs_diepint0_intknepmis : R/W; bitpos: [5]; default: 0; + * IN Token Received with EP Mismatch (INTknEPMis) + * + * Applies to non-periodic IN endpoints only. + * + * Indicates that the data in the top of the non-periodic TxFIFO belongs to an + * endpoint other than the one for which the IN token was received. This interrupt is + * asserted on the endpoint for which the IN token was received. + */ + uint32_t otgfs_diepint0_intknepmis:1; + /** otgfs_diepint0_inepnakeff : R/W; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective (INEPNakEff) + * + * Applies to periodic IN endpoints only. + * + * This bit can be cleared when the application clears the IN endpoint NAK by writing + * to DIEPCTLn.CNAK. + * + * This interrupt indicates that the core has sampled the NAK bit + * + * Set (either by the application or by the core). + * + * The interrupt indicates that the IN endpoint NAK bit Set by the application has + * taken effect in the core. + * + * This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL + * bit takes priority over a NAK bit. + */ + uint32_t otgfs_diepint0_inepnakeff:1; + /** otgfs_diepint0_txfemp : RO; bitpos: [7]; default: 1; + * Transmit FIFO Empty (TxFEmp) + * + * This bit is valid only for IN Endpoints + * + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty. The half or completely empty status is determined by the TxFIFO + * Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + */ + uint32_t otgfs_diepint0_txfemp:1; + /** otgfs_diepint0_txfifoundrn : R/W; bitpos: [8]; default: 0; + * Fifo Underrun (TxfifoUndrn) + * + * Applies to IN endpoints only. + * + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint. + */ + uint32_t otgfs_diepint0_txfifoundrn:1; + /** otgfs_diepint0_bnaintr : R/W; bitpos: [9]; default: 0; + * BNA (Buffer Not Available) Interrupt (BNAIntr) + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done. + */ + uint32_t otgfs_diepint0_bnaintr:1; + uint32_t reserved_10:1; + /** otgfs_diepint0_pktdrpsts : R/W; bitpos: [11]; default: 0; + * Packet Drop Status (PktDrpSts) + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an interrupt. + * + * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer + * interrupt feature is selected. + */ + uint32_t otgfs_diepint0_pktdrpsts:1; + /** otgfs_diepint0_bbleerr : R/W; bitpos: [12]; default: 0; + * NAK Interrupt (BbleErr) + * + * The core generates this interrupt when babble is received for the endpoint. + */ + uint32_t otgfs_diepint0_bbleerr:1; + /** otgfs_diepint0_nakintrpt : R/W; bitpos: [13]; default: 0; + * NAK Interrupt (NAKInterrupt) + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. + * +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16)) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register + * USB uart out endpoint timeout configuration. + */ +#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0; + * USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer + * is automatically cleared and reg_serial_timeout_status is asserted. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S 0 +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0; + * Serial out ep triggers a timeout event. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S 1 +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear reg_serial_timeout_status. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S 2 + +/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register + * USB uart out endpoint timeout configuration. + */ +#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768; + * USB serial out ep timeout max threshold value, indicates the maximum time that + * waiting for ESP to take away data in memory. This value is in steps of 20.83ns. + */ +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX 0xFFFFFFFFU +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S) +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37777456; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32h4/register/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..e7bca05829 --- /dev/null +++ b/components/soc/esp32h4/register/soc/usb_serial_jtag_struct.h @@ -0,0 +1,982 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of serial_jtag_ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** serial_jtag_rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t serial_jtag_rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of serial_jtag_ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** serial_jtag_wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t serial_jtag_wr_done:1; + /** serial_jtag_serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_jtag_serial_in_ep_data_free:1; + /** serial_jtag_serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_jtag_serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of serial_jtag_conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** serial_jtag_exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t serial_jtag_exchg_pins_override:1; + /** serial_jtag_exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t serial_jtag_exchg_pins:1; + /** serial_jtag_vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t serial_jtag_vrefh:2; + /** serial_jtag_vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t serial_jtag_vrefl:2; + /** serial_jtag_vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t serial_jtag_vref_override:1; + /** serial_jtag_pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t serial_jtag_pad_pull_override:1; + /** serial_jtag_dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t serial_jtag_dp_pullup:1; + /** serial_jtag_dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t serial_jtag_dp_pulldown:1; + /** serial_jtag_dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t serial_jtag_dm_pullup:1; + /** serial_jtag_dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t serial_jtag_dm_pulldown:1; + /** serial_jtag_pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t serial_jtag_pullup_value:1; + /** serial_jtag_usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t serial_jtag_usb_pad_enable:1; + /** serial_jtag_usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t serial_jtag_usb_jtag_bridge_en:1; + /** serial_jtag_usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ + uint32_t serial_jtag_usb_phy_tx_edge_sel:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of serial_jtag_test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** serial_jtag_test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t serial_jtag_test_enable:1; + /** serial_jtag_test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t serial_jtag_test_usb_oe:1; + /** serial_jtag_test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t serial_jtag_test_tx_dp:1; + /** serial_jtag_test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t serial_jtag_test_tx_dm:1; + /** serial_jtag_test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t serial_jtag_test_rx_rcv:1; + /** serial_jtag_test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t serial_jtag_test_rx_dp:1; + /** serial_jtag_test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t serial_jtag_test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of serial_jtag_misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** serial_jtag_clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t serial_jtag_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of serial_jtag_mem_conf register + * Memory power control + */ +typedef union { + struct { + /** serial_jtag_usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t serial_jtag_usb_mem_pd:1; + /** serial_jtag_usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t serial_jtag_usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of serial_jtag_chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** serial_jtag_rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t serial_jtag_rts:1; + /** serial_jtag_dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t serial_jtag_dtr:1; + /** serial_jtag_usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t serial_jtag_usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of serial_jtag_get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of serial_jtag_get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bdata_bits:8; + /** serial_jtag_get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bparity_type:8; + /** serial_jtag_get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t serial_jtag_get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of serial_jtag_config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** serial_jtag_config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t serial_jtag_config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of serial_jtag_ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_jtag_serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_reset_wr:1; + /** serial_jtag_serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_reset_rd:1; + /** serial_jtag_serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_reset_wr:1; + /** serial_jtag_serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_reset_rd:1; + /** serial_jtag_serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_jtag_serial_out_afifo_rempty:1; + /** serial_jtag_serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_jtag_serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + +/** Type of serial_jtag_serial_ep_timeout0 register + * USB uart out endpoint timeout configuration. + */ +typedef union { + struct { + /** serial_jtag_serial_timeout_en : R/W; bitpos: [0]; default: 0; + * USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer + * is automatically cleared and reg_serial_timeout_status is asserted. + */ + uint32_t serial_jtag_serial_timeout_en:1; + /** serial_jtag_serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0; + * Serial out ep triggers a timeout event. + */ + uint32_t serial_jtag_serial_timeout_status:1; + /** serial_jtag_serial_timeout_status_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear reg_serial_timeout_status. + */ + uint32_t serial_jtag_serial_timeout_status_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_serial_ep_timeout0_reg_t; + +/** Type of serial_jtag_serial_ep_timeout1 register + * USB uart out endpoint timeout configuration. + */ +typedef union { + struct { + /** serial_jtag_serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768; + * USB serial out ep timeout max threshold value, indicates the maximum time that + * waiting for ESP to take away data in memory. This value is in steps of 20.83ns. + */ + uint32_t serial_jtag_serial_timeout_max:32; + }; + uint32_t val; +} usb_serial_jtag_serial_ep_timeout1_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of serial_jtag_int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t serial_jtag_jtag_in_flush_int_raw:1; + /** serial_jtag_sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t serial_jtag_sof_int_raw:1; + /** serial_jtag_serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_raw:1; + /** serial_jtag_serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_jtag_serial_in_empty_int_raw:1; + /** serial_jtag_pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t serial_jtag_pid_err_int_raw:1; + /** serial_jtag_crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t serial_jtag_crc5_err_int_raw:1; + /** serial_jtag_crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t serial_jtag_crc16_err_int_raw:1; + /** serial_jtag_stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t serial_jtag_stuff_err_int_raw:1; + /** serial_jtag_in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_raw:1; + /** serial_jtag_usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t serial_jtag_usb_bus_reset_int_raw:1; + /** serial_jtag_out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_raw:1; + /** serial_jtag_out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_raw:1; + /** serial_jtag_rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t serial_jtag_rts_chg_int_raw:1; + /** serial_jtag_dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t serial_jtag_dtr_chg_int_raw:1; + /** serial_jtag_get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t serial_jtag_get_line_code_int_raw:1; + /** serial_jtag_set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t serial_jtag_set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of serial_jtag_int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_st:1; + /** serial_jtag_sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_st:1; + /** serial_jtag_serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_st:1; + /** serial_jtag_serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_st:1; + /** serial_jtag_pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_st:1; + /** serial_jtag_crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_st:1; + /** serial_jtag_crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_st:1; + /** serial_jtag_stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_st:1; + /** serial_jtag_in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_st:1; + /** serial_jtag_usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_st:1; + /** serial_jtag_out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_st:1; + /** serial_jtag_out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_st:1; + /** serial_jtag_rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_st:1; + /** serial_jtag_dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_st:1; + /** serial_jtag_get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_st:1; + /** serial_jtag_set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of serial_jtag_int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_ena:1; + /** serial_jtag_sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_ena:1; + /** serial_jtag_serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_ena:1; + /** serial_jtag_serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_ena:1; + /** serial_jtag_pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_ena:1; + /** serial_jtag_crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_ena:1; + /** serial_jtag_crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_ena:1; + /** serial_jtag_stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_ena:1; + /** serial_jtag_in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_ena:1; + /** serial_jtag_usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_ena:1; + /** serial_jtag_out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_ena:1; + /** serial_jtag_out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_ena:1; + /** serial_jtag_rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_ena:1; + /** serial_jtag_dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_ena:1; + /** serial_jtag_get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_ena:1; + /** serial_jtag_set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of serial_jtag_int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** serial_jtag_jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t serial_jtag_jtag_in_flush_int_clr:1; + /** serial_jtag_sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t serial_jtag_sof_int_clr:1; + /** serial_jtag_serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_jtag_serial_out_recv_pkt_int_clr:1; + /** serial_jtag_serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_jtag_serial_in_empty_int_clr:1; + /** serial_jtag_pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t serial_jtag_pid_err_int_clr:1; + /** serial_jtag_crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc5_err_int_clr:1; + /** serial_jtag_crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t serial_jtag_crc16_err_int_clr:1; + /** serial_jtag_stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t serial_jtag_stuff_err_int_clr:1; + /** serial_jtag_in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t serial_jtag_in_token_rec_in_ep1_int_clr:1; + /** serial_jtag_usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t serial_jtag_usb_bus_reset_int_clr:1; + /** serial_jtag_out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep1_zero_payload_int_clr:1; + /** serial_jtag_out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t serial_jtag_out_ep2_zero_payload_int_clr:1; + /** serial_jtag_rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t serial_jtag_rts_chg_int_clr:1; + /** serial_jtag_dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t serial_jtag_dtr_chg_int_clr:1; + /** serial_jtag_get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_get_line_code_int_clr:1; + /** serial_jtag_set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t serial_jtag_set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of serial_jtag_jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** serial_jtag_in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t serial_jtag_in_fifo_cnt:2; + /** serial_jtag_in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t serial_jtag_in_fifo_empty:1; + /** serial_jtag_in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t serial_jtag_in_fifo_full:1; + /** serial_jtag_out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t serial_jtag_out_fifo_cnt:2; + /** serial_jtag_out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t serial_jtag_out_fifo_empty:1; + /** serial_jtag_out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t serial_jtag_out_fifo_full:1; + /** serial_jtag_in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t serial_jtag_in_fifo_reset:1; + /** serial_jtag_out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t serial_jtag_out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of serial_jtag_fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** serial_jtag_sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t serial_jtag_sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of serial_jtag_in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t serial_jtag_in_ep0_state:2; + /** serial_jtag_in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t serial_jtag_in_ep0_wr_addr:7; + /** serial_jtag_in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t serial_jtag_in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of serial_jtag_in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t serial_jtag_in_ep1_state:2; + /** serial_jtag_in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t serial_jtag_in_ep1_wr_addr:7; + /** serial_jtag_in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t serial_jtag_in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of serial_jtag_in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t serial_jtag_in_ep2_state:2; + /** serial_jtag_in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t serial_jtag_in_ep2_wr_addr:7; + /** serial_jtag_in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t serial_jtag_in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of serial_jtag_in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t serial_jtag_in_ep3_state:2; + /** serial_jtag_in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t serial_jtag_in_ep3_wr_addr:7; + /** serial_jtag_in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t serial_jtag_in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of serial_jtag_out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t serial_jtag_out_ep0_state:2; + /** serial_jtag_out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t serial_jtag_out_ep0_wr_addr:7; + /** serial_jtag_out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t serial_jtag_out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of serial_jtag_out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t serial_jtag_out_ep1_state:2; + /** serial_jtag_out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t serial_jtag_out_ep1_wr_addr:7; + /** serial_jtag_out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t serial_jtag_out_ep1_rd_addr:7; + /** serial_jtag_out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t serial_jtag_out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of serial_jtag_out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** serial_jtag_out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t serial_jtag_out_ep2_state:2; + /** serial_jtag_out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t serial_jtag_out_ep2_wr_addr:7; + /** serial_jtag_out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t serial_jtag_out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of serial_jtag_set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of serial_jtag_set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** serial_jtag_bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bchar_format:8; + /** serial_jtag_bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bparity_type:8; + /** serial_jtag_bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t serial_jtag_bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of serial_jtag_bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** serial_jtag_usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t serial_jtag_usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of serial_jtag_date register + * Date register + */ +typedef union { + struct { + /** serial_jtag_date : R/W; bitpos: [31:0]; default: 37777456; + * register version. + */ + uint32_t serial_jtag_date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct { + volatile usb_serial_jtag_ep1_reg_t serial_jtag_ep1; + volatile usb_serial_jtag_ep1_conf_reg_t serial_jtag_ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t serial_jtag_int_raw; + volatile usb_serial_jtag_int_st_reg_t serial_jtag_int_st; + volatile usb_serial_jtag_int_ena_reg_t serial_jtag_int_ena; + volatile usb_serial_jtag_int_clr_reg_t serial_jtag_int_clr; + volatile usb_serial_jtag_conf0_reg_t serial_jtag_conf0; + volatile usb_serial_jtag_test_reg_t serial_jtag_test; + volatile usb_serial_jtag_jfifo_st_reg_t serial_jtag_jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t serial_jtag_fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t serial_jtag_in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t serial_jtag_in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t serial_jtag_in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t serial_jtag_in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t serial_jtag_out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t serial_jtag_out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t serial_jtag_out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t serial_jtag_misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t serial_jtag_mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t serial_jtag_chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t serial_jtag_set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t serial_jtag_set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t serial_jtag_get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t serial_jtag_get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t serial_jtag_config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t serial_jtag_ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t serial_jtag_bus_reset_st; + volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_jtag_serial_ep_timeout0; + volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_jtag_serial_ep_timeout1; + uint32_t reserved_074[3]; + volatile usb_serial_jtag_date_reg_t serial_jtag_date; +} usb_dev_t; + +extern usb_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_dev_t) == 0x84, "Invalid size of usb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/usb_wrap_reg.h b/components/soc/esp32h4/register/soc/usb_wrap_reg.h new file mode 100644 index 0000000000..671d904287 --- /dev/null +++ b/components/soc/esp32h4/register/soc/usb_wrap_reg.h @@ -0,0 +1,168 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_WRAP_OTG_CONF_REG register + * USB wrapper configuration registers. + */ +#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_BASE + 0x0) +/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ +#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0)) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0 +/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ +#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1)) +#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S) +#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001U +#define USB_WRAP_SRP_SESSEND_VALUE_S 1 +/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ +#define USB_WRAP_PHY_SEL (BIT(2)) +#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S) +#define USB_WRAP_PHY_SEL_V 0x00000001U +#define USB_WRAP_PHY_SEL_S 2 +/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ +#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4)) +#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S) +#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001U +#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4 +/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ +#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5)) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5 +/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ +#define USB_WRAP_EXCHG_PINS (BIT(6)) +#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S) +#define USB_WRAP_EXCHG_PINS_V 0x00000001U +#define USB_WRAP_EXCHG_PINS_S 6 +/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ +#define USB_WRAP_VREFH 0x00000003U +#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S) +#define USB_WRAP_VREFH_V 0x00000003U +#define USB_WRAP_VREFH_S 7 +/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ +#define USB_WRAP_VREFL 0x00000003U +#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S) +#define USB_WRAP_VREFL_V 0x00000003U +#define USB_WRAP_VREFL_S 9 +/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ +#define USB_WRAP_VREF_OVERRIDE (BIT(11)) +#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S) +#define USB_WRAP_VREF_OVERRIDE_V 0x00000001U +#define USB_WRAP_VREF_OVERRIDE_S 11 +/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ +#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12)) +#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S) +#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_WRAP_PAD_PULL_OVERRIDE_S 12 +/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DP_PULLUP (BIT(13)) +#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S) +#define USB_WRAP_DP_PULLUP_V 0x00000001U +#define USB_WRAP_DP_PULLUP_S 13 +/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DP_PULLDOWN (BIT(14)) +#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S) +#define USB_WRAP_DP_PULLDOWN_V 0x00000001U +#define USB_WRAP_DP_PULLDOWN_S 14 +/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ +#define USB_WRAP_DM_PULLUP (BIT(15)) +#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S) +#define USB_WRAP_DM_PULLUP_V 0x00000001U +#define USB_WRAP_DM_PULLUP_S 15 +/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ +#define USB_WRAP_DM_PULLDOWN (BIT(16)) +#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S) +#define USB_WRAP_DM_PULLDOWN_V 0x00000001U +#define USB_WRAP_DM_PULLDOWN_S 16 +/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ +#define USB_WRAP_PULLUP_VALUE (BIT(17)) +#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S) +#define USB_WRAP_PULLUP_VALUE_V 0x00000001U +#define USB_WRAP_PULLUP_VALUE_S 17 +/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ +#define USB_WRAP_USB_PAD_ENABLE (BIT(18)) +#define USB_WRAP_USB_PAD_ENABLE_M (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S) +#define USB_WRAP_USB_PAD_ENABLE_V 0x00000001U +#define USB_WRAP_USB_PAD_ENABLE_S 18 +/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ +#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19)) +#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S) +#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_AHB_CLK_FORCE_ON_S 19 +/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ +#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20)) +#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S) +#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001U +#define USB_WRAP_PHY_CLK_FORCE_ON_S 20 +/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ +#define USB_WRAP_CLK_EN (BIT(31)) +#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S) +#define USB_WRAP_CLK_EN_V 0x00000001U +#define USB_WRAP_CLK_EN_S 31 + +/** USB_WRAP_DATE_REG register + * Date register. + */ +#define USB_WRAP_DATE_REG (DR_REG_USB_BASE + 0x3fc) +/** USB_WRAP_USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 37761536; + * Date register. + */ +#define USB_WRAP_USB_WRAP_DATE 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_M (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S) +#define USB_WRAP_USB_WRAP_DATE_V 0xFFFFFFFFU +#define USB_WRAP_USB_WRAP_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/usb_wrap_struct.h b/components/soc/esp32h4/register/soc/usb_wrap_struct.h new file mode 100644 index 0000000000..7680b6dc8f --- /dev/null +++ b/components/soc/esp32h4/register/soc/usb_wrap_struct.h @@ -0,0 +1,130 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: USB wrapper registers. */ +/** Type of wrap_otg_conf register + * USB wrapper configuration registers. + */ +typedef union { + struct { + /** wrap_srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software over-ride of srp session end signal. 1'b0: + * the signal is controlled by the chip input, 1'b1: the signal is controlled by the + * software. + */ + uint32_t wrap_srp_sessend_override:1; + /** wrap_srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software over-ride value of srp session end signal. + */ + uint32_t wrap_srp_sessend_value:1; + /** wrap_phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + */ + uint32_t wrap_phy_sel:1; + uint32_t reserved_3:1; + /** wrap_dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + */ + uint32_t wrap_dbnce_fltr_bypass:1; + /** wrap_exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software controlle USB D+ D- exchange + */ + uint32_t wrap_exchg_pins_override:1; + /** wrap_exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + */ + uint32_t wrap_exchg_pins:1; + /** wrap_vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV. + */ + uint32_t wrap_vrefh:2; + /** wrap_vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV. + */ + uint32_t wrap_vrefl:2; + /** wrap_vref_override : R/W; bitpos: [11]; default: 0; + * Enable software controlle input threshold. + */ + uint32_t wrap_vref_override:1; + /** wrap_pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software controlle USB D+ D- pullup pulldown. + */ + uint32_t wrap_pad_pull_override:1; + /** wrap_dp_pullup : R/W; bitpos: [13]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t wrap_dp_pullup:1; + /** wrap_dp_pulldown : R/W; bitpos: [14]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t wrap_dp_pulldown:1; + /** wrap_dm_pullup : R/W; bitpos: [15]; default: 0; + * Controlle USB D+ pullup. + */ + uint32_t wrap_dm_pullup:1; + /** wrap_dm_pulldown : R/W; bitpos: [16]; default: 0; + * Controlle USB D+ pulldown. + */ + uint32_t wrap_dm_pulldown:1; + /** wrap_pullup_value : R/W; bitpos: [17]; default: 0; + * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + */ + uint32_t wrap_pullup_value:1; + /** wrap_usb_pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t wrap_usb_pad_enable:1; + /** wrap_ahb_clk_force_on : R/W; bitpos: [19]; default: 0; + * Force ahb clock always on. + */ + uint32_t wrap_ahb_clk_force_on:1; + /** wrap_phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force phy clock always on. + */ + uint32_t wrap_phy_clk_force_on:1; + uint32_t reserved_21:10; + /** wrap_clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t wrap_clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of wrap_date register + * Date register. + */ +typedef union { + struct { + /** wrap_usb_wrap_date : R/W; bitpos: [31:0]; default: 37761536; + * Date register. + */ + uint32_t wrap_usb_wrap_date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct { + volatile usb_wrap_otg_conf_reg_t wrap_otg_conf; + uint32_t reserved_004[254]; + volatile usb_wrap_date_reg_t wrap_date; +} usb_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(usb_dev_t) == 0x400, "Invalid size of usb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif