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Merge branch 'refactor/adc_unify_adc_unit' into 'master'

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adc: adc single driver NG pre-step - unify adc_ll_num_t and adc_unit_t

See merge request espressif/esp-idf!17408
This commit is contained in:
Armando (Dou Yiwen)
2022-03-18 20:29:36 +08:00
parent 93987e6b79 109f2a7449
commit 36457b1346
40 changed files with 830 additions and 918 deletions
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87
components/driver/adc.c
View File

@@ -73,7 +73,7 @@ portMUX_TYPE adc_reg_lock = portMUX_INITIALIZER_UNLOCKED;
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
typedef struct adc_digi_context_t { typedef struct adc_digi_context_t {
uint8_t *rx_dma_buf; //dma buffer uint8_t *rx_dma_buf; //dma buffer
adc_hal_context_t hal; //hal context adc_hal_dma_ctx_t hal; //hal context
#if SOC_GDMA_SUPPORTED #if SOC_GDMA_SUPPORTED
gdma_channel_handle_t rx_dma_channel; //dma rx channel handle gdma_channel_handle_t rx_dma_channel; //dma rx channel handle
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -102,7 +102,7 @@ extern esp_pm_lock_handle_t adc_digi_arbiter_lock;
#endif //CONFIG_PM_ENABLE #endif //CONFIG_PM_ENABLE
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan, adc_atten_t atten); uint32_t adc_get_calibration_offset(adc_unit_t adc_n, adc_channel_t chan, adc_atten_t atten);
#endif #endif
/*--------------------------------------------------------------- /*---------------------------------------------------------------
@@ -117,9 +117,11 @@ static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan
static IRAM_ATTR void adc_dma_intr_handler(void *arg); static IRAM_ATTR void adc_dma_intr_handler(void *arg);
#endif #endif
static int8_t adc_digi_get_io_num(uint8_t adc_unit, uint8_t adc_channel) static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{ {
return adc_channel_io_map[adc_unit][adc_channel]; assert(adc_unit <= SOC_ADC_PERIPH_NUM);
uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
return adc_channel_io_map[adc_n][adc_channel];
} }
static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask) static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
@@ -197,13 +199,13 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
//init gpio pins //init gpio pins
if (init_config->adc1_chan_mask) { if (init_config->adc1_chan_mask) {
ret = adc_digi_gpio_init(ADC_NUM_1, init_config->adc1_chan_mask); ret = adc_digi_gpio_init(ADC_UNIT_1, init_config->adc1_chan_mask);
if (ret != ESP_OK) { if (ret != ESP_OK) {
goto cleanup; goto cleanup;
} }
} }
if (init_config->adc2_chan_mask) { if (init_config->adc2_chan_mask) {
ret = adc_digi_gpio_init(ADC_NUM_2, init_config->adc2_chan_mask); ret = adc_digi_gpio_init(ADC_UNIT_2, init_config->adc2_chan_mask);
if (ret != ESP_OK) { if (ret != ESP_OK) {
goto cleanup; goto cleanup;
} }
@@ -270,7 +272,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
} }
#endif #endif
adc_hal_config_t config = { adc_hal_dma_config_t config = {
#if SOC_GDMA_SUPPORTED #if SOC_GDMA_SUPPORTED
.dev = (void *)GDMA_LL_GET_HW(0), .dev = (void *)GDMA_LL_GET_HW(0),
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -282,7 +284,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
.dma_chan = dma_chan, .dma_chan = dma_chan,
.eof_num = init_config->conv_num_each_intr / ADC_HAL_DATA_LEN_PER_CONV .eof_num = init_config->conv_num_each_intr / ADC_HAL_DATA_LEN_PER_CONV
}; };
adc_hal_context_config(&s_adc_digi_ctx->hal, &config); adc_hal_dma_ctx_config(&s_adc_digi_ctx->hal, &config);
//enable ADC digital part //enable ADC digital part
periph_module_enable(PERIPH_SARADC_MODULE); periph_module_enable(PERIPH_SARADC_MODULE);
@@ -290,8 +292,8 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
periph_module_reset(PERIPH_SARADC_MODULE); periph_module_reset(PERIPH_SARADC_MODULE);
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_NUM_1); adc_hal_calibration_init(ADC_UNIT_1);
adc_hal_calibration_init(ADC_NUM_2); adc_hal_calibration_init(ADC_UNIT_2);
#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
return ret; return ret;
@@ -383,23 +385,22 @@ esp_err_t adc_digi_start(void)
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
if (s_adc_digi_ctx->use_adc1) { if (s_adc_digi_ctx->use_adc1) {
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc1_atten); uint32_t cal_val = adc_get_calibration_offset(ADC_UNIT_1, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc1_atten);
adc_hal_set_calibration_param(ADC_NUM_1, cal_val); adc_hal_set_calibration_param(ADC_UNIT_1, cal_val);
} }
if (s_adc_digi_ctx->use_adc2) { if (s_adc_digi_ctx->use_adc2) {
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc2_atten); uint32_t cal_val = adc_get_calibration_offset(ADC_UNIT_2, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc2_atten);
adc_hal_set_calibration_param(ADC_NUM_2, cal_val); adc_hal_set_calibration_param(ADC_UNIT_2, cal_val);
} }
#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_init();
#if SOC_ADC_ARBITER_SUPPORTED #if SOC_ADC_ARBITER_SUPPORTED
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
adc_hal_arbiter_config(&config); adc_hal_arbiter_config(&config);
#endif //#if SOC_ADC_ARBITER_SUPPORTED #endif //#if SOC_ADC_ARBITER_SUPPORTED
adc_hal_set_controller(ADC_NUM_1, ADC_HAL_CONTINUOUS_READ_MODE); adc_hal_set_controller(ADC_UNIT_1, ADC_HAL_CONTINUOUS_READ_MODE);
adc_hal_set_controller(ADC_NUM_2, ADC_HAL_CONTINUOUS_READ_MODE); adc_hal_set_controller(ADC_UNIT_2, ADC_HAL_CONTINUOUS_READ_MODE);
adc_hal_digi_init(&s_adc_digi_ctx->hal); adc_hal_digi_init(&s_adc_digi_ctx->hal);
adc_hal_digi_controller_config(&s_adc_digi_ctx->hal, &s_adc_digi_ctx->hal_digi_ctrlr_cfg); adc_hal_digi_controller_config(&s_adc_digi_ctx->hal, &s_adc_digi_ctx->hal_digi_ctrlr_cfg);
@@ -602,7 +603,7 @@ esp_err_t adc_digi_controller_configure(const adc_digi_configuration_t *config)
s_adc_digi_ctx->use_adc2 = 0; s_adc_digi_ctx->use_adc2 = 0;
for (int i = 0; i < config->pattern_num; i++) { for (int i = 0; i < config->pattern_num; i++) {
const adc_digi_pattern_config_t *pat = &config->adc_pattern[i]; const adc_digi_pattern_config_t *pat = &config->adc_pattern[i];
if (pat->unit == ADC_NUM_1) { if (pat->unit == ADC_UNIT_1) {
s_adc_digi_ctx->use_adc1 = 1; s_adc_digi_ctx->use_adc1 = 1;
if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) { if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) {
@@ -610,7 +611,7 @@ esp_err_t adc_digi_controller_configure(const adc_digi_configuration_t *config)
} else if (s_adc_digi_ctx->adc1_atten != pat->atten) { } else if (s_adc_digi_ctx->adc1_atten != pat->atten) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
} else if (pat->unit == ADC_NUM_2) { } else if (pat->unit == ADC_UNIT_2) {
//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
s_adc_digi_ctx->use_adc2 = 1; s_adc_digi_ctx->use_adc2 = 1;
@@ -639,7 +640,7 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
uint32_t channel = ADC2_CHANNEL_MAX; uint32_t channel = ADC2_CHANNEL_MAX;
if (adc_unit == ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
for (int i = 0; i < ADC2_CHANNEL_MAX; i++) { for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
if (gpio == ADC_GET_IO_NUM(ADC_NUM_2, i)) { if (gpio == ADC_GET_IO_NUM(ADC_UNIT_2, i)) {
channel = i; channel = i;
break; break;
} }
@@ -650,17 +651,17 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
} }
adc_power_acquire(); adc_power_acquire();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_hal_vref_output(ADC_NUM_1, channel, true); adc_hal_vref_output(ADC_UNIT_1, channel, true);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
} else if (adc_unit & ADC_UNIT_2) { } else { //ADC_UNIT_2
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_hal_vref_output(ADC_NUM_2, channel, true); adc_hal_vref_output(ADC_UNIT_2, channel, true);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
} }
ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel)); ret = adc_digi_gpio_init(ADC_UNIT_2, BIT(channel));
return ret; return ret;
} }
@@ -677,14 +678,14 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
{ {
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_NUM_1), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC1 channel error"); ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC1 channel error");
ESP_RETURN_ON_FALSE((atten < ADC_ATTEN_MAX), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err"); ESP_RETURN_ON_FALSE((atten < ADC_ATTEN_MAX), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err");
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
s_atten1_single[channel] = atten; s_atten1_single[channel] = atten;
ret = adc_digi_gpio_init(ADC_NUM_1, BIT(channel)); ret = adc_digi_gpio_init(ADC_UNIT_1, BIT(channel));
adc_hal_calibration_init(ADC_NUM_1); adc_hal_calibration_init(ADC_UNIT_1);
return ret; return ret;
} }
@@ -699,12 +700,12 @@ int adc1_get_raw(adc1_channel_t channel)
SAR_ADC1_LOCK_ACQUIRE(); SAR_ADC1_LOCK_ACQUIRE();
adc_atten_t atten = s_atten1_single[channel]; adc_atten_t atten = s_atten1_single[channel];
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, channel, atten); uint32_t cal_val = adc_get_calibration_offset(ADC_UNIT_1, channel, atten);
adc_hal_set_calibration_param(ADC_NUM_1, cal_val); adc_hal_set_calibration_param(ADC_UNIT_1, cal_val);
ADC_REG_LOCK_ENTER(); ADC_REG_LOCK_ENTER();
adc_hal_set_atten(ADC_NUM_2, channel, atten); adc_hal_set_atten(ADC_UNIT_2, channel, atten);
adc_hal_convert(ADC_NUM_1, channel, &raw_out); adc_hal_convert(ADC_UNIT_1, channel, &raw_out);
ADC_REG_LOCK_EXIT(); ADC_REG_LOCK_EXIT();
SAR_ADC1_LOCK_RELEASE(); SAR_ADC1_LOCK_RELEASE();
@@ -717,14 +718,14 @@ int adc1_get_raw(adc1_channel_t channel)
esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
{ {
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_NUM_2), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 channel error"); ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 channel error");
ESP_RETURN_ON_FALSE((atten <= ADC_ATTEN_11db), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err"); ESP_RETURN_ON_FALSE((atten <= ADC_ATTEN_11db), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err");
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
s_atten2_single[channel] = atten; s_atten2_single[channel] = atten;
ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel)); ret = adc_digi_gpio_init(ADC_UNIT_2, BIT(channel));
adc_hal_calibration_init(ADC_NUM_2); adc_hal_calibration_init(ADC_UNIT_2);
return ret; return ret;
} }
@@ -747,12 +748,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
adc_hal_arbiter_config(&config); adc_hal_arbiter_config(&config);
adc_atten_t atten = s_atten2_single[channel]; adc_atten_t atten = s_atten2_single[channel];
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten); uint32_t cal_val = adc_get_calibration_offset(ADC_UNIT_2, channel, atten);
adc_hal_set_calibration_param(ADC_NUM_2, cal_val); adc_hal_set_calibration_param(ADC_UNIT_2, cal_val);
ADC_REG_LOCK_ENTER(); ADC_REG_LOCK_ENTER();
adc_hal_set_atten(ADC_NUM_2, channel, atten); adc_hal_set_atten(ADC_UNIT_2, channel, atten);
ret = adc_hal_convert(ADC_NUM_2, channel, raw_out); ret = adc_hal_convert(ADC_UNIT_2, channel, raw_out);
ADC_REG_LOCK_EXIT(); ADC_REG_LOCK_EXIT();
SAR_ADC2_LOCK_RELEASE(); SAR_ADC2_LOCK_RELEASE();
@@ -842,7 +843,7 @@ static uint16_t s_adc_cali_param[SOC_ADC_PERIPH_NUM][ADC_ATTEN_MAX] = {};
// 1. Semaphore when reading efuse // 1. Semaphore when reading efuse
// 2. Lock (Spinlock, or Mutex) if we actually do ADC calibration in the future // 2. Lock (Spinlock, or Mutex) if we actually do ADC calibration in the future
//This function shoudn't be called inside critical section or ISR //This function shoudn't be called inside critical section or ISR
uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) uint32_t adc_get_calibration_offset(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{ {
if (s_adc_cali_param[adc_n][atten]) { if (s_adc_cali_param[adc_n][atten]) {
ESP_LOGV(ADC_TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n, atten, s_adc_cali_param[adc_n][atten]); ESP_LOGV(ADC_TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n, atten, s_adc_cali_param[adc_n][atten]);
@@ -874,7 +875,7 @@ uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, a
} }
// Internal function to calibrate PWDET for WiFi // Internal function to calibrate PWDET for WiFi
esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) esp_err_t adc_cal_offset(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{ {
adc_hal_calibration_init(adc_n); adc_hal_calibration_init(adc_n);
uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten); uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten);
@@ -918,7 +919,7 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
s_adc_digi_ctx->use_adc2 = 0; s_adc_digi_ctx->use_adc2 = 0;
for (int i = 0; i < config->adc_pattern_len; i++) { for (int i = 0; i < config->adc_pattern_len; i++) {
const adc_digi_pattern_config_t *pat = &s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i]; const adc_digi_pattern_config_t *pat = &s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i];
if (pat->unit == ADC_NUM_1) { if (pat->unit == ADC_UNIT_1) {
s_adc_digi_ctx->use_adc1 = 1; s_adc_digi_ctx->use_adc1 = 1;
if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) { if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) {
@@ -926,7 +927,7 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
} else if (s_adc_digi_ctx->adc1_atten != pat->atten) { } else if (s_adc_digi_ctx->adc1_atten != pat->atten) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
} else if (pat->unit == ADC_NUM_2) { } else if (pat->unit == ADC_UNIT_2) {
//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
s_adc_digi_ctx->use_adc2 = 1; s_adc_digi_ctx->use_adc2 = 1;

108
components/driver/adc_common.c
View File

@@ -195,9 +195,9 @@ void adc_power_off(void)
esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num) esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
{ {
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
int io = ADC_GET_IO_NUM(ADC_NUM_1, channel); int io = ADC_GET_IO_NUM(ADC_UNIT_1, channel);
if (io < 0) { if (io < 0) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} else { } else {
@@ -209,9 +209,9 @@ esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num) esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
{ {
ADC_CHANNEL_CHECK(ADC_NUM_2, channel); ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
int io = ADC_GET_IO_NUM(ADC_NUM_2, channel); int io = ADC_GET_IO_NUM(ADC_UNIT_2, channel);
if (io < 0) { if (io < 0) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} else { } else {
@@ -225,10 +225,10 @@ esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
#if SOC_ADC_RTC_CTRL_SUPPORTED #if SOC_ADC_RTC_CTRL_SUPPORTED
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
static uint32_t get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan) static uint32_t get_calibration_offset(adc_unit_t adc_n, adc_channel_t chan)
{ {
adc_atten_t atten = adc_ll_get_atten(adc_n, chan); adc_atten_t atten = adc_ll_get_atten(adc_n, chan);
extern uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten); extern uint32_t adc_get_calibration_offset(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten);
return adc_get_calibration_offset(adc_n, chan, atten); return adc_get_calibration_offset(adc_n, chan, atten);
} }
@@ -244,23 +244,23 @@ esp_err_t adc_set_clk_div(uint8_t clk_div)
static void adc_rtc_chan_init(adc_unit_t adc_unit) static void adc_rtc_chan_init(adc_unit_t adc_unit)
{ {
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
/* Workaround: Disable the synchronization operation function of ADC1 and DAC. /* Workaround: Disable the synchronization operation function of ADC1 and DAC.
If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */ If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */
#if SOC_DAC_SUPPORTED #if SOC_DAC_SUPPORTED
dac_hal_rtc_sync_by_adc(false); dac_hal_rtc_sync_by_adc(false);
#endif #endif
adc_hal_rtc_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT); adc_hal_rtc_output_invert(ADC_UNIT_1, ADC_HAL_DATA_INVERT_DEFAULT(ADC_UNIT_1));
adc_ll_set_sar_clk_div(ADC_NUM_1, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_1)); adc_ll_set_sar_clk_div(ADC_UNIT_1, ADC_HAL_SAR_CLK_DIV_DEFAULT(ADC_UNIT_1));
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
adc_ll_hall_disable(); //Disable other peripherals. adc_ll_hall_disable(); //Disable other peripherals.
adc_ll_amp_disable(); //Currently the LNA is not open, close it by default. adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
#endif #endif
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT); adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
adc_hal_rtc_output_invert(ADC_NUM_2, SOC_ADC2_DATA_INVERT_DEFAULT); adc_hal_rtc_output_invert(ADC_UNIT_2, ADC_HAL_DATA_INVERT_DEFAULT(ADC_UNIT_2));
adc_ll_set_sar_clk_div(ADC_NUM_2, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_2)); adc_ll_set_sar_clk_div(ADC_UNIT_2, ADC_HAL_SAR_CLK_DIV_DEFAULT(ADC_UNIT_2));
} }
} }
@@ -273,17 +273,17 @@ esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
//If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run //If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
gpio_num = ADC_GET_IO_NUM(ADC_NUM_1, channel); gpio_num = ADC_GET_IO_NUM(ADC_UNIT_1, channel);
ADC_CHECK_RET(rtc_gpio_init(gpio_num)); ADC_CHECK_RET(rtc_gpio_init(gpio_num));
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
ADC_CHANNEL_CHECK(ADC_NUM_2, channel); ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
gpio_num = ADC_GET_IO_NUM(ADC_NUM_2, channel); gpio_num = ADC_GET_IO_NUM(ADC_UNIT_2, channel);
ADC_CHECK_RET(rtc_gpio_init(gpio_num)); ADC_CHECK_RET(rtc_gpio_init(gpio_num));
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
@@ -295,14 +295,14 @@ esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en) esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
{ {
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
SARADC1_ENTER(); SARADC1_ENTER();
adc_hal_rtc_output_invert(ADC_NUM_1, inv_en); adc_hal_rtc_output_invert(ADC_UNIT_1, inv_en);
SARADC1_EXIT(); SARADC1_EXIT();
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
SARADC2_ENTER(); SARADC2_ENTER();
adc_hal_rtc_output_invert(ADC_NUM_2, inv_en); adc_hal_rtc_output_invert(ADC_UNIT_2, inv_en);
SARADC2_EXIT(); SARADC2_EXIT();
} }
@@ -317,14 +317,14 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG); ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
#endif #endif
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
SARADC1_ENTER(); SARADC1_ENTER();
adc_hal_rtc_set_output_format(ADC_NUM_1, width_bit); adc_hal_rtc_set_output_format(ADC_UNIT_1, width_bit);
SARADC1_EXIT(); SARADC1_EXIT();
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
SARADC2_ENTER(); SARADC2_ENTER();
adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit); adc_hal_rtc_set_output_format(ADC_UNIT_2, width_bit);
SARADC2_EXIT(); SARADC2_EXIT();
} }
@@ -352,17 +352,17 @@ esp_err_t adc_rtc_reset(void)
*------------------------------------------------------------------------------------*/ *------------------------------------------------------------------------------------*/
esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
{ {
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG); ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG);
adc_common_gpio_init(ADC_UNIT_1, channel); adc_common_gpio_init(ADC_UNIT_1, channel);
SARADC1_ENTER(); SARADC1_ENTER();
adc_rtc_chan_init(ADC_UNIT_1); adc_rtc_chan_init(ADC_UNIT_1);
adc_hal_set_atten(ADC_NUM_1, channel, atten); adc_hal_set_atten(ADC_UNIT_1, channel, atten);
SARADC1_EXIT(); SARADC1_EXIT();
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_NUM_1); adc_hal_calibration_init(ADC_UNIT_1);
#endif #endif
return ESP_OK; return ESP_OK;
@@ -377,7 +377,7 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
#endif #endif
SARADC1_ENTER(); SARADC1_ENTER();
adc_hal_rtc_set_output_format(ADC_NUM_1, width_bit); adc_hal_rtc_set_output_format(ADC_UNIT_1, width_bit);
SARADC1_EXIT(); SARADC1_EXIT();
return ESP_OK; return ESP_OK;
@@ -394,7 +394,7 @@ esp_err_t adc1_dma_mode_acquire(void)
SARADC1_ENTER(); SARADC1_ENTER();
/* switch SARADC into DIG channel */ /* switch SARADC into DIG channel */
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_DIG); adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
SARADC1_EXIT(); SARADC1_EXIT();
return ESP_OK; return ESP_OK;
@@ -409,7 +409,7 @@ esp_err_t adc1_rtc_mode_acquire(void)
SARADC1_ENTER(); SARADC1_ENTER();
/* switch SARADC into RTC channel. */ /* switch SARADC into RTC channel. */
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC); adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC);
SARADC1_EXIT(); SARADC1_EXIT();
return ESP_OK; return ESP_OK;
@@ -428,13 +428,13 @@ esp_err_t adc1_lock_release(void)
int adc1_get_raw(adc1_channel_t channel) int adc1_get_raw(adc1_channel_t channel)
{ {
int adc_value; int adc_value;
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
adc1_rtc_mode_acquire(); adc1_rtc_mode_acquire();
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
// Get calibration value before going into critical section // Get calibration value before going into critical section
uint32_t cal_val = get_calibration_offset(ADC_NUM_1, channel); uint32_t cal_val = get_calibration_offset(ADC_UNIT_1, channel);
adc_hal_set_calibration_param(ADC_NUM_1, cal_val); adc_hal_set_calibration_param(ADC_UNIT_1, cal_val);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
SARADC1_ENTER(); SARADC1_ENTER();
@@ -442,8 +442,8 @@ int adc1_get_raw(adc1_channel_t channel)
adc_ll_hall_disable(); //Disable other peripherals. adc_ll_hall_disable(); //Disable other peripherals.
adc_ll_amp_disable(); //Currently the LNA is not open, close it by default. adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
#endif #endif
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC); //Set controller adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC); //Set controller
adc_hal_convert(ADC_NUM_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid. adc_hal_convert(ADC_UNIT_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid.
#if !CONFIG_IDF_TARGET_ESP32 #if !CONFIG_IDF_TARGET_ESP32
adc_ll_rtc_reset(); //Reset FSM of rtc controller adc_ll_rtc_reset(); //Reset FSM of rtc controller
#endif #endif
@@ -464,7 +464,7 @@ void adc1_ulp_enable(void)
adc_power_acquire(); adc_power_acquire();
SARADC1_ENTER(); SARADC1_ENTER();
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_ULP); adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
/* since most users do not need LNA and HALL with uLP, we disable them here /* since most users do not need LNA and HALL with uLP, we disable them here
open them in the uLP if needed. */ open them in the uLP if needed. */
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
@@ -499,7 +499,7 @@ esp_err_t adc2_wifi_release(void)
esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
{ {
ADC_CHANNEL_CHECK(ADC_NUM_2, channel); ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG); ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG);
adc_common_gpio_init(ADC_UNIT_2, channel); adc_common_gpio_init(ADC_UNIT_2, channel);
@@ -512,13 +512,13 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
//avoid collision with other tasks //avoid collision with other tasks
SARADC2_ENTER(); SARADC2_ENTER();
adc_rtc_chan_init(ADC_UNIT_2); adc_rtc_chan_init(ADC_UNIT_2);
adc_hal_set_atten(ADC_NUM_2, channel, atten); adc_hal_set_atten(ADC_UNIT_2, channel, atten);
SARADC2_EXIT(); SARADC2_EXIT();
SARADC2_RELEASE(); SARADC2_RELEASE();
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
adc_hal_calibration_init(ADC_NUM_2); adc_hal_calibration_init(ADC_UNIT_2);
#endif #endif
return ESP_OK; return ESP_OK;
@@ -576,8 +576,8 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
// Get calibration value before going into critical section // Get calibration value before going into critical section
uint32_t cal_val = get_calibration_offset(ADC_NUM_2, channel); uint32_t cal_val = get_calibration_offset(ADC_UNIT_2, channel);
adc_hal_set_calibration_param(ADC_NUM_2, cal_val); adc_hal_set_calibration_param(ADC_UNIT_2, cal_val);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
if ( SARADC2_TRY_ACQUIRE() == -1 ) { if ( SARADC2_TRY_ACQUIRE() == -1 ) {
@@ -598,12 +598,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#ifdef CONFIG_ADC_DISABLE_DAC #ifdef CONFIG_ADC_DISABLE_DAC
adc2_dac_disable(channel); //disable other peripherals adc2_dac_disable(channel); //disable other peripherals
#endif #endif
adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit); adc_hal_rtc_set_output_format(ADC_UNIT_2, width_bit);
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_RTC);// set controller adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_RTC);// set controller
#else #else
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_ARB);// set controller adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_ARB);// set controller
#endif #endif
#if CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32S2
@@ -614,7 +614,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif //CONFIG_PM_ENABLE #endif //CONFIG_PM_ENABLE
#endif //CONFIG_IDF_TARGET_ESP32 #endif //CONFIG_IDF_TARGET_ESP32
ret = adc_hal_convert(ADC_NUM_2, channel, &adc_value); ret = adc_hal_convert(ADC_UNIT_2, channel, &adc_value);
if (ret != ESP_OK) { if (ret != ESP_OK) {
adc_value = -1; adc_value = -1;
} }
@@ -644,14 +644,14 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio) esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
{ {
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
} }
#endif #endif
adc2_channel_t ch = ADC2_CHANNEL_MAX; adc2_channel_t ch = ADC2_CHANNEL_MAX;
/* Check if the GPIO supported. */ /* Check if the GPIO supported. */
for (int i = 0; i < ADC2_CHANNEL_MAX; i++) { for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
if (gpio == ADC_GET_IO_NUM(ADC_NUM_2, i)) { if (gpio == ADC_GET_IO_NUM(ADC_UNIT_2, i)) {
ch = i; ch = i;
break; break;
} }
@@ -661,13 +661,13 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
} }
adc_power_acquire(); adc_power_acquire();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
VREF_ENTER(1); VREF_ENTER(1);
adc_hal_vref_output(ADC_NUM_1, ch, true); adc_hal_vref_output(ADC_UNIT_1, ch, true);
VREF_EXIT(1); VREF_EXIT(1);
} else if (adc_unit & ADC_UNIT_2) { } else if (adc_unit == ADC_UNIT_2) {
VREF_ENTER(2); VREF_ENTER(2);
adc_hal_vref_output(ADC_NUM_2, ch, true); adc_hal_vref_output(ADC_UNIT_2, ch, true);
VREF_EXIT(2); VREF_EXIT(2);
} }

176
components/driver/adc_deprecated.c
View File

@@ -15,6 +15,7 @@
#include "driver/rtc_io.h" #include "driver/rtc_io.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
#include "hal/adc_types.h" #include "hal/adc_types.h"
#include "hal/adc_hal_conf.h"
#ifdef CONFIG_PM_ENABLE #ifdef CONFIG_PM_ENABLE
#include "esp_pm.h" #include "esp_pm.h"
#endif #endif
@@ -66,7 +67,13 @@ esp_pm_lock_handle_t adc_digi_arbiter_lock = NULL;
esp_err_t adc_digi_init(void) esp_err_t adc_digi_init(void)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_hal_init(); adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
} }
@@ -92,17 +99,17 @@ static inline void adc_ll_digi_set_output_format(bool data_sel)
SYSCON.saradc_ctrl.data_sar_sel = data_sel; SYSCON.saradc_ctrl.data_sar_sel = data_sel;
} }
static inline void adc_ll_digi_prepare_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern) static inline void adc_ll_digi_prepare_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
uint8_t offset = (pattern_index % 4) * 8; uint8_t offset = (pattern_index % 4) * 8;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -131,22 +138,22 @@ void adc_digi_controller_reg_set(const adc_digi_config_t *cfg)
} }
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_DIG); adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
if (cfg->adc1_pattern_len) { if (cfg->adc1_pattern_len) {
adc_ll_digi_clear_pattern_table(ADC_NUM_1); adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
adc_ll_digi_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len); adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, cfg->adc1_pattern_len);
for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) { for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
adc_ll_digi_prepare_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]); adc_ll_digi_prepare_pattern_table(ADC_UNIT_1, i, cfg->adc1_pattern[i]);
} }
} }
} }
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_DIG); adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_DIG);
if (cfg->adc2_pattern_len) { if (cfg->adc2_pattern_len) {
adc_ll_digi_clear_pattern_table(ADC_NUM_2); adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
adc_ll_digi_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len); adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, cfg->adc2_pattern_len);
for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) { for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
adc_ll_digi_prepare_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]); adc_ll_digi_prepare_pattern_table(ADC_UNIT_2, i, cfg->adc2_pattern[i]);
} }
} }
} }
@@ -181,13 +188,13 @@ esp_err_t adc_set_i2s_data_source(adc_i2s_source_t src)
extern esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel); extern esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel) esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
{ {
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
ADC_CHECK((SOC_ADC_SUPPORT_DMA_MODE(ADC_NUM_1)), "ADC1 not support DMA for now.", ESP_ERR_INVALID_ARG); ADC_CHECK((SOC_ADC_SUPPORT_DMA_MODE(ADC_UNIT_1)), "ADC1 not support DMA for now.", ESP_ERR_INVALID_ARG);
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) { //ADC2 does not support DMA mode
ADC_CHECK((SOC_ADC_SUPPORT_DMA_MODE(ADC_NUM_2)), "ADC2 not support DMA for now.", ESP_ERR_INVALID_ARG); ADC_CHECK((SOC_ADC_SUPPORT_DMA_MODE(ADC_UNIT_2)), "ADC2 not support DMA for now.", ESP_ERR_INVALID_ARG);
ADC_CHANNEL_CHECK(ADC_NUM_2, channel); ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
} }
adc_digi_pattern_table_t adc1_pattern[1]; adc_digi_pattern_table_t adc1_pattern[1];
@@ -196,17 +203,16 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
.conv_limit_en = ADC_MEAS_NUM_LIM_DEFAULT, .conv_limit_en = ADC_MEAS_NUM_LIM_DEFAULT,
.conv_limit_num = ADC_MAX_MEAS_NUM_DEFAULT, .conv_limit_num = ADC_MAX_MEAS_NUM_DEFAULT,
.format = DIG_ADC_OUTPUT_FORMAT_DEFUALT, .format = DIG_ADC_OUTPUT_FORMAT_DEFUALT,
.conv_mode = (adc_digi_convert_mode_t)adc_unit, .conv_mode = ADC_CONV_SINGLE_UNIT_1,
}; };
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
adc1_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT; adc1_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT;
adc1_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT; adc1_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT;
adc1_pattern[0].channel = channel; adc1_pattern[0].channel = channel;
dig_cfg.adc1_pattern_len = 1; dig_cfg.adc1_pattern_len = 1;
dig_cfg.adc1_pattern = adc1_pattern; dig_cfg.adc1_pattern = adc1_pattern;
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) {
adc2_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT; adc2_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT;
adc2_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT; adc2_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT;
adc2_pattern[0].channel = channel; adc2_pattern[0].channel = channel;
@@ -215,7 +221,13 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
} }
adc_common_gpio_init(adc_unit, channel); adc_common_gpio_init(adc_unit, channel);
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_hal_init(); adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
adc_digi_controller_reg_set(&dig_cfg); adc_digi_controller_reg_set(&dig_cfg);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
@@ -230,7 +242,7 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config) esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config)
{ {
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
return ESP_ERR_NOT_SUPPORTED; return ESP_ERR_NOT_SUPPORTED;
} }
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
@@ -245,16 +257,16 @@ esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param intr Interrupt bitmask. * @param intr Interrupt bitmask.
*/ */
static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr) static inline void adc_ll_digi_intr_enable(adc_unit_t adc_n, adc_digi_intr_t intr)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_ena.adc1_thres = 1; APB_SARADC.int_ena.adc1_thres = 1;
} }
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 1; APB_SARADC.int_ena.adc1_done = 1;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_ena.adc2_thres = 1; APB_SARADC.int_ena.adc2_thres = 1;
} }
@@ -267,11 +279,10 @@ static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t i
esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
adc_ll_digi_intr_enable(ADC_NUM_1, intr_mask); adc_ll_digi_intr_enable(ADC_UNIT_1, intr_mask);
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) { adc_ll_digi_intr_enable(ADC_UNIT_2, intr_mask);
adc_ll_digi_intr_enable(ADC_NUM_2, intr_mask);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -283,16 +294,16 @@ esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param intr Interrupt bitmask. * @param intr Interrupt bitmask.
*/ */
static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr) static inline void adc_ll_digi_intr_disable(adc_unit_t adc_n, adc_digi_intr_t intr)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_ena.adc1_thres = 0; APB_SARADC.int_ena.adc1_thres = 0;
} }
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 0; APB_SARADC.int_ena.adc1_done = 0;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_ena.adc2_thres = 0; APB_SARADC.int_ena.adc2_thres = 0;
} }
@@ -305,11 +316,10 @@ static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t
esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
adc_ll_digi_intr_disable(ADC_NUM_1, intr_mask); adc_ll_digi_intr_disable(ADC_UNIT_1, intr_mask);
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) { adc_ll_digi_intr_disable(ADC_UNIT_2, intr_mask);
adc_ll_digi_intr_disable(ADC_NUM_2, intr_mask);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -321,16 +331,16 @@ esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param intr Interrupt bitmask. * @param intr Interrupt bitmask.
*/ */
static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr) static inline void adc_ll_digi_intr_clear(adc_unit_t adc_n, adc_digi_intr_t intr)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_clr.adc1_thres = 1; APB_SARADC.int_clr.adc1_thres = 1;
} }
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_clr.adc1_done = 1; APB_SARADC.int_clr.adc1_done = 1;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
if (intr & ADC_DIGI_INTR_MASK_MONITOR) { if (intr & ADC_DIGI_INTR_MASK_MONITOR) {
APB_SARADC.int_clr.adc2_thres = 1; APB_SARADC.int_clr.adc2_thres = 1;
} }
@@ -343,11 +353,10 @@ static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t in
esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
adc_ll_digi_intr_clear(ADC_NUM_1, intr_mask); adc_ll_digi_intr_clear(ADC_UNIT_1, intr_mask);
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) { adc_ll_digi_intr_clear(ADC_UNIT_2, intr_mask);
adc_ll_digi_intr_clear(ADC_NUM_2, intr_mask);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
@@ -361,19 +370,19 @@ esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
* @return * @return
* - intr Interrupt bitmask. * - intr Interrupt bitmask.
*/ */
static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n) static inline uint32_t adc_ll_digi_get_intr_status(adc_unit_t adc_n)
{ {
uint32_t int_st = APB_SARADC.int_st.val; uint32_t int_st = APB_SARADC.int_st.val;
uint32_t ret_msk = 0; uint32_t ret_msk = 0;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) { if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
} }
if (int_st & APB_SARADC_ADC1_THRES_INT_ST) { if (int_st & APB_SARADC_ADC1_THRES_INT_ST) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR; ret_msk |= ADC_DIGI_INTR_MASK_MONITOR;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) { if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
} }
@@ -389,11 +398,10 @@ uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit)
{ {
uint32_t ret = 0; uint32_t ret = 0;
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
ret = adc_ll_digi_get_intr_status(ADC_NUM_1); ret = adc_ll_digi_get_intr_status(ADC_UNIT_1);
} } else if (adc_unit == ADC_UNIT_2) {
if (adc_unit & ADC_UNIT_2) { ret = adc_ll_digi_get_intr_status(ADC_UNIT_2);
ret = adc_ll_digi_get_intr_status(ADC_NUM_2);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ret; return ret;
@@ -430,12 +438,18 @@ esp_err_t adc_digi_init(void)
{ {
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_hal_init(); adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
adc_hal_arbiter_config(&config); adc_hal_arbiter_config(&config);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
adc_hal_calibration_init(ADC_NUM_1); adc_hal_calibration_init(ADC_UNIT_1);
adc_hal_calibration_init(ADC_NUM_2); adc_hal_calibration_init(ADC_UNIT_2);
return ESP_OK; return ESP_OK;
} }
@@ -465,8 +479,8 @@ esp_err_t adc_digi_reset(void)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
adc_ll_digi_reset(); adc_ll_digi_reset();
adc_ll_digi_clear_pattern_table(ADC_NUM_1); adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
adc_ll_digi_clear_pattern_table(ADC_NUM_2); adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
} }
@@ -481,17 +495,17 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format
APB_SARADC.ctrl.data_sar_sel = format; APB_SARADC.ctrl.data_sar_sel = format;
} }
static inline void adc_ll_digi_prepare_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern) static inline void adc_ll_digi_prepare_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
uint8_t offset = (pattern_index % 4) * 8; uint8_t offset = (pattern_index % 4) * 8;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
tab = APB_SARADC.sar1_patt_tab[index]; // Read old register value tab = APB_SARADC.sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
APB_SARADC.sar1_patt_tab[index] = tab; // Write back APB_SARADC.sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
tab = APB_SARADC.sar2_patt_tab[index]; // Read old register value tab = APB_SARADC.sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -521,27 +535,27 @@ static void adc_digi_controller_reg_set(const adc_digi_config_t *cfg)
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
if (cfg->adc1_pattern_len) { if (cfg->adc1_pattern_len) {
adc_ll_digi_clear_pattern_table(ADC_NUM_1); adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
adc_ll_digi_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len); adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, cfg->adc1_pattern_len);
for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) { for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
adc_ll_digi_prepare_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]); adc_ll_digi_prepare_pattern_table(ADC_UNIT_1, i, cfg->adc1_pattern[i]);
} }
} }
} }
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
if (cfg->adc2_pattern_len) { if (cfg->adc2_pattern_len) {
adc_ll_digi_clear_pattern_table(ADC_NUM_2); adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
adc_ll_digi_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len); adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, cfg->adc2_pattern_len);
for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) { for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
adc_ll_digi_prepare_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]); adc_ll_digi_prepare_pattern_table(ADC_UNIT_2, i, cfg->adc2_pattern[i]);
} }
} }
} }
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_DIG); adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
} }
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) { if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_ARB); adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_ARB);
} }
adc_ll_digi_set_output_format(cfg->format); adc_ll_digi_set_output_format(cfg->format);
if (cfg->conv_limit_en) { if (cfg->conv_limit_en) {
@@ -577,12 +591,12 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
if (config->conv_mode & ADC_CONV_SINGLE_UNIT_1) { if (config->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
for (int i = 0; i < config->adc1_pattern_len; i++) { for (int i = 0; i < config->adc1_pattern_len; i++) {
adc_cal_offset(ADC_NUM_1, config->adc1_pattern[i].channel, config->adc1_pattern[i].atten); adc_cal_offset(ADC_UNIT_1, config->adc1_pattern[i].channel, config->adc1_pattern[i].atten);
} }
} }
if (config->conv_mode & ADC_CONV_SINGLE_UNIT_2) { if (config->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
for (int i = 0; i < config->adc2_pattern_len; i++) { for (int i = 0; i < config->adc2_pattern_len; i++) {
adc_cal_offset(ADC_NUM_2, config->adc2_pattern[i].channel, config->adc2_pattern[i].atten); adc_cal_offset(ADC_UNIT_2, config->adc2_pattern[i].channel, config->adc2_pattern[i].atten);
} }
} }
@@ -604,17 +618,17 @@ esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
//If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run //If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
ADC_CHANNEL_CHECK(ADC_NUM_1, channel); ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
gpio_num = ADC_GET_IO_NUM(ADC_NUM_1, channel); gpio_num = ADC_GET_IO_NUM(ADC_UNIT_1, channel);
ADC_CHECK_RET(rtc_gpio_init(gpio_num)); ADC_CHECK_RET(rtc_gpio_init(gpio_num));
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
ADC_CHANNEL_CHECK(ADC_NUM_2, channel); ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
gpio_num = ADC_GET_IO_NUM(ADC_NUM_2, channel); gpio_num = ADC_GET_IO_NUM(ADC_UNIT_2, channel);
ADC_CHECK_RET(rtc_gpio_init(gpio_num)); ADC_CHECK_RET(rtc_gpio_init(gpio_num));
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));

2
components/driver/esp32/adc.c
View File

@@ -54,7 +54,7 @@ static int hall_sensor_get_value(void) //hall sensor without LNA
adc_ll_amp_disable(); adc_ll_amp_disable();
adc_ll_hall_enable(); adc_ll_hall_enable();
// set controller // set controller
adc_ll_set_controller( ADC_NUM_1, ADC_LL_CTRL_RTC ); adc_ll_set_controller( ADC_UNIT_1, ADC_LL_CTRL_RTC );
hall_value = adc_hal_hall_convert(); hall_value = adc_hal_hall_convert();
adc_ll_hall_disable(); adc_ll_hall_disable();
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();

2
components/driver/esp32c3/adc2_init_cal.c
View File

@@ -18,7 +18,7 @@ Don't put any other code into this file. */
*/ */
static __attribute__((constructor)) void adc2_init_code_calibration(void) static __attribute__((constructor)) void adc2_init_code_calibration(void)
{ {
const adc_ll_num_t adc_n = ADC_NUM_2; const adc_unit_t adc_n = ADC_UNIT_2;
const adc_atten_t atten = ADC_ATTEN_DB_11; const adc_atten_t atten = ADC_ATTEN_DB_11;
const adc_channel_t channel = 0; const adc_channel_t channel = 0;
adc_cal_offset(adc_n, channel, atten); adc_cal_offset(adc_n, channel, atten);

30
components/driver/esp32s2/adc.c
View File

@@ -25,7 +25,7 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param config Refer to ``adc_digi_monitor_t``. * @param config Refer to ``adc_digi_monitor_t``.
*/ */
static void adc_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config) static void adc_digi_monitor_config(adc_unit_t adc_n, adc_digi_monitor_t *config)
{ {
adc_ll_digi_monitor_set_mode(adc_n, config->mode); adc_ll_digi_monitor_set_mode(adc_n, config->mode);
adc_ll_digi_monitor_set_thres(adc_n, config->threshold); adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
@@ -39,9 +39,9 @@ esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (idx == ADC_DIGI_FILTER_IDX0) { if (idx == ADC_DIGI_FILTER_IDX0) {
adc_ll_digi_filter_reset(ADC_NUM_1); adc_ll_digi_filter_reset(ADC_UNIT_1);
} else if (idx == ADC_DIGI_FILTER_IDX1) { } else if (idx == ADC_DIGI_FILTER_IDX1) {
adc_ll_digi_filter_reset(ADC_NUM_2); adc_ll_digi_filter_reset(ADC_UNIT_2);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -51,9 +51,9 @@ esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (idx == ADC_DIGI_FILTER_IDX0) { if (idx == ADC_DIGI_FILTER_IDX0) {
adc_ll_digi_filter_set_factor(ADC_NUM_1, config->mode); adc_ll_digi_filter_set_factor(ADC_UNIT_1, config->mode);
} else if (idx == ADC_DIGI_FILTER_IDX1) { } else if (idx == ADC_DIGI_FILTER_IDX1) {
adc_ll_digi_filter_set_factor(ADC_NUM_2, config->mode); adc_ll_digi_filter_set_factor(ADC_UNIT_2, config->mode);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -65,11 +65,11 @@ esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_
if (idx == ADC_DIGI_FILTER_IDX0) { if (idx == ADC_DIGI_FILTER_IDX0) {
config->adc_unit = ADC_UNIT_1; config->adc_unit = ADC_UNIT_1;
config->channel = ADC_CHANNEL_MAX; config->channel = ADC_CHANNEL_MAX;
adc_ll_digi_filter_get_factor(ADC_NUM_1, &config->mode); adc_ll_digi_filter_get_factor(ADC_UNIT_1, &config->mode);
} else if (idx == ADC_DIGI_FILTER_IDX1) { } else if (idx == ADC_DIGI_FILTER_IDX1) {
config->adc_unit = ADC_UNIT_2; config->adc_unit = ADC_UNIT_2;
config->channel = ADC_CHANNEL_MAX; config->channel = ADC_CHANNEL_MAX;
adc_ll_digi_filter_get_factor(ADC_NUM_2, &config->mode); adc_ll_digi_filter_get_factor(ADC_UNIT_2, &config->mode);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -79,9 +79,9 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (idx == ADC_DIGI_FILTER_IDX0) { if (idx == ADC_DIGI_FILTER_IDX0) {
adc_ll_digi_filter_enable(ADC_NUM_1, enable); adc_ll_digi_filter_enable(ADC_UNIT_1, enable);
} else if (idx == ADC_DIGI_FILTER_IDX1) { } else if (idx == ADC_DIGI_FILTER_IDX1) {
adc_ll_digi_filter_enable(ADC_NUM_2, enable); adc_ll_digi_filter_enable(ADC_UNIT_2, enable);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -98,9 +98,9 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
int adc_digi_filter_read_data(adc_digi_filter_idx_t idx) int adc_digi_filter_read_data(adc_digi_filter_idx_t idx)
{ {
if (idx == ADC_DIGI_FILTER_IDX0) { if (idx == ADC_DIGI_FILTER_IDX0) {
return adc_ll_digi_filter_read_data(ADC_NUM_1); return adc_ll_digi_filter_read_data(ADC_UNIT_1);
} else if (idx == ADC_DIGI_FILTER_IDX1) { } else if (idx == ADC_DIGI_FILTER_IDX1) {
return adc_ll_digi_filter_read_data(ADC_NUM_2); return adc_ll_digi_filter_read_data(ADC_UNIT_2);
} else { } else {
return -1; return -1;
} }
@@ -114,9 +114,9 @@ esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monit
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (idx == ADC_DIGI_MONITOR_IDX0) { if (idx == ADC_DIGI_MONITOR_IDX0) {
adc_digi_monitor_config(ADC_NUM_1, config); adc_digi_monitor_config(ADC_UNIT_1, config);
} else if (idx == ADC_DIGI_MONITOR_IDX1) { } else if (idx == ADC_DIGI_MONITOR_IDX1) {
adc_digi_monitor_config(ADC_NUM_2, config); adc_digi_monitor_config(ADC_UNIT_2, config);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;
@@ -126,9 +126,9 @@ esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable)
{ {
ADC_ENTER_CRITICAL(); ADC_ENTER_CRITICAL();
if (idx == ADC_DIGI_MONITOR_IDX0) { if (idx == ADC_DIGI_MONITOR_IDX0) {
adc_ll_digi_monitor_enable(ADC_NUM_1, enable); adc_ll_digi_monitor_enable(ADC_UNIT_1, enable);
} else if (idx == ADC_DIGI_MONITOR_IDX1) { } else if (idx == ADC_DIGI_MONITOR_IDX1) {
adc_ll_digi_monitor_enable(ADC_NUM_2, enable); adc_ll_digi_monitor_enable(ADC_UNIT_2, enable);
} }
ADC_EXIT_CRITICAL(); ADC_EXIT_CRITICAL();
return ESP_OK; return ESP_OK;

2
components/driver/esp32s2/adc2_init_cal.c
View File

@@ -18,7 +18,7 @@ Don't put any other code into this file. */
*/ */
static __attribute__((constructor)) void adc2_init_code_calibration(void) static __attribute__((constructor)) void adc2_init_code_calibration(void)
{ {
const adc_ll_num_t adc_n = ADC_NUM_2; const adc_unit_t adc_n = ADC_UNIT_2;
const adc_atten_t atten = ADC_ATTEN_DB_11; const adc_atten_t atten = ADC_ATTEN_DB_11;
const adc_channel_t channel = 0; const adc_channel_t channel = 0;
adc_cal_offset(adc_n, channel, atten); adc_cal_offset(adc_n, channel, atten);

2
components/driver/include/esp_private/adc_cali.h
View File

@@ -24,7 +24,7 @@ extern "C" {
* @param atten Attenuation to use * @param atten Attenuation to use
* @return Always ESP_OK * @return Always ESP_OK
*/ */
extern esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten); extern esp_err_t adc_cal_offset(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten);
#endif #endif

16
components/driver/test/test_adc_common.c
View File

@@ -71,7 +71,7 @@ static const int adc2_ch[ADC2_TEST_CHANNEL_NUM] = {
void adc_fake_tie_middle(adc_unit_t adc_unit, adc_channel_t channel) void adc_fake_tie_middle(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel); gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
@@ -79,7 +79,7 @@ void adc_fake_tie_middle(adc_unit_t adc_unit, adc_channel_t channel)
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_PULLDOWN)); TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_PULLUP_PULLDOWN));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel); gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
@@ -93,7 +93,7 @@ void adc_fake_tie_middle(adc_unit_t adc_unit, adc_channel_t channel)
void adc_fake_tie_high(adc_unit_t adc_unit, adc_channel_t channel) void adc_fake_tie_high(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel); gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
@@ -102,7 +102,7 @@ void adc_fake_tie_high(adc_unit_t adc_unit, adc_channel_t channel)
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY)); TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 1)); TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 1));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel); gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_en(gpio_num));
@@ -117,7 +117,7 @@ void adc_fake_tie_high(adc_unit_t adc_unit, adc_channel_t channel)
void adc_fake_tie_low(adc_unit_t adc_unit, adc_channel_t channel) void adc_fake_tie_low(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel); gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
@@ -126,7 +126,7 @@ void adc_fake_tie_low(adc_unit_t adc_unit, adc_channel_t channel)
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY)); TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_OUTPUT_ONLY));
TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 0)); TEST_ESP_OK(rtc_gpio_set_level(gpio_num, 0));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel); gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
@@ -141,7 +141,7 @@ void adc_fake_tie_low(adc_unit_t adc_unit, adc_channel_t channel)
void adc_io_normal(adc_unit_t adc_unit, adc_channel_t channel) void adc_io_normal(adc_unit_t adc_unit, adc_channel_t channel)
{ {
gpio_num_t gpio_num = 0; gpio_num_t gpio_num = 0;
if (adc_unit & ADC_UNIT_1) { if (adc_unit == ADC_UNIT_1) {
gpio_num = ADC_GET_IO_NUM(0, channel); gpio_num = ADC_GET_IO_NUM(0, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));
@@ -149,7 +149,7 @@ void adc_io_normal(adc_unit_t adc_unit, adc_channel_t channel)
TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_FLOATING)); TEST_ESP_OK(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); TEST_ESP_OK(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
} }
if (adc_unit & ADC_UNIT_2) { if (adc_unit == ADC_UNIT_2) {
gpio_num = ADC_GET_IO_NUM(1, channel); gpio_num = ADC_GET_IO_NUM(1, channel);
TEST_ESP_OK(rtc_gpio_init(gpio_num)); TEST_ESP_OK(rtc_gpio_init(gpio_num));
TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num)); TEST_ESP_OK(rtc_gpio_pullup_dis(gpio_num));

6
components/efuse/esp32s2/esp_efuse_rtc_table.c
View File

@@ -9,6 +9,7 @@
#include "esp_efuse.h" #include "esp_efuse.h"
#include "esp_efuse_table.h" #include "esp_efuse_table.h"
#include "esp_log.h" #include "esp_log.h"
#include "hal/adc_types.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#define RTC_TBL_LOG_TAG "efuse_rtc_table" #define RTC_TBL_LOG_TAG "efuse_rtc_table"
@@ -96,6 +97,7 @@ int esp_efuse_rtc_table_read_calib_version(void)
int esp_efuse_rtc_table_get_tag(int version, int adc_num, int atten, int extra_params) int esp_efuse_rtc_table_get_tag(int version, int adc_num, int atten, int extra_params)
{ {
int index = (adc_num == ADC_UNIT_1) ? 0 : 1;
int param_offset; // used to index which (adc_num, atten) array to use. int param_offset; // used to index which (adc_num, atten) array to use.
if (version == 1 && extra_params == RTCCALIB_V1_PARAM_VLOW) { // Volage LOW, Version 1 if (version == 1 && extra_params == RTCCALIB_V1_PARAM_VLOW) { // Volage LOW, Version 1
param_offset = RTCCALIB_V1_ADCREADINGLOW_OFFSET; param_offset = RTCCALIB_V1_ADCREADINGLOW_OFFSET;
@@ -109,8 +111,8 @@ int esp_efuse_rtc_table_get_tag(int version, int adc_num, int atten, int extra_p
return -1; return -1;
} }
int result = param_offset + (adc_num - 1) * RTCCALIB_ESP32S2_ATTENCOUNT + atten; int result = param_offset + index * RTCCALIB_ESP32S2_ATTENCOUNT + atten;
ESP_EARLY_LOGV(RTC_TBL_LOG_TAG, "V%d ADC%d ATTEN%d PARAM%d -> %d", version, adc_num, atten, extra_params, result); ESP_EARLY_LOGV(RTC_TBL_LOG_TAG, "V%d ADC%d ATTEN%d PARAM%d -> %d", version, adc_num + 1, atten, extra_params, result);
return result; return result;
} }

18
components/efuse/esp32s3/esp_efuse_rtc_calib.c
View File

@@ -9,13 +9,7 @@
#include "esp_log.h" #include "esp_log.h"
#include "esp_efuse.h" #include "esp_efuse.h"
#include "esp_efuse_table.h" #include "esp_efuse_table.h"
#include "hal/adc_types.h"
//Don't introduce new dependency of ADC, keep these macro same as ADC related definations
#define ADC_ATTEN_MAX 4
#define ADC_NUM_MAX 2
#define ADC_NUM_1 0
#define ADC_NUM_2 1
int esp_efuse_rtc_calib_get_ver(void) int esp_efuse_rtc_calib_get_ver(void)
{ {
@@ -34,14 +28,14 @@ uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int a
{ {
assert(version == 1); assert(version == 1);
assert(atten < 4); assert(atten < 4);
assert(adc_unit < ADC_NUM_MAX); assert(adc_unit <= ADC_UNIT_2);
const esp_efuse_desc_t **desc[8] = {ESP_EFUSE_ADC1_INIT_CODE_ATTEN0, ESP_EFUSE_ADC1_INIT_CODE_ATTEN1, ESP_EFUSE_ADC1_INIT_CODE_ATTEN2, ESP_EFUSE_ADC1_INIT_CODE_ATTEN3, const esp_efuse_desc_t **desc[8] = {ESP_EFUSE_ADC1_INIT_CODE_ATTEN0, ESP_EFUSE_ADC1_INIT_CODE_ATTEN1, ESP_EFUSE_ADC1_INIT_CODE_ATTEN2, ESP_EFUSE_ADC1_INIT_CODE_ATTEN3,
ESP_EFUSE_ADC2_INIT_CODE_ATTEN0, ESP_EFUSE_ADC2_INIT_CODE_ATTEN1, ESP_EFUSE_ADC2_INIT_CODE_ATTEN2, ESP_EFUSE_ADC2_INIT_CODE_ATTEN3}; ESP_EFUSE_ADC2_INIT_CODE_ATTEN0, ESP_EFUSE_ADC2_INIT_CODE_ATTEN1, ESP_EFUSE_ADC2_INIT_CODE_ATTEN2, ESP_EFUSE_ADC2_INIT_CODE_ATTEN3};
int efuse_icode_bits = 0; int efuse_icode_bits = 0;
uint32_t adc_icode[4] = {}; uint32_t adc_icode[4] = {};
uint32_t adc_icode_diff[4] = {}; uint32_t adc_icode_diff[4] = {};
uint8_t desc_index = (adc_unit == ADC_NUM_1) ? 0 : 4; uint8_t desc_index = (adc_unit == ADC_UNIT_1) ? 0 : 4;
for (int diff_index = 0; diff_index < 4; diff_index++) { for (int diff_index = 0; diff_index < 4; diff_index++) {
efuse_icode_bits = esp_efuse_get_field_size(desc[desc_index]); efuse_icode_bits = esp_efuse_get_field_size(desc[desc_index]);
@@ -50,7 +44,7 @@ uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int a
} }
//Version 1 logic for calculating ADC ICode based on EFUSE burnt value //Version 1 logic for calculating ADC ICode based on EFUSE burnt value
if (adc_unit == ADC_NUM_1) { if (adc_unit == ADC_UNIT_1) {
adc_icode[0] = adc_icode_diff[0] + 1850; adc_icode[0] = adc_icode_diff[0] + 1850;
adc_icode[1] = adc_icode_diff[1] + adc_icode[0] + 90; adc_icode[1] = adc_icode_diff[1] + adc_icode[0] + 90;
adc_icode[2] = adc_icode_diff[2] + adc_icode[1]; adc_icode[2] = adc_icode_diff[2] + adc_icode[1];
@@ -69,7 +63,7 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
{ {
assert(version == 1); assert(version == 1);
assert(atten < 4); assert(atten < 4);
assert(adc_unit < ADC_NUM_MAX); assert(adc_unit <= ADC_UNIT_2);
int efuse_vol_bits = 0; int efuse_vol_bits = 0;
uint32_t adc_vol_diff[8] = {}; uint32_t adc_vol_diff[8] = {};
@@ -91,7 +85,7 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
adc2_vol[1] = adc1_vol[1] - adc_vol_diff[5] + 10; adc2_vol[1] = adc1_vol[1] - adc_vol_diff[5] + 10;
adc2_vol[0] = adc1_vol[0] - adc_vol_diff[4] + 40; adc2_vol[0] = adc1_vol[0] - adc_vol_diff[4] + 40;
*out_digi = (adc_unit == ADC_NUM_1) ? adc1_vol[atten] : adc2_vol[atten]; *out_digi = (adc_unit == ADC_UNIT_1) ? adc1_vol[atten] : adc2_vol[atten];
*out_vol_mv = 850; *out_vol_mv = 850;
return ESP_OK; return ESP_OK;

2
components/esp_adc_cal/esp32s3/esp_adc_cal.c
View File

@@ -93,7 +93,7 @@ static esp_err_t get_reference_point(int version_num, adc_unit_t adc_num, adc_at
uint32_t voltage = 0; uint32_t voltage = 0;
uint32_t digi = 0; uint32_t digi = 0;
ret = esp_efuse_rtc_calib_get_cal_voltage(version_num, ((adc_num == ADC_UNIT_1) ? 0 : 1), atten, &digi, &voltage); ret = esp_efuse_rtc_calib_get_cal_voltage(version_num, adc_num, atten, &digi, &voltage);
assert(ret == ESP_OK); assert(ret == ESP_OK);
calib_info->ref_data.ver1.voltage = voltage; calib_info->ref_data.ver1.voltage = voltage;
calib_info->ref_data.ver1.digi = digi; calib_info->ref_data.ver1.digi = digi;

2
components/esp_adc_cal/include/esp_adc_cal.h
View File

@@ -33,7 +33,7 @@ typedef enum {
* @note Call esp_adc_cal_characterize() to initialize the structure * @note Call esp_adc_cal_characterize() to initialize the structure
*/ */
typedef struct { typedef struct {
adc_unit_t adc_num; /**< ADC number*/ adc_unit_t adc_num; /**< ADC unit*/
adc_atten_t atten; /**< ADC attenuation*/ adc_atten_t atten; /**< ADC attenuation*/
adc_bits_width_t bit_width; /**< ADC bit width */ adc_bits_width_t bit_width; /**< ADC bit width */
uint32_t coeff_a; /**< Gradient of ADC-Voltage curve*/ uint32_t coeff_a; /**< Gradient of ADC-Voltage curve*/

161
components/hal/adc_hal.c
View File

@@ -107,18 +107,6 @@ typedef enum {
#endif #endif
void adc_hal_init(void)
{
// Set internal FSM wait time, fixed value.
adc_ll_digi_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
adc_ll_digi_output_invert(ADC_NUM_1, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_1));
adc_ll_digi_output_invert(ADC_NUM_2, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_2));
adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
}
#if SOC_ADC_ARBITER_SUPPORTED #if SOC_ADC_ARBITER_SUPPORTED
void adc_hal_arbiter_config(adc_arbiter_t *config) void adc_hal_arbiter_config(adc_arbiter_t *config)
{ {
@@ -127,12 +115,47 @@ void adc_hal_arbiter_config(adc_arbiter_t *config)
} }
#endif // #if SOC_ADC_ARBITER_SUPPORTED #endif // #if SOC_ADC_ARBITER_SUPPORTED
void adc_hal_digi_deinit(adc_hal_context_t *hal) void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config)
{
hal->desc_dummy_head.next = hal->rx_desc;
hal->dev = config->dev;
hal->desc_max_num = config->desc_max_num;
hal->dma_chan = config->dma_chan;
hal->eof_num = config->eof_num;
}
void adc_hal_digi_init(adc_hal_dma_ctx_t *hal)
{
// Set internal FSM wait time, fixed value.
adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
adc_dma_ll_rx_enable_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
adc_ll_digi_dma_set_eof_num(hal->dev, hal->eof_num);
#if CONFIG_IDF_TARGET_ESP32
i2s_ll_rx_set_sample_bit(hal->dev, SAMPLE_BITS, SAMPLE_BITS);
i2s_ll_rx_enable_mono_mode(hal->dev, 1);
i2s_ll_rx_force_enable_fifo_mod(hal->dev, 1);
i2s_ll_enable_builtin_adc(hal->dev, 1);
#endif
#if CONFIG_IDF_TARGET_ESP32C3
adc_ll_onetime_sample_enable(ADC_UNIT_1, false);
adc_ll_onetime_sample_enable(ADC_UNIT_2, false);
#endif
}
void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal)
{ {
adc_ll_digi_trigger_disable(hal->dev); adc_ll_digi_trigger_disable(hal->dev);
adc_ll_digi_dma_disable(); adc_ll_digi_dma_disable();
adc_ll_digi_clear_pattern_table(ADC_NUM_1); adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
adc_ll_digi_clear_pattern_table(ADC_NUM_2); adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
adc_ll_digi_reset(hal->dev); adc_ll_digi_reset(hal->dev);
adc_ll_digi_controller_clk_disable(); adc_ll_digi_controller_clk_disable();
} }
@@ -140,9 +163,9 @@ void adc_hal_digi_deinit(adc_hal_context_t *hal)
/*--------------------------------------------------------------- /*---------------------------------------------------------------
Controller Setting Controller Setting
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
static adc_ll_controller_t get_controller(adc_ll_num_t unit, adc_hal_work_mode_t work_mode) static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
{ {
if (unit == ADC_NUM_1) { if (unit == ADC_UNIT_1) {
switch (work_mode) { switch (work_mode) {
#if SOC_ULP_SUPPORTED #if SOC_ULP_SUPPORTED
case ADC_HAL_ULP_MODE: case ADC_HAL_ULP_MODE:
@@ -182,7 +205,7 @@ static adc_ll_controller_t get_controller(adc_ll_num_t unit, adc_hal_work_mode_t
} }
} }
void adc_hal_set_controller(adc_ll_num_t unit, adc_hal_work_mode_t work_mode) void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
{ {
adc_ll_controller_t ctrlr = get_controller(unit, work_mode); adc_ll_controller_t ctrlr = get_controller(unit, work_mode);
adc_ll_set_controller(unit, ctrlr); adc_ll_set_controller(unit, ctrlr);
@@ -221,7 +244,7 @@ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t conve
* - Enable clock and select clock source for ADC digital controller. * - Enable clock and select clock source for ADC digital controller.
* For esp32, use I2S clock * For esp32, use I2S clock
*/ */
static void adc_hal_digi_sample_freq_config(adc_hal_context_t *hal, uint32_t freq) static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, uint32_t freq)
{ {
#if !CONFIG_IDF_TARGET_ESP32 #if !CONFIG_IDF_TARGET_ESP32
uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / freq; uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / freq;
@@ -243,7 +266,7 @@ static void adc_hal_digi_sample_freq_config(adc_hal_context_t *hal, uint32_t fre
#endif #endif
} }
void adc_hal_digi_controller_config(adc_hal_context_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg) void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg)
{ {
#if (SOC_ADC_DIGI_CONTROLLER_NUM == 1) #if (SOC_ADC_DIGI_CONTROLLER_NUM == 1)
//Only one pattern table, this variable is for readability //Only one pattern table, this variable is for readability
@@ -259,22 +282,22 @@ void adc_hal_digi_controller_config(adc_hal_context_t *hal, const adc_hal_digi_c
uint32_t adc1_pattern_idx = 0; uint32_t adc1_pattern_idx = 0;
uint32_t adc2_pattern_idx = 0; uint32_t adc2_pattern_idx = 0;
adc_ll_digi_clear_pattern_table(ADC_NUM_1); adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
adc_ll_digi_clear_pattern_table(ADC_NUM_2); adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
for (int i = 0; i < cfg->adc_pattern_len; i++) { for (int i = 0; i < cfg->adc_pattern_len; i++) {
if (cfg->adc_pattern[i].unit == ADC_NUM_1) { if (cfg->adc_pattern[i].unit == ADC_UNIT_1) {
adc_ll_digi_set_pattern_table(ADC_NUM_1, adc1_pattern_idx, cfg->adc_pattern[i]); adc_ll_digi_set_pattern_table(ADC_UNIT_1, adc1_pattern_idx, cfg->adc_pattern[i]);
adc1_pattern_idx++; adc1_pattern_idx++;
} else if (cfg->adc_pattern[i].unit == ADC_NUM_2) { } else if (cfg->adc_pattern[i].unit == ADC_UNIT_2) {
adc_ll_digi_set_pattern_table(ADC_NUM_2, adc2_pattern_idx, cfg->adc_pattern[i]); adc_ll_digi_set_pattern_table(ADC_UNIT_2, adc2_pattern_idx, cfg->adc_pattern[i]);
adc2_pattern_idx++; adc2_pattern_idx++;
} else { } else {
abort(); abort();
} }
} }
adc_ll_digi_set_pattern_table_len(ADC_NUM_1, adc1_pattern_idx); adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, adc1_pattern_idx);
adc_ll_digi_set_pattern_table_len(ADC_NUM_2, adc2_pattern_idx); adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, adc2_pattern_idx);
#endif #endif
@@ -291,32 +314,6 @@ void adc_hal_digi_controller_config(adc_hal_context_t *hal, const adc_hal_digi_c
adc_hal_digi_sample_freq_config(hal, cfg->sample_freq_hz); adc_hal_digi_sample_freq_config(hal, cfg->sample_freq_hz);
} }
void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *config)
{
hal->desc_dummy_head.next = hal->rx_desc;
hal->dev = config->dev;
hal->desc_max_num = config->desc_max_num;
hal->dma_chan = config->dma_chan;
hal->eof_num = config->eof_num;
}
void adc_hal_digi_init(adc_hal_context_t *hal)
{
adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
adc_dma_ll_rx_enable_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
adc_ll_digi_dma_set_eof_num(hal->dev, hal->eof_num);
#if CONFIG_IDF_TARGET_ESP32
i2s_ll_rx_set_sample_bit(hal->dev, SAMPLE_BITS, SAMPLE_BITS);
i2s_ll_rx_enable_mono_mode(hal->dev, 1);
i2s_ll_rx_force_enable_fifo_mod(hal->dev, 1);
i2s_ll_enable_builtin_adc(hal->dev, 1);
#endif
#if CONFIG_IDF_TARGET_ESP32C3
adc_ll_onetime_sample_enable(ADC_NUM_1, false);
adc_ll_onetime_sample_enable(ADC_NUM_2, false);
#endif
}
static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t size, uint32_t num) static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t size, uint32_t num)
{ {
HAL_ASSERT(((uint32_t)data_buf % 4) == 0); HAL_ASSERT(((uint32_t)data_buf % 4) == 0);
@@ -338,7 +335,7 @@ static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *d
desc[n-1].next = NULL; desc[n-1].next = NULL;
} }
void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf) void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
{ {
//stop peripheral and DMA //stop peripheral and DMA
adc_hal_digi_stop(hal); adc_hal_digi_stop(hal);
@@ -361,18 +358,18 @@ void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf)
} }
#if !SOC_GDMA_SUPPORTED #if !SOC_GDMA_SUPPORTED
intptr_t adc_hal_get_desc_addr(adc_hal_context_t *hal) intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal)
{ {
return adc_dma_ll_get_in_suc_eof_desc_addr(hal->dev, hal->dma_chan); return adc_dma_ll_get_in_suc_eof_desc_addr(hal->dev, hal->dma_chan);
} }
bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask) bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask)
{ {
return adc_dma_ll_rx_get_intr(hal->dev, mask); return adc_dma_ll_rx_get_intr(hal->dev, mask);
} }
#endif //#if !SOC_GDMA_SUPPORTED #endif //#if !SOC_GDMA_SUPPORTED
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc) adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc)
{ {
HAL_ASSERT(hal->cur_desc_ptr); HAL_ASSERT(hal->cur_desc_ptr);
if (!hal->cur_desc_ptr->next) { if (!hal->cur_desc_ptr->next) {
@@ -388,17 +385,17 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, con
return ADC_HAL_DMA_DESC_VALID; return ADC_HAL_DMA_DESC_VALID;
} }
void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask) void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
{ {
adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask); adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask);
} }
void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask) void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
{ {
adc_dma_ll_rx_disable_intr(hal->dev, hal->dma_chan, mask); adc_dma_ll_rx_disable_intr(hal->dev, hal->dma_chan, mask);
} }
void adc_hal_digi_stop(adc_hal_context_t *hal) void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal)
{ {
//stop ADC //stop ADC
adc_ll_digi_trigger_disable(hal->dev); adc_ll_digi_trigger_disable(hal->dev);
@@ -468,11 +465,11 @@ static void adc_hal_onetime_start(void)
//No need to delay here. Becuase if the start signal is not seen, there won't be a done intr. //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
} }
static esp_err_t adc_hal_single_read(adc_ll_num_t adc_n, int *out_raw) static esp_err_t adc_hal_single_read(adc_unit_t adc_n, int *out_raw)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
*out_raw = adc_ll_adc1_read(); *out_raw = adc_ll_adc1_read();
} else if (adc_n == ADC_NUM_2) { } else if (adc_n == ADC_UNIT_2) {
*out_raw = adc_ll_adc2_read(); *out_raw = adc_ll_adc2_read();
if (adc_ll_analysis_raw_data(adc_n, *out_raw)) { if (adc_ll_analysis_raw_data(adc_n, *out_raw)) {
return ESP_ERR_INVALID_STATE; return ESP_ERR_INVALID_STATE;
@@ -481,20 +478,20 @@ static esp_err_t adc_hal_single_read(adc_ll_num_t adc_n, int *out_raw)
return ESP_OK; return ESP_OK;
} }
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw) esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw)
{ {
esp_err_t ret; esp_err_t ret;
adc_hal_event_t event; adc_hal_event_t event;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
event = ADC_EVENT_ADC1_DONE; event = ADC_EVENT_ADC1_DONE;
} else { } else {
event = ADC_EVENT_ADC2_DONE; event = ADC_EVENT_ADC2_DONE;
} }
adc_hal_intr_clear(event); adc_hal_intr_clear(event);
adc_ll_onetime_sample_enable(ADC_NUM_1, false); adc_ll_onetime_sample_enable(ADC_UNIT_1, false);
adc_ll_onetime_sample_enable(ADC_NUM_2, false); adc_ll_onetime_sample_enable(ADC_UNIT_2, false);
adc_ll_onetime_sample_enable(adc_n, true); adc_ll_onetime_sample_enable(adc_n, true);
adc_ll_onetime_set_channel(adc_n, channel); adc_ll_onetime_set_channel(adc_n, channel);
@@ -509,7 +506,7 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
} }
#else // #if SOC_ADC_RTC_CTRL_SUPPORTED #else // #if SOC_ADC_RTC_CTRL_SUPPORTED
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw) esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw)
{ {
adc_ll_rtc_enable_channel(adc_n, channel); adc_ll_rtc_enable_channel(adc_n, channel);
adc_ll_rtc_start_convert(adc_n, channel); adc_ll_rtc_start_convert(adc_n, channel);
@@ -529,14 +526,14 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
ADC calibration setting ADC calibration setting
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
#if SOC_ADC_CALIBRATION_V1_SUPPORTED #if SOC_ADC_CALIBRATION_V1_SUPPORTED
void adc_hal_calibration_init(adc_ll_num_t adc_n) void adc_hal_calibration_init(adc_unit_t adc_n)
{ {
adc_ll_calibration_init(adc_n); adc_ll_calibration_init(adc_n);
} }
static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {-1, -1}; static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {-1, -1};
void adc_hal_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
if (param != s_previous_init_code[adc_n]) { if (param != s_previous_init_code[adc_n]) {
adc_ll_set_calibration_param(adc_n, param); adc_ll_set_calibration_param(adc_n, param);
@@ -545,7 +542,7 @@ void adc_hal_set_calibration_param(adc_ll_num_t adc_n, uint32_t param)
} }
#if SOC_ADC_RTC_CTRL_SUPPORTED #if SOC_ADC_RTC_CTRL_SUPPORTED
static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd) static void cal_setup(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
{ {
adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE); //Set controller adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE); //Set controller
@@ -559,7 +556,7 @@ static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t att
} }
} }
static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel) static uint32_t read_cal_channel(adc_unit_t adc_n, int channel)
{ {
adc_ll_rtc_start_convert(adc_n, channel); adc_ll_rtc_start_convert(adc_n, channel);
while (adc_ll_rtc_convert_is_done(adc_n) != true); while (adc_ll_rtc_convert_is_done(adc_n) != true);
@@ -568,13 +565,13 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
//For those RTC controller not supported chips, they use digital controller to do the single read. e.g.: esp32c3 //For those RTC controller not supported chips, they use digital controller to do the single read. e.g.: esp32c3
#elif SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED #elif SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd) static void cal_setup(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
{ {
adc_ll_onetime_sample_enable(ADC_NUM_1, false); adc_ll_onetime_sample_enable(ADC_UNIT_1, false);
adc_ll_onetime_sample_enable(ADC_NUM_2, false); adc_ll_onetime_sample_enable(ADC_UNIT_2, false);
/* Enable/disable internal connect GND (for calibration). */ /* Enable/disable internal connect GND (for calibration). */
if (internal_gnd) { if (internal_gnd) {
const int esp32c3_invalid_chan = (adc_n == ADC_NUM_1)? 0xF: 0x1; const int esp32c3_invalid_chan = (adc_n == ADC_UNIT_1)? 0xF: 0x1;
adc_ll_onetime_set_channel(adc_n, esp32c3_invalid_chan); adc_ll_onetime_set_channel(adc_n, esp32c3_invalid_chan);
} else { } else {
adc_ll_onetime_set_channel(adc_n, channel); adc_ll_onetime_set_channel(adc_n, channel);
@@ -583,7 +580,7 @@ static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t att
adc_ll_onetime_sample_enable(adc_n, true); adc_ll_onetime_sample_enable(adc_n, true);
} }
static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel) static uint32_t read_cal_channel(adc_unit_t adc_n, int channel)
{ {
adc_ll_intr_clear(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE); adc_ll_intr_clear(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE);
adc_ll_onetime_start(false); adc_ll_onetime_start(false);
@@ -593,9 +590,9 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
while(!adc_ll_intr_get_raw(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE)); while(!adc_ll_intr_get_raw(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE));
uint32_t read_val = -1; uint32_t read_val = -1;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
read_val = adc_ll_adc1_read(); read_val = adc_ll_adc1_read();
} else if (adc_n == ADC_NUM_2) { } else if (adc_n == ADC_UNIT_2) {
read_val = adc_ll_adc2_read(); read_val = adc_ll_adc2_read();
if (adc_ll_analysis_raw_data(adc_n, read_val)) { if (adc_ll_analysis_raw_data(adc_n, read_val)) {
return -1; return -1;
@@ -608,9 +605,9 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
#define ADC_HAL_CAL_TIMES (10) #define ADC_HAL_CAL_TIMES (10)
#define ADC_HAL_CAL_OFFSET_RANGE (4096) #define ADC_HAL_CAL_OFFSET_RANGE (4096)
uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd) uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
{ {
if (adc_n == ADC_NUM_2) { if (adc_n == ADC_UNIT_2) {
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
adc_hal_arbiter_config(&config); adc_hal_arbiter_config(&config);
} }

8
components/hal/esp32/adc_hal.c
View File

@@ -20,11 +20,11 @@ int adc_hal_hall_convert(void)
int hall_value; int hall_value;
// convert for 4 times with different phase and outputs // convert for 4 times with different phase and outputs
adc_ll_hall_phase_disable(); // hall phase adc_ll_hall_phase_disable(); // hall phase
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp0 ); adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_0, &Sens_Vp0 );
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn0 ); adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_3, &Sens_Vn0 );
adc_ll_hall_phase_enable(); adc_ll_hall_phase_enable();
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_0, &Sens_Vp1 ); adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_0, &Sens_Vp1 );
adc_hal_convert( ADC_NUM_1, ADC_CHANNEL_3, &Sens_Vn1 ); adc_hal_convert( ADC_UNIT_1, ADC_CHANNEL_3, &Sens_Vn1 );
hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0); hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
return hall_value; return hall_value;
} }

49
components/hal/esp32/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (1) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (1) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (16)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (16)

103
components/hal/esp32/include/hal/adc_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -19,11 +19,6 @@
extern "C" { extern "C" {
#endif #endif
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
@@ -182,11 +177,11 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* *
* @prarm adc_n ADC unit. * @prarm adc_n ADC unit.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -210,11 +205,11 @@ static inline void adc_ll_digi_set_data_source(bool src)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 16. * @param patt_len Items range: 1 ~ 16.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1; SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1; SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
} }
} }
@@ -229,7 +224,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 15. * @param pattern_index Items index. Range: 0 ~ 15.
* @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``. * @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
@@ -255,12 +250,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
} }
pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4); pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
if (table.unit == ADC_NUM_1) { if (table.unit == ADC_UNIT_1) {
tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -273,12 +268,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SYSCON.saradc_ctrl.sar1_patt_p_clear = 1; SYSCON.saradc_ctrl.sar1_patt_p_clear = 1;
SYSCON.saradc_ctrl.sar1_patt_p_clear = 0; SYSCON.saradc_ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SYSCON.saradc_ctrl.sar2_patt_p_clear = 1; SYSCON.saradc_ctrl.sar2_patt_p_clear = 1;
SYSCON.saradc_ctrl.sar2_patt_p_clear = 0; SYSCON.saradc_ctrl.sar2_patt_p_clear = 0;
} }
@@ -328,11 +323,11 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* *
* @param div Division factor. * @param div Division factor.
*/ */
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
} }
} }
@@ -343,12 +338,12 @@ static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param bits Output data bits width option, see ``adc_bits_width_t``. * @param bits Output data bits width option, see ``adc_bits_width_t``.
*/ */
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) static inline void adc_ll_rtc_set_output_format(adc_unit_t adc_n, adc_bits_width_t bits)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_start_force.sar1_bit_width = bits; SENS.sar_start_force.sar1_bit_width = bits;
SENS.sar_read_ctrl.sar1_sample_bit = bits; SENS.sar_read_ctrl.sar1_sample_bit = bits;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_start_force.sar2_bit_width = bits; SENS.sar_start_force.sar2_bit_width = bits;
SENS.sar_read_ctrl2.sar2_sample_bit = bits; SENS.sar_read_ctrl2.sar2_sample_bit = bits;
} }
@@ -362,11 +357,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_enable_channel(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
} }
} }
@@ -378,11 +373,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) static inline void adc_ll_rtc_disable_channel(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas_start1.sar1_en_pad = 0; //only one channel is selected. SENS.sar_meas_start1.sar1_en_pad = 0; //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.sar2_en_pad = 0; //only one channel is selected. SENS.sar_meas_start2.sar2_en_pad = 0; //only one channel is selected.
} }
} }
@@ -395,13 +390,13 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_start_convert(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {} while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
SENS.sar_meas_start1.meas1_start_sar = 0; SENS.sar_meas_start1.meas1_start_sar = 0;
SENS.sar_meas_start1.meas1_start_sar = 1; SENS.sar_meas_start1.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0 SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1 SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
} }
@@ -415,12 +410,12 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
* -true : The conversion process is finish. * -true : The conversion process is finish.
* -false : The conversion process is not finish. * -false : The conversion process is not finish.
*/ */
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) static inline bool adc_ll_rtc_convert_is_done(adc_unit_t adc_n)
{ {
bool ret = true; bool ret = true;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret = (bool)SENS.sar_meas_start1.meas1_done_sar; ret = (bool)SENS.sar_meas_start1.meas1_done_sar;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret = (bool)SENS.sar_meas_start2.meas2_done_sar; ret = (bool)SENS.sar_meas_start2.meas2_done_sar;
} }
return ret; return ret;
@@ -433,12 +428,12 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
* @return * @return
* - Converted value. * - Converted value.
*/ */
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) static inline int adc_ll_rtc_get_convert_value(adc_unit_t adc_n)
{ {
int ret_val = 0; int ret_val = 0;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
} }
return ret_val; return ret_val;
@@ -449,11 +444,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_rtc_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_read_ctrl2.sar2_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_read_ctrl2.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -466,7 +461,7 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
* @return * @return
* - 0: The data is correct to use. * - 0: The data is correct to use.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_unit_t adc_n, uint16_t raw_data)
{ {
/* ADC1 don't need check data */ /* ADC1 don't need check data */
return ADC_RTC_DATA_OK; return ADC_RTC_DATA_OK;
@@ -475,11 +470,11 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
/** /**
* Set the attenuation of a particular channel on ADCn. * Set the attenuation of a particular channel on ADCn.
*/ */
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) static inline void adc_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} }
} }
@@ -491,9 +486,9 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
* @param channel ADCn channel number. * @param channel ADCn channel number.
* @return atten The attenuation option. * @return atten The attenuation option.
*/ */
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel) static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
} else { } else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
@@ -531,9 +526,9 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param ctrl ADC controller. * @param ctrl ADC controller.
*/ */
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
switch ( ctrl ) { switch ( ctrl ) {
case ADC_LL_CTRL_RTC: case ADC_LL_CTRL_RTC:
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
@@ -559,7 +554,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
default: default:
break; break;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
switch ( ctrl ) { switch ( ctrl ) {
case ADC_LL_CTRL_RTC: case ADC_LL_CTRL_RTC:
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start. SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
@@ -669,9 +664,11 @@ static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl
* @param[in] channel ADC2 channel number * @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
if (adc != ADC_NUM_2) return; if (adc != ADC_UNIT_2) {
return;
}
if (en) { if (en) {
RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode

31
components/hal/esp32c2/include/hal/adc_hal_conf.h
View File

@@ -6,18 +6,23 @@
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (0) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)

51
components/hal/esp32c2/include/hal/adc_ll.h
View File

@@ -28,11 +28,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
@@ -190,7 +185,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8. * @param patt_len Items range: 1 ~ 8.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// APB_SARADC.ctrl.sar_patt_len = patt_len - 1; // APB_SARADC.ctrl.sar_patt_len = patt_len - 1;
@@ -206,7 +201,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 7. * @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules. * @param pattern Stored conversion rules.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// uint32_t tab; // uint32_t tab;
@@ -226,7 +221,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// APB_SARADC.ctrl.sar_patt_p_clear = 1; // APB_SARADC.ctrl.sar_patt_p_clear = 1;
@@ -251,12 +246,12 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert // APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
// } else { // adc_n == ADC_NUM_2 // } else { // adc_n == ADC_UNIT_2
// APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert // APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
// } // }
} }
@@ -338,7 +333,7 @@ static inline void adc_ll_digi_controller_clk_disable(void)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// APB_SARADC.filter_ctrl0.filter_reset = 1; // APB_SARADC.filter_ctrl0.filter_reset = 1;
@@ -519,10 +514,10 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* - 0: The data is correct to use. * - 0: The data is correct to use.
* - -1: The data is invalid. * - -1: The data is invalid.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, int raw_data)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// return ADC_RTC_DATA_OK; // return ADC_RTC_DATA_OK;
// } // }
@@ -559,7 +554,7 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
// } // }
} }
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
//Not used on ESP32-C2 //Not used on ESP32-C2
} }
@@ -637,10 +632,10 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig,
/** /**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET). * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/ */
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
// } else { // } else {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1);
@@ -657,11 +652,11 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage. * false: Use IO external voltage as calibration voltage.
*/ */
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// /* Enable/disable internal connect GND (for calibration). */ // /* Enable/disable internal connect GND (for calibration). */
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// if (internal_gnd) { // if (internal_gnd) {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
// } else { // } else {
@@ -681,10 +676,10 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
// } else { // } else {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
@@ -698,12 +693,12 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// uint8_t msb = param >> 8; // uint8_t msb = param >> 8;
// uint8_t lsb = param & 0xFF; // uint8_t lsb = param & 0xFF;
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
// } else { // } else {
@@ -724,7 +719,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC1 channel number * @param[in] channel ADC1 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (en) { // if (en) {
@@ -740,7 +735,7 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
// APB_SARADC.onetime_sample.adc1_onetime_sample = 1; // APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
// APB_SARADC.onetime_sample.onetime_channel = channel; // APB_SARADC.onetime_sample.onetime_channel = channel;
// SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); // SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
// if (adc == ADC_NUM_1) { // if (adc == ADC_UNIT_1) {
// /* Config test mux to route v_ref to ADC1 Channels */ // /* Config test mux to route v_ref to ADC1 Channels */
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); // REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
@@ -784,7 +779,7 @@ static inline void adc_ll_onetime_start(bool val)
// APB_SARADC.onetime_sample.onetime_start = val; // APB_SARADC.onetime_sample.onetime_start = val;
} }
static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel) static inline void adc_ll_onetime_set_channel(adc_unit_t unit, adc_channel_t channel)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); // APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel);
@@ -826,10 +821,10 @@ static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
// return (APB_SARADC.int_st.val & mask); // return (APB_SARADC.int_st.val & mask);
} }
static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_onetime_sample_enable(adc_unit_t adc_n, bool enable)
{ {
abort(); //TODO IDF-3908 abort(); //TODO IDF-3908
// if (adc_n == ADC_NUM_1) { // if (adc_n == ADC_UNIT_1) {
// APB_SARADC.onetime_sample.adc1_onetime_sample = enable; // APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
// } else { // } else {
// APB_SARADC.onetime_sample.adc2_onetime_sample = enable; // APB_SARADC.onetime_sample.adc2_onetime_sample = enable;

49
components/hal/esp32c3/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (0) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)

52
components/hal/esp32c3/include/hal/adc_ll.h
View File

@@ -28,12 +28,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */ ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
@@ -184,7 +178,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8. * @param patt_len Items range: 1 ~ 8.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
APB_SARADC.ctrl.sar_patt_len = patt_len - 1; APB_SARADC.ctrl.sar_patt_len = patt_len - 1;
} }
@@ -199,7 +193,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 7. * @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules. * @param pattern Stored conversion rules.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
@@ -218,7 +212,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
APB_SARADC.ctrl.sar_patt_p_clear = 1; APB_SARADC.ctrl.sar_patt_p_clear = 1;
APB_SARADC.ctrl.sar_patt_p_clear = 0; APB_SARADC.ctrl.sar_patt_p_clear = 0;
@@ -241,11 +235,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -321,7 +315,7 @@ static inline void adc_ll_digi_controller_clk_disable(void)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{ {
APB_SARADC.filter_ctrl0.filter_reset = 1; APB_SARADC.filter_ctrl0.filter_reset = 1;
} }
@@ -490,9 +484,9 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* - 0: The data is correct to use. * - 0: The data is correct to use.
* - -1: The data is invalid. * - -1: The data is invalid.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, int raw_data)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return ADC_RTC_DATA_OK; return ADC_RTC_DATA_OK;
} }
@@ -528,7 +522,7 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
} }
} }
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
//Not used on ESP32C3 //Not used on ESP32C3
} }
@@ -604,9 +598,9 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig,
/** /**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET). * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/ */
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1);
@@ -623,10 +617,10 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage. * false: Use IO external voltage as calibration voltage.
*/ */
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{ {
/* Enable/disable internal connect GND (for calibration). */ /* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (internal_gnd) { if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else { } else {
@@ -646,9 +640,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
@@ -662,11 +656,11 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
uint8_t msb = param >> 8; uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF; uint8_t lsb = param & 0xFF;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else { } else {
@@ -687,7 +681,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC1 channel number * @param[in] channel ADC1 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
if (en) { if (en) {
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3);
@@ -702,7 +696,7 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
APB_SARADC.onetime_sample.adc1_onetime_sample = 1; APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
APB_SARADC.onetime_sample.onetime_channel = channel; APB_SARADC.onetime_sample.onetime_channel = channel;
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
if (adc == ADC_NUM_1) { if (adc == ADC_UNIT_1) {
/* Config test mux to route v_ref to ADC1 Channels */ /* Config test mux to route v_ref to ADC1 Channels */
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
@@ -745,7 +739,7 @@ static inline void adc_ll_onetime_start(bool val)
APB_SARADC.onetime_sample.onetime_start = val; APB_SARADC.onetime_sample.onetime_start = val;
} }
static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel) static inline void adc_ll_onetime_set_channel(adc_unit_t unit, adc_channel_t channel)
{ {
APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel);
} }
@@ -780,9 +774,9 @@ static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
return (APB_SARADC.int_st.val & mask); return (APB_SARADC.int_st.val & mask);
} }
static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_onetime_sample_enable(adc_unit_t adc_n, bool enable)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.onetime_sample.adc1_onetime_sample = enable; APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
} else { } else {
APB_SARADC.onetime_sample.adc2_onetime_sample = enable; APB_SARADC.onetime_sample.adc2_onetime_sample = enable;

49
components/hal/esp32h2/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (0) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)

50
components/hal/esp32h2/include/hal/adc_ll.h
View File

@@ -28,12 +28,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */ ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
@@ -184,7 +178,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8. * @param patt_len Items range: 1 ~ 8.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
APB_SARADC.ctrl.sar_patt_len = patt_len - 1; APB_SARADC.ctrl.sar_patt_len = patt_len - 1;
} }
@@ -199,7 +193,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 7. * @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules. * @param pattern Stored conversion rules.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
@@ -218,7 +212,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
APB_SARADC.ctrl.sar_patt_p_clear = 1; APB_SARADC.ctrl.sar_patt_p_clear = 1;
APB_SARADC.ctrl.sar_patt_p_clear = 0; APB_SARADC.ctrl.sar_patt_p_clear = 0;
@@ -241,11 +235,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -321,7 +315,7 @@ static inline void adc_ll_digi_controller_clk_disable(void)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{ {
APB_SARADC.filter_ctrl0.filter_reset = 1; APB_SARADC.filter_ctrl0.filter_reset = 1;
} }
@@ -490,9 +484,9 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* - 0: The data is correct to use. * - 0: The data is correct to use.
* - -1: The data is invalid. * - -1: The data is invalid.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, int raw_data)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return ADC_RTC_DATA_OK; return ADC_RTC_DATA_OK;
} }
@@ -528,7 +522,7 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
} }
} }
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
//Not used on ESP32H2 //Not used on ESP32H2
} }
@@ -604,9 +598,9 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig,
/** /**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET). * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/ */
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1);
@@ -623,10 +617,10 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage. * false: Use IO external voltage as calibration voltage.
*/ */
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{ {
/* Enable/disable internal connect GND (for calibration). */ /* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (internal_gnd) { if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else { } else {
@@ -646,9 +640,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
@@ -662,11 +656,11 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
uint8_t msb = param >> 8; uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF; uint8_t lsb = param & 0xFF;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else { } else {
@@ -687,7 +681,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC1 channel number * @param[in] channel ADC1 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
abort(); abort();
} }
@@ -707,7 +701,7 @@ static inline void adc_ll_onetime_start(bool val)
APB_SARADC.onetime_sample.onetime_start = val; APB_SARADC.onetime_sample.onetime_start = val;
} }
static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel) static inline void adc_ll_onetime_set_channel(adc_unit_t unit, adc_channel_t channel)
{ {
APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel); APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel);
} }
@@ -742,9 +736,9 @@ static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
return (APB_SARADC.int_st.val & mask); return (APB_SARADC.int_st.val & mask);
} }
static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_onetime_sample_enable(adc_unit_t adc_n, bool enable)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.onetime_sample.adc1_onetime_sample = enable; APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
} else { } else {
APB_SARADC.onetime_sample.adc2_onetime_sample = enable; APB_SARADC.onetime_sample.adc2_onetime_sample = enable;

49
components/hal/esp32s2/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (0) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (3)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (2)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (3) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (2)

174
components/hal/esp32s2/include/hal/adc_ll.h
View File

@@ -27,12 +27,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */ ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
@@ -211,11 +205,11 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 16. * @param patt_len Items range: 1 ~ 16.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_len = patt_len - 1; APB_SARADC.ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_len = patt_len - 1; APB_SARADC.ctrl.sar2_patt_len = patt_len - 1;
} }
} }
@@ -230,7 +224,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 15. * @param pattern_index Items index. Range: 0 ~ 15.
* @param pattern Stored conversion rules. * @param pattern Stored conversion rules.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
@@ -238,12 +232,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
adc_ll_digi_pattern_table_t pattern = {0}; adc_ll_digi_pattern_table_t pattern = {0};
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 4); pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 4);
if (table.unit == ADC_NUM_1) { if (table.unit == ADC_UNIT_1) {
tab = APB_SARADC.sar1_patt_tab[index]; // Read old register value tab = APB_SARADC.sar1_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
APB_SARADC.sar1_patt_tab[index] = tab; // Write back APB_SARADC.sar1_patt_tab[index] = tab; // Write back
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
tab = APB_SARADC.sar2_patt_tab[index]; // Read old register value tab = APB_SARADC.sar2_patt_tab[index]; // Read old register value
tab &= (~(0xFF000000 >> offset)); // clear old data tab &= (~(0xFF000000 >> offset)); // clear old data
tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
@@ -256,12 +250,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_p_clear = 1; APB_SARADC.ctrl.sar1_patt_p_clear = 1;
APB_SARADC.ctrl.sar1_patt_p_clear = 0; APB_SARADC.ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_p_clear = 1; APB_SARADC.ctrl.sar2_patt_p_clear = 1;
APB_SARADC.ctrl.sar2_patt_p_clear = 0; APB_SARADC.ctrl.sar2_patt_p_clear = 0;
} }
@@ -284,11 +278,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -367,12 +361,12 @@ static inline void adc_ll_digi_controller_clk_disable(void)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_reset = 1; APB_SARADC.filter_ctrl.adc1_filter_reset = 1;
APB_SARADC.filter_ctrl.adc1_filter_reset = 0; APB_SARADC.filter_ctrl.adc1_filter_reset = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_reset = 1; APB_SARADC.filter_ctrl.adc2_filter_reset = 1;
APB_SARADC.filter_ctrl.adc2_filter_reset = 0; APB_SARADC.filter_ctrl.adc2_filter_reset = 0;
} }
@@ -384,7 +378,7 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/ */
static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor) static inline void adc_ll_digi_filter_set_factor(adc_unit_t adc_n, adc_digi_filter_mode_t factor)
{ {
int mode = 0; int mode = 0;
switch (factor) { switch (factor) {
@@ -395,9 +389,9 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
case ADC_DIGI_FILTER_IIR_64: mode = 64; break; case ADC_DIGI_FILTER_IIR_64: mode = 64; break;
default: mode = 8; break; default: mode = 8; break;
} }
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_factor = mode; APB_SARADC.filter_ctrl.adc1_filter_factor = mode;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_factor = mode; APB_SARADC.filter_ctrl.adc2_filter_factor = mode;
} }
} }
@@ -408,12 +402,12 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/ */
static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor) static inline void adc_ll_digi_filter_get_factor(adc_unit_t adc_n, adc_digi_filter_mode_t *factor)
{ {
int mode = 0; int mode = 0;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
mode = APB_SARADC.filter_ctrl.adc1_filter_factor; mode = APB_SARADC.filter_ctrl.adc1_filter_factor;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
mode = APB_SARADC.filter_ctrl.adc2_filter_factor; mode = APB_SARADC.filter_ctrl.adc2_filter_factor;
} }
switch (mode) { switch (mode) {
@@ -433,11 +427,11 @@ static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_fi
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time. * @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_digi_filter_enable(adc_unit_t adc_n, bool enable)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.filter_ctrl.adc1_filter_en = enable; APB_SARADC.filter_ctrl.adc1_filter_en = enable;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.filter_ctrl.adc2_filter_en = enable; APB_SARADC.filter_ctrl.adc2_filter_en = enable;
} }
} }
@@ -450,11 +444,11 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @return Filtered data. * @return Filtered data.
*/ */
static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) static inline uint32_t adc_ll_digi_filter_read_data(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data); return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data); return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data);
} }
} }
@@ -467,11 +461,11 @@ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
* @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt.
* false: If ADC_OUT < threshold, Generates monitor interrupt. * false: If ADC_OUT < threshold, Generates monitor interrupt.
*/ */
static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger) static inline void adc_ll_digi_monitor_set_mode(adc_unit_t adc_n, bool is_larger)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres_mode = is_larger; APB_SARADC.thres_ctrl.adc1_thres_mode = is_larger;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres_mode = is_larger; APB_SARADC.thres_ctrl.adc2_thres_mode = is_larger;
} }
} }
@@ -483,11 +477,11 @@ static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larg
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param threshold Monitor threshold. * @param threshold Monitor threshold.
*/ */
static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold) static inline void adc_ll_digi_monitor_set_thres(adc_unit_t adc_n, uint32_t threshold)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres = threshold; APB_SARADC.thres_ctrl.adc1_thres = threshold;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres = threshold; APB_SARADC.thres_ctrl.adc2_thres = threshold;
} }
} }
@@ -498,11 +492,11 @@ static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t th
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_digi_monitor_enable(adc_unit_t adc_n, bool enable)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.thres_ctrl.adc1_thres_en = enable; APB_SARADC.thres_ctrl.adc1_thres_en = enable;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.thres_ctrl.adc2_thres_en = enable; APB_SARADC.thres_ctrl.adc2_thres_en = enable;
} }
} }
@@ -578,11 +572,11 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* *
* @param div Division factor. * @param div Division factor.
*/ */
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
} }
} }
@@ -594,7 +588,7 @@ static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
* @prarm adc_n ADC unit. * @prarm adc_n ADC unit.
* @prarm bits Output data bits width option. * @prarm bits Output data bits width option.
*/ */
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) static inline void adc_ll_rtc_set_output_format(adc_unit_t adc_n, adc_bits_width_t bits)
{ {
return; return;
} }
@@ -607,11 +601,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_enable_channel(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected.
} }
} }
@@ -624,11 +618,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) static inline void adc_ll_rtc_disable_channel(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected. SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected. SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected.
} }
} }
@@ -641,13 +635,13 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_start_convert(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {} while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
SENS.sar_meas1_ctrl2.meas1_start_sar = 0; SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
SENS.sar_meas1_ctrl2.meas1_start_sar = 1; SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0 SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0
SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1 SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1
} }
@@ -661,12 +655,12 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
* -true : The conversion process is finish. * -true : The conversion process is finish.
* -false : The conversion process is not finish. * -false : The conversion process is not finish.
*/ */
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) static inline bool adc_ll_rtc_convert_is_done(adc_unit_t adc_n)
{ {
bool ret = true; bool ret = true;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar; ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar; ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar;
} }
return ret; return ret;
@@ -679,12 +673,12 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
* @return * @return
* - Converted value. * - Converted value.
*/ */
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) static inline int adc_ll_rtc_get_convert_value(adc_unit_t adc_n)
{ {
int ret_val = 0; int ret_val = 0;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
} }
return ret_val; return ret_val;
@@ -696,11 +690,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_rtc_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -710,12 +704,12 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n) static inline void adc_ll_rtc_intr_enable(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 1; SENS.sar_reader1_ctrl.sar1_int_en = 1;
RTCCNTL.int_ena.rtc_saradc1 = 1; RTCCNTL.int_ena.rtc_saradc1 = 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 1; SENS.sar_reader2_ctrl.sar2_int_en = 1;
RTCCNTL.int_ena.rtc_saradc2 = 1; RTCCNTL.int_ena.rtc_saradc2 = 1;
} }
@@ -726,12 +720,12 @@ static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n) static inline void adc_ll_rtc_intr_disable(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 0; SENS.sar_reader1_ctrl.sar1_int_en = 0;
RTCCNTL.int_ena.rtc_saradc1 = 0; RTCCNTL.int_ena.rtc_saradc1 = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 0; SENS.sar_reader2_ctrl.sar2_int_en = 0;
RTCCNTL.int_ena.rtc_saradc2 = 0; RTCCNTL.int_ena.rtc_saradc2 = 0;
} }
@@ -769,10 +763,10 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
* - 2: The data is invalid. The current controller process was interrupted by a higher priority controller. * - 2: The data is invalid. The current controller process was interrupted by a higher priority controller.
* - -1: The data is error. * - -1: The data is error.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_unit_t adc_n, uint16_t raw_data)
{ {
/* ADC1 don't need check data */ /* ADC1 don't need check data */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return ADC_RTC_DATA_OK; return ADC_RTC_DATA_OK;
} }
adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data; adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data;
@@ -820,11 +814,11 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
* @param channel ADCn channel number. * @param channel ADCn channel number.
* @param atten The attenuation option. * @param atten The attenuation option.
*/ */
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) static inline void adc_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} }
} }
@@ -836,9 +830,9 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
* @param channel ADCn channel number. * @param channel ADCn channel number.
* @return atten The attenuation option. * @return atten The attenuation option.
*/ */
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel) static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
} else { } else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
@@ -879,9 +873,9 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param ctrl ADC controller. * @param ctrl ADC controller.
*/ */
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
switch (ctrl) { switch (ctrl) {
case ADC_LL_CTRL_RTC: case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
@@ -901,7 +895,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
default: default:
break; break;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
switch (ctrl) { switch (ctrl) {
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2. //If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
case ADC_LL_CTRL_ARB: case ADC_LL_CTRL_ARB:
@@ -1018,9 +1012,9 @@ static inline void adc_ll_disable_sleep_controller(void)
/** /**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET). * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/ */
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
@@ -1037,7 +1031,7 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage. * false: Use IO external voltage as calibration voltage.
*/ */
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{ {
/* Should be called before writing I2C registers. */ /* Should be called before writing I2C registers. */
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
@@ -1046,7 +1040,7 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
/* Enable/disable internal connect GND (for calibration). */ /* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (internal_gnd) { if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else { } else {
@@ -1066,9 +1060,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
@@ -1082,7 +1076,7 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
uint8_t msb = param >> 8; uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF; uint8_t lsb = param & 0xFF;
@@ -1091,7 +1085,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else { } else {
@@ -1112,7 +1106,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC2 channel number * @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
/* Should be called before writing I2C registers. */ /* Should be called before writing I2C registers. */
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
@@ -1120,7 +1114,7 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
if (en) { if (en) {
if (adc == ADC_NUM_1) { if (adc == ADC_UNIT_1) {
/* Config test mux to route v_ref to ADC1 Channels */ /* Config test mux to route v_ref to ADC1 Channels */
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);

49
components/hal/esp32s3/include/hal/adc_hal_conf.h
View File

@@ -1,31 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once #pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (0) /*---------------------------------------------------------------
#define SOC_ADC2_DATA_INVERT_DEFAULT (0) Single Read
---------------------------------------------------------------*/
#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) /*---------------------------------------------------------------
DMA Read
---------------------------------------------------------------*/
#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8)
#define ADC_HAL_FSM_START_WAIT_DEFAULT (5)
#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) /*---------------------------------------------------------------
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) PWDET (Power Detect)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) ---------------------------------------------------------------*/
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) #define ADC_HAL_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)

146
components/hal/esp32s3/include/hal/adc_ll.h
View File

@@ -28,12 +28,6 @@ extern "C" {
#define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0 #define ADC_LL_CLKM_DIV_A_DEFAULT 0
typedef enum {
ADC_NUM_1 = 0, /*!< SAR ADC 1 */
ADC_NUM_2 = 1, /*!< SAR ADC 2 */
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum { typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */ ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */ ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
@@ -218,11 +212,11 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 16. * @param patt_len Items range: 1 ~ 16.
*/ */
static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_len = patt_len - 1; APB_SARADC.ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_len = patt_len - 1; APB_SARADC.ctrl.sar2_patt_len = patt_len - 1;
} }
} }
@@ -237,7 +231,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
* @param pattern_index Items index. Range: 0 ~ 11. * @param pattern_index Items index. Range: 0 ~ 11.
* @param pattern Stored conversion rules. * @param pattern Stored conversion rules.
*/ */
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{ {
uint32_t tab; uint32_t tab;
uint8_t index = pattern_index / 4; uint8_t index = pattern_index / 4;
@@ -245,7 +239,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
adc_ll_digi_pattern_table_t pattern = {0}; adc_ll_digi_pattern_table_t pattern = {0};
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2); pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
if (table.unit == ADC_NUM_1){ if (table.unit == ADC_UNIT_1){
tab = APB_SARADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value tab = APB_SARADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
tab &= (~(0xFC0000 >> offset)); //Clear old data tab &= (~(0xFC0000 >> offset)); //Clear old data
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
@@ -263,12 +257,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl.sar1_patt_p_clear = 1; APB_SARADC.ctrl.sar1_patt_p_clear = 1;
APB_SARADC.ctrl.sar1_patt_p_clear = 0; APB_SARADC.ctrl.sar1_patt_p_clear = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl.sar2_patt_p_clear = 1; APB_SARADC.ctrl.sar2_patt_p_clear = 1;
APB_SARADC.ctrl.sar2_patt_p_clear = 0; APB_SARADC.ctrl.sar2_patt_p_clear = 0;
} }
@@ -291,11 +285,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -373,7 +367,7 @@ static inline void adc_ll_digi_controller_clk_disable(void)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{ {
abort(); abort();
} }
@@ -384,7 +378,7 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/ */
static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor) static inline void adc_ll_digi_filter_set_factor(adc_unit_t adc_n, adc_digi_filter_mode_t factor)
{ {
abort(); abort();
} }
@@ -395,7 +389,7 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
*/ */
static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor) static inline void adc_ll_digi_filter_get_factor(adc_unit_t adc_n, adc_digi_filter_mode_t *factor)
{ {
abort(); abort();
} }
@@ -407,7 +401,7 @@ static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_fi
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time. * @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_digi_filter_enable(adc_unit_t adc_n, bool enable)
{ {
abort(); abort();
} }
@@ -420,7 +414,7 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @return Filtered data. * @return Filtered data.
*/ */
static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) static inline uint32_t adc_ll_digi_filter_read_data(adc_unit_t adc_n)
{ {
abort(); abort();
} }
@@ -433,7 +427,7 @@ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
* @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt.
* false: If ADC_OUT < threshold, Generates monitor interrupt. * false: If ADC_OUT < threshold, Generates monitor interrupt.
*/ */
static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger) static inline void adc_ll_digi_monitor_set_mode(adc_unit_t adc_n, bool is_larger)
{ {
abort(); abort();
} }
@@ -445,7 +439,7 @@ static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larg
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param threshold Monitor threshold. * @param threshold Monitor threshold.
*/ */
static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold) static inline void adc_ll_digi_monitor_set_thres(adc_unit_t adc_n, uint32_t threshold)
{ {
abort(); abort();
} }
@@ -456,7 +450,7 @@ static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t th
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable) static inline void adc_ll_digi_monitor_enable(adc_unit_t adc_n, bool enable)
{ {
abort(); abort();
} }
@@ -558,9 +552,9 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param ctrl ADC controller. * @param ctrl ADC controller.
*/ */
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
switch (ctrl) { switch (ctrl) {
case ADC_LL_CTRL_RTC: case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control. SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
@@ -580,7 +574,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
default: default:
break; break;
} }
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2. //If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
switch (ctrl) { switch (ctrl) {
case ADC_LL_CTRL_ARB: case ADC_LL_CTRL_ARB:
@@ -695,9 +689,9 @@ static inline void adc_ll_disable_sleep_controller(void)
/** /**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET). * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/ */
static inline void adc_ll_calibration_init(adc_ll_num_t adc_n) static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
@@ -712,7 +706,7 @@ static inline void adc_ll_calibration_init(adc_ll_num_t adc_n)
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage. * false: Use IO external voltage as calibration voltage.
*/ */
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd)
{ {
/* Should be called before writing I2C registers. */ /* Should be called before writing I2C registers. */
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M);
@@ -720,13 +714,13 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M); SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
/* Enable/disable internal connect GND (for calibration). */ /* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
if (internal_gnd) { if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else { } else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} }
} else { //adc_n == ADC_NUM_2 } else { //adc_n == ADC_UNIT_2
if (internal_gnd) { if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
} else { } else {
@@ -740,11 +734,11 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
} else { //adc_n == ADC_NUM_2 } else { //adc_n == ADC_UNIT_2
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
} }
} }
@@ -756,11 +750,11 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
* *
* @param adc_n ADC index number. * @param adc_n ADC index number.
*/ */
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
{ {
uint8_t msb = param >> 8; uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF; uint8_t lsb = param & 0xFF;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else { } else {
@@ -780,7 +774,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
* @param[in] channel ADC2 channel number * @param[in] channel ADC2 channel number
* @param[in] en Enable/disable the reference voltage output * @param[in] en Enable/disable the reference voltage output
*/ */
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{ {
abort(); abort();
} }
@@ -793,11 +787,11 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
* *
* @param div Division factor. * @param div Division factor.
*/ */
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
} }
} }
@@ -805,13 +799,13 @@ static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
/** /**
* Set adc output data format for RTC controller. * Set adc output data format for RTC controller.
* *
* @note ESP32S3 RTC controller only support 13bit. * @note ESP32S3 RTC controller only support 12bit.
* @prarm adc_n ADC unit. * @prarm adc_n ADC unit.
* @prarm bits Output data bits width option. * @prarm bits Output data bits width option.
*/ */
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) static inline void adc_ll_rtc_set_output_format(adc_unit_t adc_n, adc_bits_width_t bits)
{ {
//ESP32S3 only supports 12bit, leave here for compatibility
} }
/** /**
@@ -822,11 +816,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_enable_channel(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected. SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected.
} }
} }
@@ -839,11 +833,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) static inline void adc_ll_rtc_disable_channel(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected. SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected.
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected. SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected.
} }
} }
@@ -856,13 +850,13 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param channel ADC channel number for each ADCn. * @param channel ADC channel number for each ADCn.
*/ */
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) static inline void adc_ll_rtc_start_convert(adc_unit_t adc_n, int channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {} while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
SENS.sar_meas1_ctrl2.meas1_start_sar = 0; SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
SENS.sar_meas1_ctrl2.meas1_start_sar = 1; SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0 SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0
SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1 SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1
} }
@@ -876,12 +870,12 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
* -true : The conversion process is finish. * -true : The conversion process is finish.
* -false : The conversion process is not finish. * -false : The conversion process is not finish.
*/ */
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) static inline bool adc_ll_rtc_convert_is_done(adc_unit_t adc_n)
{ {
bool ret = true; bool ret = true;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar; ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar; ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar;
} }
return ret; return ret;
@@ -894,12 +888,12 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
* @return * @return
* - Converted value. * - Converted value.
*/ */
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) static inline int adc_ll_rtc_get_convert_value(adc_unit_t adc_n)
{ {
int ret_val = 0; int ret_val = 0;
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar); ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
} }
return ret_val; return ret_val;
@@ -911,11 +905,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
* @param adc_n ADC unit. * @param adc_n ADC unit.
* @param inv_en data invert or not. * @param inv_en data invert or not.
*/ */
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) static inline void adc_ll_rtc_output_invert(adc_unit_t adc_n, bool inv_en)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
} }
} }
@@ -925,12 +919,12 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n) static inline void adc_ll_rtc_intr_enable(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 1; SENS.sar_reader1_ctrl.sar1_int_en = 1;
RTCCNTL.int_ena.rtc_saradc1 = 1; RTCCNTL.int_ena.rtc_saradc1 = 1;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 1; SENS.sar_reader2_ctrl.sar2_int_en = 1;
RTCCNTL.int_ena.rtc_saradc2 = 1; RTCCNTL.int_ena.rtc_saradc2 = 1;
} }
@@ -941,12 +935,12 @@ static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
* *
* @param adc_n ADC unit. * @param adc_n ADC unit.
*/ */
static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n) static inline void adc_ll_rtc_intr_disable(adc_unit_t adc_n)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_reader1_ctrl.sar1_int_en = 0; SENS.sar_reader1_ctrl.sar1_int_en = 0;
RTCCNTL.int_ena.rtc_saradc1 = 0; RTCCNTL.int_ena.rtc_saradc1 = 0;
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_reader2_ctrl.sar2_int_en = 0; SENS.sar_reader2_ctrl.sar2_int_en = 0;
RTCCNTL.int_ena.rtc_saradc2 = 0; RTCCNTL.int_ena.rtc_saradc2 = 0;
} }
@@ -984,10 +978,10 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
* - 2: The data is invalid. The current controller process was interrupted by a higher priority controller. * - 2: The data is invalid. The current controller process was interrupted by a higher priority controller.
* - -1: The data is error. * - -1: The data is error.
*/ */
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_unit_t adc_n, uint16_t raw_data)
{ {
/* ADC1 don't need check data */ /* ADC1 don't need check data */
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return ADC_RTC_DATA_OK; return ADC_RTC_DATA_OK;
} }
adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data; adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data;
@@ -1035,11 +1029,11 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
* @param channel ADCn channel number. * @param channel ADCn channel number.
* @param atten The attenuation option. * @param atten The attenuation option.
*/ */
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) static inline void adc_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_NUM_2 } else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2)); SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
} }
} }
@@ -1051,9 +1045,9 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
* @param channel ADCn channel number. * @param channel ADCn channel number.
* @return atten The attenuation option. * @return atten The attenuation option.
*/ */
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel) static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{ {
if (adc_n == ADC_NUM_1) { if (adc_n == ADC_UNIT_1) {
return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
} else { } else {
return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3); return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);

63
components/hal/include/hal/adc_hal.h
View File

@@ -11,6 +11,7 @@
#include "hal/dma_types.h" #include "hal/dma_types.h"
#include "hal/adc_types.h" #include "hal/adc_types.h"
#include "hal/adc_ll.h" #include "hal/adc_ll.h"
#include "hal/adc_hal_common.h"
#include "esp_err.h" #include "esp_err.h"
#if SOC_GDMA_SUPPORTED #if SOC_GDMA_SUPPORTED
@@ -43,13 +44,6 @@ extern "C" {
//For ADC module, each conversion contains 4 bytes //For ADC module, each conversion contains 4 bytes
#define ADC_HAL_DATA_LEN_PER_CONV 4 #define ADC_HAL_DATA_LEN_PER_CONV 4
typedef enum adc_hal_work_mode_t {
ADC_HAL_ULP_MODE,
ADC_HAL_SINGLE_READ_MODE,
ADC_HAL_CONTINUOUS_READ_MODE,
ADC_HAL_PWDET_MODE
} adc_hal_work_mode_t;
/** /**
* @brief Enum for DMA descriptor status * @brief Enum for DMA descriptor status
*/ */
@@ -62,17 +56,17 @@ typedef enum adc_hal_dma_desc_status_t {
/** /**
* @brief Configuration of the HAL * @brief Configuration of the HAL
*/ */
typedef struct adc_hal_config_t { typedef struct adc_hal_dma_config_t {
void *dev; ///< DMA peripheral address void *dev; ///< DMA peripheral address
uint32_t desc_max_num; ///< Number of the descriptors linked once uint32_t desc_max_num; ///< Number of the descriptors linked once
uint32_t dma_chan; ///< DMA channel to be used uint32_t dma_chan; ///< DMA channel to be used
uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts
} adc_hal_config_t; } adc_hal_dma_config_t;
/** /**
* @brief Context of the HAL * @brief Context of the HAL
*/ */
typedef struct adc_hal_context_t { typedef struct adc_hal_dma_ctx_t {
/**< this needs to be malloced by the driver layer first */ /**< this needs to be malloced by the driver layer first */
dma_descriptor_t *rx_desc; ///< DMA descriptors dma_descriptor_t *rx_desc; ///< DMA descriptors
@@ -80,12 +74,12 @@ typedef struct adc_hal_context_t {
dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start
dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor
/**< these need to be configured by `adc_hal_config_t` via driver layer*/ /**< these need to be configured by `adc_hal_dma_config_t` via driver layer*/
void *dev; ///< DMA address void *dev; ///< DMA address
uint32_t desc_max_num; ///< Number of the descriptors linked once uint32_t desc_max_num; ///< Number of the descriptors linked once
uint32_t dma_chan; ///< DMA channel to be used uint32_t dma_chan; ///< DMA channel to be used
uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts
} adc_hal_context_t; } adc_hal_dma_ctx_t;
typedef struct adc_hal_digi_ctrlr_cfg_t { typedef struct adc_hal_digi_ctrlr_cfg_t {
bool conv_limit_en; //1: adc conversion will stop when `conv_limit_num` reaches. 0: won't stop. NOTE: esp32 should always be set to 1. bool conv_limit_en; //1: adc conversion will stop when `conv_limit_num` reaches. 0: won't stop. NOTE: esp32 should always be set to 1.
@@ -108,8 +102,6 @@ typedef struct adc_hal_digi_ctrlr_cfg_t {
*/ */
#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage) #define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
void adc_hal_set_controller(adc_ll_num_t unit, adc_hal_work_mode_t work_mode);
#if SOC_ADC_ARBITER_SUPPORTED #if SOC_ADC_ARBITER_SUPPORTED
//No ADC2 controller arbiter on ESP32 //No ADC2 controller arbiter on ESP32
/** /**
@@ -163,16 +155,18 @@ void adc_hal_arbiter_config(adc_arbiter_t *config);
Digital controller setting Digital controller setting
---------------------------------------------------------------*/ ---------------------------------------------------------------*/
/** /**
* ADC module initialization. * @brief Initialize the HW
*
* @param hal Context of the HAL
*/ */
void adc_hal_init(void); void adc_hal_digi_init(adc_hal_dma_ctx_t *hal);
/** /**
* Digital controller deinitialization. * Digital controller deinitialization.
* *
* @param hal Context of the HAL * @param hal Context of the HAL
*/ */
void adc_hal_digi_deinit(adc_hal_context_t *hal); void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal);
/** /**
* @brief Initialize the hal context * @brief Initialize the hal context
@@ -180,14 +174,7 @@ void adc_hal_digi_deinit(adc_hal_context_t *hal);
* @param hal Context of the HAL * @param hal Context of the HAL
* @param config Configuration of the HAL * @param config Configuration of the HAL
*/ */
void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *config); void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config);
/**
* @brief Initialize the HW
*
* @param hal Context of the HAL
*/
void adc_hal_digi_init(adc_hal_context_t *hal);
/** /**
* Setting the digital controller. * Setting the digital controller.
@@ -195,15 +182,15 @@ void adc_hal_digi_init(adc_hal_context_t *hal);
* @param hal Context of the HAL * @param hal Context of the HAL
* @param cfg Pointer to digital controller paramter. * @param cfg Pointer to digital controller paramter.
*/ */
void adc_hal_digi_controller_config(adc_hal_context_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg); void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg);
/** /**
* @brief Start Conversion * @brief Start Conversion
* *
* @param hal Context of the HAL * @param hal Context of the HAL
* @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_context_t`` * @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_dma_ctx_t``
*/ */
void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf); void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf);
#if !SOC_GDMA_SUPPORTED #if !SOC_GDMA_SUPPORTED
/** /**
@@ -213,7 +200,7 @@ void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf);
* *
* @return DMA descriptor address * @return DMA descriptor address
*/ */
intptr_t adc_hal_get_desc_addr(adc_hal_context_t *hal); intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal);
/** /**
* @brief Check the hardware interrupt event * @brief Check the hardware interrupt event
@@ -223,7 +210,7 @@ intptr_t adc_hal_get_desc_addr(adc_hal_context_t *hal);
* *
* @return True: the event is triggered. False: the event is not triggered yet. * @return True: the event is triggered. False: the event is not triggered yet.
*/ */
bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask); bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask);
#endif #endif
/** /**
@@ -235,7 +222,7 @@ bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask);
* *
* @return See ``adc_hal_dma_desc_status_t`` * @return See ``adc_hal_dma_desc_status_t``
*/ */
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc); adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc);
/** /**
* @brief Clear interrupt * @brief Clear interrupt
@@ -243,7 +230,7 @@ adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, con
* @param hal Context of the HAL * @param hal Context of the HAL
* @param mask mask of the interrupt * @param mask mask of the interrupt
*/ */
void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask); void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask);
/** /**
* @brief Enable interrupt * @brief Enable interrupt
@@ -251,14 +238,14 @@ void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask);
* @param hal Context of the HAL * @param hal Context of the HAL
* @param mask mask of the interrupt * @param mask mask of the interrupt
*/ */
void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask); void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask);
/** /**
* @brief Stop conversion * @brief Stop conversion
* *
* @param hal Context of the HAL * @param hal Context of the HAL
*/ */
void adc_hal_digi_stop(adc_hal_context_t *hal); void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal);
/*--------------------------------------------------------------- /*---------------------------------------------------------------
@@ -326,7 +313,7 @@ void adc_hal_digi_stop(adc_hal_context_t *hal);
* - ESP_OK: The value is valid. * - ESP_OK: The value is valid.
* - ESP_ERR_INVALID_STATE: The value is invalid. * - ESP_ERR_INVALID_STATE: The value is invalid.
*/ */
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw); esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw);
/*--------------------------------------------------------------- /*---------------------------------------------------------------
ADC calibration setting ADC calibration setting
@@ -338,7 +325,7 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw);
* *
* @param adc_n ADC index numer * @param adc_n ADC index numer
*/ */
void adc_hal_calibration_init(adc_ll_num_t adc_n); void adc_hal_calibration_init(adc_unit_t adc_n);
/** /**
* Set the calibration result (initial data) to ADC. * Set the calibration result (initial data) to ADC.
@@ -348,7 +335,7 @@ void adc_hal_calibration_init(adc_ll_num_t adc_n);
* @param adc_n ADC index number. * @param adc_n ADC index number.
* @param param the calibration parameter to configure * @param param the calibration parameter to configure
*/ */
void adc_hal_set_calibration_param(adc_ll_num_t adc_n, uint32_t param); void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param);
/** /**
* Calibrate the ADC using internal connections. * Calibrate the ADC using internal connections.
@@ -364,7 +351,7 @@ void adc_hal_set_calibration_param(adc_ll_num_t adc_n, uint32_t param);
* @return * @return
* - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set. * - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set.
*/ */
uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd); uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED

38
components/hal/include/hal/adc_hal_common.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* This header file is only for hardware abstract concepts and APIs
* used by both ADC RTC controller and Digital controller
*/
/**
* ADC work mode
*/
typedef enum adc_hal_work_mode_t {
ADC_HAL_ULP_MODE,
ADC_HAL_SINGLE_READ_MODE,
ADC_HAL_CONTINUOUS_READ_MODE,
ADC_HAL_PWDET_MODE
} adc_hal_work_mode_t;
/**
* Set ADC work mode
*
* @param unit ADC unit
* @param work_mode see `adc_hal_work_mode_t`
*/
void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode);
#ifdef __cplusplus
}
#endif

7
components/hal/include/hal/adc_types.h
View File

@@ -17,11 +17,8 @@
* @note For ADC digital controller (DMA mode), ESP32 doesn't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`. * @note For ADC digital controller (DMA mode), ESP32 doesn't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`.
*/ */
typedef enum { typedef enum {
ADC_UNIT_1 = 1, /*!< SAR ADC 1. */ ADC_UNIT_1, /*!< SAR ADC 1. */
ADC_UNIT_2 = 2, /*!< SAR ADC 2. */ ADC_UNIT_2, /*!< SAR ADC 2. */
ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */
ADC_UNIT_MAX,
} adc_unit_t; } adc_unit_t;
/** /**

23
components/soc/esp32/include/soc/adc_channel.h
View File

@@ -1,19 +1,10 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0 #pragma once
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO36_CHANNEL ADC1_CHANNEL_0 #define ADC1_GPIO36_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 36 #define ADC1_CHANNEL_0_GPIO_NUM 36
@@ -68,5 +59,3 @@
#define ADC2_GPIO26_CHANNEL ADC2_CHANNEL_9 #define ADC2_GPIO26_CHANNEL ADC2_CHANNEL_9
#define ADC2_CHANNEL_9_GPIO_NUM 26 #define ADC2_CHANNEL_9_GPIO_NUM 26
#endif /* _SOC_ADC_CHANNEL_H_ */

2
components/soc/esp32c2/adc_periph.c
View File

@@ -14,6 +14,6 @@ const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
}, },
/* ADC2 */ /* ADC2 */
{ {
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 -1, -1, -1, -1, -1
} }
}; };

5
components/soc/esp32c2/include/soc/adc_channel.h
View File

@@ -4,8 +4,7 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#ifndef _SOC_ADC_CHANNEL_H #pragma once
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 #define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 0 #define ADC1_CHANNEL_0_GPIO_NUM 0
@@ -24,5 +23,3 @@
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 #define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 5 #define ADC2_CHANNEL_0_GPIO_NUM 5
#endif

33
components/soc/esp32c3/include/soc/adc_channel.h
View File

@@ -1,36 +1,25 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0 #pragma once
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H #define ADC1_GPIO0_CHANNEL ADC1_CHANNEL_0
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 0 #define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1 #define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_1
#define ADC1_CHANNEL_1_GPIO_NUM 1 #define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2 #define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_2
#define ADC1_CHANNEL_2_GPIO_NUM 2 #define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3 #define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_3
#define ADC1_CHANNEL_3_GPIO_NUM 3 #define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4 #define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_4
#define ADC1_CHANNEL_4_GPIO_NUM 4 #define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 #define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 5 #define ADC2_CHANNEL_0_GPIO_NUM 5
#endif

20
components/soc/esp32h2/adc_periph.c
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/adc_periph.h" #include "soc/adc_periph.h"
@@ -22,6 +14,6 @@ const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
}, },
/* ADC2 */ /* ADC2 */
{ {
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 -1, -1, -1, -1, -1
} }
}; };

23
components/soc/esp32h2/include/soc/adc_channel.h
View File

@@ -1,19 +1,10 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0 #pragma once
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 #define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 0 #define ADC1_CHANNEL_0_GPIO_NUM 0
@@ -32,5 +23,3 @@
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 #define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 5 #define ADC2_CHANNEL_0_GPIO_NUM 5
#endif

23
components/soc/esp32s2/include/soc/adc_channel.h
View File

@@ -1,19 +1,10 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0 #pragma once
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 #define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 1 #define ADC1_CHANNEL_0_GPIO_NUM 1
@@ -74,5 +65,3 @@
#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9 #define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9
#define ADC2_CHANNEL_9_GPIO_NUM 20 #define ADC2_CHANNEL_9_GPIO_NUM 20
#endif

23
components/soc/esp32s3/include/soc/adc_channel.h
View File

@@ -1,19 +1,10 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H #pragma once
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 #define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 1 #define ADC1_CHANNEL_0_GPIO_NUM 1
@@ -74,5 +65,3 @@
#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9 #define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9
#define ADC2_CHANNEL_9_GPIO_NUM 20 #define ADC2_CHANNEL_9_GPIO_NUM 20
#endif

3
docs/en/migration-guides/peripherals.rst
View File

@@ -20,7 +20,8 @@ To make the API clearer, we renamed the function ``esp_rom_spiflash_lock`` to ``
ADC ADC
--- ---
Previous `driver/adc2_wifi_private.h` has been moved to `esp_private/adc2_wifi.h`. - Previous `driver/adc2_wifi_private.h` has been moved to `esp_private/adc2_wifi.h`.
- Enums `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER` and `ADC_UNIT_MAX` in ``adc_unit_t`` are removed.
GPIO GPIO
---- ----

11
tools/ci/check_copyright_ignore.txt
View File

@@ -811,7 +811,6 @@ components/hal/dac_hal.c
components/hal/ds_hal.c components/hal/ds_hal.c
components/hal/esp32/brownout_hal.c components/hal/esp32/brownout_hal.c
components/hal/esp32/gpio_hal_workaround.c components/hal/esp32/gpio_hal_workaround.c
components/hal/esp32/include/hal/adc_hal_conf.h
components/hal/esp32/include/hal/aes_ll.h components/hal/esp32/include/hal/aes_ll.h
components/hal/esp32/include/hal/can_hal.h components/hal/esp32/include/hal/can_hal.h
components/hal/esp32/include/hal/can_ll.h components/hal/esp32/include/hal/can_ll.h
@@ -837,7 +836,6 @@ components/hal/esp32/include/hal/uart_ll.h
components/hal/esp32/interrupt_descriptor_table.c components/hal/esp32/interrupt_descriptor_table.c
components/hal/esp32/touch_sensor_hal.c components/hal/esp32/touch_sensor_hal.c
components/hal/esp32c3/hmac_hal.c components/hal/esp32c3/hmac_hal.c
components/hal/esp32c3/include/hal/adc_hal_conf.h
components/hal/esp32c3/include/hal/aes_ll.h components/hal/esp32c3/include/hal/aes_ll.h
components/hal/esp32c3/include/hal/ds_ll.h components/hal/esp32c3/include/hal/ds_ll.h
components/hal/esp32c3/include/hal/gpspi_flash_ll.h components/hal/esp32c3/include/hal/gpspi_flash_ll.h
@@ -859,7 +857,6 @@ components/hal/esp32c3/include/hal/uhci_ll.h
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
components/hal/esp32c3/rtc_cntl_hal.c components/hal/esp32c3/rtc_cntl_hal.c
components/hal/esp32h2/hmac_hal.c components/hal/esp32h2/hmac_hal.c
components/hal/esp32h2/include/hal/adc_hal_conf.h
components/hal/esp32h2/include/hal/aes_ll.h components/hal/esp32h2/include/hal/aes_ll.h
components/hal/esp32h2/include/hal/ds_ll.h components/hal/esp32h2/include/hal/ds_ll.h
components/hal/esp32h2/include/hal/gpspi_flash_ll.h components/hal/esp32h2/include/hal/gpspi_flash_ll.h
@@ -879,7 +876,6 @@ components/hal/esp32h2/include/hal/uhci_ll.h
components/hal/esp32h2/include/hal/uhci_types.h components/hal/esp32h2/include/hal/uhci_types.h
components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
components/hal/esp32s2/cp_dma_hal.c components/hal/esp32s2/cp_dma_hal.c
components/hal/esp32s2/include/hal/adc_hal_conf.h
components/hal/esp32s2/include/hal/aes_ll.h components/hal/esp32s2/include/hal/aes_ll.h
components/hal/esp32s2/include/hal/cp_dma_hal.h components/hal/esp32s2/include/hal/cp_dma_hal.h
components/hal/esp32s2/include/hal/cp_dma_ll.h components/hal/esp32s2/include/hal/cp_dma_ll.h
@@ -909,7 +905,6 @@ components/hal/esp32s2/include/hal/twai_ll.h
components/hal/esp32s2/include/hal/usb_ll.h components/hal/esp32s2/include/hal/usb_ll.h
components/hal/esp32s2/interrupt_descriptor_table.c components/hal/esp32s2/interrupt_descriptor_table.c
components/hal/esp32s2/touch_sensor_hal.c components/hal/esp32s2/touch_sensor_hal.c
components/hal/esp32s3/include/hal/adc_hal_conf.h
components/hal/esp32s3/include/hal/aes_ll.h components/hal/esp32s3/include/hal/aes_ll.h
components/hal/esp32s3/include/hal/gpspi_flash_ll.h components/hal/esp32s3/include/hal/gpspi_flash_ll.h
components/hal/esp32s3/include/hal/i2c_ll.h components/hal/esp32s3/include/hal/i2c_ll.h
@@ -1262,7 +1257,6 @@ components/soc/esp32/adc_periph.c
components/soc/esp32/dac_periph.c components/soc/esp32/dac_periph.c
components/soc/esp32/gpio_periph.c components/soc/esp32/gpio_periph.c
components/soc/esp32/i2c_periph.c components/soc/esp32/i2c_periph.c
components/soc/esp32/include/soc/adc_channel.h
components/soc/esp32/include/soc/apb_ctrl_reg.h components/soc/esp32/include/soc/apb_ctrl_reg.h
components/soc/esp32/include/soc/apb_ctrl_struct.h components/soc/esp32/include/soc/apb_ctrl_struct.h
components/soc/esp32/include/soc/bb_reg.h components/soc/esp32/include/soc/bb_reg.h
@@ -1340,7 +1334,6 @@ components/soc/esp32c3/adc_periph.c
components/soc/esp32c3/gpio_periph.c components/soc/esp32c3/gpio_periph.c
components/soc/esp32c3/i2c_bbpll.h components/soc/esp32c3/i2c_bbpll.h
components/soc/esp32c3/i2c_periph.c components/soc/esp32c3/i2c_periph.c
components/soc/esp32c3/include/soc/adc_channel.h
components/soc/esp32c3/include/soc/apb_ctrl_reg.h components/soc/esp32c3/include/soc/apb_ctrl_reg.h
components/soc/esp32c3/include/soc/apb_ctrl_struct.h components/soc/esp32c3/include/soc/apb_ctrl_struct.h
components/soc/esp32c3/include/soc/apb_saradc_reg.h components/soc/esp32c3/include/soc/apb_saradc_reg.h
@@ -1398,10 +1391,8 @@ components/soc/esp32c3/ledc_periph.c
components/soc/esp32c3/sigmadelta_periph.c components/soc/esp32c3/sigmadelta_periph.c
components/soc/esp32c3/spi_periph.c components/soc/esp32c3/spi_periph.c
components/soc/esp32c3/uart_periph.c components/soc/esp32c3/uart_periph.c
components/soc/esp32h2/adc_periph.c
components/soc/esp32h2/gdma_periph.c components/soc/esp32h2/gdma_periph.c
components/soc/esp32h2/i2c_periph.c components/soc/esp32h2/i2c_periph.c
components/soc/esp32h2/include/soc/adc_channel.h
components/soc/esp32h2/include/soc/apb_ctrl_reg.h components/soc/esp32h2/include/soc/apb_ctrl_reg.h
components/soc/esp32h2/include/soc/apb_ctrl_struct.h components/soc/esp32h2/include/soc/apb_ctrl_struct.h
components/soc/esp32h2/include/soc/apb_saradc_reg.h components/soc/esp32h2/include/soc/apb_saradc_reg.h
@@ -1448,7 +1439,6 @@ components/soc/esp32s2/adc_periph.c
components/soc/esp32s2/dac_periph.c components/soc/esp32s2/dac_periph.c
components/soc/esp32s2/dedic_gpio_periph.c components/soc/esp32s2/dedic_gpio_periph.c
components/soc/esp32s2/i2c_periph.c components/soc/esp32s2/i2c_periph.c
components/soc/esp32s2/include/soc/adc_channel.h
components/soc/esp32s2/include/soc/apb_ctrl_reg.h components/soc/esp32s2/include/soc/apb_ctrl_reg.h
components/soc/esp32s2/include/soc/apb_ctrl_struct.h components/soc/esp32s2/include/soc/apb_ctrl_struct.h
components/soc/esp32s2/include/soc/apb_saradc_reg.h components/soc/esp32s2/include/soc/apb_saradc_reg.h
@@ -1531,7 +1521,6 @@ components/soc/esp32s2/usb_periph.c
components/soc/esp32s3/dedic_gpio_periph.c components/soc/esp32s3/dedic_gpio_periph.c
components/soc/esp32s3/gpio_periph.c components/soc/esp32s3/gpio_periph.c
components/soc/esp32s3/i2c_periph.c components/soc/esp32s3/i2c_periph.c
components/soc/esp32s3/include/soc/adc_channel.h
components/soc/esp32s3/include/soc/apb_ctrl_reg.h components/soc/esp32s3/include/soc/apb_ctrl_reg.h
components/soc/esp32s3/include/soc/apb_ctrl_struct.h components/soc/esp32s3/include/soc/apb_ctrl_struct.h
components/soc/esp32s3/include/soc/apb_saradc_reg.h components/soc/esp32s3/include/soc/apb_saradc_reg.h