From 626fad990d461037c5f1b5eb2d7feca3d0588516 Mon Sep 17 00:00:00 2001
From: morris <maoshengrong@espressif.com>
Date: Wed, 27 Aug 2025 17:23:56 +0800
Subject: [PATCH] chore(soc): checked P4-ECO5 regsiters for
 dw_gdma,timg,etm,dsi

chore(mipi_dsi): checked the register on P4 ECO5

checked timg and etm registers
---
 components/soc/esp32p4/include/soc/soc.h      |    1 -
 .../register/hw_ver1/soc/timer_group_reg.h    |    2 +
 .../hw_ver2/soc/dw_gdma_eco5_struct.h         | 5184 -----------------
 .../hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h |  868 ---
 .../hw_ver2/soc/mipi_dsi_bridge_struct.h      |   74 +-
 .../hw_ver2/soc/mipi_dsi_host_eco5_struct.h   | 2007 -------
 .../register/hw_ver2/soc/soc_etm_struct.h     |    2 -
 .../hw_ver2/soc/timer_group_eco5_reg.h        |  716 ---
 .../hw_ver2/soc/timer_group_eco5_struct.h     |  571 --
 .../register/hw_ver2/soc/timer_group_reg.h    |    2 +-
 .../register/hw_ver2/soc/timer_group_struct.h |    2 -
 11 files changed, 64 insertions(+), 9365 deletions(-)
 delete mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
 delete mode 100644 components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h
 delete mode 100644 components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h
 delete mode 100644 components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h
 delete mode 100644 components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h

diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index 2e8bc781fd..464eee0e4e 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -19,7 +19,6 @@
 #define REG_UHCI_BASE(i)                        (DR_REG_UHCI0_BASE)                      // only one UHCI on C6
 #define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)        // UART0 and UART1
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_BASE(i) + 0x0)
-#define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000)  // SPIMEM0 and SPIMEM1
 #define REG_SPI_BASE(i)                         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)                         (DR_REG_I2C0_BASE + (i) * 0x1000)
diff --git a/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h
index 53679d5b04..7dc0d8eb3b 100644
--- a/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h
+++ b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_TIMG_BASE(i)  (DR_REG_TIMG0_BASE + (i) * 0x1000)
+
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
deleted file mode 100644
index c030f0e037..0000000000
--- a/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
+++ /dev/null
@@ -1,5184 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Version Register */
-/** Type of id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_id : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_id:32;
-    };
-    uint32_t val;
-} dmac_id0_reg_t;
-
-/** Type of compver0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
-         *  NA
-         */
-        uint32_t dmac_compver:32;
-    };
-    uint32_t val;
-} dmac_compver0_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_en:1;
-        /** int_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t int_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dmac_cfg0_reg_t;
-
-/** Type of chen0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_en:1;
-        /** ch2_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_en:1;
-        /** ch3_en : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_en:1;
-        /** ch4_en : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_en:1;
-        uint32_t reserved_4:4;
-        /** ch1_en_we : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_en_we:1;
-        /** ch2_en_we : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_en_we:1;
-        /** ch3_en_we : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_en_we:1;
-        /** ch4_en_we : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_en_we:1;
-        uint32_t reserved_12:4;
-        /** ch1_susp : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_susp:1;
-        /** ch2_susp : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_susp:1;
-        /** ch3_susp : R/W; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_susp:1;
-        /** ch4_susp : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_susp:1;
-        uint32_t reserved_20:4;
-        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_susp_we:1;
-        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_susp_we:1;
-        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_susp_we:1;
-        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_susp_we:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dmac_chen0_reg_t;
-
-/** Type of chen1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_abort : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_abort:1;
-        /** ch2_abort : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_abort:1;
-        /** ch3_abort : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_abort:1;
-        /** ch4_abort : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_abort:1;
-        uint32_t reserved_4:4;
-        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_abort_we:1;
-        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_abort_we:1;
-        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_abort_we:1;
-        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_abort_we:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dmac_chen1_reg_t;
-
-/** Type of reset0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_rst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_rst:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_reset0_reg_t;
-
-/** Type of lowpower_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t gbl_cslp_en:1;
-        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t chnl_cslp_en:1;
-        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t sbiu_cslp_en:1;
-        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t mxif_cslp_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_lowpower_cfg0_reg_t;
-
-/** Type of lowpower_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
-         *  NA
-         */
-        uint32_t glch_lpdly:8;
-        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
-         *  NA
-         */
-        uint32_t sbiu_lpdly:8;
-        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
-         *  NA
-         */
-        uint32_t mxif_lpdly:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dmac_lowpower_cfg1_reg_t;
-
-/** Type of ch1_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_sar0_reg_t;
-
-/** Type of ch1_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_sar1_reg_t;
-
-/** Type of ch1_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_dar0_reg_t;
-
-/** Type of ch1_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_dar1_reg_t;
-
-/** Type of ch1_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch1_block_ts0_reg_t;
-
-/** Type of ch1_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sms:1;
-        uint32_t reserved_1:1;
-        /** ch1_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dms:1;
-        uint32_t reserved_3:1;
-        /** ch1_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch1_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch1_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch1_src_tr_width:3;
-        /** ch1_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch1_dst_tr_width:3;
-        /** ch1_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_msize:4;
-        /** ch1_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_msize:4;
-        /** ch1_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ar_cache:4;
-        /** ch1_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_aw_cache:4;
-        /** ch1_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch1_ctl0_reg_t;
-
-/** Type of ch1_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ar_prot:3;
-        /** ch1_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_aw_prot:3;
-        /** ch1_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_arlen_en:1;
-        /** ch1_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_arlen:8;
-        /** ch1_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_awlen_en:1;
-        /** ch1_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_awlen:8;
-        /** ch1_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_stat_en:1;
-        /** ch1_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_stat_en:1;
-        /** ch1_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch1_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_last:1;
-        /** ch1_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch1_ctl1_reg_t;
-
-/** Type of ch1_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_multblk_type:2;
-        /** ch1_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch1_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch1_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch1_cfg0_reg_t;
-
-/** Type of ch1_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch1_tt_fc:3;
-        /** ch1_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_hs_sel_src:1;
-        /** ch1_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_hs_sel_dst:1;
-        /** ch1_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_hwhs_pol:1;
-        /** ch1_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_hwhs_pol:1;
-        /** ch1_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch1_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch1_ch_prior : R/W; bitpos: [19:17]; default: 3;
-         *  NA
-         */
-        uint32_t ch1_ch_prior:3;
-        /** ch1_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lock_ch:1;
-        /** ch1_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lock_ch_l:2;
-        /** ch1_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_osr_lmt:4;
-        /** ch1_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch1_cfg1_reg_t;
-
-/** Type of ch1_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lms:1;
-        uint32_t reserved_1:5;
-        /** ch1_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch1_llp0_reg_t;
-
-/** Type of ch1_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch1_llp1_reg_t;
-
-/** Type of ch1_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_src:1;
-        /** ch1_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_src_we:1;
-        /** ch1_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_src:1;
-        /** ch1_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_src_we:1;
-        /** ch1_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_src:1;
-        /** ch1_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch1_swhssrc0_reg_t;
-
-/** Type of ch1_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_dst:1;
-        /** ch1_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_dst_we:1;
-        /** ch1_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_dst:1;
-        /** ch1_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_dst_we:1;
-        /** ch1_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_dst:1;
-        /** ch1_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch1_swhsdst0_reg_t;
-
-/** Type of ch1_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch1_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch1_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch1_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch1_axi_id0_reg_t;
-
-/** Type of ch1_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_awqos:4;
-        /** ch1_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch1_axi_qos0_reg_t;
-
-/** Type of ch2_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_sar0_reg_t;
-
-/** Type of ch2_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_sar1_reg_t;
-
-/** Type of ch2_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_dar0_reg_t;
-
-/** Type of ch2_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_dar1_reg_t;
-
-/** Type of ch2_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch2_block_ts0_reg_t;
-
-/** Type of ch2_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sms:1;
-        uint32_t reserved_1:1;
-        /** ch2_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dms:1;
-        uint32_t reserved_3:1;
-        /** ch2_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch2_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch2_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_src_tr_width:3;
-        /** ch2_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_dst_tr_width:3;
-        /** ch2_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_msize:4;
-        /** ch2_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_msize:4;
-        /** ch2_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ar_cache:4;
-        /** ch2_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_aw_cache:4;
-        /** ch2_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch2_ctl0_reg_t;
-
-/** Type of ch2_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ar_prot:3;
-        /** ch2_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_aw_prot:3;
-        /** ch2_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_arlen_en:1;
-        /** ch2_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_arlen:8;
-        /** ch2_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_awlen_en:1;
-        /** ch2_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_awlen:8;
-        /** ch2_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_stat_en:1;
-        /** ch2_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_stat_en:1;
-        /** ch2_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch2_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_last:1;
-        /** ch2_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch2_ctl1_reg_t;
-
-/** Type of ch2_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_multblk_type:2;
-        /** ch2_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch2_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch2_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch2_cfg0_reg_t;
-
-/** Type of ch2_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch2_tt_fc:3;
-        /** ch2_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_hs_sel_src:1;
-        /** ch2_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_hs_sel_dst:1;
-        /** ch2_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_hwhs_pol:1;
-        /** ch2_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_hwhs_pol:1;
-        /** ch2_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch2_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch2_ch_prior : R/W; bitpos: [19:17]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_ch_prior:3;
-        /** ch2_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lock_ch:1;
-        /** ch2_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lock_ch_l:2;
-        /** ch2_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_osr_lmt:4;
-        /** ch2_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch2_cfg1_reg_t;
-
-/** Type of ch2_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lms:1;
-        uint32_t reserved_1:5;
-        /** ch2_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch2_llp0_reg_t;
-
-/** Type of ch2_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch2_llp1_reg_t;
-
-/** Type of ch2_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_src:1;
-        /** ch2_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_src_we:1;
-        /** ch2_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_src:1;
-        /** ch2_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_src_we:1;
-        /** ch2_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_src:1;
-        /** ch2_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch2_swhssrc0_reg_t;
-
-/** Type of ch2_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_dst:1;
-        /** ch2_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_dst_we:1;
-        /** ch2_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_dst:1;
-        /** ch2_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_dst_we:1;
-        /** ch2_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_dst:1;
-        /** ch2_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch2_swhsdst0_reg_t;
-
-/** Type of ch2_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch2_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch2_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch2_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch2_axi_id0_reg_t;
-
-/** Type of ch2_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_awqos:4;
-        /** ch2_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch2_axi_qos0_reg_t;
-
-/** Type of ch3_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_sar0_reg_t;
-
-/** Type of ch3_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_sar1_reg_t;
-
-/** Type of ch3_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_dar0_reg_t;
-
-/** Type of ch3_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_dar1_reg_t;
-
-/** Type of ch3_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch3_block_ts0_reg_t;
-
-/** Type of ch3_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sms:1;
-        uint32_t reserved_1:1;
-        /** ch3_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dms:1;
-        uint32_t reserved_3:1;
-        /** ch3_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch3_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch3_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch3_src_tr_width:3;
-        /** ch3_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch3_dst_tr_width:3;
-        /** ch3_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_msize:4;
-        /** ch3_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_msize:4;
-        /** ch3_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ar_cache:4;
-        /** ch3_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_aw_cache:4;
-        /** ch3_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch3_ctl0_reg_t;
-
-/** Type of ch3_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ar_prot:3;
-        /** ch3_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_aw_prot:3;
-        /** ch3_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_arlen_en:1;
-        /** ch3_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_arlen:8;
-        /** ch3_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_awlen_en:1;
-        /** ch3_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_awlen:8;
-        /** ch3_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_stat_en:1;
-        /** ch3_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_stat_en:1;
-        /** ch3_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch3_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_last:1;
-        /** ch3_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch3_ctl1_reg_t;
-
-/** Type of ch3_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_multblk_type:2;
-        /** ch3_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch3_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch3_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch3_cfg0_reg_t;
-
-/** Type of ch3_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch3_tt_fc:3;
-        /** ch3_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_hs_sel_src:1;
-        /** ch3_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_hs_sel_dst:1;
-        /** ch3_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_hwhs_pol:1;
-        /** ch3_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_hwhs_pol:1;
-        /** ch3_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch3_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch3_ch_prior : R/W; bitpos: [19:17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_ch_prior:3;
-        /** ch3_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lock_ch:1;
-        /** ch3_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lock_ch_l:2;
-        /** ch3_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_osr_lmt:4;
-        /** ch3_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch3_cfg1_reg_t;
-
-/** Type of ch3_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lms:1;
-        uint32_t reserved_1:5;
-        /** ch3_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch3_llp0_reg_t;
-
-/** Type of ch3_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch3_llp1_reg_t;
-
-/** Type of ch3_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_src:1;
-        /** ch3_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_src_we:1;
-        /** ch3_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_src:1;
-        /** ch3_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_src_we:1;
-        /** ch3_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_src:1;
-        /** ch3_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch3_swhssrc0_reg_t;
-
-/** Type of ch3_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_dst:1;
-        /** ch3_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_dst_we:1;
-        /** ch3_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_dst:1;
-        /** ch3_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_dst_we:1;
-        /** ch3_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_dst:1;
-        /** ch3_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch3_swhsdst0_reg_t;
-
-/** Type of ch3_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch3_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch3_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch3_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch3_axi_id0_reg_t;
-
-/** Type of ch3_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_awqos:4;
-        /** ch3_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch3_axi_qos0_reg_t;
-
-/** Type of ch4_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_sar0_reg_t;
-
-/** Type of ch4_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_sar1_reg_t;
-
-/** Type of ch4_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_dar0_reg_t;
-
-/** Type of ch4_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_dar1_reg_t;
-
-/** Type of ch4_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch4_block_ts0_reg_t;
-
-/** Type of ch4_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sms:1;
-        uint32_t reserved_1:1;
-        /** ch4_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dms:1;
-        uint32_t reserved_3:1;
-        /** ch4_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch4_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch4_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch4_src_tr_width:3;
-        /** ch4_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch4_dst_tr_width:3;
-        /** ch4_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_msize:4;
-        /** ch4_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_msize:4;
-        /** ch4_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ar_cache:4;
-        /** ch4_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_aw_cache:4;
-        /** ch4_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch4_ctl0_reg_t;
-
-/** Type of ch4_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ar_prot:3;
-        /** ch4_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_aw_prot:3;
-        /** ch4_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_arlen_en:1;
-        /** ch4_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_arlen:8;
-        /** ch4_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_awlen_en:1;
-        /** ch4_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_awlen:8;
-        /** ch4_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_stat_en:1;
-        /** ch4_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_stat_en:1;
-        /** ch4_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch4_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_last:1;
-        /** ch4_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch4_ctl1_reg_t;
-
-/** Type of ch4_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_multblk_type:2;
-        /** ch4_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch4_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch4_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch4_cfg0_reg_t;
-
-/** Type of ch4_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch4_tt_fc:3;
-        /** ch4_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_hs_sel_src:1;
-        /** ch4_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_hs_sel_dst:1;
-        /** ch4_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_hwhs_pol:1;
-        /** ch4_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_hwhs_pol:1;
-        /** ch4_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch4_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch4_ch_prior : R/W; bitpos: [19:17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_prior:3;
-        /** ch4_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lock_ch:1;
-        /** ch4_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lock_ch_l:2;
-        /** ch4_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_osr_lmt:4;
-        /** ch4_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch4_cfg1_reg_t;
-
-/** Type of ch4_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lms:1;
-        uint32_t reserved_1:5;
-        /** ch4_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch4_llp0_reg_t;
-
-/** Type of ch4_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch4_llp1_reg_t;
-
-/** Type of ch4_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_src:1;
-        /** ch4_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_src_we:1;
-        /** ch4_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_src:1;
-        /** ch4_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_src_we:1;
-        /** ch4_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_src:1;
-        /** ch4_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch4_swhssrc0_reg_t;
-
-/** Type of ch4_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_dst:1;
-        /** ch4_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_dst_we:1;
-        /** ch4_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_dst:1;
-        /** ch4_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_dst_we:1;
-        /** ch4_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_dst:1;
-        /** ch4_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch4_swhsdst0_reg_t;
-
-/** Type of ch4_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch4_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch4_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch4_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch4_axi_id0_reg_t;
-
-/** Type of ch4_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_awqos:4;
-        /** ch4_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch4_axi_qos0_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_intstat:1;
-        /** ch2_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_intstat:1;
-        /** ch3_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_intstat:1;
-        /** ch4_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_intstat:1;
-        uint32_t reserved_4:12;
-        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t commonreg_intstat:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_intstatus0_reg_t;
-
-/** Type of commonreg_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_dec_err_intstat:1;
-        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wr2ro_err_intstat:1;
-        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_rd2wo_err_intstat:1;
-        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wrparity_err_intstat:1;
-        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_undefinedreg_dec_err_intstat:1;
-        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat:1;
-        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat:1;
-        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_bch_eccprot_correrr_intstat:1;
-        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat:1;
-        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat:1;
-        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_bch_eccprot_correrr_intstat:1;
-        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intclear0_reg_t;
-
-/** Type of commonreg_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_dec_err_intstat:1;
-        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wr2ro_err_intstat:1;
-        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_rd2wo_err_intstat:1;
-        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wrparity_err_intstat:1;
-        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_undefinedreg_dec_err_intstat:1;
-        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat:1;
-        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat:1;
-        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_correrr_intstat:1;
-        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat:1;
-        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat:1;
-        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_correrr_intstat:1;
-        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intstatus_enable0_reg_t;
-
-/** Type of commonreg_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_dec_err_intsignal:1;
-        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal:1;
-        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal:1;
-        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wronhold_err_intsignal:1;
-        uint32_t reserved_4:3;
-        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wrparity_err_intsignal:1;
-        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_undefinedreg_dec_err_intsignal:1;
-        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intsignal_enable0_reg_t;
-
-/** Type of commonreg_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_dec_err_intstat:1;
-        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wr2ro_err_intstat:1;
-        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_rd2wo_err_intstat:1;
-        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wrparity_err_intstat:1;
-        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_undefinedreg_dec_err_intstat:1;
-        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch0_eccprot_correrr_intstat:1;
-        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch1_eccprot_correrr_intstat:1;
-        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_bch_eccprot_correrr_intstat:1;
-        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch0_eccprot_correrr_intstat:1;
-        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch1_eccprot_correrr_intstat:1;
-        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_bch_eccprot_correrr_intstat:1;
-        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intstatus0_reg_t;
-
-/** Type of ch1_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_block_tfr_done_intstat:1;
-        /** ch1_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_transcomp_intstat:1;
-        /** ch1_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_transcomp_intstat:1;
-        /** ch1_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_dec_err_intstat:1;
-        /** ch1_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_dec_err_intstat:1;
-        /** ch1_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_slv_err_intstat:1;
-        /** ch1_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_slv_err_intstat:1;
-        /** ch1_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_dec_err_intstat:1;
-        /** ch1_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_dec_err_intstat:1;
-        /** ch1_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_slv_err_intstat:1;
-        /** ch1_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_slv_err_intstat:1;
-        /** ch1_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_dec_err_intstat:1;
-        /** ch1_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wr2ro_err_intstat:1;
-        /** ch1_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch1_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronchen_err_intstat:1;
-        /** ch1_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_lock_cleared_intstat:1;
-        /** ch1_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_src_suspended_intstat:1;
-        /** ch1_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_suspended_intstat:1;
-        /** ch1_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_disabled_intstat:1;
-        /** ch1_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus_enable0_reg_t;
-
-/** Type of ch1_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus_enable1_reg_t;
-
-/** Type of ch1_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_block_tfr_done_intstat:1;
-        /** ch1_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_transcomp_intstat:1;
-        /** ch1_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_transcomp_intstat:1;
-        /** ch1_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_dec_err_intstat:1;
-        /** ch1_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_dec_err_intstat:1;
-        /** ch1_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_slv_err_intstat:1;
-        /** ch1_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_slv_err_intstat:1;
-        /** ch1_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_rd_dec_err_intstat:1;
-        /** ch1_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_wr_dec_err_intstat:1;
-        /** ch1_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_rd_slv_err_intstat:1;
-        /** ch1_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_wr_slv_err_intstat:1;
-        /** ch1_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_dec_err_intstat:1;
-        /** ch1_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wr2ro_err_intstat:1;
-        /** ch1_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_rd2rwo_err_intstat:1;
-        /** ch1_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wronchen_err_intstat:1;
-        /** ch1_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_lock_cleared_intstat:1;
-        /** ch1_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_src_suspended_intstat:1;
-        /** ch1_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_suspended_intstat:1;
-        /** ch1_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_disabled_intstat:1;
-        /** ch1_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus0_reg_t;
-
-/** Type of ch1_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus1_reg_t;
-
-/** Type of ch1_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_block_tfr_done_intsignal:1;
-        /** ch1_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch1_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_transcomp_intsignal:1;
-        /** ch1_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_transcomp_intsignal:1;
-        /** ch1_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_dec_err_intsignal:1;
-        /** ch1_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_dec_err_intsignal:1;
-        /** ch1_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_slv_err_intsignal:1;
-        /** ch1_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_slv_err_intsignal:1;
-        /** ch1_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_dec_err_intsignal:1;
-        /** ch1_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_dec_err_intsignal:1;
-        /** ch1_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_slv_err_intsignal:1;
-        /** ch1_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_slv_err_intsignal:1;
-        /** ch1_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch1_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch1_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_dec_err_intsignal:1;
-        /** ch1_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch1_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch1_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronchen_err_intsignal:1;
-        /** ch1_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch1_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch1_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch1_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_lock_cleared_intsignal:1;
-        /** ch1_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_src_suspended_intsignal:1;
-        /** ch1_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_suspended_intsignal:1;
-        /** ch1_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_disabled_intsignal:1;
-        /** ch1_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch1_intsignal_enable0_reg_t;
-
-/** Type of ch1_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch1_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch1_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intsignal_enable1_reg_t;
-
-/** Type of ch1_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_block_tfr_done_intstat:1;
-        /** ch1_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_transcomp_intstat:1;
-        /** ch1_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_transcomp_intstat:1;
-        /** ch1_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_dec_err_intstat:1;
-        /** ch1_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_dec_err_intstat:1;
-        /** ch1_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_slv_err_intstat:1;
-        /** ch1_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_slv_err_intstat:1;
-        /** ch1_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_rd_dec_err_intstat:1;
-        /** ch1_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_wr_dec_err_intstat:1;
-        /** ch1_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_rd_slv_err_intstat:1;
-        /** ch1_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_wr_slv_err_intstat:1;
-        /** ch1_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_dec_err_intstat:1;
-        /** ch1_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wr2ro_err_intstat:1;
-        /** ch1_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch1_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wronchen_err_intstat:1;
-        /** ch1_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_lock_cleared_intstat:1;
-        /** ch1_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_src_suspended_intstat:1;
-        /** ch1_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_suspended_intstat:1;
-        /** ch1_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_disabled_intstat:1;
-        /** ch1_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intclear0_reg_t;
-
-/** Type of ch1_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intclear1_reg_t;
-
-/** Type of ch2_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_block_tfr_done_intstat:1;
-        /** ch2_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_transcomp_intstat:1;
-        /** ch2_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_transcomp_intstat:1;
-        /** ch2_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_dec_err_intstat:1;
-        /** ch2_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_dec_err_intstat:1;
-        /** ch2_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_slv_err_intstat:1;
-        /** ch2_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_slv_err_intstat:1;
-        /** ch2_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_dec_err_intstat:1;
-        /** ch2_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_dec_err_intstat:1;
-        /** ch2_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_slv_err_intstat:1;
-        /** ch2_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_slv_err_intstat:1;
-        /** ch2_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_dec_err_intstat:1;
-        /** ch2_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wr2ro_err_intstat:1;
-        /** ch2_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch2_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronchen_err_intstat:1;
-        /** ch2_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_lock_cleared_intstat:1;
-        /** ch2_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_src_suspended_intstat:1;
-        /** ch2_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_suspended_intstat:1;
-        /** ch2_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_disabled_intstat:1;
-        /** ch2_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus_enable0_reg_t;
-
-/** Type of ch2_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus_enable1_reg_t;
-
-/** Type of ch2_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_block_tfr_done_intstat:1;
-        /** ch2_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_transcomp_intstat:1;
-        /** ch2_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_transcomp_intstat:1;
-        /** ch2_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_dec_err_intstat:1;
-        /** ch2_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_dec_err_intstat:1;
-        /** ch2_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_slv_err_intstat:1;
-        /** ch2_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_slv_err_intstat:1;
-        /** ch2_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_rd_dec_err_intstat:1;
-        /** ch2_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_wr_dec_err_intstat:1;
-        /** ch2_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_rd_slv_err_intstat:1;
-        /** ch2_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_wr_slv_err_intstat:1;
-        /** ch2_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_dec_err_intstat:1;
-        /** ch2_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wr2ro_err_intstat:1;
-        /** ch2_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_rd2rwo_err_intstat:1;
-        /** ch2_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wronchen_err_intstat:1;
-        /** ch2_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_lock_cleared_intstat:1;
-        /** ch2_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_src_suspended_intstat:1;
-        /** ch2_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_suspended_intstat:1;
-        /** ch2_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_disabled_intstat:1;
-        /** ch2_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus0_reg_t;
-
-/** Type of ch2_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus1_reg_t;
-
-/** Type of ch2_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_block_tfr_done_intsignal:1;
-        /** ch2_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch2_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_transcomp_intsignal:1;
-        /** ch2_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_transcomp_intsignal:1;
-        /** ch2_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_dec_err_intsignal:1;
-        /** ch2_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_dec_err_intsignal:1;
-        /** ch2_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_slv_err_intsignal:1;
-        /** ch2_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_slv_err_intsignal:1;
-        /** ch2_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_dec_err_intsignal:1;
-        /** ch2_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_dec_err_intsignal:1;
-        /** ch2_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_slv_err_intsignal:1;
-        /** ch2_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_slv_err_intsignal:1;
-        /** ch2_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch2_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch2_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_dec_err_intsignal:1;
-        /** ch2_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch2_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch2_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronchen_err_intsignal:1;
-        /** ch2_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch2_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch2_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch2_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_lock_cleared_intsignal:1;
-        /** ch2_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_src_suspended_intsignal:1;
-        /** ch2_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_suspended_intsignal:1;
-        /** ch2_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_disabled_intsignal:1;
-        /** ch2_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch2_intsignal_enable0_reg_t;
-
-/** Type of ch2_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch2_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch2_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intsignal_enable1_reg_t;
-
-/** Type of ch2_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_block_tfr_done_intstat:1;
-        /** ch2_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_transcomp_intstat:1;
-        /** ch2_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_transcomp_intstat:1;
-        /** ch2_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_dec_err_intstat:1;
-        /** ch2_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_dec_err_intstat:1;
-        /** ch2_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_slv_err_intstat:1;
-        /** ch2_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_slv_err_intstat:1;
-        /** ch2_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_rd_dec_err_intstat:1;
-        /** ch2_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_wr_dec_err_intstat:1;
-        /** ch2_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_rd_slv_err_intstat:1;
-        /** ch2_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_wr_slv_err_intstat:1;
-        /** ch2_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_dec_err_intstat:1;
-        /** ch2_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wr2ro_err_intstat:1;
-        /** ch2_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch2_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wronchen_err_intstat:1;
-        /** ch2_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_lock_cleared_intstat:1;
-        /** ch2_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_src_suspended_intstat:1;
-        /** ch2_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_suspended_intstat:1;
-        /** ch2_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_disabled_intstat:1;
-        /** ch2_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intclear0_reg_t;
-
-/** Type of ch2_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intclear1_reg_t;
-
-/** Type of ch3_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_block_tfr_done_intstat:1;
-        /** ch3_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_transcomp_intstat:1;
-        /** ch3_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_transcomp_intstat:1;
-        /** ch3_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_dec_err_intstat:1;
-        /** ch3_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_dec_err_intstat:1;
-        /** ch3_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_slv_err_intstat:1;
-        /** ch3_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_slv_err_intstat:1;
-        /** ch3_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_dec_err_intstat:1;
-        /** ch3_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_dec_err_intstat:1;
-        /** ch3_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_slv_err_intstat:1;
-        /** ch3_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_slv_err_intstat:1;
-        /** ch3_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_dec_err_intstat:1;
-        /** ch3_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wr2ro_err_intstat:1;
-        /** ch3_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch3_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronchen_err_intstat:1;
-        /** ch3_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_lock_cleared_intstat:1;
-        /** ch3_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_src_suspended_intstat:1;
-        /** ch3_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_suspended_intstat:1;
-        /** ch3_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_disabled_intstat:1;
-        /** ch3_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus_enable0_reg_t;
-
-/** Type of ch3_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus_enable1_reg_t;
-
-/** Type of ch3_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_block_tfr_done_intstat:1;
-        /** ch3_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_transcomp_intstat:1;
-        /** ch3_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_transcomp_intstat:1;
-        /** ch3_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_dec_err_intstat:1;
-        /** ch3_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_dec_err_intstat:1;
-        /** ch3_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_slv_err_intstat:1;
-        /** ch3_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_slv_err_intstat:1;
-        /** ch3_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_rd_dec_err_intstat:1;
-        /** ch3_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_wr_dec_err_intstat:1;
-        /** ch3_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_rd_slv_err_intstat:1;
-        /** ch3_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_wr_slv_err_intstat:1;
-        /** ch3_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_dec_err_intstat:1;
-        /** ch3_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wr2ro_err_intstat:1;
-        /** ch3_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_rd2rwo_err_intstat:1;
-        /** ch3_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wronchen_err_intstat:1;
-        /** ch3_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_lock_cleared_intstat:1;
-        /** ch3_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_src_suspended_intstat:1;
-        /** ch3_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_suspended_intstat:1;
-        /** ch3_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_disabled_intstat:1;
-        /** ch3_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus0_reg_t;
-
-/** Type of ch3_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus1_reg_t;
-
-/** Type of ch3_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_block_tfr_done_intsignal:1;
-        /** ch3_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch3_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_transcomp_intsignal:1;
-        /** ch3_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_transcomp_intsignal:1;
-        /** ch3_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_dec_err_intsignal:1;
-        /** ch3_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_dec_err_intsignal:1;
-        /** ch3_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_slv_err_intsignal:1;
-        /** ch3_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_slv_err_intsignal:1;
-        /** ch3_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_dec_err_intsignal:1;
-        /** ch3_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_dec_err_intsignal:1;
-        /** ch3_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_slv_err_intsignal:1;
-        /** ch3_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_slv_err_intsignal:1;
-        /** ch3_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch3_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch3_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_dec_err_intsignal:1;
-        /** ch3_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch3_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch3_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronchen_err_intsignal:1;
-        /** ch3_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch3_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch3_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch3_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_lock_cleared_intsignal:1;
-        /** ch3_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_src_suspended_intsignal:1;
-        /** ch3_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_suspended_intsignal:1;
-        /** ch3_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_disabled_intsignal:1;
-        /** ch3_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch3_intsignal_enable0_reg_t;
-
-/** Type of ch3_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch3_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch3_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intsignal_enable1_reg_t;
-
-/** Type of ch3_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_block_tfr_done_intstat:1;
-        /** ch3_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_transcomp_intstat:1;
-        /** ch3_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_transcomp_intstat:1;
-        /** ch3_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_dec_err_intstat:1;
-        /** ch3_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_dec_err_intstat:1;
-        /** ch3_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_slv_err_intstat:1;
-        /** ch3_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_slv_err_intstat:1;
-        /** ch3_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_rd_dec_err_intstat:1;
-        /** ch3_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_wr_dec_err_intstat:1;
-        /** ch3_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_rd_slv_err_intstat:1;
-        /** ch3_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_wr_slv_err_intstat:1;
-        /** ch3_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_dec_err_intstat:1;
-        /** ch3_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wr2ro_err_intstat:1;
-        /** ch3_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch3_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wronchen_err_intstat:1;
-        /** ch3_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_lock_cleared_intstat:1;
-        /** ch3_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_src_suspended_intstat:1;
-        /** ch3_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_suspended_intstat:1;
-        /** ch3_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_disabled_intstat:1;
-        /** ch3_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intclear0_reg_t;
-
-/** Type of ch3_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intclear1_reg_t;
-
-/** Type of ch4_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_block_tfr_done_intstat:1;
-        /** ch4_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_transcomp_intstat:1;
-        /** ch4_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_transcomp_intstat:1;
-        /** ch4_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_dec_err_intstat:1;
-        /** ch4_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_dec_err_intstat:1;
-        /** ch4_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_slv_err_intstat:1;
-        /** ch4_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_slv_err_intstat:1;
-        /** ch4_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_dec_err_intstat:1;
-        /** ch4_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_dec_err_intstat:1;
-        /** ch4_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_slv_err_intstat:1;
-        /** ch4_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_slv_err_intstat:1;
-        /** ch4_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_dec_err_intstat:1;
-        /** ch4_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wr2ro_err_intstat:1;
-        /** ch4_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch4_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronchen_err_intstat:1;
-        /** ch4_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_lock_cleared_intstat:1;
-        /** ch4_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_src_suspended_intstat:1;
-        /** ch4_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_suspended_intstat:1;
-        /** ch4_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_disabled_intstat:1;
-        /** ch4_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus_enable0_reg_t;
-
-/** Type of ch4_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus_enable1_reg_t;
-
-/** Type of ch4_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_block_tfr_done_intstat:1;
-        /** ch4_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_transcomp_intstat:1;
-        /** ch4_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_transcomp_intstat:1;
-        /** ch4_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_dec_err_intstat:1;
-        /** ch4_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_dec_err_intstat:1;
-        /** ch4_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_slv_err_intstat:1;
-        /** ch4_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_slv_err_intstat:1;
-        /** ch4_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_rd_dec_err_intstat:1;
-        /** ch4_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_wr_dec_err_intstat:1;
-        /** ch4_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_rd_slv_err_intstat:1;
-        /** ch4_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_wr_slv_err_intstat:1;
-        /** ch4_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_dec_err_intstat:1;
-        /** ch4_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wr2ro_err_intstat:1;
-        /** ch4_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_rd2rwo_err_intstat:1;
-        /** ch4_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wronchen_err_intstat:1;
-        /** ch4_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_lock_cleared_intstat:1;
-        /** ch4_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_src_suspended_intstat:1;
-        /** ch4_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_suspended_intstat:1;
-        /** ch4_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_disabled_intstat:1;
-        /** ch4_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus0_reg_t;
-
-/** Type of ch4_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus1_reg_t;
-
-/** Type of ch4_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_block_tfr_done_intsignal:1;
-        /** ch4_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch4_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_transcomp_intsignal:1;
-        /** ch4_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_transcomp_intsignal:1;
-        /** ch4_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_dec_err_intsignal:1;
-        /** ch4_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_dec_err_intsignal:1;
-        /** ch4_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_slv_err_intsignal:1;
-        /** ch4_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_slv_err_intsignal:1;
-        /** ch4_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_dec_err_intsignal:1;
-        /** ch4_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_dec_err_intsignal:1;
-        /** ch4_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_slv_err_intsignal:1;
-        /** ch4_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_slv_err_intsignal:1;
-        /** ch4_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch4_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch4_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_dec_err_intsignal:1;
-        /** ch4_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch4_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch4_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronchen_err_intsignal:1;
-        /** ch4_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch4_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch4_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch4_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_lock_cleared_intsignal:1;
-        /** ch4_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_src_suspended_intsignal:1;
-        /** ch4_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_suspended_intsignal:1;
-        /** ch4_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_disabled_intsignal:1;
-        /** ch4_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch4_intsignal_enable0_reg_t;
-
-/** Type of ch4_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch4_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch4_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intsignal_enable1_reg_t;
-
-/** Type of ch4_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_block_tfr_done_intstat:1;
-        /** ch4_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_transcomp_intstat:1;
-        /** ch4_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_transcomp_intstat:1;
-        /** ch4_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_dec_err_intstat:1;
-        /** ch4_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_dec_err_intstat:1;
-        /** ch4_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_slv_err_intstat:1;
-        /** ch4_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_slv_err_intstat:1;
-        /** ch4_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_rd_dec_err_intstat:1;
-        /** ch4_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_wr_dec_err_intstat:1;
-        /** ch4_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_rd_slv_err_intstat:1;
-        /** ch4_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_wr_slv_err_intstat:1;
-        /** ch4_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_dec_err_intstat:1;
-        /** ch4_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wr2ro_err_intstat:1;
-        /** ch4_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch4_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wronchen_err_intstat:1;
-        /** ch4_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_lock_cleared_intstat:1;
-        /** ch4_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_src_suspended_intstat:1;
-        /** ch4_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_suspended_intstat:1;
-        /** ch4_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_disabled_intstat:1;
-        /** ch4_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intclear0_reg_t;
-
-/** Type of ch4_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intclear1_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of ch1_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch1_status0_reg_t;
-
-/** Type of ch1_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch1_status1_reg_t;
-
-/** Type of ch1_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstat0_reg_t;
-
-/** Type of ch1_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstat0_reg_t;
-
-/** Type of ch1_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstatar0_reg_t;
-
-/** Type of ch1_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstatar1_reg_t;
-
-/** Type of ch1_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstatar0_reg_t;
-
-/** Type of ch1_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstatar1_reg_t;
-
-/** Type of ch2_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch2_status0_reg_t;
-
-/** Type of ch2_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch2_status1_reg_t;
-
-/** Type of ch2_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstat0_reg_t;
-
-/** Type of ch2_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstat0_reg_t;
-
-/** Type of ch2_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstatar0_reg_t;
-
-/** Type of ch2_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstatar1_reg_t;
-
-/** Type of ch2_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstatar0_reg_t;
-
-/** Type of ch2_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstatar1_reg_t;
-
-/** Type of ch3_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch3_status0_reg_t;
-
-/** Type of ch3_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch3_status1_reg_t;
-
-/** Type of ch3_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstat0_reg_t;
-
-/** Type of ch3_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstat0_reg_t;
-
-/** Type of ch3_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstatar0_reg_t;
-
-/** Type of ch3_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstatar1_reg_t;
-
-/** Type of ch3_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstatar0_reg_t;
-
-/** Type of ch3_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstatar1_reg_t;
-
-/** Type of ch4_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch4_status0_reg_t;
-
-/** Type of ch4_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch4_status1_reg_t;
-
-/** Type of ch4_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstat0_reg_t;
-
-/** Type of ch4_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstat0_reg_t;
-
-/** Type of ch4_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstatar0_reg_t;
-
-/** Type of ch4_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstatar1_reg_t;
-
-/** Type of ch4_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstatar0_reg_t;
-
-/** Type of ch4_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstatar1_reg_t;
-
-
-typedef struct {
-    volatile dmac_id0_reg_t id0;
-    uint32_t reserved_004;
-    volatile dmac_compver0_reg_t compver0;
-    uint32_t reserved_00c;
-    volatile dmac_cfg0_reg_t cfg0;
-    uint32_t reserved_014;
-    volatile dmac_chen0_reg_t chen0;
-    volatile dmac_chen1_reg_t chen1;
-    uint32_t reserved_020[4];
-    volatile dmac_intstatus0_reg_t intstatus0;
-    uint32_t reserved_034;
-    volatile dmac_commonreg_intclear0_reg_t commonreg_intclear0;
-    uint32_t reserved_03c;
-    volatile dmac_commonreg_intstatus_enable0_reg_t commonreg_intstatus_enable0;
-    uint32_t reserved_044;
-    volatile dmac_commonreg_intsignal_enable0_reg_t commonreg_intsignal_enable0;
-    uint32_t reserved_04c;
-    volatile dmac_commonreg_intstatus0_reg_t commonreg_intstatus0;
-    uint32_t reserved_054;
-    volatile dmac_reset0_reg_t reset0;
-    uint32_t reserved_05c;
-    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
-    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
-    uint32_t reserved_068[38];
-    volatile dmac_ch1_sar0_reg_t ch1_sar0;
-    volatile dmac_ch1_sar1_reg_t ch1_sar1;
-    volatile dmac_ch1_dar0_reg_t ch1_dar0;
-    volatile dmac_ch1_dar1_reg_t ch1_dar1;
-    volatile dmac_ch1_block_ts0_reg_t ch1_block_ts0;
-    uint32_t reserved_114;
-    volatile dmac_ch1_ctl0_reg_t ch1_ctl0;
-    volatile dmac_ch1_ctl1_reg_t ch1_ctl1;
-    volatile dmac_ch1_cfg0_reg_t ch1_cfg0;
-    volatile dmac_ch1_cfg1_reg_t ch1_cfg1;
-    volatile dmac_ch1_llp0_reg_t ch1_llp0;
-    volatile dmac_ch1_llp1_reg_t ch1_llp1;
-    volatile dmac_ch1_status0_reg_t ch1_status0;
-    volatile dmac_ch1_status1_reg_t ch1_status1;
-    volatile dmac_ch1_swhssrc0_reg_t ch1_swhssrc0;
-    uint32_t reserved_13c;
-    volatile dmac_ch1_swhsdst0_reg_t ch1_swhsdst0;
-    uint32_t reserved_144;
-    volatile dmac_ch1_blk_tfr_resumereq0_reg_t ch1_blk_tfr_resumereq0;
-    uint32_t reserved_14c;
-    volatile dmac_ch1_axi_id0_reg_t ch1_axi_id0;
-    uint32_t reserved_154;
-    volatile dmac_ch1_axi_qos0_reg_t ch1_axi_qos0;
-    uint32_t reserved_15c;
-    volatile dmac_ch1_sstat0_reg_t ch1_sstat0;
-    uint32_t reserved_164;
-    volatile dmac_ch1_dstat0_reg_t ch1_dstat0;
-    uint32_t reserved_16c;
-    volatile dmac_ch1_sstatar0_reg_t ch1_sstatar0;
-    volatile dmac_ch1_sstatar1_reg_t ch1_sstatar1;
-    volatile dmac_ch1_dstatar0_reg_t ch1_dstatar0;
-    volatile dmac_ch1_dstatar1_reg_t ch1_dstatar1;
-    volatile dmac_ch1_intstatus_enable0_reg_t ch1_intstatus_enable0;
-    volatile dmac_ch1_intstatus_enable1_reg_t ch1_intstatus_enable1;
-    volatile dmac_ch1_intstatus0_reg_t ch1_intstatus0;
-    volatile dmac_ch1_intstatus1_reg_t ch1_intstatus1;
-    volatile dmac_ch1_intsignal_enable0_reg_t ch1_intsignal_enable0;
-    volatile dmac_ch1_intsignal_enable1_reg_t ch1_intsignal_enable1;
-    volatile dmac_ch1_intclear0_reg_t ch1_intclear0;
-    volatile dmac_ch1_intclear1_reg_t ch1_intclear1;
-    uint32_t reserved_1a0[24];
-    volatile dmac_ch2_sar0_reg_t ch2_sar0;
-    volatile dmac_ch2_sar1_reg_t ch2_sar1;
-    volatile dmac_ch2_dar0_reg_t ch2_dar0;
-    volatile dmac_ch2_dar1_reg_t ch2_dar1;
-    volatile dmac_ch2_block_ts0_reg_t ch2_block_ts0;
-    uint32_t reserved_214;
-    volatile dmac_ch2_ctl0_reg_t ch2_ctl0;
-    volatile dmac_ch2_ctl1_reg_t ch2_ctl1;
-    volatile dmac_ch2_cfg0_reg_t ch2_cfg0;
-    volatile dmac_ch2_cfg1_reg_t ch2_cfg1;
-    volatile dmac_ch2_llp0_reg_t ch2_llp0;
-    volatile dmac_ch2_llp1_reg_t ch2_llp1;
-    volatile dmac_ch2_status0_reg_t ch2_status0;
-    volatile dmac_ch2_status1_reg_t ch2_status1;
-    volatile dmac_ch2_swhssrc0_reg_t ch2_swhssrc0;
-    uint32_t reserved_23c;
-    volatile dmac_ch2_swhsdst0_reg_t ch2_swhsdst0;
-    uint32_t reserved_244;
-    volatile dmac_ch2_blk_tfr_resumereq0_reg_t ch2_blk_tfr_resumereq0;
-    uint32_t reserved_24c;
-    volatile dmac_ch2_axi_id0_reg_t ch2_axi_id0;
-    uint32_t reserved_254;
-    volatile dmac_ch2_axi_qos0_reg_t ch2_axi_qos0;
-    uint32_t reserved_25c;
-    volatile dmac_ch2_sstat0_reg_t ch2_sstat0;
-    uint32_t reserved_264;
-    volatile dmac_ch2_dstat0_reg_t ch2_dstat0;
-    uint32_t reserved_26c;
-    volatile dmac_ch2_sstatar0_reg_t ch2_sstatar0;
-    volatile dmac_ch2_sstatar1_reg_t ch2_sstatar1;
-    volatile dmac_ch2_dstatar0_reg_t ch2_dstatar0;
-    volatile dmac_ch2_dstatar1_reg_t ch2_dstatar1;
-    volatile dmac_ch2_intstatus_enable0_reg_t ch2_intstatus_enable0;
-    volatile dmac_ch2_intstatus_enable1_reg_t ch2_intstatus_enable1;
-    volatile dmac_ch2_intstatus0_reg_t ch2_intstatus0;
-    volatile dmac_ch2_intstatus1_reg_t ch2_intstatus1;
-    volatile dmac_ch2_intsignal_enable0_reg_t ch2_intsignal_enable0;
-    volatile dmac_ch2_intsignal_enable1_reg_t ch2_intsignal_enable1;
-    volatile dmac_ch2_intclear0_reg_t ch2_intclear0;
-    volatile dmac_ch2_intclear1_reg_t ch2_intclear1;
-    uint32_t reserved_2a0[24];
-    volatile dmac_ch3_sar0_reg_t ch3_sar0;
-    volatile dmac_ch3_sar1_reg_t ch3_sar1;
-    volatile dmac_ch3_dar0_reg_t ch3_dar0;
-    volatile dmac_ch3_dar1_reg_t ch3_dar1;
-    volatile dmac_ch3_block_ts0_reg_t ch3_block_ts0;
-    uint32_t reserved_314;
-    volatile dmac_ch3_ctl0_reg_t ch3_ctl0;
-    volatile dmac_ch3_ctl1_reg_t ch3_ctl1;
-    volatile dmac_ch3_cfg0_reg_t ch3_cfg0;
-    volatile dmac_ch3_cfg1_reg_t ch3_cfg1;
-    volatile dmac_ch3_llp0_reg_t ch3_llp0;
-    volatile dmac_ch3_llp1_reg_t ch3_llp1;
-    volatile dmac_ch3_status0_reg_t ch3_status0;
-    volatile dmac_ch3_status1_reg_t ch3_status1;
-    volatile dmac_ch3_swhssrc0_reg_t ch3_swhssrc0;
-    uint32_t reserved_33c;
-    volatile dmac_ch3_swhsdst0_reg_t ch3_swhsdst0;
-    uint32_t reserved_344;
-    volatile dmac_ch3_blk_tfr_resumereq0_reg_t ch3_blk_tfr_resumereq0;
-    uint32_t reserved_34c;
-    volatile dmac_ch3_axi_id0_reg_t ch3_axi_id0;
-    uint32_t reserved_354;
-    volatile dmac_ch3_axi_qos0_reg_t ch3_axi_qos0;
-    uint32_t reserved_35c;
-    volatile dmac_ch3_sstat0_reg_t ch3_sstat0;
-    uint32_t reserved_364;
-    volatile dmac_ch3_dstat0_reg_t ch3_dstat0;
-    uint32_t reserved_36c;
-    volatile dmac_ch3_sstatar0_reg_t ch3_sstatar0;
-    volatile dmac_ch3_sstatar1_reg_t ch3_sstatar1;
-    volatile dmac_ch3_dstatar0_reg_t ch3_dstatar0;
-    volatile dmac_ch3_dstatar1_reg_t ch3_dstatar1;
-    volatile dmac_ch3_intstatus_enable0_reg_t ch3_intstatus_enable0;
-    volatile dmac_ch3_intstatus_enable1_reg_t ch3_intstatus_enable1;
-    volatile dmac_ch3_intstatus0_reg_t ch3_intstatus0;
-    volatile dmac_ch3_intstatus1_reg_t ch3_intstatus1;
-    volatile dmac_ch3_intsignal_enable0_reg_t ch3_intsignal_enable0;
-    volatile dmac_ch3_intsignal_enable1_reg_t ch3_intsignal_enable1;
-    volatile dmac_ch3_intclear0_reg_t ch3_intclear0;
-    volatile dmac_ch3_intclear1_reg_t ch3_intclear1;
-    uint32_t reserved_3a0[24];
-    volatile dmac_ch4_sar0_reg_t ch4_sar0;
-    volatile dmac_ch4_sar1_reg_t ch4_sar1;
-    volatile dmac_ch4_dar0_reg_t ch4_dar0;
-    volatile dmac_ch4_dar1_reg_t ch4_dar1;
-    volatile dmac_ch4_block_ts0_reg_t ch4_block_ts0;
-    uint32_t reserved_414;
-    volatile dmac_ch4_ctl0_reg_t ch4_ctl0;
-    volatile dmac_ch4_ctl1_reg_t ch4_ctl1;
-    volatile dmac_ch4_cfg0_reg_t ch4_cfg0;
-    volatile dmac_ch4_cfg1_reg_t ch4_cfg1;
-    volatile dmac_ch4_llp0_reg_t ch4_llp0;
-    volatile dmac_ch4_llp1_reg_t ch4_llp1;
-    volatile dmac_ch4_status0_reg_t ch4_status0;
-    volatile dmac_ch4_status1_reg_t ch4_status1;
-    volatile dmac_ch4_swhssrc0_reg_t ch4_swhssrc0;
-    uint32_t reserved_43c;
-    volatile dmac_ch4_swhsdst0_reg_t ch4_swhsdst0;
-    uint32_t reserved_444;
-    volatile dmac_ch4_blk_tfr_resumereq0_reg_t ch4_blk_tfr_resumereq0;
-    uint32_t reserved_44c;
-    volatile dmac_ch4_axi_id0_reg_t ch4_axi_id0;
-    uint32_t reserved_454;
-    volatile dmac_ch4_axi_qos0_reg_t ch4_axi_qos0;
-    uint32_t reserved_45c;
-    volatile dmac_ch4_sstat0_reg_t ch4_sstat0;
-    uint32_t reserved_464;
-    volatile dmac_ch4_dstat0_reg_t ch4_dstat0;
-    uint32_t reserved_46c;
-    volatile dmac_ch4_sstatar0_reg_t ch4_sstatar0;
-    volatile dmac_ch4_sstatar1_reg_t ch4_sstatar1;
-    volatile dmac_ch4_dstatar0_reg_t ch4_dstatar0;
-    volatile dmac_ch4_dstatar1_reg_t ch4_dstatar1;
-    volatile dmac_ch4_intstatus_enable0_reg_t ch4_intstatus_enable0;
-    volatile dmac_ch4_intstatus_enable1_reg_t ch4_intstatus_enable1;
-    volatile dmac_ch4_intstatus0_reg_t ch4_intstatus0;
-    volatile dmac_ch4_intstatus1_reg_t ch4_intstatus1;
-    volatile dmac_ch4_intsignal_enable0_reg_t ch4_intsignal_enable0;
-    volatile dmac_ch4_intsignal_enable1_reg_t ch4_intsignal_enable1;
-    volatile dmac_ch4_intclear0_reg_t ch4_intclear0;
-    volatile dmac_ch4_intclear1_reg_t ch4_intclear1;
-} dmac_dev_t;
-
-extern dmac_dev_t GDMA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(dmac_dev_t) == 0x4a0, "Invalid size of dmac_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h
deleted file mode 100644
index f2f78f4ec9..0000000000
--- a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h
+++ /dev/null
@@ -1,868 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of clk_en register
- *  dsi bridge clk control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  this bit configures force_on of dsi_bridge register clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_brg_clk_en_reg_t;
-
-/** Type of en register
- *  dsi bridge en register
- */
-typedef union {
-    struct {
-        /** dsi_en : R/W; bitpos: [0]; default: 0;
-         *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
-         */
-        uint32_t dsi_en:1;
-        /** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
-         *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
-         */
-        uint32_t dsi_brig_rst:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_en_reg_t;
-
-/** Type of dma_req_cfg register
- *  dsi bridge dma burst len register
- */
-typedef union {
-    struct {
-        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
-         *  this field configures the num of 64-bit in one dma burst transfer, valid only when
-         *  dsi_bridge as flow controller
-         */
-        uint32_t dma_burst_len:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dsi_brg_dma_req_cfg_reg_t;
-
-/** Type of raw_num_cfg register
- *  dsi bridge raw number control register
- */
-typedef union {
-    struct {
-        /** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
-         *  this field configures number of total pix bits/64
-         */
-        uint32_t raw_num_total:22;
-        /** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
-         *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
-         *  to 64-bit, 1: unalign to 64-bit
-         */
-        uint32_t unalign_64bit_en:1;
-        uint32_t reserved_23:8;
-        /** raw_num_total_set : WT; bitpos: [31]; default: 0;
-         *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
-         *  1: enable. valid only when dsi_bridge as flow controller
-         */
-        uint32_t raw_num_total_set:1;
-    };
-    uint32_t val;
-} dsi_brg_raw_num_cfg_reg_t;
-
-/** Type of raw_buf_credit_ctl register
- *  dsi bridge credit register
- */
-typedef union {
-    struct {
-        /** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
-         *  this field configures the threshold whether dsi_bridge fifo can receive one more
-         *  64-bit, valid only when dsi_bridge as flow controller
-         */
-        uint32_t credit_thrd:15;
-        uint32_t reserved_15:1;
-        /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
-         *  this field configures the threshold whether dsi_bridge fifo can receive one more
-         *  dma burst, valid only when dsi_bridge as flow controller
-         */
-        uint32_t credit_burst_thrd:15;
-        /** credit_reset : R/W; bitpos: [31]; default: 0;
-         *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
-         *  dsi_bridge as flow controller
-         */
-        uint32_t credit_reset:1;
-    };
-    uint32_t val;
-} dsi_brg_raw_buf_credit_ctl_reg_t;
-
-/** Type of pixel_type register
- *  dsi bridge dpi type control register
- */
-typedef union {
-    struct {
-        /** raw_type : R/W; bitpos: [3:0]; default: 0;
-         *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
-         *  9:yuv422, 10:yuv420, 12:gray
-         */
-        uint32_t raw_type:4;
-        /** dpi_config : R/W; bitpos: [5:4]; default: 0;
-         *  this field configures the pixel arrange type of dpi interface
-         */
-        uint32_t dpi_config:2;
-        /** data_in_type : R/W; bitpos: [6]; default: 0;
-         *  input data type, 0: not yuv, 1: yuv
-         */
-        uint32_t data_in_type:1;
-        /** dpi_type : R/W; bitpos: [10:7]; default: 0;
-         *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
-         */
-        uint32_t dpi_type:4;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} dsi_brg_pixel_type_reg_t;
-
-/** Type of dma_block_interval register
- *  dsi bridge dma block interval control register
- */
-typedef union {
-    struct {
-        /** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
-         *  this field configures the max block_slot_cnt
-         */
-        uint32_t dma_block_slot:10;
-        /** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
-         *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
-         *  when block_slot_cnt if full
-         */
-        uint32_t dma_block_interval:18;
-        /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
-         *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
-         */
-        uint32_t raw_num_total_auto_reload:1;
-        /** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
-         *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
-         *  enable
-         */
-        uint32_t dma_block_interval_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} dsi_brg_dma_block_interval_reg_t;
-
-/** Type of dma_req_interval register
- *  dsi bridge dma req interval control register
- */
-typedef union {
-    struct {
-        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
-         *  this field configures the interval between dma req events
-         */
-        uint32_t dma_req_interval:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_brg_dma_req_interval_reg_t;
-
-/** Type of dpi_lcd_ctl register
- *  dsi bridge dpi signal control register
- */
-typedef union {
-    struct {
-        /** dpishutdn : R/W; bitpos: [0]; default: 0;
-         *  this bit configures dpishutdn signal in dpi interface
-         */
-        uint32_t dpishutdn:1;
-        /** dpicolorm : R/W; bitpos: [1]; default: 0;
-         *  this bit configures dpicolorm signal in dpi interface
-         */
-        uint32_t dpicolorm:1;
-        /** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
-         *  this bit configures dpiupdatecfg signal in dpi interface
-         */
-        uint32_t dpiupdatecfg:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} dsi_brg_dpi_lcd_ctl_reg_t;
-
-/** Type of dpi_rsv_dpi_data register
- *  dsi bridge dpi reserved data register
- */
-typedef union {
-    struct {
-        /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
-         *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
-         */
-        uint32_t dpi_rsv_data:30;
-        /** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
-         *  Configures data debug feature enable. 0: disable, 1: enable
-         */
-        uint32_t dpi_dbg_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dsi_brg_dpi_rsv_dpi_data_reg_t;
-
-/** Type of dpi_v_cfg0 register
- *  dsi bridge dpi v config register 0
- */
-typedef union {
-    struct {
-        /** vtotal : R/W; bitpos: [11:0]; default: 525;
-         *  this field configures the total length of one frame (by line) for dpi output, must
-         *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
-         */
-        uint32_t vtotal:12;
-        uint32_t reserved_12:4;
-        /** vdisp : R/W; bitpos: [27:16]; default: 480;
-         *  this field configures the length of valid line (by line) for dpi output
-         */
-        uint32_t vdisp:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dsi_brg_dpi_v_cfg0_reg_t;
-
-/** Type of dpi_v_cfg1 register
- *  dsi bridge dpi v config register 1
- */
-typedef union {
-    struct {
-        /** vbank : R/W; bitpos: [11:0]; default: 33;
-         *  this field configures the length between vsync and valid line (by line) for dpi
-         *  output
-         */
-        uint32_t vbank:12;
-        uint32_t reserved_12:4;
-        /** vsync : R/W; bitpos: [27:16]; default: 2;
-         *  this field configures the length of vsync (by line) for dpi output
-         */
-        uint32_t vsync:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dsi_brg_dpi_v_cfg1_reg_t;
-
-/** Type of dpi_h_cfg0 register
- *  dsi bridge dpi h config register 0
- */
-typedef union {
-    struct {
-        /** htotal : R/W; bitpos: [11:0]; default: 800;
-         *  this field configures the total length of one line (by pixel num) for dpi output,
-         *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
-         */
-        uint32_t htotal:12;
-        uint32_t reserved_12:4;
-        /** hdisp : R/W; bitpos: [27:16]; default: 640;
-         *  this field configures the length of valid pixel data (by pixel num) for dpi output
-         */
-        uint32_t hdisp:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dsi_brg_dpi_h_cfg0_reg_t;
-
-/** Type of dpi_h_cfg1 register
- *  dsi bridge dpi h config register 1
- */
-typedef union {
-    struct {
-        /** hbank : R/W; bitpos: [11:0]; default: 48;
-         *  this field configures the length between hsync and pixel data valid (by pixel num)
-         *  for dpi output
-         */
-        uint32_t hbank:12;
-        uint32_t reserved_12:4;
-        /** hsync : R/W; bitpos: [27:16]; default: 96;
-         *  this field configures the length of hsync (by pixel num) for dpi output
-         */
-        uint32_t hsync:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dsi_brg_dpi_h_cfg1_reg_t;
-
-/** Type of dpi_misc_config register
- *  dsi_bridge dpi misc config register
- */
-typedef union {
-    struct {
-        /** dpi_en : R/W; bitpos: [0]; default: 0;
-         *  this bit configures enable of dpi output, 0: disable, 1: enable
-         */
-        uint32_t dpi_en:1;
-        uint32_t reserved_1:3;
-        /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
-         *  this field configures the underrun interrupt musk, when underrun occurs and line
-         *  cnt is less then this field
-         */
-        uint32_t fifo_underrun_discard_vcnt:12;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_brg_dpi_misc_config_reg_t;
-
-/** Type of dpi_config_update register
- *  dsi_bridge dpi config update register
- */
-typedef union {
-    struct {
-        /** dpi_config_update : WT; bitpos: [0]; default: 0;
-         *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
-         */
-        uint32_t dpi_config_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_brg_dpi_config_update_reg_t;
-
-/** Type of host_trigger_rev register
- *  dsi_bridge host trigger reverse control register
- */
-typedef union {
-    struct {
-        /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
-         *  tx_trigger reverse. 0: disable, 1: enable
-         */
-        uint32_t tx_trigger_rev_en:1;
-        /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
-         *  rx_trigger reverse. 0: disable, 1: enable
-         */
-        uint32_t rx_trigger_rev_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_host_trigger_rev_reg_t;
-
-/** Type of blk_raw_num_cfg register
- *  dsi_bridge block raw number control register
- */
-typedef union {
-    struct {
-        /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
-         *  this field configures number of total block pix bits/64
-         */
-        uint32_t blk_raw_num_total:22;
-        uint32_t reserved_22:9;
-        /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
-         *  write 1 to reload reg_blk_raw_num_total to internal cnt
-         */
-        uint32_t blk_raw_num_total_set:1;
-    };
-    uint32_t val;
-} dsi_brg_blk_raw_num_cfg_reg_t;
-
-/** Type of dma_frame_interval register
- *  dsi_bridge dam frame interval control register
- */
-typedef union {
-    struct {
-        /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
-         *  this field configures the max frame_slot_cnt
-         */
-        uint32_t dma_frame_slot:10;
-        /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
-         *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
-         *  when frame_slot_cnt if full
-         */
-        uint32_t dma_frame_interval:18;
-        /** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
-         *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
-         */
-        uint32_t dma_multiblk_en:1;
-        /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
-         *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
-         */
-        uint32_t dma_frame_interval_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} dsi_brg_dma_frame_interval_reg_t;
-
-/** Type of mem_aux_ctrl register
- *  dsi_bridge mem aux control register
- */
-typedef union {
-    struct {
-        /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
-         *  this field configures dsi_bridge fifo memory aux ctrl
-         */
-        uint32_t dsi_mem_aux_ctrl:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_brg_mem_aux_ctrl_reg_t;
-
-/** Type of rdn_eco_low register
- *  dsi_bridge rdn eco all low register
- */
-typedef union {
-    struct {
-        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  rdn_eco_low
-         */
-        uint32_t rdn_eco_low:32;
-    };
-    uint32_t val;
-} dsi_brg_rdn_eco_low_reg_t;
-
-/** Type of rdn_eco_high register
- *  dsi_bridge rdn eco all high register
- */
-typedef union {
-    struct {
-        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  rdn_eco_high
-         */
-        uint32_t rdn_eco_high:32;
-    };
-    uint32_t val;
-} dsi_brg_rdn_eco_high_reg_t;
-
-/** Type of host_ctrl register
- *  dsi_bridge host control register
- */
-typedef union {
-    struct {
-        /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
-         *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
-         *  enable
-         */
-        uint32_t dsi_cfg_ref_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_brg_host_ctrl_reg_t;
-
-/** Type of mem_clk_ctrl register
- *  dsi_bridge mem force on control register
- */
-typedef union {
-    struct {
-        /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
-         *  force on
-         */
-        uint32_t dsi_bridge_mem_clk_force_on:1;
-        /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
-         */
-        uint32_t dsi_mem_clk_force_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_mem_clk_ctrl_reg_t;
-
-/** Type of dma_flow_ctrl register
- *  dsi_bridge dma flow controller register
- */
-typedef union {
-    struct {
-        /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
-         *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
-         *  as flow controller
-         */
-        uint32_t dsi_dma_flow_controller:1;
-        uint32_t reserved_1:3;
-        /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
-         *  this field configures the num of blocks when multi-blk is enable and dmac as flow
-         *  controller
-         */
-        uint32_t dma_flow_multiblk_num:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dsi_brg_dma_flow_ctrl_reg_t;
-
-/** Type of raw_buf_almost_empty_thrd register
- *  dsi_bridge buffer empty threshold register
- */
-typedef union {
-    struct {
-        /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
-         *  this field configures the fifo almost empty threshold, is valid only when dmac as
-         *  flow controller
-         */
-        uint32_t dsi_raw_buf_almost_empty_thrd:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
-
-/** Type of yuv_cfg register
- *  dsi_bridge yuv format config register
- */
-typedef union {
-    struct {
-        /** protocol : R/W; bitpos: [0]; default: 0;
-         *  this bit configures yuv protoocl, 0: bt.601, 1: bt.709
-         */
-        uint32_t protocol:1;
-        /** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
-         *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
-         */
-        uint32_t yuv_pix_endian:1;
-        /** yuv422_format : R/W; bitpos: [3:2]; default: 0;
-         *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
-         */
-        uint32_t yuv422_format:2;
-        /** yuv_range : R/W; bitpos: [4]; default: 0;
-         *  Configures yuv pixel range, 0: limit range, 1: full range
-         */
-        uint32_t yuv_range:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} dsi_brg_yuv_cfg_reg_t;
-
-/** Type of phy_lp_loopback_ctrl register
- *  dsi phy lp_loopback test ctrl
- */
-typedef union {
-    struct {
-        /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
-         *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txdataesc_1:8;
-        /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
-         *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txrequestesc_1:1;
-        /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
-         *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txvalidesc_1:1;
-        /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
-         *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txlpdtesc_1:1;
-        /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
-         *  basedir_1 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_basedir_1:1;
-        uint32_t reserved_12:4;
-        /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
-         *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txdataesc_0:8;
-        /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
-         *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txrequestesc_0:1;
-        /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
-         *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txvalidesc_0:1;
-        /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
-         *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_txlpdtesc_0:1;
-        /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
-         *  basedir_0 ctrl when enable dsi phy lp_loopback_test
-         */
-        uint32_t phy_lp_basedir_0:1;
-        /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
-         *  dsi phy lp_loopback test start check
-         */
-        uint32_t phy_lp_loopback_check:1;
-        /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
-         *  dsi phy lp_loopback test check done
-         */
-        uint32_t phy_lp_loopback_check_done:1;
-        /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
-         *  dsi phy lp_loopback ctrl en
-         */
-        uint32_t phy_lp_loopback_en:1;
-        /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
-         *  result of dsi phy lp_loopback test
-         */
-        uint32_t phy_lp_loopback_ok:1;
-    };
-    uint32_t val;
-} dsi_brg_phy_lp_loopback_ctrl_reg_t;
-
-/** Type of phy_hs_loopback_ctrl register
- *  dsi phy hp_loopback test ctrl
- */
-typedef union {
-    struct {
-        /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
-         *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_txdatahs_1:8;
-        /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
-         *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_txrequestdatahs_1:1;
-        /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
-         *  basedir_1 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_basedir_1:1;
-        uint32_t reserved_10:6;
-        /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
-         *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_txdatahs_0:8;
-        /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
-         *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_txrequestdatahs_0:1;
-        /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
-         *  basedir_0 ctrl when enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_basedir_0:1;
-        uint32_t reserved_26:1;
-        /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
-         *  txrequesthsclk when  enable dsi phy hs_loopback_test
-         */
-        uint32_t phy_hs_txrequesthsclk:1;
-        /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
-         *  dsi phy hs_loopback test start check
-         */
-        uint32_t phy_hs_loopback_check:1;
-        /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
-         *  dsi phy hs_loopback test check done
-         */
-        uint32_t phy_hs_loopback_check_done:1;
-        /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
-         *  dsi phy hs_loopback ctrl en
-         */
-        uint32_t phy_hs_loopback_en:1;
-        /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
-         *  result of dsi phy hs_loopback test
-         */
-        uint32_t phy_hs_loopback_ok:1;
-    };
-    uint32_t val;
-} dsi_brg_phy_hs_loopback_ctrl_reg_t;
-
-/** Type of phy_loopback_cnt register
- *  loopback test cnt
- */
-typedef union {
-    struct {
-        /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
-         *  hs_loopback test check cnt
-         */
-        uint32_t phy_hs_check_cnt_th:8;
-        uint32_t reserved_8:8;
-        /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
-         *  lp_loopback test check cnt
-         */
-        uint32_t phy_lp_check_cnt_th:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dsi_brg_phy_loopback_cnt_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of fifo_flow_status register
- *  dsi bridge raw buffer depth register
- */
-typedef union {
-    struct {
-        /** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
-         *  this field configures the depth of dsi_bridge fifo depth
-         */
-        uint32_t raw_buf_depth:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_brg_fifo_flow_status_reg_t;
-
-/** Type of host_bist_ctl register
- *  dsi_bridge host bist control register
- */
-typedef union {
-    struct {
-        /** bistok : RO; bitpos: [0]; default: 0;
-         *  bistok
-         */
-        uint32_t bistok:1;
-        /** biston : R/W; bitpos: [1]; default: 0;
-         *  biston
-         */
-        uint32_t biston:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_host_bist_ctl_reg_t;
-
-/** Type of rdn_eco_cs register
- *  dsi_bridge rdn eco cs register
- */
-typedef union {
-    struct {
-        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  rdn_eco_en
-         */
-        uint32_t rdn_eco_en:1;
-        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  rdn_eco_result
-         */
-        uint32_t rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_rdn_eco_cs_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_ena register
- *  dsi_bridge interrupt enable register
- */
-typedef union {
-    struct {
-        /** underrun_int_ena : R/W; bitpos: [0]; default: 0;
-         *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
-         *  by dpi_underrun  interrupt signal
-         */
-        uint32_t underrun_int_ena:1;
-        /** vsync_int_ena : R/W; bitpos: [1]; default: 0;
-         *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
-         *  dpi_vsync  interrupt signal
-         */
-        uint32_t vsync_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_int_ena_reg_t;
-
-/** Type of int_clr register
- *  dsi_bridge interrupt clear register
- */
-typedef union {
-    struct {
-        /** underrun_int_clr : WT; bitpos: [0]; default: 0;
-         *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
-         */
-        uint32_t underrun_int_clr:1;
-        /** vsync_int_clr : WT; bitpos: [1]; default: 0;
-         *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
-         */
-        uint32_t vsync_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_int_clr_reg_t;
-
-/** Type of int_raw register
- *  dsi_bridge raw interrupt register
- */
-typedef union {
-    struct {
-        /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  the raw interrupt status of dpi_underrun
-         */
-        uint32_t underrun_int_raw:1;
-        /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  the raw interrupt status of dpi_vsync
-         */
-        uint32_t vsync_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_int_raw_reg_t;
-
-/** Type of int_st register
- *  dsi_bridge masked interrupt register
- */
-typedef union {
-    struct {
-        /** underrun_int_st : RO; bitpos: [0]; default: 0;
-         *  the masked interrupt status of dpi_underrun
-         */
-        uint32_t underrun_int_st:1;
-        /** vsync_int_st : RO; bitpos: [1]; default: 0;
-         *  the masked interrupt status of dpi_vsync
-         */
-        uint32_t vsync_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_brg_int_st_reg_t;
-
-
-/** Group: Version Register */
-/** Type of ver_date register
- *  version control register
- */
-typedef union {
-    struct {
-        /** ver_data : R/W; bitpos: [31:0]; default: 539296009;
-         *  Represents csv version
-         */
-        uint32_t ver_data:32;
-    };
-    uint32_t val;
-} dsi_brg_ver_date_reg_t;
-
-
-typedef struct {
-    volatile dsi_brg_clk_en_reg_t clk_en;
-    volatile dsi_brg_en_reg_t en;
-    volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
-    volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
-    volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
-    volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
-    volatile dsi_brg_pixel_type_reg_t pixel_type;
-    volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
-    volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
-    volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
-    volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
-    uint32_t reserved_02c;
-    volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
-    volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
-    volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
-    volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
-    volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
-    volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
-    uint32_t reserved_048[2];
-    volatile dsi_brg_int_ena_reg_t int_ena;
-    volatile dsi_brg_int_clr_reg_t int_clr;
-    volatile dsi_brg_int_raw_reg_t int_raw;
-    volatile dsi_brg_int_st_reg_t int_st;
-    volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
-    volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
-    volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
-    volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
-    volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
-    volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
-    volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
-    volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
-    volatile dsi_brg_host_ctrl_reg_t host_ctrl;
-    volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
-    volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
-    volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
-    volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
-    volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
-    volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
-    volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
-    uint32_t reserved_0a0[24];
-    volatile dsi_brg_ver_date_reg_t ver_date;
-} dsi_brg_dev_t;
-
-extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h
index 3da6f91b24..266f441ec6 100644
--- a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h
+++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h
@@ -34,7 +34,11 @@ typedef union {
          *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
          */
         uint32_t dsi_en:1;
-        uint32_t reserved_1:31;
+        /** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
+         *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
+         */
+        uint32_t dsi_brig_rst:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } dsi_brg_en_reg_t;
@@ -109,7 +113,8 @@ typedef union {
 typedef union {
     struct {
         /** raw_type : R/W; bitpos: [3:0]; default: 0;
-         *  this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
+         *  9:yuv422, 10:yuv420, 12:gray
          */
         uint32_t raw_type:4;
         /** dpi_config : R/W; bitpos: [5:4]; default: 0;
@@ -117,10 +122,14 @@ typedef union {
          */
         uint32_t dpi_config:2;
         /** data_in_type : R/W; bitpos: [6]; default: 0;
-         *  input data type, 0: rgb, 1: yuv
+         *  input data type, 0: not yuv, 1: yuv
          */
         uint32_t data_in_type:1;
-        uint32_t reserved_7:25;
+        /** dpi_type : R/W; bitpos: [10:7]; default: 0;
+         *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         */
+        uint32_t dpi_type:4;
+        uint32_t reserved_11:21;
     };
     uint32_t val;
 } dsi_brg_pixel_type_reg_t;
@@ -198,7 +207,11 @@ typedef union {
          *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
          */
         uint32_t dpi_rsv_data:30;
-        uint32_t reserved_30:2;
+        /** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
+         *  Configures data debug feature enable. 0: disable, 1: enable
+         */
+        uint32_t dpi_dbg_en:1;
+        uint32_t reserved_31:1;
     };
     uint32_t val;
 } dsi_brg_dpi_rsv_dpi_data_reg_t;
@@ -507,7 +520,11 @@ typedef union {
          *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
          */
         uint32_t yuv422_format:2;
-        uint32_t reserved_4:28;
+        /** yuv_range : R/W; bitpos: [4]; default: 0;
+         *  Configures yuv pixel range, 0: limit range, 1: full range
+         */
+        uint32_t yuv_range:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
 } dsi_brg_yuv_cfg_reg_t;
@@ -716,7 +733,12 @@ typedef union {
          *  by dpi_underrun  interrupt signal
          */
         uint32_t underrun_int_ena:1;
-        uint32_t reserved_1:31;
+        /** vsync_int_ena : R/W; bitpos: [1]; default: 0;
+         *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
+         *  dpi_vsync  interrupt signal
+         */
+        uint32_t vsync_int_ena:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } dsi_brg_int_ena_reg_t;
@@ -730,7 +752,11 @@ typedef union {
          *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
          */
         uint32_t underrun_int_clr:1;
-        uint32_t reserved_1:31;
+        /** vsync_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t vsync_int_clr:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } dsi_brg_int_clr_reg_t;
@@ -744,7 +770,11 @@ typedef union {
          *  the raw interrupt status of dpi_underrun
          */
         uint32_t underrun_int_raw:1;
-        uint32_t reserved_1:31;
+        /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_raw:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } dsi_brg_int_raw_reg_t;
@@ -758,11 +788,28 @@ typedef union {
          *  the masked interrupt status of dpi_underrun
          */
         uint32_t underrun_int_st:1;
-        uint32_t reserved_1:31;
+        /** vsync_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_st:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } dsi_brg_int_st_reg_t;
 
+/** Group: Version Register */
+/** Type of ver_date register
+ *  version control register
+ */
+typedef union {
+    struct {
+        /** ver_data : R/W; bitpos: [31:0]; default: 539296009;
+         *  Represents csv version
+         */
+        uint32_t ver_data:32;
+    };
+    uint32_t val;
+} dsi_brg_ver_date_reg_t;
 
 typedef struct dsi_brg_dev_t {
     volatile dsi_brg_clk_en_reg_t clk_en;
@@ -804,15 +851,16 @@ typedef struct dsi_brg_dev_t {
     volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
     volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
     volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
+    uint32_t reserved_0a0[24];
+    volatile dsi_brg_ver_date_reg_t ver_date;
 } dsi_brg_dev_t;
 
+extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure");
+_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
 #endif
 
-extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h
deleted file mode 100644
index 496ea0095f..0000000000
--- a/components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_host_eco5_struct.h
+++ /dev/null
@@ -1,2007 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Version Register */
-/** Type of version register
- *  NA
- */
-typedef union {
-    struct {
-        /** version : RO; bitpos: [31:0]; default: 825504042;
-         *  NA
-         */
-        uint32_t version:32;
-    };
-    uint32_t val;
-} dsi_host_version_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of pwr_up register
- *  NA
- */
-typedef union {
-    struct {
-        /** shutdownz : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t shutdownz:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_host_pwr_up_reg_t;
-
-/** Type of clkmgr_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t tx_esc_clk_division:8;
-        /** to_clk_division : R/W; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t to_clk_division:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_clkmgr_cfg_reg_t;
-
-/** Type of dpi_vcid register
- *  NA
- */
-typedef union {
-    struct {
-        /** dpi_vcid : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_vcid:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_host_dpi_vcid_reg_t;
-
-/** Type of dpi_color_coding register
- *  NA
- */
-typedef union {
-    struct {
-        /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_color_coding:4;
-        uint32_t reserved_4:4;
-        /** loosely18_en : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t loosely18_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} dsi_host_dpi_color_coding_reg_t;
-
-/** Type of dpi_cfg_pol register
- *  NA
- */
-typedef union {
-    struct {
-        /** dataen_active_low : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dataen_active_low:1;
-        /** vsync_active_low : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t vsync_active_low:1;
-        /** hsync_active_low : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t hsync_active_low:1;
-        /** shutd_active_low : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t shutd_active_low:1;
-        /** colorm_active_low : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t colorm_active_low:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} dsi_host_dpi_cfg_pol_reg_t;
-
-/** Type of dpi_lp_cmd_tim register
- *  NA
- */
-typedef union {
-    struct {
-        /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t invact_lpcmd_time:8;
-        uint32_t reserved_8:8;
-        /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t outvact_lpcmd_time:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dsi_host_dpi_lp_cmd_tim_reg_t;
-
-/** Type of dbi_vcid register
- *  NA
- */
-typedef union {
-    struct {
-        /** dbi_vcid : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t dbi_vcid:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_host_dbi_vcid_reg_t;
-
-/** Type of dbi_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t in_dbi_conf:4;
-        uint32_t reserved_4:4;
-        /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0;
-         *  NA
-         */
-        uint32_t out_dbi_conf:4;
-        uint32_t reserved_12:4;
-        /** lut_size_conf : R/W; bitpos: [17:16]; default: 0;
-         *  NA
-         */
-        uint32_t lut_size_conf:2;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} dsi_host_dbi_cfg_reg_t;
-
-/** Type of dbi_partitioning_en register
- *  NA
- */
-typedef union {
-    struct {
-        /** partitioning_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t partitioning_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_host_dbi_partitioning_en_reg_t;
-
-/** Type of dbi_cmdsize register
- *  NA
- */
-typedef union {
-    struct {
-        /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t wr_cmd_size:16;
-        /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0;
-         *  NA
-         */
-        uint32_t allowed_cmd_size:16;
-    };
-    uint32_t val;
-} dsi_host_dbi_cmdsize_reg_t;
-
-/** Type of pckhdl_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** eotp_tx_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t eotp_tx_en:1;
-        /** eotp_rx_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t eotp_rx_en:1;
-        /** bta_en : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t bta_en:1;
-        /** ecc_rx_en : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ecc_rx_en:1;
-        /** crc_rx_en : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t crc_rx_en:1;
-        /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t eotp_tx_lp_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dsi_host_pckhdl_cfg_reg_t;
-
-/** Type of gen_vcid register
- *  NA
- */
-typedef union {
-    struct {
-        /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t gen_vcid_rx:2;
-        uint32_t reserved_2:6;
-        /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0;
-         *  NA
-         */
-        uint32_t gen_vcid_tear_auto:2;
-        uint32_t reserved_10:6;
-        /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0;
-         *  NA
-         */
-        uint32_t gen_vcid_tx_auto:2;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} dsi_host_gen_vcid_reg_t;
-
-/** Type of mode_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** cmd_video_mode : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t cmd_video_mode:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_host_mode_cfg_reg_t;
-
-/** Type of vid_mode_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_mode_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_mode_type:2;
-        uint32_t reserved_2:6;
-        /** lp_vsa_en : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vsa_en:1;
-        /** lp_vbp_en : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vbp_en:1;
-        /** lp_vfp_en : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vfp_en:1;
-        /** lp_vact_en : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vact_en:1;
-        /** lp_hbp_en : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t lp_hbp_en:1;
-        /** lp_hfp_en : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t lp_hfp_en:1;
-        /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t frame_bta_ack_en:1;
-        /** lp_cmd_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t lp_cmd_en:1;
-        /** vpg_en : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t vpg_en:1;
-        uint32_t reserved_17:3;
-        /** vpg_mode : R/W; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t vpg_mode:1;
-        uint32_t reserved_21:3;
-        /** vpg_orientation : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t vpg_orientation:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} dsi_host_vid_mode_cfg_reg_t;
-
-/** Type of vid_pkt_size register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_pkt_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_host_vid_pkt_size_reg_t;
-
-/** Type of vid_num_chunks register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_num_chunks:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} dsi_host_vid_num_chunks_reg_t;
-
-/** Type of vid_null_size register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_null_size : R/W; bitpos: [12:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_null_size:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} dsi_host_vid_null_size_reg_t;
-
-/** Type of vid_hsa_time register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hsa_time:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dsi_host_vid_hsa_time_reg_t;
-
-/** Type of vid_hbp_time register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hbp_time:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dsi_host_vid_hbp_time_reg_t;
-
-/** Type of vid_hline_time register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hline_time : R/W; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hline_time:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dsi_host_vid_hline_time_reg_t;
-
-/** Type of vid_vsa_lines register
- *  NA
- */
-typedef union {
-    struct {
-        /** vsa_lines : R/W; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vsa_lines:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vsa_lines_reg_t;
-
-/** Type of vid_vbp_lines register
- *  NA
- */
-typedef union {
-    struct {
-        /** vbp_lines : R/W; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vbp_lines:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vbp_lines_reg_t;
-
-/** Type of vid_vfp_lines register
- *  NA
- */
-typedef union {
-    struct {
-        /** vfp_lines : R/W; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vfp_lines:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vfp_lines_reg_t;
-
-/** Type of vid_vactive_lines register
- *  NA
- */
-typedef union {
-    struct {
-        /** v_active_lines : R/W; bitpos: [13:0]; default: 0;
-         *  NA
-         */
-        uint32_t v_active_lines:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_host_vid_vactive_lines_reg_t;
-
-/** Type of edpi_cmd_size register
- *  NA
- */
-typedef union {
-    struct {
-        /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t edpi_allowed_cmd_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_edpi_cmd_size_reg_t;
-
-/** Type of cmd_mode_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** tear_fx_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t tear_fx_en:1;
-        /** ack_rqst_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ack_rqst_en:1;
-        uint32_t reserved_2:6;
-        /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sw_0p_tx:1;
-        /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sw_1p_tx:1;
-        /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sw_2p_tx:1;
-        /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sr_0p_tx:1;
-        /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sr_1p_tx:1;
-        /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t gen_sr_2p_tx:1;
-        /** gen_lw_tx : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t gen_lw_tx:1;
-        uint32_t reserved_15:1;
-        /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t dcs_sw_0p_tx:1;
-        /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t dcs_sw_1p_tx:1;
-        /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t dcs_sr_0p_tx:1;
-        /** dcs_lw_tx : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t dcs_lw_tx:1;
-        uint32_t reserved_20:4;
-        /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t max_rd_pkt_size:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} dsi_host_cmd_mode_cfg_reg_t;
-
-/** Type of gen_hdr register
- *  NA
- */
-typedef union {
-    struct {
-        /** gen_dt : R/W; bitpos: [5:0]; default: 0;
-         *  NA
-         */
-        uint32_t gen_dt:6;
-        /** gen_vc : R/W; bitpos: [7:6]; default: 0;
-         *  NA
-         */
-        uint32_t gen_vc:2;
-        /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t gen_wc_lsbyte:8;
-        /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t gen_wc_msbyte:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dsi_host_gen_hdr_reg_t;
-
-/** Type of gen_pld_data register
- *  NA
- */
-typedef union {
-    struct {
-        /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_b1:8;
-        /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_b2:8;
-        /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_b3:8;
-        /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_b4:8;
-    };
-    uint32_t val;
-} dsi_host_gen_pld_data_reg_t;
-
-/** Type of to_cnt_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t lprx_to_cnt:16;
-        /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0;
-         *  NA
-         */
-        uint32_t hstx_to_cnt:16;
-    };
-    uint32_t val;
-} dsi_host_to_cnt_cfg_reg_t;
-
-/** Type of hs_rd_to_cnt register
- *  NA
- */
-typedef union {
-    struct {
-        /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t hs_rd_to_cnt:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_hs_rd_to_cnt_reg_t;
-
-/** Type of lp_rd_to_cnt register
- *  NA
- */
-typedef union {
-    struct {
-        /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t lp_rd_to_cnt:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_lp_rd_to_cnt_reg_t;
-
-/** Type of hs_wr_to_cnt register
- *  NA
- */
-typedef union {
-    struct {
-        /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t hs_wr_to_cnt:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_hs_wr_to_cnt_reg_t;
-
-/** Type of lp_wr_to_cnt register
- *  NA
- */
-typedef union {
-    struct {
-        /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t lp_wr_to_cnt:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_lp_wr_to_cnt_reg_t;
-
-/** Type of bta_to_cnt register
- *  NA
- */
-typedef union {
-    struct {
-        /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0;
-         *  NA
-         */
-        uint32_t bta_to_cnt:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_bta_to_cnt_reg_t;
-
-/** Type of sdf_3d register
- *  NA
- */
-typedef union {
-    struct {
-        /** mode_3d : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t mode_3d:2;
-        /** format_3d : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t format_3d:2;
-        /** second_vsync : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t second_vsync:1;
-        /** right_first : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t right_first:1;
-        uint32_t reserved_6:10;
-        /** send_3d_cfg : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t send_3d_cfg:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dsi_host_sdf_3d_reg_t;
-
-/** Type of lpclk_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_txrequestclkhs:1;
-        /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t auto_clklane_ctrl:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_host_lpclk_ctrl_reg_t;
-
-/** Type of phy_tmr_lpclk_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_clklp2hs_time:10;
-        uint32_t reserved_10:6;
-        /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0;
-         *  NA
-         */
-        uint32_t phy_clkhs2lp_time:10;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} dsi_host_phy_tmr_lpclk_cfg_reg_t;
-
-/** Type of phy_tmr_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_lp2hs_time:10;
-        uint32_t reserved_10:6;
-        /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0;
-         *  NA
-         */
-        uint32_t phy_hs2lp_time:10;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} dsi_host_phy_tmr_cfg_reg_t;
-
-/** Type of phy_rstz register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_shutdownz:1;
-        /** phy_rstz : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_rstz:1;
-        /** phy_enableclk : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t phy_enableclk:1;
-        /** phy_forcepll : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t phy_forcepll:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dsi_host_phy_rstz_reg_t;
-
-/** Type of phy_if_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** n_lanes : R/W; bitpos: [1:0]; default: 1;
-         *  NA
-         */
-        uint32_t n_lanes:2;
-        uint32_t reserved_2:6;
-        /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stop_wait_time:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} dsi_host_phy_if_cfg_reg_t;
-
-/** Type of phy_ulps_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_txrequlpsclk:1;
-        /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_txexitulpsclk:1;
-        /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t phy_txrequlpslan:1;
-        /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t phy_txexitulpslan:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dsi_host_phy_ulps_ctrl_reg_t;
-
-/** Type of phy_tx_triggers register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_tx_triggers:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dsi_host_phy_tx_triggers_reg_t;
-
-/** Type of phy_tst_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_testclr : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t phy_testclr:1;
-        /** phy_testclk : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testclk:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_host_phy_tst_ctrl0_reg_t;
-
-/** Type of phy_tst_ctrl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testdin:8;
-        /** pht_testdout : RO; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t pht_testdout:8;
-        /** phy_testen : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testen:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dsi_host_phy_tst_ctrl1_reg_t;
-
-/** Type of phy_cal register
- *  NA
- */
-typedef union {
-    struct {
-        /** txskewcalhs : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t txskewcalhs:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dsi_host_phy_cal_reg_t;
-
-/** Type of dsc_parameter register
- *  NA
- */
-typedef union {
-    struct {
-        /** compression_mode : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t compression_mode:1;
-        uint32_t reserved_1:7;
-        /** compress_algo : R/W; bitpos: [9:8]; default: 0;
-         *  NA
-         */
-        uint32_t compress_algo:2;
-        uint32_t reserved_10:6;
-        /** pps_sel : R/W; bitpos: [17:16]; default: 0;
-         *  NA
-         */
-        uint32_t pps_sel:2;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} dsi_host_dsc_parameter_reg_t;
-
-/** Type of phy_tmr_rd_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** max_rd_time : R/W; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t max_rd_time:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dsi_host_phy_tmr_rd_cfg_reg_t;
-
-/** Type of vid_shadow_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_shadow_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_shadow_en:1;
-        uint32_t reserved_1:7;
-        /** vid_shadow_req : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t vid_shadow_req:1;
-        uint32_t reserved_9:7;
-        /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t vid_shadow_pin_req:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dsi_host_vid_shadow_ctrl_reg_t;
-
-/** Type of edpi_te_hw_cfg register
- *  NA
- */
-typedef union {
-    struct {
-        /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t hw_tear_effect_on:1;
-        /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t hw_tear_effect_gen:1;
-        uint32_t reserved_2:2;
-        /** hw_set_scan_line : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t hw_set_scan_line:1;
-        uint32_t reserved_5:11;
-        /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0;
-         *  NA
-         */
-        uint32_t scan_line_parameter:16;
-    };
-    uint32_t val;
-} dsi_host_edpi_te_hw_cfg_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of cmd_pkt_status register
- *  NA
- */
-typedef union {
-    struct {
-        /** gen_cmd_empty : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t gen_cmd_empty:1;
-        /** gen_cmd_full : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t gen_cmd_full:1;
-        /** gen_pld_w_empty : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t gen_pld_w_empty:1;
-        /** gen_pld_w_full : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_w_full:1;
-        /** gen_pld_r_empty : RO; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t gen_pld_r_empty:1;
-        /** gen_pld_r_full : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_r_full:1;
-        /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t gen_rd_cmd_busy:1;
-        uint32_t reserved_7:9;
-        /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t gen_buff_cmd_empty:1;
-        /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t gen_buff_cmd_full:1;
-        /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t gen_buff_pld_empty:1;
-        /** gen_buff_pld_full : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t gen_buff_pld_full:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} dsi_host_cmd_pkt_status_reg_t;
-
-/** Type of phy_status register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_lock : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_lock:1;
-        /** phy_direction : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_direction:1;
-        /** phy_stopstateclklane : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstateclklane:1;
-        /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t phy_ulpsactivenotclk:1;
-        /** phy_stopstate0lane : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstate0lane:1;
-        /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t phy_ulpsactivenot0lane:1;
-        /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t phy_rxulpsesc0lane:1;
-        /** phy_stopstate1lane : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstate1lane:1;
-        /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t phy_ulpsactivenot1lane:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} dsi_host_phy_status_reg_t;
-
-/** Type of dpi_vcid_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_vcid_act:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dsi_host_dpi_vcid_act_reg_t;
-
-/** Type of dpi_color_coding_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_color_coding_act:4;
-        uint32_t reserved_4:4;
-        /** loosely18_en_act : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t loosely18_en_act:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} dsi_host_dpi_color_coding_act_reg_t;
-
-/** Type of dpi_lp_cmd_tim_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t invact_lpcmd_time_act:8;
-        uint32_t reserved_8:8;
-        /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t outvact_lpcmd_time_act:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dsi_host_dpi_lp_cmd_tim_act_reg_t;
-
-/** Type of vid_mode_cfg_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_mode_type_act:2;
-        /** lp_vsa_en_act : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vsa_en_act:1;
-        /** lp_vbp_en_act : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vbp_en_act:1;
-        /** lp_vfp_en_act : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vfp_en_act:1;
-        /** lp_vact_en_act : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t lp_vact_en_act:1;
-        /** lp_hbp_en_act : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t lp_hbp_en_act:1;
-        /** lp_hfp_en_act : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t lp_hfp_en_act:1;
-        /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t frame_bta_ack_en_act:1;
-        /** lp_cmd_en_act : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t lp_cmd_en_act:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_mode_cfg_act_reg_t;
-
-/** Type of vid_pkt_size_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_pkt_size_act:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_host_vid_pkt_size_act_reg_t;
-
-/** Type of vid_num_chunks_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_num_chunks_act:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} dsi_host_vid_num_chunks_act_reg_t;
-
-/** Type of vid_null_size_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_null_size_act : RO; bitpos: [12:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_null_size_act:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} dsi_host_vid_null_size_act_reg_t;
-
-/** Type of vid_hsa_time_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hsa_time_act:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dsi_host_vid_hsa_time_act_reg_t;
-
-/** Type of vid_hbp_time_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hbp_time_act:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dsi_host_vid_hbp_time_act_reg_t;
-
-/** Type of vid_hline_time_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t vid_hline_time_act:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dsi_host_vid_hline_time_act_reg_t;
-
-/** Type of vid_vsa_lines_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vsa_lines_act : RO; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vsa_lines_act:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vsa_lines_act_reg_t;
-
-/** Type of vid_vbp_lines_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vbp_lines_act : RO; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vbp_lines_act:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vbp_lines_act_reg_t;
-
-/** Type of vid_vfp_lines_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** vfp_lines_act : RO; bitpos: [9:0]; default: 0;
-         *  NA
-         */
-        uint32_t vfp_lines_act:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} dsi_host_vid_vfp_lines_act_reg_t;
-
-/** Type of vid_vactive_lines_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** v_active_lines_act : RO; bitpos: [13:0]; default: 0;
-         *  NA
-         */
-        uint32_t v_active_lines_act:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} dsi_host_vid_vactive_lines_act_reg_t;
-
-/** Type of vid_pkt_status register
- *  NA
- */
-typedef union {
-    struct {
-        /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t dpi_cmd_w_empty:1;
-        /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_cmd_w_full:1;
-        /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t dpi_pld_w_empty:1;
-        /** dpi_pld_w_full : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_pld_w_full:1;
-        uint32_t reserved_4:12;
-        /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t dpi_buff_pld_empty:1;
-        /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_buff_pld_full:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} dsi_host_vid_pkt_status_reg_t;
-
-/** Type of sdf_3d_act register
- *  NA
- */
-typedef union {
-    struct {
-        /** mode_3d_act : RO; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t mode_3d_act:2;
-        /** format_3d_act : RO; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t format_3d_act:2;
-        /** second_vsync_act : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t second_vsync_act:1;
-        /** right_first_act : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t right_first_act:1;
-        uint32_t reserved_6:10;
-        /** send_3d_cfg_act : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t send_3d_cfg_act:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dsi_host_sdf_3d_act_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_st0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ack_with_err_0 : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_0:1;
-        /** ack_with_err_1 : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_1:1;
-        /** ack_with_err_2 : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_2:1;
-        /** ack_with_err_3 : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_3:1;
-        /** ack_with_err_4 : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_4:1;
-        /** ack_with_err_5 : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_5:1;
-        /** ack_with_err_6 : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_6:1;
-        /** ack_with_err_7 : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_7:1;
-        /** ack_with_err_8 : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_8:1;
-        /** ack_with_err_9 : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_9:1;
-        /** ack_with_err_10 : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_10:1;
-        /** ack_with_err_11 : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_11:1;
-        /** ack_with_err_12 : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_12:1;
-        /** ack_with_err_13 : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_13:1;
-        /** ack_with_err_14 : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_14:1;
-        /** ack_with_err_15 : RO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ack_with_err_15:1;
-        /** dphy_errors_0 : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_errors_0:1;
-        /** dphy_errors_1 : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_errors_1:1;
-        /** dphy_errors_2 : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_errors_2:1;
-        /** dphy_errors_3 : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_errors_3:1;
-        /** dphy_errors_4 : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_errors_4:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dsi_host_int_st0_reg_t;
-
-/** Type of int_st1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** to_hs_tx : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t to_hs_tx:1;
-        /** to_lp_rx : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t to_lp_rx:1;
-        /** ecc_single_err : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ecc_single_err:1;
-        /** ecc_milti_err : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ecc_milti_err:1;
-        /** crc_err : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t crc_err:1;
-        /** pkt_size_err : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t pkt_size_err:1;
-        /** eopt_err : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t eopt_err:1;
-        /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_pld_wr_err:1;
-        /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t gen_cmd_wr_err:1;
-        /** gen_pld_wr_err : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_wr_err:1;
-        /** gen_pld_send_err : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_send_err:1;
-        /** gen_pld_rd_err : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_rd_err:1;
-        /** gen_pld_recev_err : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t gen_pld_recev_err:1;
-        uint32_t reserved_13:6;
-        /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t dpi_buff_pld_under:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} dsi_host_int_st1_reg_t;
-
-/** Type of int_msk0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_0:1;
-        /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_1:1;
-        /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_2:1;
-        /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_3:1;
-        /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_4:1;
-        /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_5:1;
-        /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_6:1;
-        /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_7:1;
-        /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_8:1;
-        /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_9:1;
-        /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_10:1;
-        /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_11:1;
-        /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_12:1;
-        /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_13:1;
-        /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_14:1;
-        /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ack_with_err_15:1;
-        /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dphy_errors_0:1;
-        /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dphy_errors_1:1;
-        /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dphy_errors_2:1;
-        /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dphy_errors_3:1;
-        /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dphy_errors_4:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dsi_host_int_msk0_reg_t;
-
-/** Type of int_msk1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_to_hs_tx:1;
-        /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_to_lp_rx:1;
-        /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ecc_single_err:1;
-        /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_ecc_milti_err:1;
-        /** mask_crc_err : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_crc_err:1;
-        /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_pkt_size_err:1;
-        /** mask_eopt_err : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_eopt_err:1;
-        /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dpi_pld_wr_err:1;
-        /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_gen_cmd_wr_err:1;
-        /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_gen_pld_wr_err:1;
-        /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_gen_pld_send_err:1;
-        /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_gen_pld_rd_err:1;
-        /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_gen_pld_recev_err:1;
-        uint32_t reserved_13:6;
-        /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t mask_dpi_buff_pld_under:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} dsi_host_int_msk1_reg_t;
-
-/** Type of int_force0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_0:1;
-        /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_1:1;
-        /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_2:1;
-        /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_3:1;
-        /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_4:1;
-        /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_5:1;
-        /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_6:1;
-        /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_7:1;
-        /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_8:1;
-        /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_9:1;
-        /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_10:1;
-        /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_11:1;
-        /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_12:1;
-        /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_13:1;
-        /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_14:1;
-        /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_ack_with_err_15:1;
-        /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t force_dphy_errors_0:1;
-        /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t force_dphy_errors_1:1;
-        /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t force_dphy_errors_2:1;
-        /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t force_dphy_errors_3:1;
-        /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t force_dphy_errors_4:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dsi_host_int_force0_reg_t;
-
-/** Type of int_force1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_to_hs_tx : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_to_hs_tx:1;
-        /** force_to_lp_rx : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_to_lp_rx:1;
-        /** force_ecc_single_err : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_ecc_single_err:1;
-        /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_ecc_milti_err:1;
-        /** force_crc_err : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_crc_err:1;
-        /** force_pkt_size_err : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_pkt_size_err:1;
-        /** force_eopt_err : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_eopt_err:1;
-        /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_dpi_pld_wr_err:1;
-        /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_gen_cmd_wr_err:1;
-        /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_gen_pld_wr_err:1;
-        /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_gen_pld_send_err:1;
-        /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_gen_pld_rd_err:1;
-        /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_gen_pld_recev_err:1;
-        uint32_t reserved_13:6;
-        /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t force_dpi_buff_pld_under:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} dsi_host_int_force1_reg_t;
-
-
-typedef struct {
-    volatile dsi_host_version_reg_t version;
-    volatile dsi_host_pwr_up_reg_t pwr_up;
-    volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg;
-    volatile dsi_host_dpi_vcid_reg_t dpi_vcid;
-    volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding;
-    volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol;
-    volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim;
-    volatile dsi_host_dbi_vcid_reg_t dbi_vcid;
-    volatile dsi_host_dbi_cfg_reg_t dbi_cfg;
-    volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en;
-    volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize;
-    volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg;
-    volatile dsi_host_gen_vcid_reg_t gen_vcid;
-    volatile dsi_host_mode_cfg_reg_t mode_cfg;
-    volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg;
-    volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size;
-    volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks;
-    volatile dsi_host_vid_null_size_reg_t vid_null_size;
-    volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time;
-    volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time;
-    volatile dsi_host_vid_hline_time_reg_t vid_hline_time;
-    volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines;
-    volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines;
-    volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines;
-    volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines;
-    volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size;
-    volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg;
-    volatile dsi_host_gen_hdr_reg_t gen_hdr;
-    volatile dsi_host_gen_pld_data_reg_t gen_pld_data;
-    volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status;
-    volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg;
-    volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt;
-    volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt;
-    volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt;
-    volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt;
-    volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt;
-    volatile dsi_host_sdf_3d_reg_t sdf_3d;
-    volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl;
-    volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg;
-    volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg;
-    volatile dsi_host_phy_rstz_reg_t phy_rstz;
-    volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg;
-    volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl;
-    volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers;
-    volatile dsi_host_phy_status_reg_t phy_status;
-    volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0;
-    volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1;
-    volatile dsi_host_int_st0_reg_t int_st0;
-    volatile dsi_host_int_st1_reg_t int_st1;
-    volatile dsi_host_int_msk0_reg_t int_msk0;
-    volatile dsi_host_int_msk1_reg_t int_msk1;
-    volatile dsi_host_phy_cal_reg_t phy_cal;
-    uint32_t reserved_0d0[2];
-    volatile dsi_host_int_force0_reg_t int_force0;
-    volatile dsi_host_int_force1_reg_t int_force1;
-    uint32_t reserved_0e0[4];
-    volatile dsi_host_dsc_parameter_reg_t dsc_parameter;
-    volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg;
-    uint32_t reserved_0f8[2];
-    volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl;
-    uint32_t reserved_104[2];
-    volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act;
-    volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act;
-    uint32_t reserved_114;
-    volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act;
-    volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg;
-    uint32_t reserved_120[6];
-    volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act;
-    volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act;
-    volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act;
-    volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act;
-    volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act;
-    volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act;
-    volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act;
-    volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act;
-    volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act;
-    volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act;
-    volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act;
-    uint32_t reserved_164;
-    volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status;
-    uint32_t reserved_16c[9];
-    volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act;
-} dsi_host_dev_t;
-
-extern dsi_host_dev_t MIPI_DSI_HOST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h
index 63d820d1c5..9d8b56cdc9 100644
--- a/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h
+++ b/components/soc/esp32p4/register/hw_ver2/soc/soc_etm_struct.h
@@ -10,8 +10,6 @@
 extern "C" {
 #endif
 
-// TODO: IDF-13428
-
 /** Group: Status register */
 /** Type of ch_ena_ad0 register
  *  Channel enable status register
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h
deleted file mode 100644
index cb893d2353..0000000000
--- a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h
+++ /dev/null
@@ -1,716 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TIMG_T0CONFIG_REG register
- *  Timer 0 configuration register
- */
-#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
-/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
- *  When set, the alarm is enabled. This bit is automatically cleared once an
- *  alarm occurs.
- */
-#define TIMG_T0_ALARM_EN    (BIT(10))
-#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
-#define TIMG_T0_ALARM_EN_V  0x00000001U
-#define TIMG_T0_ALARM_EN_S  10
-/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
- *  When set, Timer 0 's clock divider counter will be reset.
- */
-#define TIMG_T0_DIVCNT_RST    (BIT(12))
-#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
-#define TIMG_T0_DIVCNT_RST_V  0x00000001U
-#define TIMG_T0_DIVCNT_RST_S  12
-/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
- *  Timer 0 clock (T0_clk) prescaler value.
- */
-#define TIMG_T0_DIVIDER    0x0000FFFFU
-#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
-#define TIMG_T0_DIVIDER_V  0x0000FFFFU
-#define TIMG_T0_DIVIDER_S  13
-/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
- *  When set, timer 0 auto-reload at alarm is enabled.
- */
-#define TIMG_T0_AUTORELOAD    (BIT(29))
-#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
-#define TIMG_T0_AUTORELOAD_V  0x00000001U
-#define TIMG_T0_AUTORELOAD_S  29
-/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
- *  When set, the timer 0 time-base counter will increment every clock tick. When
- *  cleared, the timer 0 time-base counter will decrement.
- */
-#define TIMG_T0_INCREASE    (BIT(30))
-#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
-#define TIMG_T0_INCREASE_V  0x00000001U
-#define TIMG_T0_INCREASE_S  30
-/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
- *  When set, the timer 0 time-base counter is enabled.
- */
-#define TIMG_T0_EN    (BIT(31))
-#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
-#define TIMG_T0_EN_V  0x00000001U
-#define TIMG_T0_EN_S  31
-
-/** TIMG_T0LO_REG register
- *  Timer 0 current value, low 32 bits
- */
-#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
-/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
- *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
- *  of timer 0 can be read here.
- */
-#define TIMG_T0_LO    0xFFFFFFFFU
-#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
-#define TIMG_T0_LO_V  0xFFFFFFFFU
-#define TIMG_T0_LO_S  0
-
-/** TIMG_T0HI_REG register
- *  Timer 0 current value, high 22 bits
- */
-#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
-/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
- *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
- *  of timer 0 can be read here.
- */
-#define TIMG_T0_HI    0x003FFFFFU
-#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
-#define TIMG_T0_HI_V  0x003FFFFFU
-#define TIMG_T0_HI_S  0
-
-/** TIMG_T0UPDATE_REG register
- *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
- */
-#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
-/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
- *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
- */
-#define TIMG_T0_UPDATE    (BIT(31))
-#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
-#define TIMG_T0_UPDATE_V  0x00000001U
-#define TIMG_T0_UPDATE_S  31
-
-/** TIMG_T0ALARMLO_REG register
- *  Timer 0 alarm value, low 32 bits
- */
-#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
-/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
- *  Timer 0 alarm trigger time-base counter value, low 32 bits.
- */
-#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
-#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
-#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
-#define TIMG_T0_ALARM_LO_S  0
-
-/** TIMG_T0ALARMHI_REG register
- *  Timer 0 alarm value, high bits
- */
-#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
-/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
- *  Timer 0 alarm trigger time-base counter value, high 22 bits.
- */
-#define TIMG_T0_ALARM_HI    0x003FFFFFU
-#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
-#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
-#define TIMG_T0_ALARM_HI_S  0
-
-/** TIMG_T0LOADLO_REG register
- *  Timer 0 reload value, low 32 bits
- */
-#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
-/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  Low 32 bits of the value that a reload will load onto timer 0 time-base
- *  Counter.
- */
-#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
-#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
-#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
-#define TIMG_T0_LOAD_LO_S  0
-
-/** TIMG_T0LOADHI_REG register
- *  Timer 0 reload value, high 22 bits
- */
-#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
-/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
- *  High 22 bits of the value that a reload will load onto timer 0 time-base
- *  counter.
- */
-#define TIMG_T0_LOAD_HI    0x003FFFFFU
-#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
-#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
-#define TIMG_T0_LOAD_HI_S  0
-
-/** TIMG_T0LOAD_REG register
- *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
- */
-#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
-/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
- *
- *  Write any value to trigger a timer 0 time-base counter reload.
- */
-#define TIMG_T0_LOAD    0xFFFFFFFFU
-#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
-#define TIMG_T0_LOAD_V  0xFFFFFFFFU
-#define TIMG_T0_LOAD_S  0
-
-/** TIMG_T1CONFIG_REG register
- *  Timer 1 configuration register
- */
-#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24)
-/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
- *  When set, the alarm is enabled. This bit is automatically cleared once an
- *  alarm occurs.
- */
-#define TIMG_T1_ALARM_EN    (BIT(10))
-#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
-#define TIMG_T1_ALARM_EN_V  0x00000001U
-#define TIMG_T1_ALARM_EN_S  10
-/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
- *  When set, Timer 1 's clock divider counter will be reset.
- */
-#define TIMG_T1_DIVCNT_RST    (BIT(12))
-#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
-#define TIMG_T1_DIVCNT_RST_V  0x00000001U
-#define TIMG_T1_DIVCNT_RST_S  12
-/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
- *  Timer 1 clock (T1_clk) prescaler value.
- */
-#define TIMG_T1_DIVIDER    0x0000FFFFU
-#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
-#define TIMG_T1_DIVIDER_V  0x0000FFFFU
-#define TIMG_T1_DIVIDER_S  13
-/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
- *  When set, timer 1 auto-reload at alarm is enabled.
- */
-#define TIMG_T1_AUTORELOAD    (BIT(29))
-#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
-#define TIMG_T1_AUTORELOAD_V  0x00000001U
-#define TIMG_T1_AUTORELOAD_S  29
-/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
- *  When set, the timer 1 time-base counter will increment every clock tick. When
- *  cleared, the timer 1 time-base counter will decrement.
- */
-#define TIMG_T1_INCREASE    (BIT(30))
-#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
-#define TIMG_T1_INCREASE_V  0x00000001U
-#define TIMG_T1_INCREASE_S  30
-/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
- *  When set, the timer 1 time-base counter is enabled.
- */
-#define TIMG_T1_EN    (BIT(31))
-#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
-#define TIMG_T1_EN_V  0x00000001U
-#define TIMG_T1_EN_S  31
-
-/** TIMG_T1LO_REG register
- *  Timer 1 current value, low 32 bits
- */
-#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28)
-/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
- *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
- *  of timer 1 can be read here.
- */
-#define TIMG_T1_LO    0xFFFFFFFFU
-#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
-#define TIMG_T1_LO_V  0xFFFFFFFFU
-#define TIMG_T1_LO_S  0
-
-/** TIMG_T1HI_REG register
- *  Timer 1 current value, high 22 bits
- */
-#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c)
-/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
- *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
- *  of timer 1 can be read here.
- */
-#define TIMG_T1_HI    0x003FFFFFU
-#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
-#define TIMG_T1_HI_V  0x003FFFFFU
-#define TIMG_T1_HI_S  0
-
-/** TIMG_T1UPDATE_REG register
- *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
- */
-#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30)
-/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
- *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
- */
-#define TIMG_T1_UPDATE    (BIT(31))
-#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
-#define TIMG_T1_UPDATE_V  0x00000001U
-#define TIMG_T1_UPDATE_S  31
-
-/** TIMG_T1ALARMLO_REG register
- *  Timer 1 alarm value, low 32 bits
- */
-#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34)
-/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
- *  Timer 1 alarm trigger time-base counter value, low 32 bits.
- */
-#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
-#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
-#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
-#define TIMG_T1_ALARM_LO_S  0
-
-/** TIMG_T1ALARMHI_REG register
- *  Timer 1 alarm value, high bits
- */
-#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38)
-/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
- *  Timer 1 alarm trigger time-base counter value, high 22 bits.
- */
-#define TIMG_T1_ALARM_HI    0x003FFFFFU
-#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
-#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
-#define TIMG_T1_ALARM_HI_S  0
-
-/** TIMG_T1LOADLO_REG register
- *  Timer 1 reload value, low 32 bits
- */
-#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c)
-/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  Low 32 bits of the value that a reload will load onto timer 1 time-base
- *  Counter.
- */
-#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
-#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
-#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
-#define TIMG_T1_LOAD_LO_S  0
-
-/** TIMG_T1LOADHI_REG register
- *  Timer 1 reload value, high 22 bits
- */
-#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40)
-/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
- *  High 22 bits of the value that a reload will load onto timer 1 time-base
- *  counter.
- */
-#define TIMG_T1_LOAD_HI    0x003FFFFFU
-#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
-#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
-#define TIMG_T1_LOAD_HI_S  0
-
-/** TIMG_T1LOAD_REG register
- *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
- */
-#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44)
-/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
- *
- *  Write any value to trigger a timer 1 time-base counter reload.
- */
-#define TIMG_T1_LOAD    0xFFFFFFFFU
-#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
-#define TIMG_T1_LOAD_V  0xFFFFFFFFU
-#define TIMG_T1_LOAD_S  0
-
-/** TIMG_WDTCONFIG0_REG register
- *  Watchdog timer configuration register
- */
-#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
-/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
- *  WDT reset CPU enable.
- */
-#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
-#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
-#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
-#define TIMG_WDT_APPCPU_RESET_EN_S  12
-/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
- *  WDT reset CPU enable.
- */
-#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
-#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
-#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
-#define TIMG_WDT_PROCPU_RESET_EN_S  13
-/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
- *  When set, Flash boot protection is enabled.
- */
-#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
-#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
-#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
-#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
-/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
- *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
- *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
- */
-#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
-#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
-#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
-#define TIMG_WDT_SYS_RESET_LENGTH_S  15
-/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
- *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
- *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
- */
-#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
-#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
-#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define TIMG_WDT_CPU_RESET_LENGTH_S  18
-/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
- *  update the WDT configuration registers
- */
-#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
-#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
-#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
-#define TIMG_WDT_CONF_UPDATE_EN_S  22
-/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
- *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG3    0x00000003U
-#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
-#define TIMG_WDT_STG3_V  0x00000003U
-#define TIMG_WDT_STG3_S  23
-/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
- *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG2    0x00000003U
-#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
-#define TIMG_WDT_STG2_V  0x00000003U
-#define TIMG_WDT_STG2_S  25
-/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
- *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG1    0x00000003U
-#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
-#define TIMG_WDT_STG1_V  0x00000003U
-#define TIMG_WDT_STG1_S  27
-/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
- *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG0    0x00000003U
-#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
-#define TIMG_WDT_STG0_V  0x00000003U
-#define TIMG_WDT_STG0_S  29
-/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
- *  When set, MWDT is enabled.
- */
-#define TIMG_WDT_EN    (BIT(31))
-#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
-#define TIMG_WDT_EN_V  0x00000001U
-#define TIMG_WDT_EN_S  31
-
-/** TIMG_WDTCONFIG1_REG register
- *  Watchdog timer prescaler register
- */
-#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
-/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
- *  When set, WDT 's clock divider counter will be reset.
- */
-#define TIMG_WDT_DIVCNT_RST    (BIT(0))
-#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
-#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
-#define TIMG_WDT_DIVCNT_RST_S  0
-/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
- *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
- *  TIMG_WDT_CLK_PRESCALE.
- */
-#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
-#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
-#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
-#define TIMG_WDT_CLK_PRESCALE_S  16
-
-/** TIMG_WDTCONFIG2_REG register
- *  Watchdog timer stage 0 timeout value
- */
-#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
-/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
- *  Stage 0 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
-#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG0_HOLD_S  0
-
-/** TIMG_WDTCONFIG3_REG register
- *  Watchdog timer stage 1 timeout value
- */
-#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
-/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
- *  Stage 1 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
-#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG1_HOLD_S  0
-
-/** TIMG_WDTCONFIG4_REG register
- *  Watchdog timer stage 2 timeout value
- */
-#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
-/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
- *  Stage 2 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
-#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG2_HOLD_S  0
-
-/** TIMG_WDTCONFIG5_REG register
- *  Watchdog timer stage 3 timeout value
- */
-#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
-/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
- *  Stage 3 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
-#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG3_HOLD_S  0
-
-/** TIMG_WDTFEED_REG register
- *  Write to feed the watchdog timer
- */
-#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
-/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
- *  Write any value to feed the MWDT. (WO)
- */
-#define TIMG_WDT_FEED    0xFFFFFFFFU
-#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
-#define TIMG_WDT_FEED_V  0xFFFFFFFFU
-#define TIMG_WDT_FEED_S  0
-
-/** TIMG_WDTWPROTECT_REG register
- *  Watchdog write protect register
- */
-#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
-/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
- *  If the register contains a different value than its reset value, write
- *  protection is enabled.
- */
-#define TIMG_WDT_WKEY    0xFFFFFFFFU
-#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
-#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
-#define TIMG_WDT_WKEY_S  0
-
-/** TIMG_RTCCALICFG_REG register
- *  RTC calibration configure register
- */
-#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
-/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
- *  0: one-shot frequency calculation,1: periodic frequency calculation,
- */
-#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
-#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
-#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
-#define TIMG_RTC_CALI_START_CYCLING_S  12
-/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
- *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
- */
-#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
-#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
-#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
-#define TIMG_RTC_CALI_CLK_SEL_S  13
-/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
- *  indicate one-shot frequency calculation is done.
- */
-#define TIMG_RTC_CALI_RDY    (BIT(15))
-#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
-#define TIMG_RTC_CALI_RDY_V  0x00000001U
-#define TIMG_RTC_CALI_RDY_S  15
-/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
- *  Configure the time to calculate RTC slow clock's frequency.
- */
-#define TIMG_RTC_CALI_MAX    0x00007FFFU
-#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
-#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
-#define TIMG_RTC_CALI_MAX_S  16
-/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start one-shot frequency calculation.
- */
-#define TIMG_RTC_CALI_START    (BIT(31))
-#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
-#define TIMG_RTC_CALI_START_V  0x00000001U
-#define TIMG_RTC_CALI_START_S  31
-
-/** TIMG_RTCCALICFG1_REG register
- *  RTC calibration configure1 register
- */
-#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
-/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
- *  indicate periodic frequency calculation is done.
- */
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
-/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
- *  When one-shot or periodic frequency calculation is done, read this value to
- *  calculate RTC slow clock's frequency.
- */
-#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
-#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
-#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
-#define TIMG_RTC_CALI_VALUE_S  7
-
-/** TIMG_INT_ENA_TIMERS_REG register
- *  Interrupt enable bits
- */
-#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
-/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_ENA    (BIT(0))
-#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
-#define TIMG_T0_INT_ENA_V  0x00000001U
-#define TIMG_T0_INT_ENA_S  0
-/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T1_INT_ENA    (BIT(1))
-#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
-#define TIMG_T1_INT_ENA_V  0x00000001U
-#define TIMG_T1_INT_ENA_S  1
-/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_ENA    (BIT(2))
-#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
-#define TIMG_WDT_INT_ENA_V  0x00000001U
-#define TIMG_WDT_INT_ENA_S  2
-
-/** TIMG_INT_RAW_TIMERS_REG register
- *  Raw interrupt status
- */
-#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
-/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_RAW    (BIT(0))
-#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
-#define TIMG_T0_INT_RAW_V  0x00000001U
-#define TIMG_T0_INT_RAW_S  0
-/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T1_INT_RAW    (BIT(1))
-#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
-#define TIMG_T1_INT_RAW_V  0x00000001U
-#define TIMG_T1_INT_RAW_S  1
-/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_RAW    (BIT(2))
-#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
-#define TIMG_WDT_INT_RAW_V  0x00000001U
-#define TIMG_WDT_INT_RAW_S  2
-
-/** TIMG_INT_ST_TIMERS_REG register
- *  Masked interrupt status
- */
-#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
-/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_ST    (BIT(0))
-#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
-#define TIMG_T0_INT_ST_V  0x00000001U
-#define TIMG_T0_INT_ST_S  0
-/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T1_INT_ST    (BIT(1))
-#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
-#define TIMG_T1_INT_ST_V  0x00000001U
-#define TIMG_T1_INT_ST_S  1
-/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_ST    (BIT(2))
-#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
-#define TIMG_WDT_INT_ST_V  0x00000001U
-#define TIMG_WDT_INT_ST_S  2
-
-/** TIMG_INT_CLR_TIMERS_REG register
- *  Interrupt clear bits
- */
-#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
-/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_CLR    (BIT(0))
-#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
-#define TIMG_T0_INT_CLR_V  0x00000001U
-#define TIMG_T0_INT_CLR_S  0
-/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T1_INT_CLR    (BIT(1))
-#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
-#define TIMG_T1_INT_CLR_V  0x00000001U
-#define TIMG_T1_INT_CLR_S  1
-/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_CLR    (BIT(2))
-#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
-#define TIMG_WDT_INT_CLR_V  0x00000001U
-#define TIMG_WDT_INT_CLR_S  2
-
-/** TIMG_RTCCALICFG2_REG register
- *  Timer group calibration register
- */
-#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
-/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
- *  RTC calibration timeout indicator
- */
-#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
-#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
-#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
-#define TIMG_RTC_CALI_TIMEOUT_S  0
-/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
- *  Cycles that release calibration timeout reset
- */
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
-/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
- *  Threshold value for the RTC calibration timer. If the calibration timer's value
- *  exceeds this threshold, a timeout is triggered.
- */
-#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
-#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
-#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
-#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
-
-/** TIMG_NTIMERS_DATE_REG register
- *  Timer version control register
- */
-#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
-/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
- *  Timer version control register
- */
-#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
-#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
-#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
-#define TIMG_NTIMGS_DATE_S  0
-
-/** TIMG_REGCLK_REG register
- *  Timer group clock gate register
- */
-#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
-/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
- *  enable timer's etm task and event
- */
-#define TIMG_ETM_EN    (BIT(28))
-#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
-#define TIMG_ETM_EN_V  0x00000001U
-#define TIMG_ETM_EN_S  28
-/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
- *  Registers can not be read or written to by software.
- */
-#define TIMG_CLK_EN    (BIT(31))
-#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
-#define TIMG_CLK_EN_V  0x00000001U
-#define TIMG_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h
deleted file mode 100644
index 363dff92d1..0000000000
--- a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: T0 Control and configuration registers */
-/** Type of txconfig register
- *  Timer x configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
-         *  When set, the alarm is enabled. This bit is automatically cleared once an
-         *  alarm occurs.
-         */
-        uint32_t tx_alarm_en:1;
-        uint32_t reserved_11:1;
-        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
-         *  When set, Timer x 's clock divider counter will be reset.
-         */
-        uint32_t tx_divcnt_rst:1;
-        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
-         *  Timer x clock (Tx_clk) prescaler value.
-         */
-        uint32_t tx_divider:16;
-        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
-         *  When set, timer x auto-reload at alarm is enabled.
-         */
-        uint32_t tx_autoreload:1;
-        /** tx_increase : R/W; bitpos: [30]; default: 1;
-         *  When set, the timer x time-base counter will increment every clock tick. When
-         *  cleared, the timer x time-base counter will decrement.
-         */
-        uint32_t tx_increase:1;
-        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
-         *  When set, the timer x time-base counter is enabled.
-         */
-        uint32_t tx_en:1;
-    };
-    uint32_t val;
-} timg_txconfig_reg_t;
-
-/** Type of txlo register
- *  Timer x current value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_lo : RO; bitpos: [31:0]; default: 0;
-         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
-         *  of timer x can be read here.
-         */
-        uint32_t tx_lo:32;
-    };
-    uint32_t val;
-} timg_txlo_reg_t;
-
-/** Type of txhi register
- *  Timer x current value, high 22 bits
- */
-typedef union {
-    struct {
-        /** tx_hi : RO; bitpos: [21:0]; default: 0;
-         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
-         *  of timer x can be read here.
-         */
-        uint32_t tx_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txhi_reg_t;
-
-/** Type of txupdate register
- *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
-         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
-         */
-        uint32_t tx_update:1;
-    };
-    uint32_t val;
-} timg_txupdate_reg_t;
-
-/** Type of txalarmlo register
- *  Timer x alarm value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
-         *  Timer x alarm trigger time-base counter value, low 32 bits.
-         */
-        uint32_t tx_alarm_lo:32;
-    };
-    uint32_t val;
-} timg_txalarmlo_reg_t;
-
-/** Type of txalarmhi register
- *  Timer x alarm value, high bits
- */
-typedef union {
-    struct {
-        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
-         *  Timer x alarm trigger time-base counter value, high 22 bits.
-         */
-        uint32_t tx_alarm_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txalarmhi_reg_t;
-
-/** Type of txloadlo register
- *  Timer x reload value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
-         *  Low 32 bits of the value that a reload will load onto timer x time-base
-         *  Counter.
-         */
-        uint32_t tx_load_lo:32;
-    };
-    uint32_t val;
-} timg_txloadlo_reg_t;
-
-/** Type of txloadhi register
- *  Timer x reload value, high 22 bits
- */
-typedef union {
-    struct {
-        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
-         *  High 22 bits of the value that a reload will load onto timer x time-base
-         *  counter.
-         */
-        uint32_t tx_load_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txloadhi_reg_t;
-
-/** Type of txload register
- *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
- */
-typedef union {
-    struct {
-        /** tx_load : WT; bitpos: [31:0]; default: 0;
-         *
-         *  Write any value to trigger a timer x time-base counter reload.
-         */
-        uint32_t tx_load:32;
-    };
-    uint32_t val;
-} timg_txload_reg_t;
-
-/** Group: WDT Control and configuration registers */
-/** Type of wdtconfig0 register
- *  Watchdog timer configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
-         *  WDT reset CPU enable.
-         */
-        uint32_t wdt_appcpu_reset_en:1;
-        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
-         *  WDT reset CPU enable.
-         */
-        uint32_t wdt_procpu_reset_en:1;
-        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
-         *  When set, Flash boot protection is enabled.
-         */
-        uint32_t wdt_flashboot_mod_en:1;
-        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
-         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
-         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
-         */
-        uint32_t wdt_sys_reset_length:3;
-        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
-         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
-         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
-         */
-        uint32_t wdt_cpu_reset_length:3;
-        uint32_t reserved_21:1;
-        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
-         *  update the WDT configuration registers
-         */
-        uint32_t wdt_conf_update_en:1;
-        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
-         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg3:2;
-        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
-         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg2:2;
-        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
-         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg1:2;
-        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
-         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg0:2;
-        /** wdt_en : R/W; bitpos: [31]; default: 0;
-         *  When set, MWDT is enabled.
-         */
-        uint32_t wdt_en:1;
-    };
-    uint32_t val;
-} timg_wdtconfig0_reg_t;
-
-/** Type of wdtconfig1 register
- *  Watchdog timer prescaler register
- */
-typedef union {
-    struct {
-        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
-         *  When set, WDT 's clock divider counter will be reset.
-         */
-        uint32_t wdt_divcnt_rst:1;
-        uint32_t reserved_1:15;
-        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
-         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
-         *  TIMG_WDT_CLK_PRESCALE.
-         */
-        uint32_t wdt_clk_prescale:16;
-    };
-    uint32_t val;
-} timg_wdtconfig1_reg_t;
-
-/** Type of wdtconfig2 register
- *  Watchdog timer stage 0 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
-         *  Stage 0 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg0_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig2_reg_t;
-
-/** Type of wdtconfig3 register
- *  Watchdog timer stage 1 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
-         *  Stage 1 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg1_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig3_reg_t;
-
-/** Type of wdtconfig4 register
- *  Watchdog timer stage 2 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
-         *  Stage 2 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg2_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig4_reg_t;
-
-/** Type of wdtconfig5 register
- *  Watchdog timer stage 3 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
-         *  Stage 3 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg3_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig5_reg_t;
-
-/** Type of wdtfeed register
- *  Write to feed the watchdog timer
- */
-typedef union {
-    struct {
-        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
-         *  Write any value to feed the MWDT. (WO)
-         */
-        uint32_t wdt_feed:32;
-    };
-    uint32_t val;
-} timg_wdtfeed_reg_t;
-
-/** Type of wdtwprotect register
- *  Watchdog write protect register
- */
-typedef union {
-    struct {
-        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
-         *  If the register contains a different value than its reset value, write
-         *  protection is enabled.
-         */
-        uint32_t wdt_wkey:32;
-    };
-    uint32_t val;
-} timg_wdtwprotect_reg_t;
-
-
-/** Group: RTC CALI Control and configuration registers */
-/** Type of rtccalicfg register
- *  RTC calibration configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
-         *  0: one-shot frequency calculation,1: periodic frequency calculation,
-         */
-        uint32_t rtc_cali_start_cycling:1;
-        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
-         */
-        uint32_t rtc_cali_clk_sel:2;
-        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
-         *  indicate one-shot frequency calculation is done.
-         */
-        uint32_t rtc_cali_rdy:1;
-        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
-         *  Configure the time to calculate RTC slow clock's frequency.
-         */
-        uint32_t rtc_cali_max:15;
-        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start one-shot frequency calculation.
-         */
-        uint32_t rtc_cali_start:1;
-    };
-    uint32_t val;
-} timg_rtccalicfg_reg_t;
-
-/** Type of rtccalicfg1 register
- *  RTC calibration configure1 register
- */
-typedef union {
-    struct {
-        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
-         *  indicate periodic frequency calculation is done.
-         */
-        uint32_t rtc_cali_cycling_data_vld:1;
-        uint32_t reserved_1:6;
-        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
-         *  When one-shot or periodic frequency calculation is done, read this value to
-         *  calculate RTC slow clock's frequency.
-         */
-        uint32_t rtc_cali_value:25;
-    };
-    uint32_t val;
-} timg_rtccalicfg1_reg_t;
-
-/** Type of rtccalicfg2 register
- *  Timer group calibration register
- */
-typedef union {
-    struct {
-        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
-         *  RTC calibration timeout indicator
-         */
-        uint32_t rtc_cali_timeout:1;
-        uint32_t reserved_1:2;
-        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
-         *  Cycles that release calibration timeout reset
-         */
-        uint32_t rtc_cali_timeout_rst_cnt:4;
-        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
-         *  Threshold value for the RTC calibration timer. If the calibration timer's value
-         *  exceeds this threshold, a timeout is triggered.
-         */
-        uint32_t rtc_cali_timeout_thres:25;
-    };
-    uint32_t val;
-} timg_rtccalicfg2_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_ena_timers register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_ena:1;
-        /** t1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t1_int_ena:1;
-        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_ena_timers_reg_t;
-
-/** Type of int_raw_timers register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_raw:1;
-        /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t1_int_raw:1;
-        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_raw_timers_reg_t;
-
-/** Type of int_st_timers register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** t0_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_st:1;
-        /** t1_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t1_int_st:1;
-        /** wdt_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_st_timers_reg_t;
-
-/** Type of int_clr_timers register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** t0_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_clr:1;
-        /** t1_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t1_int_clr:1;
-        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_clr_timers_reg_t;
-
-
-/** Group: Version register */
-/** Type of ntimers_date register
- *  Timer version control register
- */
-typedef union {
-    struct {
-        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
-         *  Timer version control register
-         */
-        uint32_t ntimgs_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} timg_ntimers_date_reg_t;
-
-
-/** Group: Clock configuration registers */
-/** Type of regclk register
- *  Timer group clock gate register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** etm_en : R/W; bitpos: [28]; default: 1;
-         *  enable timer's etm task and event
-         */
-        uint32_t etm_en:1;
-        uint32_t reserved_29:2;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
-         *  Registers can not be read or written to by software.
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} timg_regclk_reg_t;
-
-
-typedef struct {
-    volatile timg_txconfig_reg_t t0config;
-    volatile timg_txlo_reg_t t0lo;
-    volatile timg_txhi_reg_t t0hi;
-    volatile timg_txupdate_reg_t t0update;
-    volatile timg_txalarmlo_reg_t t0alarmlo;
-    volatile timg_txalarmhi_reg_t t0alarmhi;
-    volatile timg_txloadlo_reg_t t0loadlo;
-    volatile timg_txloadhi_reg_t t0loadhi;
-    volatile timg_txload_reg_t t0load;
-    volatile timg_txconfig_reg_t t1config;
-    volatile timg_txlo_reg_t t1lo;
-    volatile timg_txhi_reg_t t1hi;
-    volatile timg_txupdate_reg_t t1update;
-    volatile timg_txalarmlo_reg_t t1alarmlo;
-    volatile timg_txalarmhi_reg_t t1alarmhi;
-    volatile timg_txloadlo_reg_t t1loadlo;
-    volatile timg_txloadhi_reg_t t1loadhi;
-    volatile timg_txload_reg_t t1load;
-    volatile timg_wdtconfig0_reg_t wdtconfig0;
-    volatile timg_wdtconfig1_reg_t wdtconfig1;
-    volatile timg_wdtconfig2_reg_t wdtconfig2;
-    volatile timg_wdtconfig3_reg_t wdtconfig3;
-    volatile timg_wdtconfig4_reg_t wdtconfig4;
-    volatile timg_wdtconfig5_reg_t wdtconfig5;
-    volatile timg_wdtfeed_reg_t wdtfeed;
-    volatile timg_wdtwprotect_reg_t wdtwprotect;
-    volatile timg_rtccalicfg_reg_t rtccalicfg;
-    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
-    volatile timg_int_ena_timers_reg_t int_ena_timers;
-    volatile timg_int_raw_timers_reg_t int_raw_timers;
-    volatile timg_int_st_timers_reg_t int_st_timers;
-    volatile timg_int_clr_timers_reg_t int_clr_timers;
-    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
-    uint32_t reserved_084[29];
-    volatile timg_ntimers_date_reg_t ntimers_date;
-    volatile timg_regclk_reg_t regclk;
-} timg_dev_t;
-
-extern timg_dev_t TIMERG0;
-extern timg_dev_t TIMERG1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h
index 7df8a1271f..c260234634 100644
--- a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h
+++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h
@@ -11,7 +11,7 @@
 extern "C" {
 #endif
 
-// TODO: IDF-13422
+#define REG_TIMG_BASE(i)     (DR_REG_TIMG0_BASE + (i) * 0x1000)
 
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h
index 1189b1d491..1f2b1535dd 100644
--- a/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h
+++ b/components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h
@@ -10,8 +10,6 @@
 extern "C" {
 #endif
 
-// TODO: IDF-13422
-
 /** Group: T0 Control and configuration registers */
 /** Type of txconfig register
  *  Timer x configuration register