From 36d0e275a077c4df4337200b96d866af420d214c Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 13 Feb 2023 12:36:51 +0700 Subject: [PATCH] hal: always inline clk_tree_ll functions --- .../hal/esp32/include/hal/clk_tree_ll.h | 66 +++++++++---------- .../hal/esp32c2/include/hal/clk_tree_ll.h | 50 +++++++------- .../hal/esp32c3/include/hal/clk_tree_ll.h | 52 +++++++-------- .../hal/esp32c6/include/hal/clk_tree_ll.h | 56 ++++++++-------- .../hal/esp32h2/include/hal/clk_tree_ll.h | 66 +++++++++---------- .../hal/esp32h4/include/hal/clk_tree_ll.h | 48 +++++++------- .../hal/esp32s2/include/hal/clk_tree_ll.h | 64 +++++++++--------- .../hal/esp32s3/include/hal/clk_tree_ll.h | 50 +++++++------- 8 files changed, 226 insertions(+), 226 deletions(-) diff --git a/components/hal/esp32/include/hal/clk_tree_ll.h b/components/hal/esp32/include/hal/clk_tree_ll.h index d6a15c2bed..79ea9fc003 100644 --- a/components/hal/esp32/include/hal/clk_tree_ll.h +++ b/components/hal/esp32/include/hal/clk_tree_ll.h @@ -127,7 +127,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Power up APLL circuit */ -static inline void clk_ll_apll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -136,7 +136,7 @@ static inline void clk_ll_apll_enable(void) /** * @brief Power down APLL circuit */ -static inline void clk_ll_apll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -147,7 +147,7 @@ static inline void clk_ll_apll_disable(void) * * @return True if APLL is under force power down; otherwise false */ -static inline bool clk_ll_apll_is_fpd(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_is_fpd(void) { return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); } @@ -160,7 +160,7 @@ static inline bool clk_ll_apll_is_fpd(void) * @param[out] sdm1 Frequency adjustment parameter, 0..255 * @param[out] sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) { *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV); *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0); @@ -177,7 +177,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3 * @param sdm1 Frequency adjustment parameter, 0..255 * @param sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { uint8_t sdm_stop_val_2 = CLK_LL_APLL_SDM_STOP_VAL_2_REV1; if (is_rev0) { @@ -196,7 +196,7 @@ static inline void clk_ll_apll_set_config(bool is_rev0, uint32_t o_div, uint32_t /** * @brief Set APLL calibration parameters */ -static inline void clk_ll_apll_set_calibration(void) +static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void) { REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1); REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2); @@ -208,7 +208,7 @@ static inline void clk_ll_apll_set_calibration(void) * * @return True if calibration is done; otherwise false */ -static inline bool clk_ll_apll_calibration_is_done(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void) { return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END); } @@ -218,7 +218,7 @@ static inline bool clk_ll_apll_calibration_is_done(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k // Default mode as CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL @@ -244,7 +244,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd status CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M); @@ -255,7 +255,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K); } @@ -283,7 +283,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -296,7 +296,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -307,7 +307,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -317,7 +317,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -325,7 +325,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -333,7 +333,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -343,7 +343,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -351,7 +351,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -359,7 +359,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -367,7 +367,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -375,7 +375,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -385,7 +385,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -395,7 +395,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) * * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. */ -static inline uint32_t clk_ll_bbpll_get_freq_mhz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void) { // ESP32 BBPLL frequency is determined by the cpu freq sel uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); @@ -641,7 +641,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @return Divider. Returns 0 means invalid. */ -static inline uint32_t clk_ll_cpu_get_divider_from_apll(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void) { // APLL path divider choice shares the same register with CPUPERIOD_SEL uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); @@ -695,7 +695,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -718,7 +718,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -739,7 +739,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D4: @@ -759,7 +759,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -788,7 +788,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -804,7 +804,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -857,7 +857,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -875,7 +875,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -887,7 +887,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32c2/include/hal/clk_tree_ll.h b/components/hal/esp32c2/include/hal/clk_tree_ll.h index 3329f4dd07..169056a628 100644 --- a/components/hal/esp32c2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c2/include/hal/clk_tree_ll.h @@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -95,7 +95,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -106,7 +106,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -116,7 +116,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -124,7 +124,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -132,7 +132,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -142,7 +142,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -150,7 +150,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -158,7 +158,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -166,7 +166,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -174,7 +174,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -184,7 +184,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -388,7 +388,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -411,7 +411,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -432,7 +432,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -452,7 +452,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -470,7 +470,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -483,7 +483,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -493,7 +493,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -512,7 +512,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -583,7 +583,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -595,7 +595,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } @@ -605,7 +605,7 @@ static inline uint32_t clk_ll_rtc_slow_load_cal(void) * * @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes */ -static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) { REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us); REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32); @@ -616,7 +616,7 @@ static inline void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us) * * @return The value used to correct the time obtained from the rtc timer when the calibration value changes */ -static inline uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) +static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void) { return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32); } diff --git a/components/hal/esp32c3/include/hal/clk_tree_ll.h b/components/hal/esp32c3/include/hal/clk_tree_ll.h index 1eec6acfd6..57cd49fcdf 100644 --- a/components/hal/esp32c3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c3/include/hal/clk_tree_ll.h @@ -81,7 +81,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -100,7 +100,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -148,7 +148,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -161,7 +161,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -172,7 +172,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -182,7 +182,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -190,7 +190,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -198,7 +198,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -208,7 +208,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -216,7 +216,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -224,7 +224,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -232,7 +232,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -240,7 +240,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -250,7 +250,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -495,7 +495,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -518,7 +518,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -539,7 +539,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -559,7 +559,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -577,7 +577,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -590,7 +590,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -600,7 +600,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -619,7 +619,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -672,7 +672,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -690,7 +690,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -702,7 +702,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h index afa24bea94..8f8cfaa5ae 100644 --- a/components/hal/esp32c6/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c6/include/hal/clk_tree_ll.h @@ -83,7 +83,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { // No need to configure anything for OSC_SLOW_CLK @@ -102,7 +102,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); @@ -113,7 +113,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } @@ -121,7 +121,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Enable rc32k xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -130,7 +130,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Disable rc32k xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -141,7 +141,7 @@ static inline void clk_ll_rc32k_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; } @@ -167,7 +167,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; } @@ -175,7 +175,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 1; } @@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 0; } @@ -193,7 +193,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_fosc; } @@ -201,7 +201,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1; } @@ -209,7 +209,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0; } @@ -219,7 +219,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } @@ -227,7 +227,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; } @@ -235,7 +235,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; } @@ -245,7 +245,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_osc32k; } @@ -566,7 +566,7 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide * * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) */ -static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC32K: @@ -589,7 +589,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s * * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) */ -static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) { uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; switch (clk_sel) { @@ -609,7 +609,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -635,7 +635,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; switch (clk_sel) { @@ -657,7 +657,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_RC_FAST: @@ -677,7 +677,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; switch (clk_sel) { @@ -695,7 +695,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { // No divider on the target, always return divider = 1 return 1; @@ -717,7 +717,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -734,7 +734,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -773,7 +773,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -785,7 +785,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32h2/include/hal/clk_tree_ll.h b/components/hal/esp32h2/include/hal/clk_tree_ll.h index 19d3d1983a..236cc9f6c3 100644 --- a/components/hal/esp32h2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h2/include/hal/clk_tree_ll.h @@ -80,7 +80,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Enable the internal oscillator output for LP_PLL_CLK */ -static inline void clk_ll_lp_pll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_enable(void) { // Enable lp_pll xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL); @@ -89,7 +89,7 @@ static inline void clk_ll_lp_pll_enable(void) /** * @brief Disable the internal oscillator output for LP_PLL_CLK */ -static inline void clk_ll_lp_pll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void) { // Disable lp_pll xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL); @@ -100,7 +100,7 @@ static inline void clk_ll_lp_pll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { // No need to configure anything for OSC_SLOW_CLK @@ -119,7 +119,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Disable xtal32k xpd CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); @@ -130,7 +130,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; } @@ -138,7 +138,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Enable rc32k xpd status SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -147,7 +147,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Disable rc32k xpd status CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); @@ -158,7 +158,7 @@ static inline void clk_ll_rc32k_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; } @@ -184,7 +184,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; } @@ -192,7 +192,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 1; } @@ -200,7 +200,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_fosc = 0; } @@ -210,7 +210,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_fosc; } @@ -218,7 +218,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1; } @@ -226,7 +226,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0; } @@ -236,7 +236,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; } @@ -244,7 +244,7 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; } @@ -252,7 +252,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; } @@ -262,7 +262,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return LP_CLKRST.clk_to_hp.icg_hp_osc32k; } @@ -455,7 +455,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi * * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) */ -static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC32K: @@ -478,7 +478,7 @@ static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_s * * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) */ -static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) { uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; switch (clk_sel) { @@ -498,7 +498,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; switch (clk_sel) { @@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_lp_pll_clk_src_t */ -static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) { uint32_t field_value; switch (in_sel) { @@ -568,7 +568,7 @@ static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_lp_pll_clk_src_t values) */ -static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) +static inline __attribute__((always_inline)) soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) { uint32_t clk_sel = REGI2C_READ_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF); switch (clk_sel) { @@ -586,7 +586,7 @@ static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void) * * @return LP_PLL clock frequency, in MHz */ -static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_lp_pll_get_freq_mhz(void) { // The target has a fixed 8MHz LP_PLL return CLK_LL_PLL_8M_FREQ_MHZ; @@ -597,7 +597,7 @@ static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_RC_FAST: @@ -620,7 +620,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; switch (clk_sel) { @@ -640,7 +640,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -651,7 +651,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { // No divider on the target, always return divider = 1 return 1; @@ -662,7 +662,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { // No divider on the target HAL_ASSERT(divider == 1); @@ -679,7 +679,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -718,7 +718,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -730,7 +730,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32h4/include/hal/clk_tree_ll.h b/components/hal/esp32h4/include/hal/clk_tree_ll.h index 24adea1c0a..6afa9205a9 100644 --- a/components/hal/esp32h4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h4/include/hal/clk_tree_ll.h @@ -77,7 +77,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k (or only for mode == CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL?) clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -96,7 +96,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -109,7 +109,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -124,7 +124,7 @@ static inline bool clk_ll_xtal32k_is_enabled(void) /** * @brief Enable the internal oscillator output for RC32K_CLK */ -static inline void clk_ll_rc32k_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) { // Configure rc32k REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); @@ -135,7 +135,7 @@ static inline void clk_ll_rc32k_enable(void) /** * @brief Disable the internal oscillator output for RC32k_CLK */ -static inline void clk_ll_rc32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) { // Configure rc32k REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); @@ -146,7 +146,7 @@ static inline void clk_ll_rc32k_disable(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -154,7 +154,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -164,7 +164,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -172,7 +172,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); } @@ -180,7 +180,7 @@ static inline void clk_ll_rc32k_digi_enable(void) /** * @brief Disable the digital RC32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); } @@ -190,7 +190,7 @@ static inline void clk_ll_rc32k_digi_disable(void) * * @return True if the digital RC32K_CLK is enabled */ -static inline bool clk_ll_rc32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN); } @@ -198,7 +198,7 @@ static inline bool clk_ll_rc32k_digi_is_enabled(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -206,7 +206,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -216,7 +216,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -383,7 +383,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -406,7 +406,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -427,7 +427,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -447,7 +447,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -465,7 +465,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -478,7 +478,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -488,7 +488,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -507,7 +507,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -558,7 +558,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -570,7 +570,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32s2/include/hal/clk_tree_ll.h b/components/hal/esp32s2/include/hal/clk_tree_ll.h index ae4b9f0b96..f7d67937ee 100644 --- a/components/hal/esp32s2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s2/include/hal/clk_tree_ll.h @@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) /** * @brief Power up APLL circuit */ -static inline void clk_ll_apll_enable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -103,7 +103,7 @@ static inline void clk_ll_apll_enable(void) /** * @brief Power down APLL circuit */ -static inline void clk_ll_apll_disable(void) +static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); @@ -117,7 +117,7 @@ static inline void clk_ll_apll_disable(void) * @param[out] sdm1 Frequency adjustment parameter, 0..255 * @param[out] sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2) { *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV); *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0); @@ -133,7 +133,7 @@ static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint3 * @param sdm1 Frequency adjustment parameter, 0..255 * @param sdm2 Frequency adjustment parameter, 0..63 */ -static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) +static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2) { REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2); REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0); @@ -146,7 +146,7 @@ static inline void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_ /** * @brief Set APLL calibration parameters */ -static inline void clk_ll_apll_set_calibration(void) +static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void) { REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1); REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2); @@ -158,7 +158,7 @@ static inline void clk_ll_apll_set_calibration(void) * * @return True if calibration is done; otherwise false */ -static inline bool clk_ll_apll_calibration_is_done(void) +static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void) { return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END); } @@ -168,7 +168,7 @@ static inline bool clk_ll_apll_calibration_is_done(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -187,7 +187,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -200,7 +200,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -235,7 +235,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -248,7 +248,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -259,7 +259,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -269,7 +269,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -277,7 +277,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -285,7 +285,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -295,7 +295,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -303,7 +303,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -311,7 +311,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -319,7 +319,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -327,7 +327,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -337,7 +337,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -565,7 +565,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @return Divider. Returns 0 means invalid. */ -static inline uint32_t clk_ll_cpu_get_divider_from_apll(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider_from_apll(void) { // APLL path divider choice depends on PLL_FREQ_SEL and CPUPERIOD_SEL uint32_t pll_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); @@ -611,7 +611,7 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -634,7 +634,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -655,7 +655,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D4: @@ -675,7 +675,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -693,7 +693,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -706,7 +706,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -716,7 +716,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -747,7 +747,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint3 * * @return The stored APB frequency, in Hz */ -static inline uint32_t clk_ll_apb_load_freq_hz(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_load_freq_hz(void) { // Read from RTC storage register uint32_t apb_freq_hz = (READ_PERI_REG(RTC_APB_FREQ_REG) & UINT16_MAX) << 12; @@ -765,7 +765,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void) * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -777,7 +777,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); } diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h index c247c36b3f..c2534134a7 100644 --- a/components/hal/esp32s3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s3/include/hal/clk_tree_ll.h @@ -82,7 +82,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) * * @param mode Used to determine the xtal32k configuration parameters */ -static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) { // Configure xtal32k clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); @@ -101,7 +101,7 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) /** * @brief Disable the 32kHz crystal oscillator */ -static inline void clk_ll_xtal32k_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) { // Set xtal32k xpd to be controlled by software SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); @@ -114,7 +114,7 @@ static inline void clk_ll_xtal32k_disable(void) * * @return True if the 32kHz XTAL is enabled */ -static inline bool clk_ll_xtal32k_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) { uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); /* If xtal xpd is controlled by software */ @@ -149,7 +149,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) * * @return True if the oscillator is enabled */ -static inline bool clk_ll_rc_fast_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; } @@ -162,7 +162,7 @@ static inline bool clk_ll_rc_fast_is_enabled(void) * so is not exposed in the code. * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. */ -static inline void clk_ll_rc_fast_d256_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_enable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -173,7 +173,7 @@ static inline void clk_ll_rc_fast_d256_enable(void) * * Disabling this divider could reduce power consumption. */ -static inline void clk_ll_rc_fast_d256_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_disable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } @@ -183,7 +183,7 @@ static inline void clk_ll_rc_fast_d256_disable(void) * * @return True if the divided output is enabled */ -static inline bool clk_ll_rc_fast_d256_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_d256_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } @@ -191,7 +191,7 @@ static inline bool clk_ll_rc_fast_d256_is_enabled(void) /** * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -199,7 +199,7 @@ static inline void clk_ll_rc_fast_digi_enable(void) /** * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -209,7 +209,7 @@ static inline void clk_ll_rc_fast_digi_disable(void) * * @return True if the digital RC_FAST_CLK is enabled */ -static inline bool clk_ll_rc_fast_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) { return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); } @@ -217,7 +217,7 @@ static inline bool clk_ll_rc_fast_digi_is_enabled(void) /** * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -225,7 +225,7 @@ static inline void clk_ll_rc_fast_d256_digi_enable(void) /** * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. */ -static inline void clk_ll_rc_fast_d256_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_d256_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); } @@ -233,7 +233,7 @@ static inline void clk_ll_rc_fast_d256_digi_disable(void) /** * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_enable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -241,7 +241,7 @@ static inline void clk_ll_xtal32k_digi_enable(void) /** * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. */ -static inline void clk_ll_xtal32k_digi_disable(void) +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); } @@ -251,7 +251,7 @@ static inline void clk_ll_xtal32k_digi_disable(void) * * @return True if the digital XTAL32K_CLK is enabled */ -static inline bool clk_ll_xtal32k_digi_is_enabled(void) +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); } @@ -501,7 +501,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi * * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t */ -static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: @@ -524,7 +524,7 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) */ -static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); switch (clk_sel) { @@ -546,7 +546,7 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) * * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t */ -static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) { switch (in_sel) { case SOC_RTC_FAST_CLK_SRC_XTAL_D2: @@ -566,7 +566,7 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) * * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) */ -static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) { uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); switch (clk_sel) { @@ -584,7 +584,7 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) * * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); @@ -597,7 +597,7 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider) * * @return Divider. Divider = (CK8M_DIV_SEL + 1). */ -static inline uint32_t clk_ll_rc_fast_get_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; } @@ -607,7 +607,7 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void) * * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. */ -static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) { HAL_ASSERT(divider > 0); CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); @@ -626,7 +626,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider) * otherwise there will be a conflict with the low bit, which is used to disable logs * in the ROM code. */ -static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) { // Read the status of whether disabling logging from ROM code uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; @@ -665,7 +665,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz( * * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) { REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); } @@ -677,7 +677,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) * * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format */ -static inline uint32_t clk_ll_rtc_slow_load_cal(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) { return REG_READ(RTC_SLOW_CLK_CAL_REG); }