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feat(system): updated H4 reset reasons

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This commit is contained in:
Marius Vikhammer
2025-07-09 17:09:58 +08:00
parent dee2895ab4
commit 374b31049b
3 changed files with 15 additions and 4 deletions
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5
components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h
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@@ -81,7 +81,6 @@ typedef enum {
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/
@@ -92,10 +91,12 @@ typedef enum {
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset*/
EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
CPU_LOCKUP_RESET = 25, /**<25, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -112,10 +113,12 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_CORE_PWR_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
typedef enum {
NO_SLEEP = 0,

10
components/esp_system/port/soc/esp32h4/reset_reason.c
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@@ -10,7 +10,6 @@
#include "soc/rtc_periph.h"
#include "esp32h4/rom/rtc.h"
// TODO: [ESP32H4] IDF-12307 inherited from verification branch, need check
// IDF-11910 need refactor
static void esp_reset_reason_clear_hint(void);
@@ -53,10 +52,19 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case RESET_REASON_CORE_PWR_GLITCH:
return ESP_RST_PWR_GLITCH;
case RESET_REASON_CORE_EFUSE_CRC:
return ESP_RST_EFUSE;
case RESET_REASON_CORE_USB_UART:
case RESET_REASON_CORE_USB_JTAG:
return ESP_RST_USB;
case RESET_REASON_CPU_LOCKUP:
return ESP_RST_CPU_LOCKUP;
default:
return ESP_RST_UNKNOWN;
}

4
components/soc/esp32h4/include/soc/reset_reasons.h
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@@ -22,8 +22,6 @@
extern "C" {
#endif
//TODO: [ESP32H4] IDF-12307 inherit from verify code, need check
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
@@ -43,10 +41,12 @@ typedef enum {
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_CORE_PWR_GLITCH = 0x13, // Glitch on power resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system)
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
RESET_REASON_CPU_LOCKUP = 0x19, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
} soc_reset_reason_t;
#ifdef __cplusplus