mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-03 20:54:32 +02:00
fix(esp_system): force enable uart0 sclk in esp_restart
This commit is contained in:
@@ -22,6 +22,7 @@
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#include "soc/rtc_periph.h"
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#include "soc/uart_reg.h"
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#include "hal/wdt_hal.h"
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#include "hal/uart_ll.h"
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#if SOC_MODEM_CLOCK_SUPPORTED
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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@@ -78,6 +79,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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// UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
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// it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
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uart_ll_sclk_enable(&UART0);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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@@ -20,6 +20,7 @@
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#include "esp_private/rtc_clk.h"
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#include "soc/rtc_periph.h"
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#include "soc/uart_reg.h"
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#include "hal/uart_ll.h"
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#include "hal/wdt_hal.h"
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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@@ -75,6 +76,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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// UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
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// it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
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uart_ll_sclk_enable(&UART0);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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@@ -20,6 +20,7 @@
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#include "esp_private/rtc_clk.h"
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#include "soc/rtc_periph.h"
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#include "soc/uart_reg.h"
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#include "hal/uart_ll.h"
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#include "hal/wdt_hal.h"
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#include "esp_private/cache_err_int.h"
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@@ -78,6 +79,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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// UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
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// it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
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uart_ll_sclk_enable(&UART0);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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@@ -23,6 +23,7 @@
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#include "soc/uart_reg.h"
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#include "hal/wdt_hal.h"
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#include "hal/spimem_flash_ll.h"
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#include "hal/uart_ll.h"
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#include "esp_private/cache_err_int.h"
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#include "esp_private/mspi_timing_tuning.h"
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@@ -73,6 +74,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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// UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
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// it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
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uart_ll_sclk_enable(&UART0);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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