From 37ed3e090412aba44bea1468a9b411df0169fe89 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 26 Sep 2025 19:05:56 +0800 Subject: [PATCH] ci(i2s): fixed occationally failure on P4 read write case can sometimes failed due to the low frequency of the default I2S clock source on P4. --- components/esp_driver_i2s/i2s_common.c | 5 +++++ .../esp_driver_i2s/test_apps/i2s/main/test_i2s.c | 6 +++--- components/hal/esp32p4/include/hal/i2s_ll.h | 13 ++++++++++++- components/soc/esp32p4/include/soc/clk_tree_defs.h | 2 +- 4 files changed, 21 insertions(+), 5 deletions(-) diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 96c8b053b0..27042989ae 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -563,6 +563,11 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) if (clk_src == I2S_CLK_SRC_APLL) { return i2s_set_get_apll_freq(mclk_freq_hz); } +#endif +#ifdef I2S_LL_DEFAULT_CLK_SRC + if (clk_src == I2S_CLK_SRC_DEFAULT) { + clk_src = I2S_LL_DEFAULT_CLK_SRC; + } #endif esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq); return clk_freq; diff --git a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c index 91386590c4..115606d69d 100644 --- a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c +++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c @@ -741,7 +741,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]") TEST_ESP_OK(i2s_del_channel(rx_handle)); } -#if SOC_I2S_NUM > 1 +#if SOC_I2S_NUM > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 TEST_CASE("I2S_master_write_slave_read_test", "[i2s]") { i2s_chan_handle_t tx_handle; @@ -907,8 +907,8 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]") TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle)); TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg)); -#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL >= 300 - std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_PLL_160M; +#ifdef I2S_LL_DEFAULT_CLK_SRC + std_cfg.clk_cfg.clk_src = I2S_LL_DEFAULT_CLK_SRC; #endif i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg); #if SOC_I2S_SUPPORTS_XTAL diff --git a/components/hal/esp32p4/include/hal/i2s_ll.h b/components/hal/esp32p4/include/hal/i2s_ll.h index 2e1353160e..e8b21cf4de 100644 --- a/components/hal/esp32p4/include/hal/i2s_ll.h +++ b/components/hal/esp32p4/include/hal/i2s_ll.h @@ -42,7 +42,14 @@ extern "C" { #define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 #define I2S_LL_XTAL_CLK_FREQ (40 * 1000000) // XTAL_CLK: 40MHz -#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define I2S_LL_DEFAULT_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz +#define I2S_LL_DEFAULT_CLK_SRC I2S_CLK_SRC_PLL_160M +#else +#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source before version 3, use XTAL as default +#define I2S_LL_DEFAULT_CLK_SRC I2S_CLK_SRC_XTAL +#endif + #define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event) \ (uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){ \ @@ -442,10 +449,14 @@ static inline uint32_t i2s_ll_get_clk_src(i2s_clock_src_t src) return 1; case I2S_CLK_SRC_EXTERNAL: return 2; + case I2S_CLK_SRC_DEFAULT: #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return 3; // Only support PLL_160M on P4 ver3 and later case I2S_CLK_SRC_PLL_160M: return 3; +#else + return 0; #endif default: HAL_ASSERT(false && "unsupported clock source"); diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index aab47bd819..94fe333253 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -350,7 +350,7 @@ typedef enum { * @brief I2S clock source enum */ typedef enum { - I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ + I2S_CLK_SRC_DEFAULT = 0, /*!< Auto select maximum clock source asdefault source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock (only supported on P4 hw_ver3) */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */