diff --git a/Kconfig b/Kconfig index d6b535b449..1325799097 100644 --- a/Kconfig +++ b/Kconfig @@ -72,6 +72,7 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_TARGET_ESP32H2_BETA_VERSION_2 bool prompt "ESP32-H2 beta2" + select ESPTOOLPY_NO_STUB # TODO: IDF-4288 endchoice config IDF_TARGET_ESP8684 @@ -92,8 +93,9 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x0002 if IDF_TARGET_ESP32S2 default 0x0005 if IDF_TARGET_ESP32C3 default 0x0009 if IDF_TARGET_ESP32S3 - default 0x000A if IDF_TARGET_ESP32H2 # ESP32H2-TODO: IDF-3475 default 0x000C if IDF_TARGET_ESP8684 + default 0x000A if IDF_TARGET_ESP32H2_BETA_VERSION_1 + default 0x000E if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3475 default 0xFFFF menu "SDK tool configuration" diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 2a1a08a33d..8733f1f3d2 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -16,8 +16,12 @@ typedef enum { ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */ ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */ - ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */ // ESP32H2-TODO: IDF-3475 ESP_CHIP_ID_ESP8684 = 0x000C, /*!< chip ID: ESP32-8684 */ +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 + ESP_CHIP_ID_ESP32H2 = 0x000E, /*!< chip ID: ESP32-H2 Beta2*/ // ESP32H2-TODO: IDF-3475 +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 + ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */ +#endif ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/esp_hw_support/port/esp32h2/rtc_sleep.c b/components/esp_hw_support/port/esp32h2/rtc_sleep.c index 2a30694de5..a0b75b5389 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32h2/rtc_sleep.c @@ -24,6 +24,18 @@ #include "soc_log.h" #include "esp_rom_uart.h" +#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 +#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG +#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG +#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 +#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG +#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG +#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG +#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG +#endif + /** * Configure whether certain peripherals are powered down in deep sleep * @param cfg power down flags as rtc_sleep_pu_config_t structure @@ -75,62 +87,34 @@ void dcdc_ctl(uint32_t mode) void regulator_set(regulator_cfg_t cfg) { -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 // DIG REGULATOR0 if (cfg.dig_regul0_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1); } // DIG REGULATOR1 if (cfg.dig_regul1_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0); } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1); } // RTC REGULATOR0 if (cfg.rtc_regul0_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0); } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1); } -#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 - // DIG REGULATOR0 - if (cfg.dig_regul0_en) { - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1); - } - // DIG REGULATOR1 - if (cfg.dig_regul1_en) { - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1); - } - // RTC REGULATOR0 - if (cfg.rtc_regul0_en) { - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1); - } -#endif } void regulator_slt(regulator_config_t regula_cfg) { -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 // dig regulator if (regula_cfg.dig_source == 1) { REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias); @@ -147,37 +131,13 @@ void regulator_slt(regulator_config_t regula_cfg) REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias); REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); } -#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 - // dig regulator - if (regula_cfg.dig_source == 1) { - REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias); - REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); - } else { - REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias); - REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); - } - // rtc regulator - if (regula_cfg.rtc_source == 1) { - REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias); - REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); - } else { - REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias); - REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); - } -#endif } void dbias_switch_set(dbias_swt_cfg_t cfg) { -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); -#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); -#endif + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); } void left_up_trx_fpu(bool fpu) @@ -240,37 +200,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); // ESP32-H2 TO-DO: IDF-3693 -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 if (cfg.deep_slp) { // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); + // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } else { - SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - // SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); + REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); + // SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } -#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 - if (cfg.deep_slp) { - // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - // CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, - RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | - RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); - } else { - SET_PERI_REG_MASK(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); - REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - // SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - } -#endif /* enable VDDSDIO control by state machine */ REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); diff --git a/components/esp_rom/eagle.pro.rom.out b/components/esp_rom/eagle.pro.rom.out deleted file mode 100755 index ccd13ee4e7..0000000000 Binary files a/components/esp_rom/eagle.pro.rom.out and /dev/null differ diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld index 588ac6b179..6c27a2dd01 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /** ROM APIs */ PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 ); diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld index fefad99c3d..7665ea5803 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32b1z.rom.ld for esp32b1z * * diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld index d70ed55864..49c7131938 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z * * diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld index e050b3c90c..953c20e02e 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z * * diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld index 7ba3b8c113..61b4b4715b 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z * * diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld index e2fe09a6df..46dd7a4b49 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM version variables for esp32b1z * * These addresses should be compatible with any ROM version for this chip. diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld index 588ac6b179..6c27a2dd01 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /** ROM APIs */ PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 ); diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld index 48952989e1..58573775ad 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld @@ -1,7 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32h2.rom.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 + * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -24,35 +30,36 @@ ets_install_putc1 = 0x40000034; ets_install_uart_printf = 0x40000038; ets_install_putc2 = 0x4000003c; PROVIDE( ets_delay_us = 0x40000040 ); -ets_get_stack_info = 0x40000044; -ets_install_lock = 0x40000048; -ets_backup_dma_copy = 0x4000004c; -ets_apb_backup_init_lock_func = 0x40000050; -UartRxString = 0x40000054; -uart_tx_one_char = 0x40000058; -uart_tx_one_char2 = 0x4000005c; -uart_rx_one_char = 0x40000060; -uart_rx_one_char_block = 0x40000064; -uart_rx_readbuff = 0x40000068; -uartAttach = 0x4000006c; -uart_tx_flush = 0x40000070; -uart_tx_wait_idle = 0x40000074; -uart_div_modify = 0x40000078; -multofup = 0x4000007c; -software_reset = 0x40000080; -software_reset_cpu = 0x40000084; -assist_debug_clock_enable = 0x40000088; -assist_debug_record_enable = 0x4000008c; -clear_super_wdt_reset_flag = 0x40000090; -disable_default_watchdog = 0x40000094; -esp_rom_set_rtc_wake_addr = 0x40000098; -esp_rom_get_rtc_wake_addr = 0x4000009c; -send_packet = 0x400000a0; -recv_packet = 0x400000a4; -GetUartDevice = 0x400000a8; -UartDwnLdProc = 0x400000ac; -Uart_Init = 0x400000b0; -ets_set_user_start = 0x400000b4; +ets_install_lock = 0x40000044; +ets_backup_dma_copy = 0x40000048; +ets_apb_backup_init_lock_func = 0x4000004c; +UartRxString = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_rx_one_char = 0x4000005c; +uart_rx_one_char_block = 0x40000060; +uart_rx_readbuff = 0x40000064; +uartAttach = 0x40000068; +uart_tx_flush = 0x4000006c; +uart_tx_wait_idle = 0x40000070; +uart_div_modify = 0x40000074; +ets_write_char_uart = 0x40000078; +uart_tx_switch = 0x4000007c; +multofup = 0x40000080; +software_reset = 0x40000084; +software_reset_cpu = 0x40000088; +assist_debug_clock_enable = 0x4000008c; +assist_debug_record_enable = 0x40000090; +clear_super_wdt_reset_flag = 0x40000094; +disable_default_watchdog = 0x40000098; +esp_rom_set_rtc_wake_addr = 0x4000009c; +esp_rom_get_rtc_wake_addr = 0x400000a0; +send_packet = 0x400000a4; +recv_packet = 0x400000a8; +GetUartDevice = 0x400000ac; +UartDwnLdProc = 0x400000b0; +Uart_Init = 0x400000b4; +ets_set_user_start = 0x400000b8; /* Data (.data, .bss, .rodata) */ ets_rom_layout_p = 0x3ff1fffc; ets_ops_table_ptr = 0x3fcdfffc; @@ -63,31 +70,22 @@ ets_ops_table_ptr = 0x3fcdfffc; ***************************************/ /* Functions */ -mz_adler32 = 0x400000b8; -mz_free = 0x400000bc; -tdefl_compress = 0x400000c0; -tdefl_compress_buffer = 0x400000c4; -tdefl_compress_mem_to_heap = 0x400000c8; -tdefl_compress_mem_to_mem = 0x400000cc; -tdefl_compress_mem_to_output = 0x400000d0; -tdefl_get_adler32 = 0x400000d4; -tdefl_get_prev_return_status = 0x400000d8; -tdefl_init = 0x400000dc; -tdefl_write_image_to_png_file_in_memory = 0x400000e0; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000e4; -tinfl_decompress = 0x400000e8; -tinfl_decompress_mem_to_callback = 0x400000ec; -tinfl_decompress_mem_to_heap = 0x400000f0; -tinfl_decompress_mem_to_mem = 0x400000f4; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -jd_prepare = 0x400000f8; -jd_decomp = 0x400000fc; +mz_adler32 = 0x400000bc; +mz_free = 0x400000c0; +tdefl_compress = 0x400000c4; +tdefl_compress_buffer = 0x400000c8; +tdefl_compress_mem_to_heap = 0x400000cc; +tdefl_compress_mem_to_mem = 0x400000d0; +tdefl_compress_mem_to_output = 0x400000d4; +tdefl_get_adler32 = 0x400000d8; +tdefl_get_prev_return_status = 0x400000dc; +tdefl_init = 0x400000e0; +tdefl_write_image_to_png_file_in_memory = 0x400000e4; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000e8; +tinfl_decompress = 0x400000ec; +tinfl_decompress_mem_to_callback = 0x400000f0; +tinfl_decompress_mem_to_heap = 0x400000f4; +tinfl_decompress_mem_to_mem = 0x400000f8; /*************************************** @@ -95,69 +93,77 @@ jd_decomp = 0x400000fc; ***************************************/ /* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x40000100 ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000104 ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000108 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000110 ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x40000114 ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000118 ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x4000011c ); -PROVIDE( esp_rom_spiflash_write = 0x40000120 ); -PROVIDE( esp_rom_spiflash_read = 0x40000124 ); -PROVIDE( esp_rom_spiflash_config_param = 0x40000128 ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x4000012c ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000130 ); -PROVIDE( esp_rom_spiflash_unlock = 0x40000134 ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000138 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x4000013c ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000140 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x40000144 ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000148 ); -PROVIDE( esp_rom_spiflash_read_status = 0x4000014c ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000150 ); -PROVIDE( esp_rom_spiflash_write_status = 0x40000154 ); -PROVIDE( spi_flash_attach = 0x40000158 ); -PROVIDE( spi_flash_get_chip_size = 0x4000015c ); -PROVIDE( spi_flash_guard_set = 0x40000160 ); -PROVIDE( spi_flash_guard_get = 0x40000164 ); -PROVIDE( spi_flash_read_encrypted = 0x40000168 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x4000016c ); -PROVIDE( spi_flash_mmap_page_num_init = 0x40000170 ); -PROVIDE( spi_flash_mmap = 0x40000174 ); -PROVIDE( spi_flash_mmap_pages = 0x40000178 ); -PROVIDE( spi_flash_munmap = 0x4000017c ); -PROVIDE( spi_flash_mmap_dump = 0x40000180 ); -PROVIDE( spi_flash_check_and_flush_cache = 0x40000184 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x40000188 ); -PROVIDE( spi_flash_cache2phys = 0x4000018c ); -PROVIDE( spi_flash_phys2cache = 0x40000190 ); -PROVIDE( spi_flash_disable_cache = 0x40000194 ); -PROVIDE( spi_flash_restore_cache = 0x40000198 ); -PROVIDE( spi_flash_cache_enabled = 0x4000019c ); -PROVIDE( spi_flash_enable_cache = 0x400001a0 ); -PROVIDE( spi_cache_mode_switch = 0x400001a4 ); -PROVIDE( spi_common_set_dummy_output = 0x400001a8 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001ac ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001b0 ); -PROVIDE( SPIEraseArea = 0x400001b4 ); -PROVIDE( SPILock = 0x400001b8 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001bc ); -PROVIDE( SPI_Common_Command = 0x400001c0 ); -PROVIDE( SPI_WakeUp = 0x400001c4 ); -PROVIDE( SPI_block_erase = 0x400001c8 ); -PROVIDE( SPI_chip_erase = 0x400001cc ); -PROVIDE( SPI_init = 0x400001d0 ); -PROVIDE( SPI_page_program = 0x400001d4 ); -PROVIDE( SPI_read_data = 0x400001d8 ); -PROVIDE( SPI_sector_erase = 0x400001dc ); -PROVIDE( SPI_write_enable = 0x400001e0 ); -PROVIDE( SelectSpiFunction = 0x400001e4 ); -PROVIDE( SetSpiDrvs = 0x400001e8 ); -PROVIDE( Wait_SPI_Idle = 0x400001ec ); -PROVIDE( spi_dummy_len_fix = 0x400001f0 ); -PROVIDE( Disable_QMode = 0x400001f4 ); -PROVIDE( Enable_QMode = 0x400001f8 ); +PROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc ); +PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 ); +PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 ); +PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 ); +PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c ); +PROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 ); +PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 ); +PROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 ); +PROVIDE( _esp_rom_spiflash_write = 0x4000011c ); +PROVIDE( _esp_rom_spiflash_read = 0x40000120 ); +PROVIDE( _esp_rom_spiflash_unlock = 0x40000124 ); +PROVIDE( _SPIEraseArea = 0x40000128 ); +PROVIDE( _SPI_write_enable = 0x4000012c ); +PROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 ); +PROVIDE( esp_rom_spiflash_erase_block = 0x40000134 ); +PROVIDE( esp_rom_spiflash_write = 0x40000138 ); +PROVIDE( esp_rom_spiflash_read = 0x4000013c ); +PROVIDE( esp_rom_spiflash_unlock = 0x40000140 ); +PROVIDE( SPIEraseArea = 0x40000144 ); +PROVIDE( SPI_write_enable = 0x40000148 ); +PROVIDE( esp_rom_spiflash_config_param = 0x4000014c ); +PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 ); +PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 ); +PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 ); +PROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c ); +PROVIDE( esp_rom_spi_flash_update_id = 0x40000160 ); +PROVIDE( esp_rom_spiflash_config_clk = 0x40000164 ); +PROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 ); +PROVIDE( esp_rom_spiflash_read_status = 0x4000016c ); +PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 ); +PROVIDE( esp_rom_spiflash_write_status = 0x40000174 ); +PROVIDE( spi_flash_attach = 0x40000178 ); +PROVIDE( spi_flash_get_chip_size = 0x4000017c ); +PROVIDE( spi_flash_guard_set = 0x40000180 ); +PROVIDE( spi_flash_guard_get = 0x40000184 ); +PROVIDE( spi_flash_read_encrypted = 0x40000188 ); +PROVIDE( spi_flash_mmap_os_func_set = 0x4000018c ); +PROVIDE( spi_flash_mmap_page_num_init = 0x40000190 ); +PROVIDE( spi_flash_mmap = 0x40000194 ); +PROVIDE( spi_flash_mmap_pages = 0x40000198 ); +PROVIDE( spi_flash_munmap = 0x4000019c ); +PROVIDE( spi_flash_mmap_dump = 0x400001a0 ); +PROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 ); +PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 ); +PROVIDE( spi_flash_cache2phys = 0x400001ac ); +PROVIDE( spi_flash_phys2cache = 0x400001b0 ); +PROVIDE( spi_flash_disable_cache = 0x400001b4 ); +PROVIDE( spi_flash_restore_cache = 0x400001b8 ); +PROVIDE( spi_flash_cache_enabled = 0x400001bc ); +PROVIDE( spi_flash_enable_cache = 0x400001c0 ); +PROVIDE( spi_cache_mode_switch = 0x400001c4 ); +PROVIDE( spi_common_set_dummy_output = 0x400001c8 ); +PROVIDE( spi_common_set_flash_cs_timing = 0x400001cc ); +PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 ); +PROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 ); +PROVIDE( SPILock = 0x400001d8 ); +PROVIDE( SPIMasterReadModeCnfig = 0x400001dc ); +PROVIDE( SPI_Common_Command = 0x400001e0 ); +PROVIDE( SPI_WakeUp = 0x400001e4 ); +PROVIDE( SPI_block_erase = 0x400001e8 ); +PROVIDE( SPI_chip_erase = 0x400001ec ); +PROVIDE( SPI_init = 0x400001f0 ); +PROVIDE( SPI_page_program = 0x400001f4 ); +PROVIDE( SPI_read_data = 0x400001f8 ); +PROVIDE( SPI_sector_erase = 0x400001fc ); +PROVIDE( SelectSpiFunction = 0x40000200 ); +PROVIDE( SetSpiDrvs = 0x40000204 ); +PROVIDE( Wait_SPI_Idle = 0x40000208 ); +PROVIDE( spi_dummy_len_fix = 0x4000020c ); +PROVIDE( Disable_QMode = 0x40000210 ); +PROVIDE( Enable_QMode = 0x40000214 ); /* Data (.data, .bss, .rodata) */ PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 ); PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 ); @@ -169,17 +175,105 @@ PROVIDE( g_flash_guard_ops = 0x3fcdfff8 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x400001fc ); -PROVIDE( spi_flash_hal_device_config = 0x40000200 ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000204 ); -PROVIDE( spi_flash_hal_common_command = 0x40000208 ); -PROVIDE( spi_flash_hal_read = 0x4000020c ); -PROVIDE( spi_flash_hal_erase_chip = 0x40000210 ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000214 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000218 ); -PROVIDE( spi_flash_hal_program_page = 0x4000021c ); -PROVIDE( spi_flash_hal_set_write_protect = 0x40000220 ); -PROVIDE( spi_flash_hal_host_idle = 0x40000224 ); +PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 ); +PROVIDE( spi_flash_hal_device_config = 0x4000021c ); +PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 ); +PROVIDE( spi_flash_hal_common_command = 0x40000224 ); +PROVIDE( spi_flash_hal_read = 0x40000228 ); +PROVIDE( spi_flash_hal_erase_chip = 0x4000022c ); +PROVIDE( spi_flash_hal_erase_sector = 0x40000230 ); +PROVIDE( spi_flash_hal_erase_block = 0x40000234 ); +PROVIDE( spi_flash_hal_program_page = 0x40000238 ); +PROVIDE( spi_flash_hal_set_write_protect = 0x4000023c ); +PROVIDE( spi_flash_hal_host_idle = 0x40000240 ); +PROVIDE( spi_flash_hal_check_status = 0x40000244 ); +PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 ); +PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c ); +PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 ); +PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 ); +PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 ); +PROVIDE( spi_flash_hal_resume = 0x4000025c ); +PROVIDE( spi_flash_hal_suspend = 0x40000260 ); +PROVIDE( spi_flash_encryption_hal_enable = 0x40000264 ); +PROVIDE( spi_flash_encryption_hal_disable = 0x40000268 ); +PROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c ); +PROVIDE( spi_flash_encryption_hal_done = 0x40000270 ); +PROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 ); +PROVIDE( spi_flash_encryption_hal_check = 0x40000278 ); +PROVIDE( wdt_hal_init = 0x4000027c ); +PROVIDE( wdt_hal_deinit = 0x40000280 ); +PROVIDE( wdt_hal_config_stage = 0x40000284 ); +PROVIDE( wdt_hal_write_protect_disable = 0x40000288 ); +PROVIDE( wdt_hal_write_protect_enable = 0x4000028c ); +PROVIDE( wdt_hal_enable = 0x40000290 ); +PROVIDE( wdt_hal_disable = 0x40000294 ); +PROVIDE( wdt_hal_handle_intr = 0x40000298 ); +PROVIDE( wdt_hal_feed = 0x4000029c ); +PROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 ); +PROVIDE( wdt_hal_is_enabled = 0x400002a4 ); +PROVIDE( systimer_hal_init = 0x400002a8 ); +PROVIDE( systimer_hal_get_counter_value = 0x400002ac ); +PROVIDE( systimer_hal_get_time = 0x400002b0 ); +PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); +PROVIDE( systimer_hal_set_alarm_period = 0x400002b8 ); +PROVIDE( systimer_hal_get_alarm_value = 0x400002bc ); +PROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 ); +PROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 ); +PROVIDE( systimer_hal_counter_value_advance = 0x400002c8 ); +PROVIDE( systimer_hal_enable_counter = 0x400002cc ); +PROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 ); +PROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 ); +PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 ); + + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +PROVIDE( tlsf_create = 0x400002dc ); +PROVIDE( tlsf_create_with_pool = 0x400002e0 ); +PROVIDE( tlsf_get_pool = 0x400002e4 ); +PROVIDE( tlsf_add_pool = 0x400002e8 ); +PROVIDE( tlsf_remove_pool = 0x400002ec ); +PROVIDE( tlsf_malloc = 0x400002f0 ); +PROVIDE( tlsf_memalign = 0x400002f4 ); +PROVIDE( tlsf_memalign_offs = 0x400002f8 ); +PROVIDE( tlsf_realloc = 0x400002fc ); +PROVIDE( tlsf_free = 0x40000300 ); +PROVIDE( tlsf_block_size = 0x40000304 ); +PROVIDE( tlsf_size = 0x40000308 ); +PROVIDE( tlsf_align_size = 0x4000030c ); +PROVIDE( tlsf_block_size_min = 0x40000310 ); +PROVIDE( tlsf_block_size_max = 0x40000314 ); +PROVIDE( tlsf_pool_overhead = 0x40000318 ); +PROVIDE( tlsf_alloc_overhead = 0x4000031c ); +PROVIDE( tlsf_walk_pool = 0x40000320 ); +PROVIDE( tlsf_check = 0x40000324 ); +PROVIDE( tlsf_check_pool = 0x40000328 ); +PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c ); +PROVIDE( multi_heap_get_block_address_impl = 0x40000330 ); +PROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 ); +PROVIDE( multi_heap_register_impl = 0x40000338 ); +PROVIDE( multi_heap_set_lock = 0x4000033c ); +PROVIDE( multi_heap_mutex_init = 0x40000340 ); +PROVIDE( multi_heap_internal_lock = 0x40000344 ); +PROVIDE( multi_heap_internal_unlock = 0x40000348 ); +PROVIDE( multi_heap_get_first_block = 0x4000034c ); +PROVIDE( multi_heap_get_next_block = 0x40000350 ); +PROVIDE( multi_heap_is_free = 0x40000354 ); +PROVIDE( multi_heap_malloc_impl = 0x40000358 ); +PROVIDE( multi_heap_free_impl = 0x4000035c ); +PROVIDE( multi_heap_realloc_impl = 0x40000360 ); +PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 ); +PROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 ); +PROVIDE( multi_heap_check = 0x4000036c ); +PROVIDE( multi_heap_dump = 0x40000370 ); +PROVIDE( multi_heap_free_size_impl = 0x40000374 ); +PROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 ); +PROVIDE( multi_heap_get_info_impl = 0x4000037c ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( heap_tlsf_table_ptr = 0x3fcdffec ); /*************************************** @@ -187,38 +281,41 @@ PROVIDE( spi_flash_hal_host_idle = 0x40000224 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000228 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x4000022c ); -PROVIDE( spi_flash_chip_generic_write = 0x40000230 ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000234 ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000238 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x4000023c ); -PROVIDE( spi_flash_chip_generic_reset = 0x40000240 ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000244 ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000248 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x4000024c ); -PROVIDE( spi_flash_chip_generic_page_program = 0x40000250 ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000254 ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000258 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x4000025c ); -PROVIDE( spi_flash_chip_generic_yield = 0x40000260 ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x40000264 ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000268 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x4000026c ); -PROVIDE( spi_flash_chip_generic_read = 0x40000270 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x40000274 ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x40000278 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x4000027c ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x40000280 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x40000284 ); -PROVIDE( spi_flash_common_set_io_mode = 0x40000288 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x4000028c ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000290 ); -PROVIDE( spi_flash_chip_gd_probe = 0x40000294 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x40000298 ); +PROVIDE( spi_flash_chip_generic_probe = 0x40000380 ); +PROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 ); +PROVIDE( spi_flash_chip_generic_write = 0x40000388 ); +PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c ); +PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 ); +PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 ); +PROVIDE( spi_flash_chip_generic_reset = 0x40000398 ); +PROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c ); +PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 ); +PROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 ); +PROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 ); +PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac ); +PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 ); +PROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 ); +PROVIDE( spi_flash_chip_generic_yield = 0x400003b8 ); +PROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc ); +PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 ); +PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 ); +PROVIDE( spi_flash_chip_generic_read = 0x400003c8 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc ); +PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc ); +PROVIDE( spi_flash_common_set_io_mode = 0x400003e0 ); +PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 ); +PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 ); +PROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec ); +PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 ); +PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 ); +PROVIDE( spi_flash_chip_gd_probe = 0x400003f8 ); +PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc ); /* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffec ); -PROVIDE( spi_flash_encryption = 0x3fcdffe8 ); +PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); +PROVIDE( spi_flash_encryption = 0x3fcdffe4 ); /*************************************** @@ -226,18 +323,18 @@ PROVIDE( spi_flash_encryption = 0x3fcdffe8 ); ***************************************/ /* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x4000029c ); -PROVIDE( memspi_host_read_status_hs = 0x400002a0 ); -PROVIDE( memspi_host_flush_cache = 0x400002a4 ); -PROVIDE( memspi_host_erase_chip = 0x400002a8 ); -PROVIDE( memspi_host_erase_sector = 0x400002ac ); -PROVIDE( memspi_host_erase_block = 0x400002b0 ); -PROVIDE( memspi_host_program_page = 0x400002b4 ); -PROVIDE( memspi_host_read = 0x400002b8 ); -PROVIDE( memspi_host_set_write_protect = 0x400002bc ); -PROVIDE( memspi_host_set_max_read_len = 0x400002c0 ); -PROVIDE( memspi_host_read_data_slicer = 0x400002c4 ); -PROVIDE( memspi_host_write_data_slicer = 0x400002c8 ); +PROVIDE( memspi_host_read_id_hs = 0x40000400 ); +PROVIDE( memspi_host_read_status_hs = 0x40000404 ); +PROVIDE( memspi_host_flush_cache = 0x40000408 ); +PROVIDE( memspi_host_erase_chip = 0x4000040c ); +PROVIDE( memspi_host_erase_sector = 0x40000410 ); +PROVIDE( memspi_host_erase_block = 0x40000414 ); +PROVIDE( memspi_host_program_page = 0x40000418 ); +PROVIDE( memspi_host_read = 0x4000041c ); +PROVIDE( memspi_host_set_write_protect = 0x40000420 ); +PROVIDE( memspi_host_set_max_read_len = 0x40000424 ); +PROVIDE( memspi_host_read_data_slicer = 0x40000428 ); +PROVIDE( memspi_host_write_data_slicer = 0x4000042c ); /*************************************** @@ -245,29 +342,30 @@ PROVIDE( memspi_host_write_data_slicer = 0x400002c8 ); ***************************************/ /* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x400002cc ); -PROVIDE( esp_flash_read_id = 0x400002d0 ); -PROVIDE( esp_flash_get_size = 0x400002d4 ); -PROVIDE( esp_flash_erase_chip = 0x400002d8 ); -PROVIDE( esp_flash_erase_region = 0x400002dc ); -PROVIDE( esp_flash_get_chip_write_protect = 0x400002e0 ); -PROVIDE( esp_flash_set_chip_write_protect = 0x400002e4 ); -PROVIDE( esp_flash_get_protectable_regions = 0x400002e8 ); -PROVIDE( esp_flash_get_protected_region = 0x400002ec ); -PROVIDE( esp_flash_set_protected_region = 0x400002f0 ); -PROVIDE( esp_flash_read = 0x400002f4 ); -PROVIDE( esp_flash_write = 0x400002f8 ); -PROVIDE( esp_flash_write_encrypted = 0x400002fc ); -PROVIDE( esp_flash_read_encrypted = 0x40000300 ); -PROVIDE( esp_flash_get_io_mode = 0x40000304 ); -PROVIDE( esp_flash_set_io_mode = 0x40000308 ); -PROVIDE( spi_flash_boot_attach = 0x4000030c ); -PROVIDE( esp_flash_read_chip_id = 0x40000310 ); -PROVIDE( detect_spi_flash_chip = 0x40000314 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x40000318 ); +PROVIDE( esp_flash_chip_driver_initialized = 0x40000430 ); +PROVIDE( esp_flash_read_id = 0x40000434 ); +PROVIDE( esp_flash_get_size = 0x40000438 ); +PROVIDE( esp_flash_erase_chip = 0x4000043c ); +PROVIDE( esp_flash_erase_region = 0x40000440 ); +PROVIDE( esp_flash_get_chip_write_protect = 0x40000444 ); +PROVIDE( esp_flash_set_chip_write_protect = 0x40000448 ); +PROVIDE( esp_flash_get_protectable_regions = 0x4000044c ); +PROVIDE( esp_flash_get_protected_region = 0x40000450 ); +PROVIDE( esp_flash_set_protected_region = 0x40000454 ); +PROVIDE( esp_flash_read = 0x40000458 ); +PROVIDE( esp_flash_write = 0x4000045c ); +PROVIDE( esp_flash_write_encrypted = 0x40000460 ); +PROVIDE( esp_flash_read_encrypted = 0x40000464 ); +PROVIDE( esp_flash_get_io_mode = 0x40000468 ); +PROVIDE( esp_flash_set_io_mode = 0x4000046c ); +PROVIDE( spi_flash_boot_attach = 0x40000470 ); +PROVIDE( esp_flash_read_chip_id = 0x40000474 ); +PROVIDE( detect_spi_flash_chip = 0x40000478 ); +PROVIDE( esp_rom_spiflash_write_disable = 0x4000047c ); +PROVIDE( esp_flash_suspend_cmd_init = 0x40000480 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffe4 ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); +PROVIDE( esp_flash_default_chip = 0x3fcdffe0 ); +PROVIDE( esp_flash_api_funcs = 0x3fcdffdc ); /*************************************** @@ -275,61 +373,61 @@ PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); ***************************************/ /* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x4000047c ); -PROVIDE( Cache_Get_Mode = 0x40000480 ); -PROVIDE( Cache_Address_Through_IBus = 0x40000484 ); -PROVIDE( Cache_Address_Through_DBus = 0x40000488 ); -PROVIDE( Cache_Set_Default_Mode = 0x4000048c ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x40000490 ); -PROVIDE( ROM_Boot_Cache_Init = 0x40000494 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x40000498 ); -PROVIDE( Cache_Op_Addr = 0x4000049c ); -PROVIDE( Cache_Invalidate_Addr = 0x400004a0 ); -PROVIDE( Cache_Invalidate_ICache_All = 0x400004a4 ); -PROVIDE( Cache_Mask_All = 0x400004a8 ); -PROVIDE( Cache_UnMask_Dram0 = 0x400004ac ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004b0 ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x400004b4 ); -PROVIDE( Cache_Start_ICache_Preload = 0x400004b8 ); -PROVIDE( Cache_ICache_Preload_Done = 0x400004bc ); -PROVIDE( Cache_End_ICache_Preload = 0x400004c0 ); -PROVIDE( Cache_Config_ICache_Autoload = 0x400004c4 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x400004c8 ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x400004cc ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x400004d0 ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x400004d4 ); -PROVIDE( Cache_Lock_ICache_Items = 0x400004d8 ); -PROVIDE( Cache_Unlock_ICache_Items = 0x400004dc ); -PROVIDE( Cache_Lock_Addr = 0x400004e0 ); -PROVIDE( Cache_Unlock_Addr = 0x400004e4 ); -PROVIDE( Cache_Disable_ICache = 0x400004e8 ); -PROVIDE( Cache_Enable_ICache = 0x400004ec ); -PROVIDE( Cache_Suspend_ICache = 0x400004f0 ); -PROVIDE( Cache_Resume_ICache = 0x400004f4 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x400004f8 ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x400004fc ); -PROVIDE( Cache_Pms_Lock = 0x40000500 ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000504 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000508 ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x4000050c ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000510 ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000514 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x40000518 ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x4000051c ); -PROVIDE( Cache_Owner_Init = 0x40000520 ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000524 ); -PROVIDE( Cache_MMU_Init = 0x40000528 ); -PROVIDE( Cache_Ibus_MMU_Set = 0x4000052c ); -PROVIDE( Cache_Dbus_MMU_Set = 0x40000530 ); -PROVIDE( Cache_Count_Flash_Pages = 0x40000534 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x40000538 ); -PROVIDE( Cache_Get_Virtual_Addr = 0x4000053c ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x40000540 ); -PROVIDE( Cache_Get_Memory_Addr = 0x40000544 ); -PROVIDE( Cache_Get_Memory_value = 0x40000548 ); +PROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 ); +PROVIDE( Cache_Get_Mode = 0x400006e4 ); +PROVIDE( Cache_Address_Through_IBus = 0x400006e8 ); +PROVIDE( Cache_Address_Through_DBus = 0x400006ec ); +PROVIDE( Cache_Set_Default_Mode = 0x400006f0 ); +PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 ); +PROVIDE( ROM_Boot_Cache_Init = 0x400006f8 ); +PROVIDE( Cache_Invalidate_ICache_Items = 0x400006fc ); +PROVIDE( Cache_Op_Addr = 0x40000700 ); +PROVIDE( Cache_Invalidate_Addr = 0x40000704 ); +PROVIDE( Cache_Invalidate_ICache_All = 0x40000708 ); +PROVIDE( Cache_Mask_All = 0x4000070c ); +PROVIDE( Cache_UnMask_Dram0 = 0x40000710 ); +PROVIDE( Cache_Suspend_ICache_Autoload = 0x40000714 ); +PROVIDE( Cache_Resume_ICache_Autoload = 0x40000718 ); +PROVIDE( Cache_Start_ICache_Preload = 0x4000071c ); +PROVIDE( Cache_ICache_Preload_Done = 0x40000720 ); +PROVIDE( Cache_End_ICache_Preload = 0x40000724 ); +PROVIDE( Cache_Config_ICache_Autoload = 0x40000728 ); +PROVIDE( Cache_Enable_ICache_Autoload = 0x4000072c ); +PROVIDE( Cache_Disable_ICache_Autoload = 0x40000730 ); +PROVIDE( Cache_Enable_ICache_PreLock = 0x40000734 ); +PROVIDE( Cache_Disable_ICache_PreLock = 0x40000738 ); +PROVIDE( Cache_Lock_ICache_Items = 0x4000073c ); +PROVIDE( Cache_Unlock_ICache_Items = 0x40000740 ); +PROVIDE( Cache_Lock_Addr = 0x40000744 ); +PROVIDE( Cache_Unlock_Addr = 0x40000748 ); +PROVIDE( Cache_Disable_ICache = 0x4000074c ); +PROVIDE( Cache_Enable_ICache = 0x40000750 ); +PROVIDE( Cache_Suspend_ICache = 0x40000754 ); +PROVIDE( Cache_Resume_ICache = 0x40000758 ); +PROVIDE( Cache_Freeze_ICache_Enable = 0x4000075c ); +PROVIDE( Cache_Freeze_ICache_Disable = 0x40000760 ); +PROVIDE( Cache_Pms_Lock = 0x40000764 ); +PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000768 ); +PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000076c ); +PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000770 ); +PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000774 ); +PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000778 ); +PROVIDE( Cache_Get_IROM_MMU_End = 0x4000077c ); +PROVIDE( Cache_Get_DROM_MMU_End = 0x40000780 ); +PROVIDE( Cache_Owner_Init = 0x40000784 ); +PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000788 ); +PROVIDE( Cache_MMU_Init = 0x4000078c ); +PROVIDE( Cache_Ibus_MMU_Set = 0x40000790 ); +PROVIDE( Cache_Dbus_MMU_Set = 0x40000794 ); +PROVIDE( Cache_Count_Flash_Pages = 0x40000798 ); +PROVIDE( Cache_Travel_Tag_Memory = 0x4000079c ); +PROVIDE( Cache_Get_Virtual_Addr = 0x400007a0 ); +PROVIDE( Cache_Get_Memory_BaseAddr = 0x400007a4 ); +PROVIDE( Cache_Get_Memory_Addr = 0x400007a8 ); +PROVIDE( Cache_Get_Memory_value = 0x400007ac ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffd4 ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); +PROVIDE( rom_cache_op_cb = 0x3fcdffd0 ); +PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc ); /*************************************** @@ -337,13 +435,13 @@ PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); ***************************************/ /* Functions */ -ets_get_apb_freq = 0x4000054c; -ets_get_cpu_frequency = 0x40000550; -ets_update_cpu_frequency = 0x40000554; -ets_get_printf_channel = 0x40000558; -ets_get_xtal_div = 0x4000055c; -ets_set_xtal_div = 0x40000560; -ets_get_xtal_freq = 0x40000564; +ets_get_apb_freq = 0x400007b0; +ets_get_cpu_frequency = 0x400007b4; +ets_update_cpu_frequency = 0x400007b8; +ets_get_printf_channel = 0x400007bc; +ets_get_xtal_div = 0x400007c0; +ets_set_xtal_div = 0x400007c4; +ets_get_xtal_freq = 0x400007c8; /*************************************** @@ -351,23 +449,23 @@ ets_get_xtal_freq = 0x40000564; ***************************************/ /* Functions */ -gpio_input_get = 0x40000568; -gpio_matrix_in = 0x4000056c; -gpio_matrix_out = 0x40000570; -gpio_output_disable = 0x40000574; -gpio_output_enable = 0x40000578; -gpio_output_set = 0x4000057c; -gpio_pad_hold = 0x40000580; -gpio_pad_input_disable = 0x40000584; -gpio_pad_input_enable = 0x40000588; -gpio_pad_pulldown = 0x4000058c; -gpio_pad_pullup = 0x40000590; -gpio_pad_select_gpio = 0x40000594; -gpio_pad_set_drv = 0x40000598; -gpio_pad_unhold = 0x4000059c; -gpio_pin_wakeup_disable = 0x400005a0; -gpio_pin_wakeup_enable = 0x400005a4; -gpio_bypass_matrix_in = 0x400005a8; +gpio_input_get = 0x400007cc; +gpio_matrix_in = 0x400007d0; +gpio_matrix_out = 0x400007d4; +gpio_output_disable = 0x400007d8; +gpio_output_enable = 0x400007dc; +gpio_output_set = 0x400007e0; +gpio_pad_hold = 0x400007e4; +gpio_pad_input_disable = 0x400007e8; +gpio_pad_input_enable = 0x400007ec; +gpio_pad_pulldown = 0x400007f0; +gpio_pad_pullup = 0x400007f4; +gpio_pad_select_gpio = 0x400007f8; +gpio_pad_set_drv = 0x400007fc; +gpio_pad_unhold = 0x40000800; +gpio_pin_wakeup_disable = 0x40000804; +gpio_pin_wakeup_enable = 0x40000808; +gpio_bypass_matrix_in = 0x4000080c; /*************************************** @@ -375,18 +473,18 @@ gpio_bypass_matrix_in = 0x400005a8; ***************************************/ /* Functions */ -esprv_intc_int_set_priority = 0x400005ac; -esprv_intc_int_set_threshold = 0x400005b0; -esprv_intc_int_enable = 0x400005b4; -esprv_intc_int_disable = 0x400005b8; -esprv_intc_int_set_type = 0x400005bc; -intr_matrix_set = 0x400005c0; -ets_intr_lock = 0x400005c4; -ets_intr_unlock = 0x400005c8; -PROVIDE( intr_handler_set = 0x400005cc ); -ets_isr_attach = 0x400005d0; -ets_isr_mask = 0x400005d4; -ets_isr_unmask = 0x400005d8; +esprv_intc_int_set_priority = 0x40000810; +esprv_intc_int_set_threshold = 0x40000814; +esprv_intc_int_enable = 0x40000818; +esprv_intc_int_disable = 0x4000081c; +esprv_intc_int_set_type = 0x40000820; +PROVIDE( intr_handler_set = 0x40000824 ); +intr_matrix_set = 0x40000828; +ets_intr_lock = 0x4000082c; +ets_intr_unlock = 0x40000830; +ets_isr_attach = 0x40000834; +ets_isr_mask = 0x40000838; +ets_isr_unmask = 0x4000083c; /*************************************** @@ -394,54 +492,52 @@ ets_isr_unmask = 0x400005d8; ***************************************/ /* Functions */ -md5_vector = 0x400005dc; -MD5Init = 0x400005e0; -MD5Update = 0x400005e4; -MD5Final = 0x400005e8; -hmac_md5_vector = 0x400005ec; -hmac_md5 = 0x400005f0; -crc32_le = 0x400005f4; -crc32_be = 0x400005f8; -crc16_le = 0x400005fc; -crc16_be = 0x40000600; -crc8_le = 0x40000604; -crc8_be = 0x40000608; -esp_crc8 = 0x4000060c; -ets_sha_enable = 0x40000610; -ets_sha_disable = 0x40000614; -ets_sha_get_state = 0x40000618; -ets_sha_init = 0x4000061c; -ets_sha_process = 0x40000620; -ets_sha_starts = 0x40000624; -ets_sha_update = 0x40000628; -ets_sha_finish = 0x4000062c; -ets_sha_clone = 0x40000630; -ets_hmac_enable = 0x40000634; -ets_hmac_disable = 0x40000638; -ets_hmac_calculate_message = 0x4000063c; -ets_hmac_calculate_downstream = 0x40000640; -ets_hmac_invalidate_downstream = 0x40000644; -ets_jtag_enable_temporarily = 0x40000648; -ets_aes_enable = 0x4000064c; -ets_aes_disable = 0x40000650; -ets_aes_setkey = 0x40000654; -ets_aes_block = 0x40000658; -ets_bigint_enable = 0x4000065c; -ets_bigint_disable = 0x40000660; -ets_bigint_multiply = 0x40000664; -ets_bigint_modmult = 0x40000668; -ets_bigint_modexp = 0x4000066c; -ets_bigint_wait_finish = 0x40000670; -ets_bigint_getz = 0x40000674; -ets_ds_enable = 0x40000678; -ets_ds_disable = 0x4000067c; -ets_ds_start_sign = 0x40000680; -ets_ds_is_busy = 0x40000684; -ets_ds_finish_sign = 0x40000688; -ets_ds_encrypt_params = 0x4000068c; -ets_aes_setkey_dec = 0x40000690; -ets_aes_setkey_enc = 0x40000694; -ets_mgf1_sha256 = 0x40000698; +md5_vector = 0x40000840; +MD5Init = 0x40000844; +MD5Update = 0x40000848; +MD5Final = 0x4000084c; +crc32_le = 0x40000850; +crc16_le = 0x40000854; +crc8_le = 0x40000858; +crc32_be = 0x4000085c; +crc16_be = 0x40000860; +crc8_be = 0x40000864; +esp_crc8 = 0x40000868; +ets_sha_enable = 0x4000086c; +ets_sha_disable = 0x40000870; +ets_sha_get_state = 0x40000874; +ets_sha_init = 0x40000878; +ets_sha_process = 0x4000087c; +ets_sha_starts = 0x40000880; +ets_sha_update = 0x40000884; +ets_sha_finish = 0x40000888; +ets_sha_clone = 0x4000088c; +ets_hmac_enable = 0x40000890; +ets_hmac_disable = 0x40000894; +ets_hmac_calculate_message = 0x40000898; +ets_hmac_calculate_downstream = 0x4000089c; +ets_hmac_invalidate_downstream = 0x400008a0; +ets_jtag_enable_temporarily = 0x400008a4; +ets_aes_enable = 0x400008a8; +ets_aes_disable = 0x400008ac; +ets_aes_setkey = 0x400008b0; +ets_aes_block = 0x400008b4; +ets_aes_setkey_dec = 0x400008b8; +ets_aes_setkey_enc = 0x400008bc; +ets_bigint_enable = 0x400008c0; +ets_bigint_disable = 0x400008c4; +ets_bigint_multiply = 0x400008c8; +ets_bigint_modmult = 0x400008cc; +ets_bigint_modexp = 0x400008d0; +ets_bigint_wait_finish = 0x400008d4; +ets_bigint_getz = 0x400008d8; +ets_ds_enable = 0x400008dc; +ets_ds_disable = 0x400008e0; +ets_ds_start_sign = 0x400008e4; +ets_ds_is_busy = 0x400008e8; +ets_ds_finish_sign = 0x400008ec; +ets_ds_encrypt_params = 0x400008f0; +ets_mgf1_sha256 = 0x400008f4; /* Data (.data, .bss, .rodata) */ crc32_le_table_ptr = 0x3ff1fff8; crc16_le_table_ptr = 0x3ff1fff4; @@ -456,36 +552,36 @@ crc8_be_table_ptr = 0x3ff1ffe4; ***************************************/ /* Functions */ -ets_efuse_read = 0x4000069c; -ets_efuse_program = 0x400006a0; -ets_efuse_clear_program_registers = 0x400006a4; -ets_efuse_write_key = 0x400006a8; -ets_efuse_get_read_register_address = 0x400006ac; -ets_efuse_get_key_purpose = 0x400006b0; -ets_efuse_key_block_unused = 0x400006b4; -ets_efuse_find_unused_key_block = 0x400006b8; -ets_efuse_rs_calculate = 0x400006bc; -ets_efuse_count_unused_key_blocks = 0x400006c0; -ets_efuse_secure_boot_enabled = 0x400006c4; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400006c8; -ets_efuse_cache_encryption_enabled = 0x400006cc; -ets_efuse_download_modes_disabled = 0x400006d0; -ets_efuse_find_purpose = 0x400006d4; -ets_efuse_force_send_resume = 0x400006dc; -ets_efuse_get_flash_delay_us = 0x400006e0; -ets_efuse_get_mac = 0x400006e4; -ets_efuse_get_spiconfig = 0x400006e8; -ets_efuse_usb_print_is_disabled = 0x400006ec; -ets_efuse_get_uart_print_control = 0x400006f4; -ets_efuse_get_wp_pad = 0x400006f8; -ets_efuse_direct_boot_mode_disabled = 0x400006fc; -ets_efuse_security_download_modes_enabled = 0x40000700; -ets_efuse_set_timing = 0x40000704; -ets_efuse_jtag_disabled = 0x40000708; -ets_efuse_usb_download_mode_disabled = 0x4000070c; -ets_efuse_usb_module_disabled = 0x40000710; -ets_efuse_usb_device_disabled = 0x40000714; -ets_efuse_secure_boot_fast_wake_enabled = 0x40000718; +ets_efuse_read = 0x400008f8; +ets_efuse_program = 0x400008fc; +ets_efuse_clear_program_registers = 0x40000900; +ets_efuse_write_key = 0x40000904; +ets_efuse_get_read_register_address = 0x40000908; +ets_efuse_get_key_purpose = 0x4000090c; +ets_efuse_key_block_unused = 0x40000910; +ets_efuse_find_unused_key_block = 0x40000914; +ets_efuse_rs_calculate = 0x40000918; +ets_efuse_count_unused_key_blocks = 0x4000091c; +ets_efuse_secure_boot_enabled = 0x40000920; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000924; +ets_efuse_cache_encryption_enabled = 0x40000928; +ets_efuse_download_modes_disabled = 0x4000092c; +ets_efuse_find_purpose = 0x40000930; +ets_efuse_force_send_resume = 0x40000934; +ets_efuse_get_flash_delay_us = 0x40000938; +ets_efuse_get_mac = 0x4000093c; +ets_efuse_get_uart_print_control = 0x40000940; +ets_efuse_direct_boot_mode_disabled = 0x40000944; +ets_efuse_security_download_modes_enabled = 0x40000948; +ets_efuse_set_timing = 0x4000094c; +ets_efuse_jtag_disabled = 0x40000950; +ets_efuse_get_spiconfig = 0x40000954; +ets_efuse_get_wp_pad = 0x40000958; +ets_efuse_usb_print_is_disabled = 0x4000095c; +ets_efuse_usb_download_mode_disabled = 0x40000960; +ets_efuse_usb_module_disabled = 0x40000964; +ets_efuse_usb_device_disabled = 0x40000968; +ets_efuse_secure_boot_fast_wake_enabled = 0x4000096c; /*************************************** @@ -493,13 +589,13 @@ ets_efuse_secure_boot_fast_wake_enabled = 0x40000718; ***************************************/ /* Functions */ -ets_emsa_pss_verify = 0x4000071c; -ets_rsa_pss_verify = 0x40000720; -ets_secure_boot_verify_bootloader_with_keys = 0x40000724; -ets_secure_boot_verify_signature = 0x40000728; -ets_secure_boot_read_key_digests = 0x4000072c; -ets_secure_boot_revoke_public_key_digest = 0x40000730; -ets_ecdsa_verify = 0x40000734; +ets_emsa_pss_verify = 0x40000970; +ets_rsa_pss_verify = 0x40000974; +ets_ecdsa_verify = 0x40000978; +ets_secure_boot_verify_bootloader_with_keys = 0x4000097c; +ets_secure_boot_verify_signature = 0x40000980; +ets_secure_boot_read_key_digests = 0x40000984; +ets_secure_boot_revoke_public_key_digest = 0x40000988; /*************************************** @@ -507,13 +603,1078 @@ ets_ecdsa_verify = 0x40000734; ***************************************/ /* Functions */ -PROVIDE( usb_uart_device_rx_one_char = 0x400008a0 ); -PROVIDE( usb_uart_device_rx_one_char_block = 0x400008a4 ); -PROVIDE( usb_uart_device_tx_flush = 0x400008a8 ); -PROVIDE( usb_uart_device_tx_one_char = 0x400008ac ); +PROVIDE( usb_uart_device_rx_one_char = 0x40000afc ); +PROVIDE( usb_uart_device_rx_one_char_block = 0x40000b00 ); +PROVIDE( usb_uart_device_tx_flush = 0x40000b04 ); +PROVIDE( usb_uart_device_tx_one_char = 0x40000b08 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( g_uart_print = 0x3fcdffcd ); -PROVIDE( g_usb_print = 0x3fcdffcc ); +PROVIDE( g_uart_print = 0x3fcdffc9 ); +PROVIDE( g_usb_print = 0x3fcdffc8 ); + + +/*************************************** + Group bluetooth + ***************************************/ + +/* Functions */ +ble_controller_rom_data_init = 0x40000b0c; +ble_osi_coex_funcs_register = 0x40000b10; +bt_rf_coex_cfg_get_default = 0x40000b14; +bt_rf_coex_dft_pti_get_default = 0x40000b18; +bt_rf_coex_hooks_p_set = 0x40000b1c; +r__os_mbuf_copypkthdr = 0x40000b20; +r__os_msys_find_pool = 0x40000b24; +r_ble_controller_get_rom_compile_version = 0x40000b28; +r_ble_hci_ram_hs_acl_tx = 0x40000b2c; +r_ble_hci_ram_hs_cmd_tx = 0x40000b30; +r_ble_hci_ram_ll_acl_tx = 0x40000b34; +r_ble_hci_ram_ll_evt_tx = 0x40000b38; +r_ble_hci_ram_reset = 0x40000b3c; +r_ble_hci_ram_set_acl_free_cb = 0x40000b40; +r_ble_hci_trans_acl_buf_alloc = 0x40000b44; +r_ble_hci_trans_buf_alloc = 0x40000b48; +r_ble_hci_trans_buf_free = 0x40000b4c; +r_ble_hci_trans_cfg_hs = 0x40000b50; +r_ble_hci_trans_cfg_ll = 0x40000b54; +r_ble_hci_trans_deinit = 0x40000b58; +r_ble_hci_trans_env_init = 0x40000b5c; +r_ble_hci_trans_init = 0x40000b60; +r_ble_hci_uart_acl_tx = 0x40000b64; +r_ble_hci_uart_cmdevt_tx = 0x40000b68; +r_ble_hci_uart_config = 0x40000b6c; +r_ble_hci_uart_free_pkt = 0x40000b70; +r_ble_hci_uart_hs_acl_tx = 0x40000b74; +r_ble_hci_uart_hs_cmd_tx = 0x40000b78; +r_ble_hci_uart_ll_acl_tx = 0x40000b7c; +r_ble_hci_uart_ll_evt_tx = 0x40000b80; +r_ble_hci_uart_rx_acl = 0x40000b84; +r_ble_hci_uart_rx_char = 0x40000b88; +r_ble_hci_uart_rx_cmd = 0x40000b8c; +r_ble_hci_uart_rx_evt = 0x40000b90; +r_ble_hci_uart_rx_evt_cb = 0x40000b94; +r_ble_hci_uart_rx_le_evt = 0x40000b98; +r_ble_hci_uart_rx_pkt_type = 0x40000b9c; +r_ble_hci_uart_rx_skip_acl = 0x40000ba0; +r_ble_hci_uart_rx_skip_cmd = 0x40000ba4; +r_ble_hci_uart_rx_skip_evt = 0x40000ba8; +r_ble_hci_uart_rx_sync_loss = 0x40000bac; +r_ble_hci_uart_set_acl_free_cb = 0x40000bb0; +r_ble_hci_uart_sync_lost = 0x40000bb4; +r_ble_hci_uart_trans_reset = 0x40000bb8; +r_ble_hci_uart_tx_char = 0x40000bbc; +r_ble_hci_uart_tx_pkt_type = 0x40000bc0; +r_ble_hw_driver_deinit = 0x40000bc4; +r_ble_hw_driver_env_init = 0x40000bc8; +r_ble_hw_encrypt_block = 0x40000bcc; +r_ble_hw_get_public_addr = 0x40000bd0; +r_ble_hw_get_static_addr = 0x40000bd4; +r_ble_hw_periodiclist_add = 0x40000bd8; +r_ble_hw_periodiclist_clear = 0x40000bdc; +r_ble_hw_periodiclist_rmv = 0x40000be0; +r_ble_hw_resolv_list_cur_entry = 0x40000be4; +r_ble_hw_resolv_list_match = 0x40000be8; +r_ble_hw_resolv_list_set = 0x40000bec; +r_ble_hw_rng_init = 0x40000bf0; +r_ble_hw_rng_start = 0x40000bf4; +r_ble_hw_rng_stop = 0x40000bf8; +r_ble_hw_rx_local_is_rpa = 0x40000bfc; +r_ble_hw_whitelist_add = 0x40000c00; +r_ble_hw_whitelist_clear = 0x40000c04; +r_ble_hw_whitelist_dev_num = 0x40000c08; +r_ble_hw_whitelist_get_base = 0x40000c0c; +r_ble_hw_whitelist_rmv = 0x40000c10; +r_ble_hw_whitelist_search = 0x40000c14; +r_ble_hw_whitelist_sort = 0x40000c18; +r_ble_ll_acl_data_in = 0x40000c1c; +r_ble_ll_addr_is_id = 0x40000c20; +r_ble_ll_addr_subtype = 0x40000c24; +r_ble_ll_adv_active_chanset_clear = 0x40000c28; +r_ble_ll_adv_active_chanset_is_pri = 0x40000c2c; +r_ble_ll_adv_active_chanset_is_sec = 0x40000c30; +r_ble_ll_adv_active_chanset_set_pri = 0x40000c34; +r_ble_ll_adv_active_chanset_set_sec = 0x40000c38; +r_ble_ll_adv_aux_calculate = 0x40000c3c; +r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000c40; +r_ble_ll_adv_aux_pdu_make = 0x40000c44; +r_ble_ll_adv_aux_scannable_pdu_make = 0x40000c48; +r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000c4c; +r_ble_ll_adv_aux_schedule = 0x40000c50; +r_ble_ll_adv_aux_schedule_first = 0x40000c54; +r_ble_ll_adv_aux_schedule_next = 0x40000c58; +r_ble_ll_adv_aux_scheduled = 0x40000c5c; +r_ble_ll_adv_aux_set_start_time = 0x40000c60; +r_ble_ll_adv_aux_txed = 0x40000c64; +r_ble_ll_adv_can_chg_whitelist = 0x40000c68; +r_ble_ll_adv_chk_rpa_timeout = 0x40000c6c; +r_ble_ll_adv_clear_all = 0x40000c70; +r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000c74; +r_ble_ll_adv_coex_dpc_process_pri = 0x40000c78; +r_ble_ll_adv_coex_dpc_process_sec = 0x40000c7c; +r_ble_ll_adv_coex_dpc_pti_get = 0x40000c80; +r_ble_ll_adv_coex_dpc_update = 0x40000c84; +r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000c88; +r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000c8c; +r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000c90; +r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000c94; +r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000c98; +r_ble_ll_adv_conn_req_rxd = 0x40000c9c; +r_ble_ll_adv_deinit = 0x40000ca0; +r_ble_ll_adv_done = 0x40000ca4; +r_ble_ll_adv_drop_event = 0x40000ca8; +r_ble_ll_adv_enabled = 0x40000cac; +r_ble_ll_adv_env_init = 0x40000cb0; +r_ble_ll_adv_event_done = 0x40000cb4; +r_ble_ll_adv_event_rmvd_from_sched = 0x40000cb8; +r_ble_ll_adv_ext_estimate_data_itvl = 0x40000cbc; +r_ble_ll_adv_ext_set_adv_data = 0x40000cc0; +r_ble_ll_adv_ext_set_enable = 0x40000cc4; +r_ble_ll_adv_ext_set_param = 0x40000cc8; +r_ble_ll_adv_ext_set_scan_rsp = 0x40000ccc; +r_ble_ll_adv_final_chan = 0x40000cd0; +r_ble_ll_adv_first_chan = 0x40000cd4; +r_ble_ll_adv_flags_clear = 0x40000cd8; +r_ble_ll_adv_flags_set = 0x40000cdc; +r_ble_ll_adv_get_local_rpa = 0x40000ce0; +r_ble_ll_adv_get_peer_rpa = 0x40000ce4; +r_ble_ll_adv_get_sec_pdu_len = 0x40000ce8; +r_ble_ll_adv_halt = 0x40000cec; +r_ble_ll_adv_hci_set_random_addr = 0x40000cf0; +r_ble_ll_adv_init = 0x40000cf4; +r_ble_ll_adv_legacy_pdu_make = 0x40000cf8; +r_ble_ll_adv_make_done = 0x40000cfc; +r_ble_ll_adv_pdu_make = 0x40000d00; +r_ble_ll_adv_periodic_check_data_itvl = 0x40000d04; +r_ble_ll_adv_periodic_done = 0x40000d08; +r_ble_ll_adv_periodic_enable = 0x40000d0c; +r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000d10; +r_ble_ll_adv_periodic_event_done = 0x40000d14; +r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000d18; +r_ble_ll_adv_periodic_schedule_first = 0x40000d1c; +r_ble_ll_adv_periodic_schedule_next = 0x40000d20; +r_ble_ll_adv_periodic_send_sync_ind = 0x40000d24; +r_ble_ll_adv_periodic_set_data = 0x40000d28; +r_ble_ll_adv_periodic_set_info_transfer = 0x40000d2c; +r_ble_ll_adv_periodic_set_param = 0x40000d30; +r_ble_ll_adv_put_aux_ptr = 0x40000d34; +r_ble_ll_adv_put_syncinfo = 0x40000d38; +r_ble_ll_adv_rd_max_adv_data_len = 0x40000d3c; +r_ble_ll_adv_rd_sup_adv_sets = 0x40000d40; +r_ble_ll_adv_read_txpwr = 0x40000d44; +r_ble_ll_adv_remove = 0x40000d48; +r_ble_ll_adv_reschedule_event = 0x40000d4c; +r_ble_ll_adv_reschedule_periodic_event = 0x40000d50; +r_ble_ll_adv_reset = 0x40000d54; +r_ble_ll_adv_rpa_timeout = 0x40000d58; +r_ble_ll_adv_rpa_update = 0x40000d5c; +r_ble_ll_adv_rx_isr_end = 0x40000d60; +r_ble_ll_adv_rx_isr_start = 0x40000d64; +r_ble_ll_adv_rx_pkt_in = 0x40000d68; +r_ble_ll_adv_rx_req = 0x40000d6c; +r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000d70; +r_ble_ll_adv_scan_rsp_pdu_make = 0x40000d74; +r_ble_ll_adv_scheduled = 0x40000d78; +r_ble_ll_adv_sec_done = 0x40000d7c; +r_ble_ll_adv_sec_event_done = 0x40000d80; +r_ble_ll_adv_secondary_tx_start_cb = 0x40000d84; +r_ble_ll_adv_send_conn_comp_ev = 0x40000d88; +r_ble_ll_adv_set_adv_data = 0x40000d8c; +r_ble_ll_adv_set_adv_params = 0x40000d90; +r_ble_ll_adv_set_enable = 0x40000d94; +r_ble_ll_adv_set_random_addr = 0x40000d98; +r_ble_ll_adv_set_scan_rsp_data = 0x40000d9c; +r_ble_ll_adv_set_sched = 0x40000da0; +r_ble_ll_adv_sm_deinit = 0x40000da4; +r_ble_ll_adv_sm_event_init = 0x40000da8; +r_ble_ll_adv_sm_event_restore = 0x40000dac; +r_ble_ll_adv_sm_event_store = 0x40000db0; +r_ble_ll_adv_sm_find_configured = 0x40000db4; +r_ble_ll_adv_sm_get = 0x40000db8; +r_ble_ll_adv_sm_init = 0x40000dbc; +r_ble_ll_adv_sm_reset = 0x40000dc0; +r_ble_ll_adv_sm_start = 0x40000dc4; +r_ble_ll_adv_sm_start_periodic = 0x40000dc8; +r_ble_ll_adv_sm_stop = 0x40000dcc; +r_ble_ll_adv_sm_stop_limit_reached = 0x40000dd0; +r_ble_ll_adv_sm_stop_periodic = 0x40000dd4; +r_ble_ll_adv_sm_stop_timeout = 0x40000dd8; +r_ble_ll_adv_sync_calculate = 0x40000ddc; +r_ble_ll_adv_sync_get_pdu_len = 0x40000de0; +r_ble_ll_adv_sync_next_scheduled = 0x40000de4; +r_ble_ll_adv_sync_pdu_make = 0x40000de8; +r_ble_ll_adv_sync_schedule = 0x40000dec; +r_ble_ll_adv_sync_tx_done = 0x40000df0; +r_ble_ll_adv_sync_tx_end = 0x40000df4; +r_ble_ll_adv_sync_tx_start_cb = 0x40000df8; +r_ble_ll_adv_tx_done = 0x40000dfc; +r_ble_ll_adv_tx_start_cb = 0x40000e00; +r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000e04; +r_ble_ll_adv_update_data_mbuf = 0x40000e08; +r_ble_ll_adv_update_did = 0x40000e0c; +r_ble_ll_adv_update_periodic_data = 0x40000e10; +r_ble_ll_adv_wfr_timer_exp = 0x40000e14; +r_ble_ll_arr_pool_init = 0x40000e18; +r_ble_ll_auth_pyld_tmo_event_send = 0x40000e1c; +r_ble_ll_aux_scan_cb = 0x40000e20; +r_ble_ll_aux_scan_drop = 0x40000e24; +r_ble_ll_aux_scan_drop_event_cb = 0x40000e28; +r_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000e2c; +r_ble_ll_calc_session_key = 0x40000e30; +r_ble_ll_calc_ticks_per_slot = 0x40000e34; +r_ble_ll_calc_us_convert_tick_unit = 0x40000e38; +r_ble_ll_check_scan_params = 0x40000e3c; +r_ble_ll_chk_txrx_octets = 0x40000e40; +r_ble_ll_chk_txrx_time = 0x40000e44; +r_ble_ll_conn_adjust_pyld_len = 0x40000e48; +r_ble_ll_conn_auth_pyld_timer_cb = 0x40000e4c; +r_ble_ll_conn_auth_pyld_timer_start = 0x40000e50; +r_ble_ll_conn_calc_dci = 0x40000e54; +r_ble_ll_conn_calc_dci_csa1 = 0x40000e58; +r_ble_ll_conn_calc_itvl_ticks = 0x40000e5c; +r_ble_ll_conn_can_send_next_pdu = 0x40000e60; +r_ble_ll_conn_chk_csm_flags = 0x40000e64; +r_ble_ll_conn_chk_phy_upd_start = 0x40000e68; +r_ble_ll_conn_coex_dpc_process = 0x40000e6c; +r_ble_ll_conn_coex_dpc_pti_get = 0x40000e70; +r_ble_ll_conn_coex_dpc_update = 0x40000e74; +r_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000e78; +r_ble_ll_conn_comp_event_send = 0x40000e7c; +r_ble_ll_conn_connect_ind_pdu_make = 0x40000e80; +r_ble_ll_conn_create = 0x40000e84; +r_ble_ll_conn_create_cancel = 0x40000e88; +r_ble_ll_conn_created = 0x40000e8c; +r_ble_ll_conn_cth_flow_alloc_credit = 0x40000e90; +r_ble_ll_conn_cth_flow_enable = 0x40000e94; +r_ble_ll_conn_cth_flow_error_fn = 0x40000e98; +r_ble_ll_conn_cth_flow_free_credit = 0x40000e9c; +r_ble_ll_conn_cth_flow_have_credit = 0x40000ea0; +r_ble_ll_conn_cth_flow_is_enabled = 0x40000ea4; +r_ble_ll_conn_cth_flow_process_cmd = 0x40000ea8; +r_ble_ll_conn_cth_flow_set_buffers = 0x40000eac; +r_ble_ll_conn_cur_pducb = 0x40000eb0; +r_ble_ll_conn_current_sm_over = 0x40000eb4; +r_ble_ll_conn_end = 0x40000eb8; +r_ble_ll_conn_enqueue_pkt = 0x40000ebc; +r_ble_ll_conn_env_init = 0x40000ec0; +r_ble_ll_conn_event_end = 0x40000ec4; +r_ble_ll_conn_event_end_timer_cb = 0x40000ec8; +r_ble_ll_conn_event_halt = 0x40000ecc; +r_ble_ll_conn_event_is_over = 0x40000ed0; +r_ble_ll_conn_event_start_cb = 0x40000ed4; +r_ble_ll_conn_ext_master_init = 0x40000ed8; +r_ble_ll_conn_ext_set_params = 0x40000edc; +r_ble_ll_conn_find_active_conn = 0x40000ee0; +r_ble_ll_conn_get_anchor = 0x40000ee4; +r_ble_ll_conn_get_ce_end_time = 0x40000ee8; +r_ble_ll_conn_get_new_pdu = 0x40000eec; +r_ble_ll_conn_get_next_sched_time = 0x40000ef0; +r_ble_ll_conn_halt = 0x40000ef4; +r_ble_ll_conn_hcc_params_set_fallback = 0x40000ef8; +r_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000efc; +r_ble_ll_conn_hci_chk_conn_params = 0x40000f00; +r_ble_ll_conn_hci_chk_scan_params = 0x40000f04; +r_ble_ll_conn_hci_disconnect_cmd = 0x40000f08; +r_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000f0c; +r_ble_ll_conn_hci_le_ltk_reply = 0x40000f10; +r_ble_ll_conn_hci_le_rd_phy = 0x40000f14; +r_ble_ll_conn_hci_le_set_phy = 0x40000f18; +r_ble_ll_conn_hci_le_start_encrypt = 0x40000f1c; +r_ble_ll_conn_hci_param_nrr = 0x40000f20; +r_ble_ll_conn_hci_param_rr = 0x40000f24; +r_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000f28; +r_ble_ll_conn_hci_rd_chan_map = 0x40000f2c; +r_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000f30; +r_ble_ll_conn_hci_rd_rssi = 0x40000f34; +r_ble_ll_conn_hci_read_rem_features = 0x40000f38; +r_ble_ll_conn_hci_set_chan_class = 0x40000f3c; +r_ble_ll_conn_hci_set_data_len = 0x40000f40; +r_ble_ll_conn_hci_update = 0x40000f44; +r_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000f48; +r_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000f4c; +r_ble_ll_conn_init_phy = 0x40000f50; +r_ble_ll_conn_init_wfr_timer_exp = 0x40000f54; +r_ble_ll_conn_is_empty_pdu = 0x40000f58; +r_ble_ll_conn_is_lru = 0x40000f5c; +r_ble_ll_conn_master_common_init = 0x40000f60; +r_ble_ll_conn_master_init = 0x40000f64; +r_ble_ll_conn_module_deinit = 0x40000f68; +r_ble_ll_conn_module_init = 0x40000f6c; +r_ble_ll_conn_module_reset = 0x40000f70; +r_ble_ll_conn_new_pducb = 0x40000f74; +r_ble_ll_conn_next_event = 0x40000f78; +r_ble_ll_conn_num_comp_pkts_event_send = 0x40000f7c; +r_ble_ll_conn_process_conn_params = 0x40000f80; +r_ble_ll_conn_recv_ack = 0x40000f84; +r_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000f88; +r_ble_ll_conn_rx_data_pdu = 0x40000f8c; +r_ble_ll_conn_rx_isr_end = 0x40000f90; +r_ble_ll_conn_rx_isr_start = 0x40000f94; +r_ble_ll_conn_rxend_unencrypt = 0x40000f98; +r_ble_ll_conn_set_csa = 0x40000f9c; +r_ble_ll_conn_set_global_chanmap = 0x40000fa0; +r_ble_ll_conn_set_md_flag = 0x40000fa4; +r_ble_ll_conn_set_phy = 0x40000fa8; +r_ble_ll_conn_set_slave_flow_control = 0x40000fac; +r_ble_ll_conn_set_txpwr_by_handle = 0x40000fb0; +r_ble_ll_conn_set_unknown_rx_octets = 0x40000fb4; +r_ble_ll_conn_slave_start = 0x40000fb8; +r_ble_ll_conn_sm_get = 0x40000fbc; +r_ble_ll_conn_sm_new = 0x40000fc0; +r_ble_ll_conn_sm_npl_deinit = 0x40000fc4; +r_ble_ll_conn_sm_npl_init = 0x40000fc8; +r_ble_ll_conn_start_rx_encrypt = 0x40000fcc; +r_ble_ll_conn_start_rx_unencrypt = 0x40000fd0; +r_ble_ll_conn_timeout = 0x40000fd4; +r_ble_ll_conn_tx_pdu = 0x40000fd8; +r_ble_ll_conn_tx_pkt_in = 0x40000fdc; +r_ble_ll_conn_txend_encrypt = 0x40000fe0; +r_ble_ll_conn_update_conn_params = 0x40000fe4; +r_ble_ll_conn_update_eff_data_len = 0x40000fe8; +r_ble_ll_conn_update_new_pdu_len = 0x40000fec; +r_ble_ll_conn_wait_txend = 0x40000ff0; +r_ble_ll_conn_wfr_timer_exp = 0x40000ff4; +r_ble_ll_copy_data = 0x40000ff8; +r_ble_ll_ctrl_chanmap_req_make = 0x40000ffc; +r_ble_ll_ctrl_chk_proc_start = 0x40001000; +r_ble_ll_ctrl_conn_param_pdu_make = 0x40001004; +r_ble_ll_ctrl_conn_param_pdu_proc = 0x40001008; +r_ble_ll_ctrl_conn_param_reply = 0x4000100c; +r_ble_ll_ctrl_conn_upd_make = 0x40001010; +r_ble_ll_ctrl_datalen_upd_make = 0x40001014; +r_ble_ll_ctrl_enc_allowed_pdu = 0x40001018; +r_ble_ll_ctrl_enc_allowed_pdu_rx = 0x4000101c; +r_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40001020; +r_ble_ll_ctrl_enc_req_make = 0x40001024; +r_ble_ll_ctrl_find_new_phy = 0x40001028; +r_ble_ll_ctrl_initiate_dle = 0x4000102c; +r_ble_ll_ctrl_is_start_enc_rsp = 0x40001030; +r_ble_ll_ctrl_is_terminate_ind = 0x40001034; +r_ble_ll_ctrl_len_proc = 0x40001038; +r_ble_ll_ctrl_phy_from_phy_mask = 0x4000103c; +r_ble_ll_ctrl_phy_req_rsp_make = 0x40001040; +r_ble_ll_ctrl_phy_tx_transition_get = 0x40001044; +r_ble_ll_ctrl_phy_update_cancel = 0x40001048; +r_ble_ll_ctrl_phy_update_ind_make = 0x4000104c; +r_ble_ll_ctrl_phy_update_proc_complete = 0x40001050; +r_ble_ll_ctrl_proc_init = 0x40001054; +r_ble_ll_ctrl_proc_rsp_timer_cb = 0x40001058; +r_ble_ll_ctrl_proc_start = 0x4000105c; +r_ble_ll_ctrl_proc_stop = 0x40001060; +r_ble_ll_ctrl_proc_unk_rsp = 0x40001064; +r_ble_ll_ctrl_proc_with_instant_initiated = 0x40001068; +r_ble_ll_ctrl_rej_ext_ind_make = 0x4000106c; +r_ble_ll_ctrl_reject_ind_send = 0x40001070; +r_ble_ll_ctrl_rx_chanmap_req = 0x40001074; +r_ble_ll_ctrl_rx_conn_param_req = 0x40001078; +r_ble_ll_ctrl_rx_conn_param_rsp = 0x4000107c; +r_ble_ll_ctrl_rx_conn_update = 0x40001080; +r_ble_ll_ctrl_rx_enc_req = 0x40001084; +r_ble_ll_ctrl_rx_enc_rsp = 0x40001088; +r_ble_ll_ctrl_rx_feature_req = 0x4000108c; +r_ble_ll_ctrl_rx_feature_rsp = 0x40001090; +r_ble_ll_ctrl_rx_pause_enc_req = 0x40001094; +r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40001098; +r_ble_ll_ctrl_rx_pdu = 0x4000109c; +r_ble_ll_ctrl_rx_periodic_sync_ind = 0x400010a0; +r_ble_ll_ctrl_rx_phy_req = 0x400010a4; +r_ble_ll_ctrl_rx_phy_rsp = 0x400010a8; +r_ble_ll_ctrl_rx_phy_update_ind = 0x400010ac; +r_ble_ll_ctrl_rx_ping_rsp = 0x400010b0; +r_ble_ll_ctrl_rx_reject_ind = 0x400010b4; +r_ble_ll_ctrl_rx_start_enc_req = 0x400010b8; +r_ble_ll_ctrl_rx_start_enc_rsp = 0x400010bc; +r_ble_ll_ctrl_rx_version_ind = 0x400010c0; +r_ble_ll_ctrl_start_enc_send = 0x400010c4; +r_ble_ll_ctrl_start_rsp_timer = 0x400010c8; +r_ble_ll_ctrl_terminate_start = 0x400010cc; +r_ble_ll_ctrl_tx_done = 0x400010d0; +r_ble_ll_ctrl_update_features = 0x400010d4; +r_ble_ll_ctrl_version_ind_make = 0x400010d8; +r_ble_ll_data_buffer_overflow = 0x400010dc; +r_ble_ll_deinit = 0x400010e0; +r_ble_ll_disconn_comp_event_send = 0x400010e4; +r_ble_ll_dtm_calculate_itvl = 0x400010e8; +r_ble_ll_dtm_ctx_free = 0x400010ec; +r_ble_ll_dtm_deinit = 0x400010f0; +r_ble_ll_dtm_end_test = 0x400010f4; +r_ble_ll_dtm_ev_rx_restart_cb = 0x400010f8; +r_ble_ll_dtm_ev_tx_resched_cb = 0x400010fc; +r_ble_ll_dtm_init = 0x40001100; +r_ble_ll_dtm_reset = 0x40001104; +r_ble_ll_dtm_rx_create_ctx = 0x40001108; +r_ble_ll_dtm_rx_isr_end = 0x4000110c; +r_ble_ll_dtm_rx_isr_start = 0x40001110; +r_ble_ll_dtm_rx_pkt_in = 0x40001114; +r_ble_ll_dtm_rx_sched_cb = 0x40001118; +r_ble_ll_dtm_rx_start = 0x4000111c; +r_ble_ll_dtm_rx_test = 0x40001120; +r_ble_ll_dtm_set_next = 0x40001124; +r_ble_ll_dtm_tx_create_ctx = 0x40001128; +r_ble_ll_dtm_tx_done = 0x4000112c; +r_ble_ll_dtm_tx_sched_cb = 0x40001130; +r_ble_ll_dtm_tx_test = 0x40001134; +r_ble_ll_dtm_wfr_timer_exp = 0x40001138; +r_ble_ll_env_init = 0x4000113c; +r_ble_ll_event_comp_pkts = 0x40001140; +r_ble_ll_event_dbuf_overflow = 0x40001144; +r_ble_ll_event_rx_pkt = 0x40001148; +r_ble_ll_event_send = 0x4000114c; +r_ble_ll_event_tx_pkt = 0x40001150; +r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001154; +r_ble_ll_ext_conn_create = 0x40001158; +r_ble_ll_ext_scan_coex_dpc_process = 0x4000115c; +r_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001160; +r_ble_ll_ext_scan_coex_dpc_update = 0x40001164; +r_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001168; +r_ble_ll_ext_scan_parse_adv_info = 0x4000116c; +r_ble_ll_ext_scan_parse_aux_ptr = 0x40001170; +r_ble_ll_flush_pkt_queue = 0x40001174; +r_ble_ll_generic_data_init = 0x40001178; +r_ble_ll_get_addr_type = 0x4000117c; +r_ble_ll_get_chan_to_scan = 0x40001180; +r_ble_ll_get_our_devaddr = 0x40001184; +r_ble_ll_get_tx_pwr_compensation = 0x40001188; +r_ble_ll_hci_acl_rx = 0x4000118c; +r_ble_ll_hci_adv_mode_ext = 0x40001190; +r_ble_ll_hci_adv_set_enable = 0x40001194; +r_ble_ll_hci_cb_host_buf_size = 0x40001198; +r_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x4000119c; +r_ble_ll_hci_cb_set_event_mask = 0x400011a0; +r_ble_ll_hci_cb_set_event_mask2 = 0x400011a4; +r_ble_ll_hci_chk_phy_masks = 0x400011a8; +r_ble_ll_hci_cmd_proc = 0x400011ac; +r_ble_ll_hci_cmd_rx = 0x400011b0; +r_ble_ll_hci_ctlr_bb_cmd_proc = 0x400011b4; +r_ble_ll_hci_deinit = 0x400011b8; +r_ble_ll_hci_disconnect = 0x400011bc; +r_ble_ll_hci_dtm_rx_test = 0x400011c0; +r_ble_ll_hci_dtm_rx_test_v2 = 0x400011c4; +r_ble_ll_hci_dtm_tx_test = 0x400011c8; +r_ble_ll_hci_dtm_tx_test_ext = 0x400011cc; +r_ble_ll_hci_dtm_tx_test_v2 = 0x400011d0; +r_ble_ll_hci_dtm_tx_test_v2_ext = 0x400011d4; +r_ble_ll_hci_env_init = 0x400011d8; +r_ble_ll_hci_ev_conn_update = 0x400011dc; +r_ble_ll_hci_ev_databuf_overflow = 0x400011e0; +r_ble_ll_hci_ev_datalen_chg = 0x400011e4; +r_ble_ll_hci_ev_encrypt_chg = 0x400011e8; +r_ble_ll_hci_ev_hw_err = 0x400011ec; +r_ble_ll_hci_ev_le_csa = 0x400011f0; +r_ble_ll_hci_ev_ltk_req = 0x400011f4; +r_ble_ll_hci_ev_phy_update = 0x400011f8; +r_ble_ll_hci_ev_rd_rem_used_feat = 0x400011fc; +r_ble_ll_hci_ev_rd_rem_ver = 0x40001200; +r_ble_ll_hci_ev_rem_conn_parm_req = 0x40001204; +r_ble_ll_hci_ev_send_adv_set_terminated = 0x40001208; +r_ble_ll_hci_ev_send_scan_req_recv = 0x4000120c; +r_ble_ll_hci_ev_send_scan_timeout = 0x40001210; +r_ble_ll_hci_ev_send_vendor_err = 0x40001214; +r_ble_ll_hci_event_send = 0x40001218; +r_ble_ll_hci_ext_scan_set_enable = 0x4000121c; +r_ble_ll_hci_get_num_cmd_pkts = 0x40001220; +r_ble_ll_hci_info_params_cmd_proc = 0x40001224; +r_ble_ll_hci_init = 0x40001228; +r_ble_ll_hci_is_event_enabled = 0x4000122c; +r_ble_ll_hci_is_le_event_enabled = 0x40001230; +r_ble_ll_hci_le_cmd_proc = 0x40001234; +r_ble_ll_hci_le_cmd_send_cmd_status = 0x40001238; +r_ble_ll_hci_le_encrypt = 0x4000123c; +r_ble_ll_hci_le_rand = 0x40001240; +r_ble_ll_hci_le_rd_max_data_len = 0x40001244; +r_ble_ll_hci_le_rd_sugg_data_len = 0x40001248; +r_ble_ll_hci_le_read_bufsize = 0x4000124c; +r_ble_ll_hci_le_read_local_features = 0x40001250; +r_ble_ll_hci_le_read_supp_states = 0x40001254; +r_ble_ll_hci_le_set_def_phy = 0x40001258; +r_ble_ll_hci_le_wr_sugg_data_len = 0x4000125c; +r_ble_ll_hci_link_ctrl_cmd_proc = 0x40001260; +r_ble_ll_hci_npl_init = 0x40001264; +r_ble_ll_hci_rd_bd_addr = 0x40001268; +r_ble_ll_hci_rd_local_supp_cmd = 0x4000126c; +r_ble_ll_hci_rd_local_supp_feat = 0x40001270; +r_ble_ll_hci_rd_local_version = 0x40001274; +r_ble_ll_hci_scan_set_enable = 0x40001278; +r_ble_ll_hci_send_adv_report = 0x4000127c; +r_ble_ll_hci_send_dir_adv_report = 0x40001280; +r_ble_ll_hci_send_ext_adv_report = 0x40001284; +r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001288; +r_ble_ll_hci_send_noop = 0x4000128c; +r_ble_ll_hci_set_adv_data = 0x40001290; +r_ble_ll_hci_set_le_event_mask = 0x40001294; +r_ble_ll_hci_set_scan_rsp_data = 0x40001298; +r_ble_ll_hci_status_params_cmd_proc = 0x4000129c; +r_ble_ll_hci_vs_cmd_proc = 0x400012a0; +r_ble_ll_hci_vs_rd_static_addr = 0x400012a4; +r_ble_ll_hw_err_timer_cb = 0x400012a8; +r_ble_ll_hw_error = 0x400012ac; +r_ble_ll_init = 0x400012b0; +r_ble_ll_init_alloc_conn_comp_ev = 0x400012b4; +r_ble_ll_init_get_conn_comp_ev = 0x400012b8; +r_ble_ll_init_rx_isr_end = 0x400012bc; +r_ble_ll_init_rx_isr_start = 0x400012c0; +r_ble_ll_init_rx_pkt_in = 0x400012c4; +r_ble_ll_is_addr_empty = 0x400012c8; +r_ble_ll_is_controller_busy = 0x400012cc; +r_ble_ll_is_on_resolv_list = 0x400012d0; +r_ble_ll_is_our_devaddr = 0x400012d4; +r_ble_ll_is_rpa = 0x400012d8; +r_ble_ll_is_valid_adv_mode = 0x400012dc; +r_ble_ll_is_valid_own_addr_type = 0x400012e0; +r_ble_ll_is_valid_public_addr = 0x400012e4; +r_ble_ll_is_valid_random_addr = 0x400012e8; +r_ble_ll_mbuf_init = 0x400012ec; +r_ble_ll_misc_options_set = 0x400012f0; +r_ble_ll_pdu_max_tx_octets_get = 0x400012f4; +r_ble_ll_pdu_tx_time_get = 0x400012f8; +r_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x400012fc; +r_ble_ll_per_adv_coex_dpc_process = 0x40001300; +r_ble_ll_per_adv_coex_dpc_pti_get = 0x40001304; +r_ble_ll_per_adv_coex_dpc_update = 0x40001308; +r_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000130c; +r_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001310; +r_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001314; +r_ble_ll_phy_to_phy_mode = 0x40001318; +r_ble_ll_process_rx_data = 0x4000131c; +r_ble_ll_qa_enable = 0x40001320; +r_ble_ll_rand = 0x40001324; +r_ble_ll_rand_data_get = 0x40001328; +r_ble_ll_rand_deinit = 0x4000132c; +r_ble_ll_rand_env_init = 0x40001330; +r_ble_ll_rand_init = 0x40001334; +r_ble_ll_rand_prand_get = 0x40001338; +r_ble_ll_rand_sample = 0x4000133c; +r_ble_ll_rand_start = 0x40001340; +r_ble_ll_read_rf_path_compensation = 0x40001344; +r_ble_ll_read_supp_features = 0x40001348; +r_ble_ll_read_supp_states = 0x4000134c; +r_ble_ll_read_tx_power = 0x40001350; +r_ble_ll_reset = 0x40001354; +r_ble_ll_resolv_clear_all_pl_bit = 0x40001358; +r_ble_ll_resolv_clear_all_wl_bit = 0x4000135c; +r_ble_ll_resolv_deinit = 0x40001360; +r_ble_ll_resolv_enable_cmd = 0x40001364; +r_ble_ll_resolv_enabled = 0x40001368; +r_ble_ll_resolv_env_init = 0x4000136c; +r_ble_ll_resolv_gen_priv_addr = 0x40001370; +r_ble_ll_resolv_gen_rpa = 0x40001374; +r_ble_ll_resolv_get_addr_pointer = 0x40001378; +r_ble_ll_resolv_get_entry = 0x4000137c; +r_ble_ll_resolv_get_index = 0x40001380; +r_ble_ll_resolv_get_irk_pointer = 0x40001384; +r_ble_ll_resolv_get_list = 0x40001388; +r_ble_ll_resolv_get_priv_addr = 0x4000138c; +r_ble_ll_resolv_get_rpa_tmo = 0x40001390; +r_ble_ll_resolv_init = 0x40001394; +r_ble_ll_resolv_irk_nonzero = 0x40001398; +r_ble_ll_resolv_list_add = 0x4000139c; +r_ble_ll_resolv_list_chg_allowed = 0x400013a0; +r_ble_ll_resolv_list_clr = 0x400013a4; +r_ble_ll_resolv_list_find = 0x400013a8; +r_ble_ll_resolv_list_read_size = 0x400013ac; +r_ble_ll_resolv_list_reset = 0x400013b0; +r_ble_ll_resolv_list_rmv = 0x400013b4; +r_ble_ll_resolv_local_addr_rd = 0x400013b8; +r_ble_ll_resolv_peer_addr_rd = 0x400013bc; +r_ble_ll_resolv_peer_rpa_any = 0x400013c0; +r_ble_ll_resolv_reset = 0x400013c4; +r_ble_ll_resolv_rpa = 0x400013c8; +r_ble_ll_resolv_rpa_timer_cb = 0x400013cc; +r_ble_ll_resolv_set_local_rpa = 0x400013d0; +r_ble_ll_resolv_set_peer_rpa = 0x400013d4; +r_ble_ll_resolv_set_rpa_tmo = 0x400013d8; +r_ble_ll_resolve_set_priv_mode = 0x400013dc; +r_ble_ll_rfmgmt_controller_sleep_en = 0x400013e0; +r_ble_ll_rfmgmt_deinit = 0x400013e4; +r_ble_ll_rfmgmt_disable = 0x400013e8; +r_ble_ll_rfmgmt_enable = 0x400013ec; +r_ble_ll_rfmgmt_enable_now = 0x400013f0; +r_ble_ll_rfmgmt_init = 0x400013f4; +r_ble_ll_rfmgmt_is_enabled = 0x400013f8; +r_ble_ll_rfmgmt_release = 0x400013fc; +r_ble_ll_rfmgmt_release_ev = 0x40001400; +r_ble_ll_rfmgmt_reset = 0x40001404; +r_ble_ll_rfmgmt_scan_changed = 0x40001408; +r_ble_ll_rfmgmt_sched_changed = 0x4000140c; +r_ble_ll_rfmgmt_set_sleep_cb = 0x40001410; +r_ble_ll_rfmgmt_ticks_to_enabled = 0x40001414; +r_ble_ll_rfmgmt_timer_exp = 0x40001418; +r_ble_ll_rfmgmt_timer_reschedule = 0x4000141c; +r_ble_ll_rx_end = 0x40001420; +r_ble_ll_rx_pdu_in = 0x40001424; +r_ble_ll_rx_pkt_in = 0x40001428; +r_ble_ll_rx_start = 0x4000142c; +r_ble_ll_rxpdu_alloc = 0x40001430; +r_ble_ll_scan_add_scan_rsp_adv = 0x40001434; +r_ble_ll_scan_adv_decode_addr = 0x40001438; +r_ble_ll_scan_aux_data_free = 0x4000143c; +r_ble_ll_scan_aux_data_ref = 0x40001440; +r_ble_ll_scan_aux_data_unref = 0x40001444; +r_ble_ll_scan_can_chg_whitelist = 0x40001448; +r_ble_ll_scan_check_periodic_sync = 0x4000144c; +r_ble_ll_scan_chk_resume = 0x40001450; +r_ble_ll_scan_clean_cur_aux_data = 0x40001454; +r_ble_ll_scan_common_init = 0x40001458; +r_ble_ll_scan_continue_en = 0x4000145c; +r_ble_ll_scan_deinit = 0x40001460; +r_ble_ll_scan_dup_check_ext = 0x40001464; +r_ble_ll_scan_dup_check_legacy = 0x40001468; +r_ble_ll_scan_dup_move_to_head = 0x4000146c; +r_ble_ll_scan_dup_new = 0x40001470; +r_ble_ll_scan_dup_update_ext = 0x40001474; +r_ble_ll_scan_dup_update_legacy = 0x40001478; +r_ble_ll_scan_duration_period_timers_restart = 0x4000147c; +r_ble_ll_scan_duration_timer_cb = 0x40001480; +r_ble_ll_scan_enabled = 0x40001484; +r_ble_ll_scan_end_adv_evt = 0x40001488; +r_ble_ll_scan_env_init = 0x4000148c; +r_ble_ll_scan_event_proc = 0x40001490; +r_ble_ll_scan_ext_adv_init = 0x40001494; +r_ble_ll_scan_ext_initiator_start = 0x40001498; +r_ble_ll_scan_get_addr_data_from_legacy = 0x4000149c; +r_ble_ll_scan_get_addr_from_ext_adv = 0x400014a0; +r_ble_ll_scan_get_cur_sm = 0x400014a4; +r_ble_ll_scan_get_ext_adv_report = 0x400014a8; +r_ble_ll_scan_get_local_rpa = 0x400014ac; +r_ble_ll_scan_get_next_adv_prim_chan = 0x400014b0; +r_ble_ll_scan_get_pdu_data = 0x400014b4; +r_ble_ll_scan_get_peer_rpa = 0x400014b8; +r_ble_ll_scan_halt = 0x400014bc; +r_ble_ll_scan_has_sent_scan_req = 0x400014c0; +r_ble_ll_scan_have_rxd_scan_rsp = 0x400014c4; +r_ble_ll_scan_init = 0x400014c8; +r_ble_ll_scan_initiator_start = 0x400014cc; +r_ble_ll_scan_interrupted = 0x400014d0; +r_ble_ll_scan_interrupted_event_cb = 0x400014d4; +r_ble_ll_scan_is_inside_window = 0x400014d8; +r_ble_ll_scan_move_window_to = 0x400014dc; +r_ble_ll_scan_npl_init = 0x400014e0; +r_ble_ll_scan_npl_reset = 0x400014e4; +r_ble_ll_scan_npl_restore = 0x400014e8; +r_ble_ll_scan_npl_store = 0x400014ec; +r_ble_ll_scan_parse_ext_hdr = 0x400014f0; +r_ble_ll_scan_period_timer_cb = 0x400014f4; +r_ble_ll_scan_record_new_adv = 0x400014f8; +r_ble_ll_scan_refresh_nrpa = 0x400014fc; +r_ble_ll_scan_req_backoff = 0x40001500; +r_ble_ll_scan_reset = 0x40001504; +r_ble_ll_scan_rx_filter = 0x40001508; +r_ble_ll_scan_rx_isr_end = 0x4000150c; +r_ble_ll_scan_rx_isr_on_aux = 0x40001510; +r_ble_ll_scan_rx_isr_on_legacy = 0x40001514; +r_ble_ll_scan_rx_isr_start = 0x40001518; +r_ble_ll_scan_rx_pkt_in = 0x4000151c; +r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001520; +r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001524; +r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001528; +r_ble_ll_scan_rxed = 0x4000152c; +r_ble_ll_scan_sched_remove = 0x40001530; +r_ble_ll_scan_send_adv_report = 0x40001534; +r_ble_ll_scan_send_truncated = 0x40001538; +r_ble_ll_scan_set_enable = 0x4000153c; +r_ble_ll_scan_set_peer_rpa = 0x40001540; +r_ble_ll_scan_set_scan_params = 0x40001544; +r_ble_ll_scan_sm_start = 0x40001548; +r_ble_ll_scan_sm_stop = 0x4000154c; +r_ble_ll_scan_start = 0x40001550; +r_ble_ll_scan_time_hci_to_ticks = 0x40001554; +r_ble_ll_scan_timer_cb = 0x40001558; +r_ble_ll_scan_update_aux_data = 0x4000155c; +r_ble_ll_scan_wfr_timer_exp = 0x40001560; +r_ble_ll_scan_whitelist_enabled = 0x40001564; +r_ble_ll_sched_adv_new = 0x40001568; +r_ble_ll_sched_adv_resched_pdu = 0x4000156c; +r_ble_ll_sched_adv_reschedule = 0x40001570; +r_ble_ll_sched_aux_scan = 0x40001574; +r_ble_ll_sched_conn_overlap = 0x40001578; +r_ble_ll_sched_conn_reschedule = 0x4000157c; +r_ble_ll_sched_deinit = 0x40001580; +r_ble_ll_sched_dtm = 0x40001584; +r_ble_ll_sched_env_init = 0x40001588; +r_ble_ll_sched_execute_item = 0x4000158c; +r_ble_ll_sched_init = 0x40001590; +r_ble_ll_sched_insert_if_empty = 0x40001594; +r_ble_ll_sched_is_overlap = 0x40001598; +r_ble_ll_sched_master_new = 0x4000159c; +r_ble_ll_sched_next_time = 0x400015a0; +r_ble_ll_sched_overlaps_current = 0x400015a4; +r_ble_ll_sched_periodic_adv = 0x400015a8; +r_ble_ll_sched_rmv_elem = 0x400015ac; +r_ble_ll_sched_rmv_elem_type = 0x400015b0; +r_ble_ll_sched_run = 0x400015b4; +r_ble_ll_sched_scan_req_over_aux_ptr = 0x400015b8; +r_ble_ll_sched_slave_new = 0x400015bc; +r_ble_ll_sched_stop = 0x400015c0; +r_ble_ll_sched_sync = 0x400015c4; +r_ble_ll_sched_sync_overlaps_current = 0x400015c8; +r_ble_ll_sched_sync_reschedule = 0x400015cc; +r_ble_ll_set_default_privacy_mode = 0x400015d0; +r_ble_ll_set_default_sync_transfer_params = 0x400015d4; +r_ble_ll_set_ext_scan_params = 0x400015d8; +r_ble_ll_set_host_feat = 0x400015dc; +r_ble_ll_set_public_addr = 0x400015e0; +r_ble_ll_set_random_addr = 0x400015e4; +r_ble_ll_set_sync_transfer_params = 0x400015e8; +r_ble_ll_slave_rx_isr_end = 0x400015ec; +r_ble_ll_state_get = 0x400015f0; +r_ble_ll_state_set = 0x400015f4; +r_ble_ll_sync_adjust_ext_hdr = 0x400015f8; +r_ble_ll_sync_cancel = 0x400015fc; +r_ble_ll_sync_cancel_complete_event = 0x40001600; +r_ble_ll_sync_chain_start_cb = 0x40001604; +r_ble_ll_sync_check_acad = 0x40001608; +r_ble_ll_sync_check_failed = 0x4000160c; +r_ble_ll_sync_coex_dpc_process = 0x40001610; +r_ble_ll_sync_coex_dpc_pti_get = 0x40001614; +r_ble_ll_sync_coex_dpc_update = 0x40001618; +r_ble_ll_sync_create = 0x4000161c; +r_ble_ll_sync_current_sm_over = 0x40001620; +r_ble_ll_sync_deinit = 0x40001624; +r_ble_ll_sync_enabled = 0x40001628; +r_ble_ll_sync_env_init = 0x4000162c; +r_ble_ll_sync_est_event_failed = 0x40001630; +r_ble_ll_sync_est_event_success = 0x40001634; +r_ble_ll_sync_established = 0x40001638; +r_ble_ll_sync_event_end = 0x4000163c; +r_ble_ll_sync_event_start_cb = 0x40001640; +r_ble_ll_sync_filter_enabled = 0x40001644; +r_ble_ll_sync_find = 0x40001648; +r_ble_ll_sync_get_cur_sm = 0x4000164c; +r_ble_ll_sync_get_event_end_time = 0x40001650; +r_ble_ll_sync_get_handle = 0x40001654; +r_ble_ll_sync_halt = 0x40001658; +r_ble_ll_sync_has_been_reported = 0x4000165c; +r_ble_ll_sync_info_event = 0x40001660; +r_ble_ll_sync_init = 0x40001664; +r_ble_ll_sync_list_add = 0x40001668; +r_ble_ll_sync_list_clear = 0x4000166c; +r_ble_ll_sync_list_empty = 0x40001670; +r_ble_ll_sync_list_get_free = 0x40001674; +r_ble_ll_sync_list_remove = 0x40001678; +r_ble_ll_sync_list_search = 0x4000167c; +r_ble_ll_sync_list_size = 0x40001680; +r_ble_ll_sync_lost_event = 0x40001684; +r_ble_ll_sync_next_event = 0x40001688; +r_ble_ll_sync_on_list = 0x4000168c; +r_ble_ll_sync_parse_aux_ptr = 0x40001690; +r_ble_ll_sync_parse_ext_hdr = 0x40001694; +r_ble_ll_sync_periodic_ind = 0x40001698; +r_ble_ll_sync_phy_mode_to_aux_phy = 0x4000169c; +r_ble_ll_sync_phy_mode_to_hci = 0x400016a0; +r_ble_ll_sync_put_syncinfo = 0x400016a4; +r_ble_ll_sync_reserve = 0x400016a8; +r_ble_ll_sync_reset = 0x400016ac; +r_ble_ll_sync_reset_sm = 0x400016b0; +r_ble_ll_sync_rmvd_from_sched = 0x400016b4; +r_ble_ll_sync_rx_isr_end = 0x400016b8; +r_ble_ll_sync_rx_isr_start = 0x400016bc; +r_ble_ll_sync_rx_pkt_in = 0x400016c0; +r_ble_ll_sync_schedule_chain = 0x400016c4; +r_ble_ll_sync_send_per_adv_rpt = 0x400016c8; +r_ble_ll_sync_send_sync_ind = 0x400016cc; +r_ble_ll_sync_send_truncated_per_adv_rpt = 0x400016d0; +r_ble_ll_sync_sm_clear = 0x400016d4; +r_ble_ll_sync_terminate = 0x400016d8; +r_ble_ll_sync_transfer = 0x400016dc; +r_ble_ll_sync_transfer_get = 0x400016e0; +r_ble_ll_sync_transfer_received = 0x400016e4; +r_ble_ll_sync_wfr_timer_exp = 0x400016e8; +r_ble_ll_task = 0x400016ec; +r_ble_ll_trace_set_func = 0x400016f0; +r_ble_ll_trace_u32 = 0x400016f4; +r_ble_ll_trace_u32x2 = 0x400016f8; +r_ble_ll_trace_u32x3 = 0x400016fc; +r_ble_ll_tx_flat_mbuf_pducb = 0x40001700; +r_ble_ll_tx_mbuf_pducb = 0x40001704; +r_ble_ll_tx_pkt_in = 0x40001708; +r_ble_ll_update_max_tx_octets_phy_mode = 0x4000170c; +r_ble_ll_usecs_to_ticks_round_up = 0x40001710; +r_ble_ll_utils_calc_access_addr = 0x40001714; +r_ble_ll_utils_calc_dci_csa2 = 0x40001718; +r_ble_ll_utils_calc_num_used_chans = 0x4000171c; +r_ble_ll_utils_calc_window_widening = 0x40001720; +r_ble_ll_utils_csa2_perm = 0x40001724; +r_ble_ll_utils_csa2_prng = 0x40001728; +r_ble_ll_utils_remapped_channel = 0x4000172c; +r_ble_ll_wfr_timer_exp = 0x40001730; +r_ble_ll_whitelist_add = 0x40001734; +r_ble_ll_whitelist_chg_allowed = 0x40001738; +r_ble_ll_whitelist_clear = 0x4000173c; +r_ble_ll_whitelist_read_size = 0x40001740; +r_ble_ll_whitelist_rmv = 0x40001744; +r_ble_ll_whitelist_search = 0x40001748; +r_ble_ll_write_rf_path_compensation = 0x4000174c; +r_ble_phy_access_addr_get = 0x40001750; +r_ble_phy_bb_bug_is_triggered = 0x40001754; +r_ble_phy_calculate_rxtx_ifs = 0x40001758; +r_ble_phy_calculate_rxwindow = 0x4000175c; +r_ble_phy_calculate_txrx_ifs = 0x40001760; +r_ble_phy_config_access_addr = 0x40001764; +r_ble_phy_data_make = 0x40001768; +r_ble_phy_disable = 0x4000176c; +r_ble_phy_disable_irq = 0x40001770; +r_ble_phy_disable_whitening = 0x40001774; +r_ble_phy_enable_scan_seq_immediately = 0x40001778; +r_ble_phy_enable_whitening = 0x4000177c; +r_ble_phy_encrypt_disable = 0x40001780; +r_ble_phy_env_init = 0x40001784; +r_ble_phy_get_current_phy = 0x40001788; +r_ble_phy_get_packet_counter = 0x4000178c; +r_ble_phy_get_packet_status = 0x40001790; +r_ble_phy_get_pyld_time_offset = 0x40001794; +r_ble_phy_get_rx_phy_mode = 0x40001798; +r_ble_phy_init = 0x4000179c; +r_ble_phy_isr = 0x400017a0; +r_ble_phy_max_data_pdu_pyld = 0x400017a4; +r_ble_phy_mode_config = 0x400017a8; +r_ble_phy_mode_convert = 0x400017ac; +r_ble_phy_mode_write = 0x400017b0; +r_ble_phy_module_deinit = 0x400017b4; +r_ble_phy_module_init = 0x400017b8; +r_ble_phy_monitor_bb_sync = 0x400017bc; +r_ble_phy_need_to_report = 0x400017c0; +r_ble_phy_pkt_received = 0x400017c4; +r_ble_phy_reset_bb_monitor = 0x400017c8; +r_ble_phy_resolv_list_disable = 0x400017cc; +r_ble_phy_resolv_list_enable = 0x400017d0; +r_ble_phy_restart_sequence = 0x400017d4; +r_ble_phy_rfclk_disable = 0x400017d8; +r_ble_phy_rfclk_enable = 0x400017dc; +r_ble_phy_rx_is_expected = 0x400017e0; +r_ble_phy_rxpdu_copy = 0x400017e4; +r_ble_phy_scan_set_start_time = 0x400017e8; +r_ble_phy_seq_encrypt_enable = 0x400017ec; +r_ble_phy_seq_encrypt_set_pkt_cntr = 0x400017f0; +r_ble_phy_sequence_adv_end = 0x400017f4; +r_ble_phy_sequence_copy_rx_flags = 0x400017f8; +r_ble_phy_sequence_end_isr = 0x400017fc; +r_ble_phy_sequence_get_mode = 0x40001800; +r_ble_phy_sequence_get_state = 0x40001804; +r_ble_phy_sequence_init_end = 0x40001808; +r_ble_phy_sequence_is_running = 0x4000180c; +r_ble_phy_sequence_is_waiting_rsp = 0x40001810; +r_ble_phy_sequence_isr_copy_data = 0x40001814; +r_ble_phy_sequence_master_end = 0x40001818; +r_ble_phy_sequence_rx_end_isr = 0x4000181c; +r_ble_phy_sequence_scan_end = 0x40001820; +r_ble_phy_sequence_single_end = 0x40001824; +r_ble_phy_sequence_slave_end = 0x40001828; +r_ble_phy_sequence_tx_end_invoke = 0x4000182c; +r_ble_phy_sequence_update_conn_params = 0x40001830; +r_ble_phy_set_adv_sequence = 0x40001834; +r_ble_phy_set_coex_pti = 0x40001838; +r_ble_phy_set_dev_address = 0x4000183c; +r_ble_phy_set_master_sequence = 0x40001840; +r_ble_phy_set_rx_pwr_compensation = 0x40001844; +r_ble_phy_set_rxhdr_flags = 0x40001848; +r_ble_phy_set_rxhdr_info = 0x4000184c; +r_ble_phy_set_scan_sequence = 0x40001850; +r_ble_phy_set_single_packet_rx_sequence = 0x40001854; +r_ble_phy_set_single_packet_tx_sequence = 0x40001858; +r_ble_phy_set_slave_sequence = 0x4000185c; +r_ble_phy_set_txend_cb = 0x40001860; +r_ble_phy_setchan = 0x40001864; +r_ble_phy_slave_set_start_time = 0x40001868; +r_ble_phy_state_get = 0x4000186c; +r_ble_phy_timer_config_start_time = 0x40001870; +r_ble_phy_timer_start_now = 0x40001874; +r_ble_phy_timer_stop = 0x40001878; +r_ble_phy_tx_set_start_time = 0x4000187c; +r_ble_phy_txpower_round = 0x40001880; +r_ble_phy_txpwr_set = 0x40001884; +r_ble_phy_wfr_enable = 0x40001888; +r_ble_phy_xcvr_state_get = 0x4000188c; +r_ble_plf_set_log_level = 0x40001890; +r_ble_vendor_hci_register = 0x40001894; +r_bleonly_os_tick_init = 0x40001898; +r_bt_rf_coex_cfg_set = 0x4000189c; +r_bt_rf_coex_coded_txrx_time_upper_lim = 0x400018a0; +r_bt_rf_coex_dft_pti_set = 0x400018a4; +r_bt_rf_coex_hook_deinit = 0x400018a8; +r_bt_rf_coex_hook_init = 0x400018ac; +r_bt_rf_coex_hook_st_set = 0x400018b0; +r_bt_rf_coex_hooks_p_set_default = 0x400018b4; +r_btdm_disable_adv_delay = 0x400018b8; +r_btdm_switch_phy_coded = 0x400018bc; +r_esp_wait_disabled = 0x400018c0; +r_get_be16 = 0x400018c4; +r_get_be24 = 0x400018c8; +r_get_be32 = 0x400018cc; +r_get_be64 = 0x400018d0; +r_get_le16 = 0x400018d4; +r_get_le24 = 0x400018d8; +r_get_le32 = 0x400018dc; +r_get_le64 = 0x400018e0; +r_get_local_irk_offset = 0x400018e4; +r_get_local_rpa_offset = 0x400018e8; +r_get_max_skip = 0x400018ec; +r_get_peer_id_offset = 0x400018f0; +r_get_peer_irk_offset = 0x400018f4; +r_get_peer_rpa_offset = 0x400018f8; +r_hal_os_tick_read_tick = 0x400018fc; +r_hal_os_tick_set_exp_tick = 0x40001900; +r_hal_rtc_intr_init = 0x40001904; +r_hal_rtc_irq_handler = 0x40001908; +r_hal_timer_deinit = 0x4000190c; +r_hal_timer_disable_irq = 0x40001910; +r_hal_timer_env_init = 0x40001914; +r_hal_timer_init = 0x40001918; +r_hal_timer_process = 0x4000191c; +r_hal_timer_read = 0x40001920; +r_hal_timer_read_tick = 0x40001924; +r_hal_timer_set_cb = 0x40001928; +r_hal_timer_set_exp_tick = 0x4000192c; +r_hal_timer_start = 0x40001930; +r_hal_timer_start_at = 0x40001934; +r_hal_timer_stop = 0x40001938; +r_hal_timer_task_start = 0x4000193c; +r_ll_assert = 0x40001940; +r_mem_init_mbuf_pool = 0x40001944; +r_mem_malloc_mbuf_pool = 0x40001948; +r_mem_malloc_mbufpkt_pool = 0x4000194c; +r_mem_malloc_mempool = 0x40001950; +r_mem_malloc_mempool_ext = 0x40001954; +r_mem_malloc_mempool_gen = 0x40001958; +r_mem_pullup_obj = 0x4000195c; +r_mem_split_frag = 0x40001960; +r_os_cputime_delay_ticks = 0x40001964; +r_os_cputime_delay_usecs = 0x40001968; +r_os_cputime_get32 = 0x4000196c; +r_os_cputime_ticks_to_usecs = 0x40001970; +r_os_cputime_timer_init = 0x40001974; +r_os_cputime_timer_relative = 0x40001978; +r_os_cputime_timer_start = 0x4000197c; +r_os_cputime_timer_stop = 0x40001980; +r_os_cputime_usecs_to_ticks = 0x40001984; +r_os_mbuf_adj = 0x40001988; +r_os_mbuf_append = 0x4000198c; +r_os_mbuf_appendfrom = 0x40001990; +r_os_mbuf_cmpf = 0x40001994; +r_os_mbuf_cmpm = 0x40001998; +r_os_mbuf_concat = 0x4000199c; +r_os_mbuf_copydata = 0x400019a0; +r_os_mbuf_copyinto = 0x400019a4; +r_os_mbuf_dup = 0x400019a8; +r_os_mbuf_extend = 0x400019ac; +r_os_mbuf_free = 0x400019b0; +r_os_mbuf_free_chain = 0x400019b4; +r_os_mbuf_get = 0x400019b8; +r_os_mbuf_get_pkthdr = 0x400019bc; +r_os_mbuf_len = 0x400019c0; +r_os_mbuf_off = 0x400019c4; +r_os_mbuf_pack_chains = 0x400019c8; +r_os_mbuf_pool_init = 0x400019cc; +r_os_mbuf_prepend = 0x400019d0; +r_os_mbuf_prepend_pullup = 0x400019d4; +r_os_mbuf_pullup = 0x400019d8; +r_os_mbuf_trim_front = 0x400019dc; +r_os_mbuf_widen = 0x400019e0; +r_os_memblock_from = 0x400019e4; +r_os_memblock_get = 0x400019e8; +r_os_memblock_put = 0x400019ec; +r_os_memblock_put_from_cb = 0x400019f0; +r_os_mempool_clear = 0x400019f4; +r_os_mempool_ext_clear = 0x400019f8; +r_os_mempool_ext_init = 0x400019fc; +r_os_mempool_info_get_next = 0x40001a00; +r_os_mempool_init = 0x40001a04; +r_os_mempool_init_internal = 0x40001a08; +r_os_mempool_is_sane = 0x40001a0c; +r_os_mempool_module_init = 0x40001a10; +r_os_mempool_unregister = 0x40001a14; +r_os_mqueue_get = 0x40001a18; +r_os_mqueue_init = 0x40001a1c; +r_os_mqueue_put = 0x40001a20; +r_os_msys_count = 0x40001a24; +r_os_msys_get = 0x40001a28; +r_os_msys_get_pkthdr = 0x40001a2c; +r_os_msys_num_free = 0x40001a30; +r_os_msys_register = 0x40001a34; +r_os_msys_reset = 0x40001a38; +r_os_tick_idle = 0x40001a3c; +r_pri_phy_valid = 0x40001a40; +r_put_be16 = 0x40001a44; +r_put_be24 = 0x40001a48; +r_put_be32 = 0x40001a4c; +r_put_be64 = 0x40001a50; +r_put_le16 = 0x40001a54; +r_put_le24 = 0x40001a58; +r_put_le32 = 0x40001a5c; +r_put_le64 = 0x40001a60; +r_rtc0_timer_handler = 0x40001a64; +r_rtc1_timer_handler = 0x40001a68; +r_sdkconfig_get_opts = 0x40001a6c; +r_sdkconfig_set_opts = 0x40001a70; +r_sec_phy_valid = 0x40001a74; +r_sub24 = 0x40001a78; +r_swap_buf = 0x40001a7c; +r_swap_in_place = 0x40001a80; +/* Data (.data, .bss, .rodata) */ +ble_hci_uart_reset_cmd = 0x3ff1ffe0; +ble_hci_trans_env_p = 0x3fcdffc4; +ble_hci_trans_mode = 0x3fcdfebc; +ble_ll_adv_env_p = 0x3fcdffc0; +ble_ll_conn_env_p = 0x3fcdffbc; +g_ble_ll_conn_cth_flow = 0x3fcdffb4; +g_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0; +g_ble_ll_ctrl_pkt_lengths_ro = 0x3ff1ffbc; +ble_ll_dtm_module_env_p = 0x3fcdffac; +channel_rf_to_index = 0x3ff1ff94; +g_ble_ll_dtm_prbs15_data = 0x3ff1fe94; +g_ble_ll_dtm_prbs9_data = 0x3ff1fd94; +ble_ll_hci_env_p = 0x3fcdffa8; +ble_ll_rand_env_p = 0x3fcdffa4; +ble_ll_resolv_env_p = 0x3fcdffa0; +g_ble_ll_resolve_hdr = 0x3fcdff98; +g_device_mode_default = 0x3fcdfeba; +g_ble_ll_rfmgmt_data = 0x3fcdff50; +g_ble_sleep_enter_cb = 0x3fcdff4c; +g_ble_sleep_exit_cb = 0x3fcdff48; +g_rfclk_enabled = 0x3fcdff44; +ble_ll_scan_env_p = 0x3fcdff40; +ble_ll_sched_env_p = 0x3fcdff3c; +g_ble_ll_supp_cmds_ro = 0x3ff1fd64; +ble_ll_sync_env_p = 0x3fcdff38; +g_ble_sca_ppm_tbl_ro = 0x3ff1fd54; +ble_ll_env_p = 0x3fcdff34; +g_ble_ll_pdu_header_tx_time_ro = 0x3ff1fd4c; +priv_config_opts = 0x3fcdfea4; +ble_hci_trans_funcs_ptr = 0x3fcdff30; +r_ble_stub_funcs_ptr = 0x3fcdff2c; +r_ext_funcs_p = 0x3fcdff28; +r_npl_funcs = 0x3fcdff24; +ble_hw_env_p = 0x3fcdff20; +ble_phy_module_env_p = 0x3fcdff1c; +g_ble_phy_chan_freq_ro = 0x3ff1fd24; +g_ble_phy_mode_pkt_start_off_ro = 0x3ff1fd1c; +g_ble_phy_rxtx_ifs_compensation_ro = 0x3ff1fd0c; +g_ble_phy_t_rxaddrdelay_ro = 0x3ff1fd08; +g_ble_phy_t_rxenddelay_ro = 0x3ff1fd04; +g_ble_phy_t_txdelay_ro = 0x3ff1fd00; +g_ble_phy_t_txenddelay_ro = 0x3ff1fcfc; +g_ble_phy_txrx_ifs_compensation_ro = 0x3ff1fcec; +hal_timer_env_p = 0x3fcdff18; +g_hal_os_tick = 0x3fcdff0c; +r_osi_coex_funcs_p = 0x3fcdff08; +bt_rf_coex_hooks = 0x3fcdff00; +bt_rf_coex_hooks_p = 0x3fcdfefc; +coex_hook_st_group_tab = 0x3ff1fce0; +coex_hook_st_group_to_coex_schm_st_tab = 0x3ff1fcdc; +s_ble_act_count_by_group = 0x3fcdfef8; +s_ble_coex_st_map = 0x3fcdfee4; +bt_rf_coex_cfg_cb = 0x3fcdfec8; +bt_rf_coex_cfg_p = 0x3fcdfec4; +bt_rf_coex_cfg_rom = 0x3ff1fcc0; +bt_rf_coex_pti_dft_p = 0x3fcdfec0; +bt_rf_coex_pti_dft_rom = 0x3fcdfe64; +conn_dynamic_pti_param_rom = 0x3ff1fca8; +conn_phy_coded_max_data_time_param_rom = 0x3ff1fca4; +ext_adv_dynamic_pti_param_rom = 0x3ff1fc70; +ext_scan_dynamic_param_rom = 0x3ff1fc38; +legacy_adv_dynamic_pti_param_rom = 0x3ff1fc18; +per_adv_dynamic_pti_param_rom = 0x3ff1fbfc; +sync_dynamic_param_rom = 0x3ff1fbe4; +g_ble_plf_log_level = 0x3fcdfe60; +g_msys_pool_list = 0x3fcdfe58; +g_os_mempool_list = 0x3fcdfe50; /*************************************** @@ -521,180 +1682,277 @@ PROVIDE( g_usb_print = 0x3fcdffcc ); ***************************************/ /* Functions */ -phy_get_romfuncs = 0x400008b0; -rom_abs_temp = 0x400008b4; -rom_bb_bss_cbw40_dig = 0x400008b8; -rom_bb_wdg_test_en = 0x400008bc; -rom_bb_wdt_get_status = 0x400008c0; -rom_bb_wdt_int_enable = 0x400008c4; -rom_bb_wdt_rst_enable = 0x400008c8; -rom_bb_wdt_timeout_clear = 0x400008cc; -rom_cbw2040_cfg = 0x400008d0; -rom_check_noise_floor = 0x400008d4; -rom_chip_i2c_readReg = 0x400008d8; -rom_chip_i2c_writeReg = 0x400008dc; -rom_correct_rf_ana_gain = 0x400008e0; -rom_dc_iq_est = 0x400008e4; -rom_disable_agc = 0x400008e8; -rom_en_pwdet = 0x400008ec; -rom_enable_agc = 0x400008f0; -rom_get_bbgain_db = 0x400008f4; -rom_get_data_sat = 0x400008f8; -rom_get_i2c_read_mask = 0x400008fc; -rom_get_pwctrl_correct = 0x40000900; -rom_get_rf_gain_qdb = 0x40000904; -rom_i2c_readReg = 0x40000908; -rom_i2c_readReg_Mask = 0x4000090c; -rom_i2c_writeReg = 0x40000910; -rom_i2c_writeReg_Mask = 0x40000914; -rom_index_to_txbbgain = 0x40000918; -rom_iq_est_disable = 0x4000091c; -rom_iq_est_enable = 0x40000920; -rom_linear_to_db = 0x40000924; -rom_loopback_mode_en = 0x40000928; -rom_mhz2ieee = 0x4000092c; -rom_noise_floor_auto_set = 0x40000930; -rom_pbus_debugmode = 0x40000934; -rom_pbus_force_mode = 0x40000938; -rom_pbus_force_test = 0x4000093c; -rom_pbus_rd = 0x40000940; -rom_pbus_rd_addr = 0x40000944; -rom_pbus_rd_shift = 0x40000948; -rom_pbus_set_dco = 0x4000094c; -rom_pbus_set_rxgain = 0x40000950; -rom_pbus_workmode = 0x40000954; -rom_pbus_xpd_rx_off = 0x40000958; -rom_pbus_xpd_rx_on = 0x4000095c; -rom_pbus_xpd_tx_off = 0x40000960; -rom_pbus_xpd_tx_on = 0x40000964; -rom_phy_byte_to_word = 0x40000968; -rom_phy_disable_cca = 0x4000096c; -rom_phy_enable_cca = 0x40000970; -rom_phy_get_noisefloor = 0x40000974; -rom_phy_get_rx_freq = 0x40000978; -rom_phy_set_bbfreq_init = 0x4000097c; -rom_pow_usr = 0x40000980; -rom_pwdet_sar2_init = 0x40000984; -rom_read_hw_noisefloor = 0x40000988; -rom_read_sar_dout = 0x4000098c; -rom_set_cal_rxdc = 0x40000990; -rom_set_chan_cal_interp = 0x40000994; -rom_set_loopback_gain = 0x40000998; -rom_set_noise_floor = 0x4000099c; -rom_set_rxclk_en = 0x400009a0; -rom_set_tx_dig_gain = 0x400009a4; -rom_set_txcap_reg = 0x400009a8; -rom_set_txclk_en = 0x400009ac; -rom_spur_cal = 0x400009b0; -rom_spur_reg_write_one_tone = 0x400009b4; -rom_target_power_add_backoff = 0x400009b8; -rom_tx_pwctrl_bg_init = 0x400009bc; -rom_txbbgain_to_index = 0x400009c0; -rom_wifi_11g_rate_chg = 0x400009c4; -rom_write_gain_mem = 0x400009c8; -chip726_phyrom_version = 0x400009cc; -rom_disable_wifi_agc = 0x400009d0; -rom_enable_wifi_agc = 0x400009d4; -rom_set_tx_gain_table = 0x400009d8; -rom_bt_index_to_bb = 0x400009dc; -rom_bt_bb_to_index = 0x400009e0; -rom_wr_bt_tx_atten = 0x400009e4; -rom_wr_bt_tx_gain_mem = 0x400009e8; -rom_spur_coef_cfg = 0x400009ec; -rom_bb_bss_cbw40 = 0x400009f0; -rom_set_cca = 0x400009f4; -rom_tx_paon_set = 0x400009f8; -rom_i2cmst_reg_init = 0x400009fc; -rom_iq_corr_enable = 0x40000a00; -rom_fe_reg_init = 0x40000a04; -rom_agc_reg_init = 0x40000a08; -rom_bb_reg_init = 0x40000a0c; -rom_mac_enable_bb = 0x40000a10; -rom_bb_wdg_cfg = 0x40000a14; -rom_force_txon = 0x40000a18; -rom_fe_txrx_reset = 0x40000a1c; -rom_set_rx_comp = 0x40000a20; -rom_set_pbus_reg = 0x40000a24; -rom_write_chan_freq = 0x40000a28; -rom_phy_xpd_rf = 0x40000a2c; -rom_set_xpd_sar = 0x40000a30; -rom_write_dac_gain2 = 0x40000a34; -rom_rtc_sar2_init = 0x40000a38; -rom_get_target_power_offset = 0x40000a3c; -rom_write_txrate_power_offset = 0x40000a40; -rom_get_rate_fcc_index = 0x40000a44; -rom_get_rate_target_power = 0x40000a48; -rom_write_wifi_dig_gain = 0x40000a4c; -rom_bt_correct_rf_ana_gain = 0x40000a50; -rom_pkdet_vol_start = 0x40000a54; -rom_read_sar2_code = 0x40000a58; -rom_get_sar2_vol = 0x40000a5c; -rom_get_pll_vol = 0x40000a60; -rom_get_phy_target_power = 0x40000a64; -rom_temp_to_power = 0x40000a68; -rom_phy_track_pll_cap = 0x40000a6c; -rom_phy_pwdet_always_en = 0x40000a70; -rom_phy_pwdet_onetime_en = 0x40000a74; -rom_get_i2c_mst0_mask = 0x40000a78; -rom_get_i2c_hostid = 0x40000a7c; -rom_enter_critical_phy = 0x40000a80; -rom_exit_critical_phy = 0x40000a84; -rom_chip_i2c_readReg_org = 0x40000a88; -rom_i2c_paral_set_mst0 = 0x40000a8c; -rom_i2c_paral_set_read = 0x40000a90; -rom_i2c_paral_read = 0x40000a94; -rom_i2c_paral_write = 0x40000a98; -rom_i2c_paral_write_num = 0x40000a9c; -rom_i2c_paral_write_mask = 0x40000aa0; -rom_bb_bss_cbw40_ana = 0x40000aa4; -rom_chan_to_freq = 0x40000aa8; -rom_open_i2c_xpd = 0x40000aac; -rom_dac_rate_set = 0x40000ab0; -rom_tsens_read_init = 0x40000ab4; -rom_tsens_code_read = 0x40000ab8; -rom_tsens_index_to_dac = 0x40000abc; -rom_tsens_index_to_offset = 0x40000ac0; -rom_tsens_dac_cal = 0x40000ac4; -rom_code_to_temp = 0x40000ac8; -rom_write_pll_cap_mem = 0x40000acc; -rom_pll_correct_dcap = 0x40000ad0; -rom_phy_en_hw_set_freq = 0x40000ad4; -rom_phy_dis_hw_set_freq = 0x40000ad8; -rom_pll_vol_cal = 0x40000adc; -rom_wrtie_pll_cap = 0x40000ae0; -rom_set_tx_gain_mem = 0x40000ae4; -rom_bt_tx_dig_gain = 0x40000ae8; -rom_bt_get_tx_gain = 0x40000aec; -rom_get_chan_target_power = 0x40000af0; -rom_get_tx_gain_value = 0x40000af4; -rom_wifi_tx_dig_gain = 0x40000af8; -rom_wifi_get_tx_gain = 0x40000afc; -rom_fe_i2c_reg_renew = 0x40000b00; -rom_wifi_agc_sat_gain = 0x40000b04; -rom_i2c_master_reset = 0x40000b08; -rom_bt_filter_reg = 0x40000b0c; -rom_phy_bbpll_cal = 0x40000b10; -rom_i2c_sar2_init_code = 0x40000b14; -rom_phy_param_addr = 0x40000b18; -rom_phy_reg_init = 0x40000b1c; -rom_set_chan_reg = 0x40000b20; -rom_phy_wakeup_init = 0x40000b24; -rom_phy_i2c_init1 = 0x40000b28; -rom_tsens_temp_read = 0x40000b2c; -rom_bt_track_pll_cap = 0x40000b30; -rom_wifi_track_pll_cap = 0x40000b34; -rom_wifi_set_tx_gain = 0x40000b38; -rom_txpwr_cal_track = 0x40000b3c; -rom_tx_pwctrl_background = 0x40000b40; -rom_bt_set_tx_gain = 0x40000b44; -rom_noise_check_loop = 0x40000b48; -rom_phy_close_rf = 0x40000b4c; -rom_phy_xpd_tsens = 0x40000b50; -rom_phy_freq_mem_backup = 0x40000b54; -rom_phy_ant_init = 0x40000b58; -rom_bt_track_tx_power = 0x40000b5c; -rom_wifi_track_tx_power = 0x40000b60; -rom_phy_dig_reg_backup = 0x40000b64; -chip726_phyrom_version_num = 0x40000b68; +phy_param_addr = 0x40001a84; +phy_get_romfuncs = 0x40001a88; +chip729_phyrom_version = 0x40001a8c; +chip729_phyrom_version_num = 0x40001a90; +rom_get_bias_ref_code = 0x40001a94; +get_rc_dout = 0x40001a98; +rc_cal = 0x40001a9c; +phy_analog_delay_cal = 0x40001aa0; +RFChannelSel = 0x40001aa4; +phy_change_channel = 0x40001aa8; +phy_set_most_tpw = 0x40001aac; +phy_rx_rifs_en = 0x40001ab0; +phy_get_most_tpw = 0x40001ab4; +esp_tx_state_out = 0x40001ab8; +phy_get_adc_rand = 0x40001abc; +phy_internal_delay = 0x40001ac0; +phy_ftm_comp = 0x40001ac4; +phy_11p_set = 0x40001ac8; +phy_current_level_set = 0x40001acc; +phy_bbpll_en_usb = 0x40001ad0; +phy_bt_power_track = 0x40001ad4; +rom_enter_critical_phy = 0x40001ad8; +rom_exit_critical_phy = 0x40001adc; +rom_bb_bss_cbw40 = 0x40001ae0; +rom_set_chan_reg = 0x40001ae4; +abs_temp = 0x40001ae8; +set_chan_cal_interp = 0x40001aec; +loopback_mode_en = 0x40001af0; +get_data_sat = 0x40001af4; +phy_byte_to_word = 0x40001af8; +phy_get_rx_freq = 0x40001afc; +i2c_master_reset = 0x40001b00; +chan14_mic_enable = 0x40001b04; +chan14_mic_cfg = 0x40001b08; +set_adc_rand = 0x40001b0c; +wr_rf_freq_mem = 0x40001b10; +freq_i2c_write_set = 0x40001b14; +write_pll_cap_mem = 0x40001b18; +get_rf_freq_cap = 0x40001b1c; +get_rf_freq_init = 0x40001b20; +freq_get_i2c_data = 0x40001b24; +freq_i2c_data_write = 0x40001b28; +set_chan_freq_hw_init = 0x40001b2c; +phy_en_hw_set_freq = 0x40001b30; +phy_dis_hw_set_freq = 0x40001b34; +register_chipv7_phy_init_param = 0x40001b38; +phy_reg_init = 0x40001b3c; +phy_xpd_rf = 0x40001b40; +phy_close_rf = 0x40001b44; +rf_cal_data_recovery = 0x40001b48; +rf_cal_data_backup = 0x40001b4c; +phy_rfcal_data_check = 0x40001b50; +rom_pwdet_sar2_init = 0x40001b54; +rom_en_pwdet = 0x40001b58; +rom_get_sar_sig_ref = 0x40001b5c; +rom_pwdet_tone_start = 0x40001b60; +rom_get_tone_sar_dout = 0x40001b64; +rom_get_fm_sar_dout = 0x40001b68; +rom_txtone_linear_pwr = 0x40001b6c; +rom_get_power_db = 0x40001b70; +rom_meas_tone_pwr_db = 0x40001b74; +rom_pkdet_vol_start = 0x40001b78; +rom_read_sar_dout = 0x40001b7c; +rom_read_sar2_code = 0x40001b80; +rom_get_sar2_vol = 0x40001b84; +rom_get_pll_vol = 0x40001b88; +rom_tx_pwctrl_bg_init = 0x40001b8c; +rom_phy_pwdet_always_en = 0x40001b90; +rom_phy_pwdet_onetime_en = 0x40001b94; +linear_to_db = 0x40001b98; +rom_get_pll_ref_code = 0x40001b9c; +mhz2ieee = 0x40001ba0; +chan_to_freq = 0x40001ba4; +restart_cal = 0x40001ba8; +write_rfpll_sdm = 0x40001bac; +wait_rfpll_cal_end = 0x40001bb0; +rfpll_set_freq = 0x40001bb4; +set_rf_freq_offset = 0x40001bb8; +set_channel_rfpll_freq = 0x40001bbc; +set_rfpll_freq = 0x40001bc0; +phy_set_freq = 0x40001bc4; +correct_rfpll_offset = 0x40001bc8; +set_chan_freq_sw_start = 0x40001bcc; +pll_vol_cal = 0x40001bd0; +write_pll_cap = 0x40001bd4; +read_pll_cap = 0x40001bd8; +chip_v7_set_chan_misc = 0x40001bdc; +chip_v7_set_chan = 0x40001be0; +chip_v7_set_chan_offset = 0x40001be4; +chip_v7_set_chan_ana = 0x40001be8; +set_chanfreq = 0x40001bec; +gen_rx_gain_table = 0x40001bf0; +wr_rx_gain_mem = 0x40001bf4; +set_rx_gain_param = 0x40001bf8; +set_rx_gain_table = 0x40001bfc; +bt_track_pll_cap = 0x40001c00; +wifi_track_pll_cap = 0x40001c04; +phy_param_track = 0x40001c08; +txpwr_correct = 0x40001c0c; +txpwr_cal_track = 0x40001c10; +tx_pwctrl_background = 0x40001c14; +bt_track_tx_power = 0x40001c18; +wifi_track_tx_power = 0x40001c1c; +bt_txdc_cal = 0x40001c20; +bt_txiq_cal = 0x40001c24; +txiq_cal_init = 0x40001c28; +get_txcap_data = 0x40001c2c; +txdc_cal_init = 0x40001c30; +txdc_cal_v70 = 0x40001c34; +txiq_get_mis_pwr = 0x40001c38; +txiq_cover = 0x40001c3c; +rfcal_txiq = 0x40001c40; +get_power_atten = 0x40001c44; +pwdet_ref_code = 0x40001c48; +pwdet_code_cal = 0x40001c4c; +rfcal_txcap = 0x40001c50; +tx_cap_init = 0x40001c54; +rfcal_pwrctrl = 0x40001c58; +tx_pwctrl_init_cal = 0x40001c5c; +tx_pwctrl_init = 0x40001c60; +bt_tx_pwctrl_init = 0x40001c64; +bt_txpwr_freq = 0x40001c68; +rom_get_i2c_read_mask = 0x40001c6c; +rom_get_i2c_mst0_mask = 0x40001c70; +rom_get_i2c_hostid = 0x40001c74; +rom_chip_i2c_readReg_org = 0x40001c78; +rom_chip_i2c_readReg = 0x40001c7c; +rom_i2c_paral_set_mst0 = 0x40001c80; +rom_i2c_paral_set_read = 0x40001c84; +rom_i2c_paral_read = 0x40001c88; +rom_i2c_paral_write = 0x40001c8c; +rom_i2c_paral_write_num = 0x40001c90; +rom_i2c_paral_write_mask = 0x40001c94; +rom_i2c_readReg = 0x40001c98; +rom_chip_i2c_writeReg = 0x40001c9c; +rom_i2c_writeReg = 0x40001ca0; +rom_i2c_readReg_Mask = 0x40001ca4; +rom_i2c_writeReg_Mask = 0x40001ca8; +rom_set_txcap_reg = 0x40001cac; +i2c_sar2_init_code = 0x40001cb0; +phy_i2c_init1 = 0x40001cb4; +phy_i2c_init2 = 0x40001cb8; +phy_get_i2c_data = 0x40001cbc; +bias_reg_set = 0x40001cc0; +i2c_bbpll_set = 0x40001cc4; +rom_pbus_force_mode = 0x40001cc8; +rom_pbus_rd_addr = 0x40001ccc; +rom_pbus_rd_shift = 0x40001cd0; +rom_pbus_force_test = 0x40001cd4; +rom_pbus_rd = 0x40001cd8; +rom_pbus_debugmode = 0x40001cdc; +rom_pbus_workmode = 0x40001ce0; +rom_pbus_set_rxgain = 0x40001ce4; +rom_pbus_xpd_rx_off = 0x40001ce8; +rom_pbus_xpd_rx_on = 0x40001cec; +rom_pbus_xpd_tx_off = 0x40001cf0; +rom_pbus_xpd_tx_on = 0x40001cf4; +rom_pbus_set_dco = 0x40001cf8; +rom_set_loopback_gain = 0x40001cfc; +rom_txcal_debuge_mode = 0x40001d00; +rom_txcal_work_mode = 0x40001d04; +set_pbus_mem = 0x40001d08; +rom_disable_agc = 0x40001d0c; +rom_enable_agc = 0x40001d10; +rom_disable_wifi_agc = 0x40001d14; +rom_enable_wifi_agc = 0x40001d18; +rom_write_gain_mem = 0x40001d1c; +rom_bb_bss_cbw40_dig = 0x40001d20; +rom_cbw2040_cfg = 0x40001d24; +rom_mac_tx_chan_offset = 0x40001d28; +rom_tx_paon_set = 0x40001d2c; +rom_i2cmst_reg_init = 0x40001d30; +rom_bt_gain_offset = 0x40001d34; +rom_fe_reg_init = 0x40001d38; +rom_mac_enable_bb = 0x40001d3c; +rom_bb_wdg_cfg = 0x40001d40; +rom_fe_txrx_reset = 0x40001d44; +rom_set_rx_comp = 0x40001d48; +rom_write_chan_freq = 0x40001d4c; +rom_agc_reg_init = 0x40001d50; +rom_bb_reg_init = 0x40001d54; +rom_write_txrate_power_offset = 0x40001d58; +rom_open_i2c_xpd = 0x40001d5c; +phy_disable_cca = 0x40001d60; +phy_enable_cca = 0x40001d64; +force_txon = 0x40001d68; +txiq_set_reg = 0x40001d6c; +rxiq_set_reg = 0x40001d70; +rx_gain_force = 0x40001d74; +set_txclk_en = 0x40001d78; +set_rxclk_en = 0x40001d7c; +start_tx_tone_step = 0x40001d80; +stop_tx_tone = 0x40001d84; +bb_wdg_test_en = 0x40001d88; +noise_floor_auto_set = 0x40001d8c; +read_hw_noisefloor = 0x40001d90; +set_cca = 0x40001d94; +set_rx_sense = 0x40001d98; +phy_rx11blr_cfg = 0x40001d9c; +bb_wdt_rst_enable = 0x40001da0; +bb_wdt_int_enable = 0x40001da4; +bb_wdt_timeout_clear = 0x40001da8; +bb_wdt_get_status = 0x40001dac; +wifi_rifs_mode_en = 0x40001db0; +phy_chan_filt_set = 0x40001db4; +iq_corr_enable = 0x40001db8; +bt_tx_dig_gain = 0x40001dbc; +wifi_tx_dig_reg = 0x40001dc0; +wifi_agc_sat_gain = 0x40001dc4; +phy_bbpll_cal = 0x40001dc8; +phy_xpd_tsens = 0x40001dcc; +phy_freq_mem_backup = 0x40001dd0; +phy_ant_init = 0x40001dd4; +phy_set_bbfreq_init = 0x40001dd8; +wifi_fbw_sel = 0x40001ddc; +phy_rx_sense_set = 0x40001de0; +ant_dft_cfg = 0x40001de4; +ant_wifitx_cfg = 0x40001de8; +ant_wifirx_cfg = 0x40001dec; +ant_bttx_cfg = 0x40001df0; +tx_state_set = 0x40001df4; +phy_chan_dump_cfg = 0x40001df8; +phy_enable_low_rate = 0x40001dfc; +phy_disable_low_rate = 0x40001e00; +phy_close_pa = 0x40001e04; +bt_filter_reg = 0x40001e08; +phy_freq_correct = 0x40001e0c; +set_pbus_reg = 0x40001e10; +phy_dig_reg_backup = 0x40001e14; +iq_est_enable = 0x40001e18; +iq_est_disable = 0x40001e1c; +dc_iq_est = 0x40001e20; +set_cal_rxdc = 0x40001e24; +rxiq_get_mis = 0x40001e28; +rxiq_cover_mg_mp = 0x40001e2c; +rfcal_rxiq = 0x40001e30; +get_rfcal_rxiq_data = 0x40001e34; +pbus_rx_dco_cal = 0x40001e38; +rxdc_est_min = 0x40001e3c; +pbus_rx_dco_cal_1step = 0x40001e40; +set_rx_gain_cal_iq = 0x40001e44; +set_rx_gain_cal_dc = 0x40001e48; +spur_reg_write_one_tone = 0x40001e4c; +spur_cal = 0x40001e50; +spur_coef_cfg = 0x40001e54; +rom_tester_wifi_cali = 0x40001e58; +esp_recover_efuse_data = 0x40001e5c; +rom_temp_to_power = 0x40001e60; +tsens_read_init = 0x40001e64; +code_to_temp = 0x40001e68; +tsens_index_to_dac = 0x40001e6c; +tsens_index_to_offset = 0x40001e70; +tsens_dac_cal = 0x40001e74; +tsens_code_read = 0x40001e78; +tsens_temp_read = 0x40001e7c; +get_temp_init = 0x40001e80; +rom_txbbgain_to_index = 0x40001e84; +rom_index_to_txbbgain = 0x40001e88; +rom_bt_index_to_bb = 0x40001e8c; +rom_bt_bb_to_index = 0x40001e90; +rom_bt_get_tx_gain = 0x40001e94; +rom_get_tx_gain_value = 0x40001e98; +rom_wifi_get_tx_gain = 0x40001e9c; +rom_set_tx_gain_mem = 0x40001ea0; +rom_get_rate_fcc_index = 0x40001ea4; +rom_get_chan_target_power = 0x40001ea8; +rom_wifi_tx_dig_gain = 0x40001eac; +rom_wifi_set_tx_gain = 0x40001eb0; +rom_bt_set_tx_gain = 0x40001eb4; +wifi_11g_rate_chg = 0x40001eb8; +bt_chan_pwr_interp = 0x40001ebc; +bt_tx_gain_init = 0x40001ec0; /* Data (.data, .bss, .rodata) */ -phy_param_rom = 0x3fcdffc8; +phy_param_rom = 0x3fcdfe4c; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld index ac0ab55199..8e383324b6 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld @@ -1,7 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32h2.rom.libgcc.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 + * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,93 +19,95 @@ ***************************************/ /* Functions */ -__absvdi2 = 0x40000738; -__absvsi2 = 0x4000073c; -__adddf3 = 0x40000740; -__addsf3 = 0x40000744; -__addvdi3 = 0x40000748; -__addvsi3 = 0x4000074c; -__ashldi3 = 0x40000750; -__ashrdi3 = 0x40000754; -__bswapdi2 = 0x40000758; -__bswapsi2 = 0x4000075c; -__clear_cache = 0x40000760; -__clrsbdi2 = 0x40000764; -__clrsbsi2 = 0x40000768; -__clzdi2 = 0x4000076c; -__clzsi2 = 0x40000770; -__cmpdi2 = 0x40000774; -__ctzdi2 = 0x40000778; -__ctzsi2 = 0x4000077c; -__divdc3 = 0x40000780; -__divdf3 = 0x40000784; -__divdi3 = 0x40000788; -__divsc3 = 0x4000078c; -__divsf3 = 0x40000790; -__divsi3 = 0x40000794; -__eqdf2 = 0x40000798; -__eqsf2 = 0x4000079c; -__extendsfdf2 = 0x400007a0; -__ffsdi2 = 0x400007a4; -__ffssi2 = 0x400007a8; -__fixdfdi = 0x400007ac; -__fixdfsi = 0x400007b0; -__fixsfdi = 0x400007b4; -__fixsfsi = 0x400007b8; -__fixunsdfsi = 0x400007bc; -__fixunssfdi = 0x400007c0; -__fixunssfsi = 0x400007c4; -__floatdidf = 0x400007c8; -__floatdisf = 0x400007cc; -__floatsidf = 0x400007d0; -__floatsisf = 0x400007d4; -__floatundidf = 0x400007d8; -__floatundisf = 0x400007dc; -__floatunsidf = 0x400007e0; -__floatunsisf = 0x400007e4; -__gcc_bcmp = 0x400007e8; -__gedf2 = 0x400007ec; -__gesf2 = 0x400007f0; -__gtdf2 = 0x400007f4; -__gtsf2 = 0x400007f8; -__ledf2 = 0x400007fc; -__lesf2 = 0x40000800; -__lshrdi3 = 0x40000804; -__ltdf2 = 0x40000808; -__ltsf2 = 0x4000080c; -__moddi3 = 0x40000810; -__modsi3 = 0x40000814; -__muldc3 = 0x40000818; -__muldf3 = 0x4000081c; -__muldi3 = 0x40000820; -__mulsc3 = 0x40000824; -__mulsf3 = 0x40000828; -__mulsi3 = 0x4000082c; -__mulvdi3 = 0x40000830; -__mulvsi3 = 0x40000834; -__nedf2 = 0x40000838; -__negdf2 = 0x4000083c; -__negdi2 = 0x40000840; -__negsf2 = 0x40000844; -__negvdi2 = 0x40000848; -__negvsi2 = 0x4000084c; -__nesf2 = 0x40000850; -__paritysi2 = 0x40000854; -__popcountdi2 = 0x40000858; -__popcountsi2 = 0x4000085c; -__powidf2 = 0x40000860; -__powisf2 = 0x40000864; -__subdf3 = 0x40000868; -__subsf3 = 0x4000086c; -__subvdi3 = 0x40000870; -__subvsi3 = 0x40000874; -__truncdfsf2 = 0x40000878; -__ucmpdi2 = 0x4000087c; -__udivdi3 = 0x40000880; -__udivmoddi4 = 0x40000884; -__udivsi3 = 0x40000888; -__udiv_w_sdiv = 0x4000088c; -__umoddi3 = 0x40000890; -__umodsi3 = 0x40000894; -__unorddf2 = 0x40000898; -__unordsf2 = 0x4000089c; +__absvdi2 = 0x4000098c; +__absvsi2 = 0x40000990; +__adddf3 = 0x40000994; +__addsf3 = 0x40000998; +__addvdi3 = 0x4000099c; +__addvsi3 = 0x400009a0; +__ashldi3 = 0x400009a4; +__ashrdi3 = 0x400009a8; +__bswapdi2 = 0x400009ac; +__bswapsi2 = 0x400009b0; +__clear_cache = 0x400009b4; +__clrsbdi2 = 0x400009b8; +__clrsbsi2 = 0x400009bc; +__clzdi2 = 0x400009c0; +__clzsi2 = 0x400009c4; +__cmpdi2 = 0x400009c8; +__ctzdi2 = 0x400009cc; +__ctzsi2 = 0x400009d0; +__divdc3 = 0x400009d4; +__divdf3 = 0x400009d8; +__divdi3 = 0x400009dc; +__divsc3 = 0x400009e0; +__divsf3 = 0x400009e4; +__divsi3 = 0x400009e8; +__eqdf2 = 0x400009ec; +__eqsf2 = 0x400009f0; +__extendsfdf2 = 0x400009f4; +__ffsdi2 = 0x400009f8; +__ffssi2 = 0x400009fc; +__fixdfdi = 0x40000a00; +__fixdfsi = 0x40000a04; +__fixsfdi = 0x40000a08; +__fixsfsi = 0x40000a0c; +__fixunsdfsi = 0x40000a10; +__fixunssfdi = 0x40000a14; +__fixunssfsi = 0x40000a18; +__floatdidf = 0x40000a1c; +__floatdisf = 0x40000a20; +__floatsidf = 0x40000a24; +__floatsisf = 0x40000a28; +__floatundidf = 0x40000a2c; +__floatundisf = 0x40000a30; +__floatunsidf = 0x40000a34; +__floatunsisf = 0x40000a38; +__gcc_bcmp = 0x40000a3c; +__gedf2 = 0x40000a40; +__gesf2 = 0x40000a44; +__gtdf2 = 0x40000a48; +__gtsf2 = 0x40000a4c; +__ledf2 = 0x40000a50; +__lesf2 = 0x40000a54; +__lshrdi3 = 0x40000a58; +__ltdf2 = 0x40000a5c; +__ltsf2 = 0x40000a60; +__moddi3 = 0x40000a64; +__modsi3 = 0x40000a68; +__muldc3 = 0x40000a6c; +__muldf3 = 0x40000a70; +__muldi3 = 0x40000a74; +__mulsc3 = 0x40000a78; +__mulsf3 = 0x40000a7c; +__mulsi3 = 0x40000a80; +__mulvdi3 = 0x40000a84; +__mulvsi3 = 0x40000a88; +__nedf2 = 0x40000a8c; +__negdf2 = 0x40000a90; +__negdi2 = 0x40000a94; +__negsf2 = 0x40000a98; +__negvdi2 = 0x40000a9c; +__negvsi2 = 0x40000aa0; +__nesf2 = 0x40000aa4; +__paritysi2 = 0x40000aa8; +__popcountdi2 = 0x40000aac; +__popcountsi2 = 0x40000ab0; +__powidf2 = 0x40000ab4; +__powisf2 = 0x40000ab8; +__subdf3 = 0x40000abc; +__subsf3 = 0x40000ac0; +__subvdi3 = 0x40000ac4; +__subvsi3 = 0x40000ac8; +__truncdfsf2 = 0x40000acc; +__ucmpdi2 = 0x40000ad0; +__udivdi3 = 0x40000ad4; +__udivmoddi4 = 0x40000ad8; +__udivsi3 = 0x40000adc; +__udiv_w_sdiv = 0x40000ae0; +__umoddi3 = 0x40000ae4; +__umodsi3 = 0x40000ae8; +__unorddf2 = 0x40000aec; +__unordsf2 = 0x40000af0; +__extenddftf2 = 0x40000af4; +__trunctfdf2 = 0x40000af8; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld index 73f10bdaf5..f6ba33d807 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld @@ -1,7 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 + * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,15 +19,30 @@ ***************************************/ /* Functions */ -__sprint_r = 0x4000044c; -_fiprintf_r = 0x40000450; -_fprintf_r = 0x40000454; -_printf_common = 0x40000458; -_printf_i = 0x4000045c; -_vfiprintf_r = 0x40000460; -_vfprintf_r = 0x40000464; -fiprintf = 0x40000468; -fprintf = 0x4000046c; -printf = 0x40000470; -vfiprintf = 0x40000474; -vfprintf = 0x40000478; +__sprint_r = 0x40000674; +_fiprintf_r = 0x40000678; +_fprintf_r = 0x4000067c; +_printf_common = 0x40000680; +_printf_i = 0x40000684; +_vfiprintf_r = 0x40000688; +_vfprintf_r = 0x4000068c; +fiprintf = 0x40000690; +fprintf = 0x40000694; +printf = 0x40000698; +vfiprintf = 0x4000069c; +vfprintf = 0x400006a0; +asprintf = 0x400006a4; +sprintf = 0x400006a8; +snprintf = 0x400006ac; +siprintf = 0x400006b0; +sniprintf = 0x400006b4; +vprintf = 0x400006b8; +viprintf = 0x400006bc; +vsnprintf = 0x400006c0; +vsniprintf = 0x400006c4; +__rom_printf_float = 0x400006c8; +__rom_scanf_float = 0x400006cc; +_scanf_i = 0x400006d0; +_scanf_chars = 0x400006d4; +sscanf = 0x400006d8; +siscanf = 0x400006dc; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld index 76bdf45cfb..199e43d118 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld @@ -1,7 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM function interface esp32h2.rom.newlib.ld for esp32h2 * * - * Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3 + * Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574 * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,82 +19,130 @@ ***************************************/ /* Functions */ -esp_rom_newlib_init_common_mutexes = 0x4000031c; -memset = 0x40000320; -memcpy = 0x40000324; -memmove = 0x40000328; -memcmp = 0x4000032c; -strcpy = 0x40000330; -strncpy = 0x40000334; -strcmp = 0x40000338; -strncmp = 0x4000033c; -strlen = 0x40000340; -strstr = 0x40000344; -bzero = 0x40000348; -_isatty_r = 0x4000034c; -sbrk = 0x40000350; -isalnum = 0x40000354; -isalpha = 0x40000358; -isascii = 0x4000035c; -isblank = 0x40000360; -iscntrl = 0x40000364; -isdigit = 0x40000368; -islower = 0x4000036c; -isgraph = 0x40000370; -isprint = 0x40000374; -ispunct = 0x40000378; -isspace = 0x4000037c; -isupper = 0x40000380; -toupper = 0x40000384; -tolower = 0x40000388; -toascii = 0x4000038c; -memccpy = 0x40000390; -memchr = 0x40000394; -memrchr = 0x40000398; -strcasecmp = 0x4000039c; -strcasestr = 0x400003a0; -strcat = 0x400003a4; -strdup = 0x400003a8; -strchr = 0x400003ac; -strcspn = 0x400003b0; -strcoll = 0x400003b4; -strlcat = 0x400003b8; -strlcpy = 0x400003bc; -strlwr = 0x400003c0; -strncasecmp = 0x400003c4; -strncat = 0x400003c8; -strndup = 0x400003cc; -strnlen = 0x400003d0; -strrchr = 0x400003d4; -strsep = 0x400003d8; -strspn = 0x400003dc; -strtok_r = 0x400003e0; -strupr = 0x400003e4; -longjmp = 0x400003e8; -setjmp = 0x400003ec; -abs = 0x400003f0; -div = 0x400003f4; -labs = 0x400003f8; -ldiv = 0x400003fc; -qsort = 0x40000400; -rand_r = 0x40000404; -rand = 0x40000408; -srand = 0x4000040c; -utoa = 0x40000410; -itoa = 0x40000414; -atoi = 0x40000418; -atol = 0x4000041c; -strtol = 0x40000420; -strtoul = 0x40000424; -PROVIDE( fflush = 0x40000428 ); -PROVIDE( _fflush_r = 0x4000042c ); -PROVIDE( _fwalk = 0x40000430 ); -PROVIDE( _fwalk_reent = 0x40000434 ); -PROVIDE( __smakebuf_r = 0x40000438 ); -PROVIDE( __swhatbuf_r = 0x4000043c ); -PROVIDE( __swbuf_r = 0x40000440 ); -__swbuf = 0x40000444; -PROVIDE( __swsetup_r = 0x40000448 ); +esp_rom_newlib_init_common_mutexes = 0x40000484; +memset = 0x40000488; +memcpy = 0x4000048c; +memmove = 0x40000490; +memcmp = 0x40000494; +strcpy = 0x40000498; +strncpy = 0x4000049c; +strcmp = 0x400004a0; +strncmp = 0x400004a4; +strlen = 0x400004a8; +strstr = 0x400004ac; +bzero = 0x400004b0; +_isatty_r = 0x400004b4; +sbrk = 0x400004b8; +isalnum = 0x400004bc; +isalpha = 0x400004c0; +isascii = 0x400004c4; +isblank = 0x400004c8; +iscntrl = 0x400004cc; +isdigit = 0x400004d0; +islower = 0x400004d4; +isgraph = 0x400004d8; +isprint = 0x400004dc; +ispunct = 0x400004e0; +isspace = 0x400004e4; +isupper = 0x400004e8; +toupper = 0x400004ec; +tolower = 0x400004f0; +toascii = 0x400004f4; +memccpy = 0x400004f8; +memchr = 0x400004fc; +memrchr = 0x40000500; +strcasecmp = 0x40000504; +strcasestr = 0x40000508; +strcat = 0x4000050c; +strdup = 0x40000510; +strchr = 0x40000514; +strcspn = 0x40000518; +strcoll = 0x4000051c; +strlcat = 0x40000520; +strlcpy = 0x40000524; +strlwr = 0x40000528; +strncasecmp = 0x4000052c; +strncat = 0x40000530; +strndup = 0x40000534; +strnlen = 0x40000538; +strrchr = 0x4000053c; +strsep = 0x40000540; +strspn = 0x40000544; +strtok_r = 0x40000548; +strupr = 0x4000054c; +longjmp = 0x40000550; +setjmp = 0x40000554; +abs = 0x40000558; +div = 0x4000055c; +labs = 0x40000560; +ldiv = 0x40000564; +qsort = 0x40000568; +rand_r = 0x4000056c; +rand = 0x40000570; +srand = 0x40000574; +utoa = 0x40000578; +itoa = 0x4000057c; +atoi = 0x40000580; +atol = 0x40000584; +strtol = 0x40000588; +strtoul = 0x4000058c; +fflush = 0x40000590; +_fflush_r = 0x40000594; +_fwalk = 0x40000598; +_fwalk_reent = 0x4000059c; +__smakebuf_r = 0x400005a0; +__swhatbuf_r = 0x400005a4; +__swbuf_r = 0x400005a8; +__swbuf = 0x400005ac; +__swsetup_r = 0x400005b0; +_strtod_l = 0x400005b4; +_strtod_r = 0x400005b8; +strtod_l = 0x400005bc; +strtod = 0x400005c0; +strtof_l = 0x400005c4; +strtof = 0x400005c8; +_strtol_r = 0x400005cc; +strtol_l = 0x400005d0; +_strtoul_r = 0x400005d4; +strtoul_l = 0x400005d8; +__match = 0x400005dc; +__hexnan = 0x400005e0; +__hexdig_fun = 0x400005e4; +__gethex = 0x400005e8; +_Balloc = 0x400005ec; +_Bfree = 0x400005f0; +__multadd = 0x400005f4; +__s2b = 0x400005f8; +__hi0bits = 0x400005fc; +__lo0bits = 0x40000600; +__i2b = 0x40000604; +__multiply = 0x40000608; +__pow5mult = 0x4000060c; +__lshift = 0x40000610; +__mcmp = 0x40000614; +__mdiff = 0x40000618; +__ulp = 0x4000061c; +__b2d = 0x40000620; +__d2b = 0x40000624; +__ratio = 0x40000628; +_mprec_log10 = 0x4000062c; +__copybits = 0x40000630; +__any_on = 0x40000634; +asctime = 0x40000638; +asctime_r = 0x4000063c; +atof = 0x40000640; +atoff = 0x40000644; +_dtoa_r = 0x40000648; +_wctomb_r = 0x4000064c; +__ascii_wctomb = 0x40000650; +_mbtowc_r = 0x40000654; +__ascii_mbtowc = 0x40000658; +puts = 0x4000065c; +putc = 0x40000660; +putchar = 0x40000664; +nan = 0x40000668; +nanf = 0x4000066c; +__errno = 0x40000670; /* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffdc; -_global_impure_ptr = 0x3fcdffd8; +syscall_table_ptr = 0x3fcdffd8; +_global_impure_ptr = 0x3fcdffd4; diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld index eb52ba15d5..29e27a2d0a 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* ROM version variables for esp32h2 * * These addresses should be compatible with any ROM version for this chip. diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index af1c95131c..76722a29c0 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -83,8 +83,8 @@ menu "ESP System Settings" default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 - default y if IDF_TARGET_ESP32H2 - depends on !IDF_TARGET_ESP8684 + default y if IDF_TARGET_ESP32H2_BETA_VERSION_1 + depends on !IDF_TARGET_ESP8684 && !IDF_TARGET_ESP32H2_BETA_VERSION_2 config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP bool "Enable RTC fast memory for dynamic allocations" diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index d3b451bd53..71a028e1c1 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -1,16 +1,8 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include "sdkconfig.h" @@ -95,7 +87,15 @@ void IRAM_ATTR esp_restart_noos(void) // Reset timer/spi/uart SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, + SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST | + SYSTEM_BT_RST | SYSTEM_BTMAC_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | + SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST + ); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0); + // Reset dma SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index 77e369823f..cc043fef80 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -2,7 +2,7 @@ menu "Serial flasher config" config ESPTOOLPY_NO_STUB bool "Disable download stub" - default "y" if IDF_TARGET="esp32h2" + default "y" if IDF_TARGET_ESP32H2 && IDF_ENV_FPGA # TODO: IDF-4288 default "n" help diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index 2b3221f9f2..8227361c9c 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit 2b3221f9f24bacd982e025dc67f25dea956366bf +Subproject commit 8227361c9cda8f07c9b505b3b665ae69bc2fda8f diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index a1802d5f03..c80f3e3b66 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -6,6 +6,14 @@ idf_build_get_property(python PYTHON) idf_build_get_property(idf_path IDF_PATH) set(chip_model ${target}) +# TODO: remove this if block when esp32h2 beta1 is no longer supported +if(target STREQUAL "esp32h2") + if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) + set(chip_model esp32h2beta1) + elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2) + set(chip_model esp32h2beta2) + endif() +endif() set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model}) set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") diff --git a/components/soc/esp32h2/CMakeLists.txt b/components/soc/esp32h2/CMakeLists.txt index 4984df5d65..24f493eabd 100644 --- a/components/soc/esp32h2/CMakeLists.txt +++ b/components/soc/esp32h2/CMakeLists.txt @@ -19,9 +19,9 @@ target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") if(target STREQUAL "esp32h2") if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) - set(inc_file "include/soc/rev1") + set(inc_file "include/rev1" "include/rev1/soc") elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2) - set(inc_file "include/soc/rev2") + set(inc_file "include/rev2" "include/rev2/soc") endif() target_include_directories(${COMPONENT_LIB} PUBLIC . include ${inc_file}) else() diff --git a/components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h b/components/soc/esp32h2/include/rev1/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h rename to components/soc/esp32h2/include/rev1/soc/assist_debug_reg.h index 2b224a9b29..2307e36149 100644 --- a/components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/assist_debug_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/include/rev1/soc/gpio_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/gpio_reg.h rename to components/soc/esp32h2/include/rev1/soc/gpio_reg.h index 56b07a3d8e..f7aa79dd4f 100644 --- a/components/soc/esp32h2/include/soc/gpio_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/gpio_reg.h @@ -1,24 +1,16 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_REG_H_ #define _SOC_GPIO_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define GPIO_PIN_CONFIG_MSB 12 #define GPIO_PIN_CONFIG_LSB 11 #define GPIO_PIN_CONFIG_MASK 0x00001800 diff --git a/components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h b/components/soc/esp32h2/include/rev1/soc/gpio_sd_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h rename to components/soc/esp32h2/include/rev1/soc/gpio_sd_reg.h index 4bda01041d..450be260fb 100644 --- a/components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/gpio_sd_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_GPIO_SD_REG_H_ #define _SOC_GPIO_SD_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) /* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ /*description: */ diff --git a/components/soc/esp32h2/include/soc/gpio_sig_map.h b/components/soc/esp32h2/include/rev1/soc/gpio_sig_map.h similarity index 92% rename from components/soc/esp32h2/include/soc/gpio_sig_map.h rename to components/soc/esp32h2/include/rev1/soc/gpio_sig_map.h index ca4b29f643..16ac67a469 100644 --- a/components/soc/esp32h2/include/soc/gpio_sig_map.h +++ b/components/soc/esp32h2/include/rev1/soc/gpio_sig_map.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_GPIO_SIG_MAP_H_ #define _SOC_GPIO_SIG_MAP_H_ diff --git a/components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h b/components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h rename to components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h index dad09391be..efcf8e0f1b 100644 --- a/components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE diff --git a/components/soc/esp32h2/include/soc/rev1/io_mux_reg.h b/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/io_mux_reg.h rename to components/soc/esp32h2/include/rev1/soc/io_mux_reg.h index 52f2c3e147..e1fc5cbcd7 100644 --- a/components/soc/esp32h2/include/soc/rev1/io_mux_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h @@ -6,7 +6,7 @@ #ifndef _SOC_IO_MUX_REG_H_ #define _SOC_IO_MUX_REG_H_ -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h b/components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h rename to components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h index 7c2d09ba65..2724f8dca5 100644 --- a/components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h @@ -21,11 +21,11 @@ #define RTC_WDT_RESET_LENGTH_1600_NS 6 #define RTC_WDT_RESET_LENGTH_3200_NS 7 +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG diff --git a/components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h b/components/soc/esp32h2/include/rev1/soc/rtc_cntl_struct.h similarity index 100% rename from components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h rename to components/soc/esp32h2/include/rev1/soc/rtc_cntl_struct.h diff --git a/components/soc/esp32h2/include/soc/rev1/sensitive_reg.h b/components/soc/esp32h2/include/rev1/soc/sensitive_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev1/sensitive_reg.h rename to components/soc/esp32h2/include/rev1/soc/sensitive_reg.h index 7248cf227d..ec506ed16a 100644 --- a/components/soc/esp32h2/include/soc/rev1/sensitive_reg.h +++ b/components/soc/esp32h2/include/rev1/soc/sensitive_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) /* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/rev1/soc/soc_caps.h similarity index 98% rename from components/soc/esp32h2/include/soc/soc_caps.h rename to components/soc/esp32h2/include/rev1/soc/soc_caps.h index 9f62fba39b..6134ecf1db 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/rev1/soc/soc_caps.h @@ -1,10 +1,14 @@ +/* + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ // The long term plan is to have a single soc_caps.h for each peripheral. // During the refactoring and multichip support development process, we // seperate these information into periph_caps.h for each peripheral and // include them here. #pragma once -#include "sdkconfig.h" /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CPU_CORES_NUM 1 @@ -80,11 +84,7 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C3 has 1 GPIO peripheral #define SOC_GPIO_PORT (1) -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 -#define SOC_GPIO_PIN_COUNT (26) -#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 #define SOC_GPIO_PIN_COUNT (22) -#endif // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC // On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. diff --git a/components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h b/components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h rename to components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h index 4bb99b76a0..8193b091dc 100644 --- a/components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_ASSIST_DEBUG_REG_H_ #define _SOC_ASSIST_DEBUG_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ diff --git a/components/soc/esp32h2/include/rev2/soc/gpio_reg.h b/components/soc/esp32h2/include/rev2/soc/gpio_reg.h new file mode 100644 index 0000000000..a3d6d1c40b --- /dev/null +++ b/components/soc/esp32h2/include/rev2/soc/gpio_reg.h @@ -0,0 +1,4861 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_GPIO_REG_H_ +#define _SOC_GPIO_REG_H_ + +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif +#define GPIO_PIN_CONFIG_MSB 12 +#define GPIO_PIN_CONFIG_LSB 11 +#define GPIO_PIN_CONFIG_MASK 0x00001800 +#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) + +#define GPIO_WAKEUP_ENABLE 1 +#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) +#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) +#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) + +#define GPIO_PIN_INT_TYPE_MASK 0x380 +#define GPIO_PIN_INT_TYPE_MSB 9 +#define GPIO_PIN_INT_TYPE_LSB 7 +#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) + +#define GPIO_PAD_DRIVER_ENABLE 1 +#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) +#define GPIO_PIN_PAD_DRIVER_MSB 2 +#define GPIO_PIN_PAD_DRIVER_LSB 2 +#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) +#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/* GPIO_OUT_DATA : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_OUT_DATA 0x3FFFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0x3FFFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/* GPIO_OUT_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_OUT_W1TS 0x3FFFFFFF +#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) +#define GPIO_OUT_W1TS_V 0x3FFFFFFF +#define GPIO_OUT_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) +/* GPIO_OUT_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_OUT_W1TC 0x3FFFFFFF +#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) +#define GPIO_OUT_W1TC_V 0x3FFFFFFF +#define GPIO_OUT_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: .*/ +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/* GPIO_ENABLE_DATA : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_ENABLE_DATA 0x3FFFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0x3FFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/* GPIO_ENABLE_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_ENABLE_W1TS 0x3FFFFFFF +#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) +#define GPIO_ENABLE_W1TS_V 0x3FFFFFFF +#define GPIO_ENABLE_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/* GPIO_ENABLE_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_ENABLE_W1TC 0x3FFFFFFF +#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) +#define GPIO_ENABLE_W1TC_V 0x3FFFFFFF +#define GPIO_ENABLE_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/*description: .*/ +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) +/* GPIO_IN_DATA : RO ;bitpos:[29:0] ;default: ; */ +/*description: .*/ +#define GPIO_IN_DATA 0x3FFFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0x3FFFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/* GPIO_STATUS_INT : R/W ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_STATUS_INT 0x3FFFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0x3FFFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/* GPIO_STATUS_W1TS : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_STATUS_W1TS 0x3FFFFFFF +#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) +#define GPIO_STATUS_W1TS_V 0x3FFFFFFF +#define GPIO_STATUS_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) +/* GPIO_STATUS_W1TC : WO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_STATUS_W1TC 0x3FFFFFFF +#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) +#define GPIO_STATUS_W1TC_V 0x3FFFFFFF +#define GPIO_STATUS_W1TC_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) +/* GPIO_PROCPU_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_PROCPU_INT 0x3FFFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0x3FFFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_PROCPU_NMI_INT 0x3FFFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/* GPIO_SDIO_INT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_SDIO_INT 0x3FFFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0x3FFFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 +/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 +/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 +/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 +/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7C) +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 +/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 +/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 +/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 +/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 +/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 +/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 +/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 +/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8C) +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 +/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 +/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 +/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 +/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 +/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 +/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 +/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 +/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9C) +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 +/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 +/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0) +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 +/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 +/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xA4) +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 +/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 +/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xA8) +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 +/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 +/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xAC) +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 +/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 +/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0) +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 +/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 +/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xB4) +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 +/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 +/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xB8) +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 +/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 +/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xBC) +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 +/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 +/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0) +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 +/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 +/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xC4) +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 +/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 +/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xC8) +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 +/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 +/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xCC) +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 +/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 +/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0) +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 +/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 +/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xD4) +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 +/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 +/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xD8) +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 +/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 +/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xDC) +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 +/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_M ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S)) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 +/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S)) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC2_BYPASS_S 0 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0) +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 +/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_M ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S)) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 +/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_M ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S)) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC2_BYPASS_S 0 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xE4) +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 +/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S)) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 +/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_M ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S)) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC2_BYPASS_S 0 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xE8) +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 +/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_M ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S)) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 +/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: .*/ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_M ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S)) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC2_BYPASS_S 0 + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) +/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[29:0] ;default: 30'h0 ; */ +/*description: .*/ +#define GPIO_STATUS_INTERRUPT_NEXT 0x3FFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3FFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG0_IN_SEL (BIT(6)) +#define GPIO_SIG0_IN_SEL_M (BIT(6)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 6 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 5 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC0_IN_SEL 0x0000001F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x1F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG1_IN_SEL (BIT(6)) +#define GPIO_SIG1_IN_SEL_M (BIT(6)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 6 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 5 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC1_IN_SEL 0x0000001F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x1F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG2_IN_SEL (BIT(6)) +#define GPIO_SIG2_IN_SEL_M (BIT(6)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 6 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 5 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC2_IN_SEL 0x0000001F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x1F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG3_IN_SEL (BIT(6)) +#define GPIO_SIG3_IN_SEL_M (BIT(6)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 6 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 5 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC3_IN_SEL 0x0000001F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x1F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG4_IN_SEL (BIT(6)) +#define GPIO_SIG4_IN_SEL_M (BIT(6)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 6 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 5 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC4_IN_SEL 0x0000001F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x1F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG5_IN_SEL (BIT(6)) +#define GPIO_SIG5_IN_SEL_M (BIT(6)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 6 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 5 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC5_IN_SEL 0x0000001F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x1F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG6_IN_SEL (BIT(6)) +#define GPIO_SIG6_IN_SEL_M (BIT(6)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 6 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 5 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC6_IN_SEL 0x0000001F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x1F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG7_IN_SEL (BIT(6)) +#define GPIO_SIG7_IN_SEL_M (BIT(6)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 6 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 5 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC7_IN_SEL 0x0000001F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x1F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG8_IN_SEL (BIT(6)) +#define GPIO_SIG8_IN_SEL_M (BIT(6)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 6 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 5 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC8_IN_SEL 0x0000001F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x1F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG9_IN_SEL (BIT(6)) +#define GPIO_SIG9_IN_SEL_M (BIT(6)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 6 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 5 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC9_IN_SEL 0x0000001F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x1F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG10_IN_SEL (BIT(6)) +#define GPIO_SIG10_IN_SEL_M (BIT(6)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 6 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 5 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC10_IN_SEL 0x0000001F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x1F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG11_IN_SEL (BIT(6)) +#define GPIO_SIG11_IN_SEL_M (BIT(6)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 6 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 5 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC11_IN_SEL 0x0000001F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x1F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG12_IN_SEL (BIT(6)) +#define GPIO_SIG12_IN_SEL_M (BIT(6)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 6 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 5 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC12_IN_SEL 0x0000001F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x1F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG13_IN_SEL (BIT(6)) +#define GPIO_SIG13_IN_SEL_M (BIT(6)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 6 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 5 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC13_IN_SEL 0x0000001F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x1F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG14_IN_SEL (BIT(6)) +#define GPIO_SIG14_IN_SEL_M (BIT(6)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 6 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 5 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC14_IN_SEL 0x0000001F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x1F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG15_IN_SEL (BIT(6)) +#define GPIO_SIG15_IN_SEL_M (BIT(6)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 6 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 5 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC15_IN_SEL 0x0000001F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x1F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG16_IN_SEL (BIT(6)) +#define GPIO_SIG16_IN_SEL_M (BIT(6)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 6 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 5 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC16_IN_SEL 0x0000001F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x1F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG17_IN_SEL (BIT(6)) +#define GPIO_SIG17_IN_SEL_M (BIT(6)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 6 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 5 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC17_IN_SEL 0x0000001F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x1F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG18_IN_SEL (BIT(6)) +#define GPIO_SIG18_IN_SEL_M (BIT(6)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 6 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 5 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC18_IN_SEL 0x0000001F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x1F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG19_IN_SEL (BIT(6)) +#define GPIO_SIG19_IN_SEL_M (BIT(6)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 6 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 5 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC19_IN_SEL 0x0000001F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x1F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG20_IN_SEL (BIT(6)) +#define GPIO_SIG20_IN_SEL_M (BIT(6)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 6 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 5 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC20_IN_SEL 0x0000001F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x1F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG21_IN_SEL (BIT(6)) +#define GPIO_SIG21_IN_SEL_M (BIT(6)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 6 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 5 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC21_IN_SEL 0x0000001F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x1F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG22_IN_SEL (BIT(6)) +#define GPIO_SIG22_IN_SEL_M (BIT(6)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 6 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 5 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC22_IN_SEL 0x0000001F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x1F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG23_IN_SEL (BIT(6)) +#define GPIO_SIG23_IN_SEL_M (BIT(6)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 6 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 5 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC23_IN_SEL 0x0000001F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x1F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG24_IN_SEL (BIT(6)) +#define GPIO_SIG24_IN_SEL_M (BIT(6)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 6 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 5 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC24_IN_SEL 0x0000001F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x1F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG25_IN_SEL (BIT(6)) +#define GPIO_SIG25_IN_SEL_M (BIT(6)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 6 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 5 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC25_IN_SEL 0x0000001F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x1F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG26_IN_SEL (BIT(6)) +#define GPIO_SIG26_IN_SEL_M (BIT(6)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 6 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 5 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC26_IN_SEL 0x0000001F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x1F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG27_IN_SEL (BIT(6)) +#define GPIO_SIG27_IN_SEL_M (BIT(6)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 6 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 5 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC27_IN_SEL 0x0000001F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x1F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG28_IN_SEL (BIT(6)) +#define GPIO_SIG28_IN_SEL_M (BIT(6)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 6 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 5 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC28_IN_SEL 0x0000001F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x1F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG29_IN_SEL (BIT(6)) +#define GPIO_SIG29_IN_SEL_M (BIT(6)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 6 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 5 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC29_IN_SEL 0x0000001F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x1F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG30_IN_SEL (BIT(6)) +#define GPIO_SIG30_IN_SEL_M (BIT(6)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 6 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 5 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC30_IN_SEL 0x0000001F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x1F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG31_IN_SEL (BIT(6)) +#define GPIO_SIG31_IN_SEL_M (BIT(6)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 6 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 5 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC31_IN_SEL 0x0000001F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x1F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG32_IN_SEL (BIT(6)) +#define GPIO_SIG32_IN_SEL_M (BIT(6)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 6 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 5 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC32_IN_SEL 0x0000001F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x1F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG33_IN_SEL (BIT(6)) +#define GPIO_SIG33_IN_SEL_M (BIT(6)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 6 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 5 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC33_IN_SEL 0x0000001F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x1F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG34_IN_SEL (BIT(6)) +#define GPIO_SIG34_IN_SEL_M (BIT(6)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 6 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 5 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC34_IN_SEL 0x0000001F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x1F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG35_IN_SEL (BIT(6)) +#define GPIO_SIG35_IN_SEL_M (BIT(6)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 6 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 5 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC35_IN_SEL 0x0000001F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x1F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG36_IN_SEL (BIT(6)) +#define GPIO_SIG36_IN_SEL_M (BIT(6)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 6 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 5 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC36_IN_SEL 0x0000001F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x1F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG37_IN_SEL (BIT(6)) +#define GPIO_SIG37_IN_SEL_M (BIT(6)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 6 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 5 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC37_IN_SEL 0x0000001F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x1F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG38_IN_SEL (BIT(6)) +#define GPIO_SIG38_IN_SEL_M (BIT(6)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 6 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 5 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC38_IN_SEL 0x0000001F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x1F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG39_IN_SEL (BIT(6)) +#define GPIO_SIG39_IN_SEL_M (BIT(6)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 6 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 5 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC39_IN_SEL 0x0000001F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x1F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG40_IN_SEL (BIT(6)) +#define GPIO_SIG40_IN_SEL_M (BIT(6)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 6 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 5 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC40_IN_SEL 0x0000001F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x1F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG41_IN_SEL (BIT(6)) +#define GPIO_SIG41_IN_SEL_M (BIT(6)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 6 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 5 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC41_IN_SEL 0x0000001F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x1F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG42_IN_SEL (BIT(6)) +#define GPIO_SIG42_IN_SEL_M (BIT(6)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 6 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 5 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC42_IN_SEL 0x0000001F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x1F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG43_IN_SEL (BIT(6)) +#define GPIO_SIG43_IN_SEL_M (BIT(6)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 6 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 5 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC43_IN_SEL 0x0000001F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x1F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG44_IN_SEL (BIT(6)) +#define GPIO_SIG44_IN_SEL_M (BIT(6)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 6 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 5 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC44_IN_SEL 0x0000001F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x1F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG45_IN_SEL (BIT(6)) +#define GPIO_SIG45_IN_SEL_M (BIT(6)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 6 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 5 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC45_IN_SEL 0x0000001F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x1F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG46_IN_SEL (BIT(6)) +#define GPIO_SIG46_IN_SEL_M (BIT(6)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 6 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 5 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC46_IN_SEL 0x0000001F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x1F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG47_IN_SEL (BIT(6)) +#define GPIO_SIG47_IN_SEL_M (BIT(6)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 6 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 5 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC47_IN_SEL 0x0000001F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x1F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG48_IN_SEL (BIT(6)) +#define GPIO_SIG48_IN_SEL_M (BIT(6)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 6 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 5 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC48_IN_SEL 0x0000001F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x1F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG49_IN_SEL (BIT(6)) +#define GPIO_SIG49_IN_SEL_M (BIT(6)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 6 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 5 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC49_IN_SEL 0x0000001F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x1F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG50_IN_SEL (BIT(6)) +#define GPIO_SIG50_IN_SEL_M (BIT(6)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 6 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 5 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC50_IN_SEL 0x0000001F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x1F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG51_IN_SEL (BIT(6)) +#define GPIO_SIG51_IN_SEL_M (BIT(6)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 6 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 5 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC51_IN_SEL 0x0000001F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x1F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG52_IN_SEL (BIT(6)) +#define GPIO_SIG52_IN_SEL_M (BIT(6)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 6 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 5 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC52_IN_SEL 0x0000001F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x1F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG53_IN_SEL (BIT(6)) +#define GPIO_SIG53_IN_SEL_M (BIT(6)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 6 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 5 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC53_IN_SEL 0x0000001F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x1F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG54_IN_SEL (BIT(6)) +#define GPIO_SIG54_IN_SEL_M (BIT(6)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 6 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 5 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC54_IN_SEL 0x0000001F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x1F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG55_IN_SEL (BIT(6)) +#define GPIO_SIG55_IN_SEL_M (BIT(6)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 6 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 5 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC55_IN_SEL 0x0000001F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x1F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG56_IN_SEL (BIT(6)) +#define GPIO_SIG56_IN_SEL_M (BIT(6)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 6 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 5 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC56_IN_SEL 0x0000001F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x1F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG57_IN_SEL (BIT(6)) +#define GPIO_SIG57_IN_SEL_M (BIT(6)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 6 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 5 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC57_IN_SEL 0x0000001F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x1F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG58_IN_SEL (BIT(6)) +#define GPIO_SIG58_IN_SEL_M (BIT(6)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 6 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 5 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC58_IN_SEL 0x0000001F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x1F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG59_IN_SEL (BIT(6)) +#define GPIO_SIG59_IN_SEL_M (BIT(6)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 6 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 5 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC59_IN_SEL 0x0000001F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x1F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG60_IN_SEL (BIT(6)) +#define GPIO_SIG60_IN_SEL_M (BIT(6)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 6 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 5 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC60_IN_SEL 0x0000001F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x1F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG61_IN_SEL (BIT(6)) +#define GPIO_SIG61_IN_SEL_M (BIT(6)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 6 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 5 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC61_IN_SEL 0x0000001F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x1F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG62_IN_SEL (BIT(6)) +#define GPIO_SIG62_IN_SEL_M (BIT(6)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 6 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 5 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC62_IN_SEL 0x0000001F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x1F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG63_IN_SEL (BIT(6)) +#define GPIO_SIG63_IN_SEL_M (BIT(6)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 6 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 5 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC63_IN_SEL 0x0000001F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x1F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG64_IN_SEL (BIT(6)) +#define GPIO_SIG64_IN_SEL_M (BIT(6)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 6 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 5 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC64_IN_SEL 0x0000001F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x1F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG65_IN_SEL (BIT(6)) +#define GPIO_SIG65_IN_SEL_M (BIT(6)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 6 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 5 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC65_IN_SEL 0x0000001F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x1F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG66_IN_SEL (BIT(6)) +#define GPIO_SIG66_IN_SEL_M (BIT(6)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 6 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 5 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC66_IN_SEL 0x0000001F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x1F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG67_IN_SEL (BIT(6)) +#define GPIO_SIG67_IN_SEL_M (BIT(6)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 6 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 5 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC67_IN_SEL 0x0000001F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x1F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG68_IN_SEL (BIT(6)) +#define GPIO_SIG68_IN_SEL_M (BIT(6)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 6 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 5 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC68_IN_SEL 0x0000001F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x1F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG69_IN_SEL (BIT(6)) +#define GPIO_SIG69_IN_SEL_M (BIT(6)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 6 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 5 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC69_IN_SEL 0x0000001F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x1F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG70_IN_SEL (BIT(6)) +#define GPIO_SIG70_IN_SEL_M (BIT(6)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 6 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 5 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC70_IN_SEL 0x0000001F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x1F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG71_IN_SEL (BIT(6)) +#define GPIO_SIG71_IN_SEL_M (BIT(6)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 6 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 5 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC71_IN_SEL 0x0000001F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x1F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG72_IN_SEL (BIT(6)) +#define GPIO_SIG72_IN_SEL_M (BIT(6)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 6 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 5 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC72_IN_SEL 0x0000001F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x1F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG73_IN_SEL (BIT(6)) +#define GPIO_SIG73_IN_SEL_M (BIT(6)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 6 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 5 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC73_IN_SEL 0x0000001F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x1F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG74_IN_SEL (BIT(6)) +#define GPIO_SIG74_IN_SEL_M (BIT(6)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 6 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 5 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC74_IN_SEL 0x0000001F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x1F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG75_IN_SEL (BIT(6)) +#define GPIO_SIG75_IN_SEL_M (BIT(6)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 6 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 5 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC75_IN_SEL 0x0000001F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x1F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG76_IN_SEL (BIT(6)) +#define GPIO_SIG76_IN_SEL_M (BIT(6)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 6 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 5 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC76_IN_SEL 0x0000001F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x1F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG77_IN_SEL (BIT(6)) +#define GPIO_SIG77_IN_SEL_M (BIT(6)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 6 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 5 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC77_IN_SEL 0x0000001F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x1F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG78_IN_SEL (BIT(6)) +#define GPIO_SIG78_IN_SEL_M (BIT(6)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 6 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 5 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC78_IN_SEL 0x0000001F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x1F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG79_IN_SEL (BIT(6)) +#define GPIO_SIG79_IN_SEL_M (BIT(6)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 6 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 5 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC79_IN_SEL 0x0000001F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x1F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG80_IN_SEL (BIT(6)) +#define GPIO_SIG80_IN_SEL_M (BIT(6)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 6 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 5 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC80_IN_SEL 0x0000001F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x1F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG81_IN_SEL (BIT(6)) +#define GPIO_SIG81_IN_SEL_M (BIT(6)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 6 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 5 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC81_IN_SEL 0x0000001F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x1F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG82_IN_SEL (BIT(6)) +#define GPIO_SIG82_IN_SEL_M (BIT(6)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 6 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 5 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC82_IN_SEL 0x0000001F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x1F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG83_IN_SEL (BIT(6)) +#define GPIO_SIG83_IN_SEL_M (BIT(6)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 6 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 5 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC83_IN_SEL 0x0000001F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x1F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG84_IN_SEL (BIT(6)) +#define GPIO_SIG84_IN_SEL_M (BIT(6)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 6 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 5 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC84_IN_SEL 0x0000001F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x1F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG85_IN_SEL (BIT(6)) +#define GPIO_SIG85_IN_SEL_M (BIT(6)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 6 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 5 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC85_IN_SEL 0x0000001F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x1F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG86_IN_SEL (BIT(6)) +#define GPIO_SIG86_IN_SEL_M (BIT(6)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 6 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 5 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC86_IN_SEL 0x0000001F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x1F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG87_IN_SEL (BIT(6)) +#define GPIO_SIG87_IN_SEL_M (BIT(6)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 6 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 5 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC87_IN_SEL 0x0000001F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x1F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG88_IN_SEL (BIT(6)) +#define GPIO_SIG88_IN_SEL_M (BIT(6)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 6 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 5 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC88_IN_SEL 0x0000001F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x1F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG89_IN_SEL (BIT(6)) +#define GPIO_SIG89_IN_SEL_M (BIT(6)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 6 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 5 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC89_IN_SEL 0x0000001F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x1F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG90_IN_SEL (BIT(6)) +#define GPIO_SIG90_IN_SEL_M (BIT(6)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 6 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 5 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC90_IN_SEL 0x0000001F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x1F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG91_IN_SEL (BIT(6)) +#define GPIO_SIG91_IN_SEL_M (BIT(6)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 6 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 5 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC91_IN_SEL 0x0000001F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x1F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG92_IN_SEL (BIT(6)) +#define GPIO_SIG92_IN_SEL_M (BIT(6)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 6 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 5 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC92_IN_SEL 0x0000001F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x1F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG93_IN_SEL (BIT(6)) +#define GPIO_SIG93_IN_SEL_M (BIT(6)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 6 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 5 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC93_IN_SEL 0x0000001F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x1F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG94_IN_SEL (BIT(6)) +#define GPIO_SIG94_IN_SEL_M (BIT(6)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 6 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 5 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC94_IN_SEL 0x0000001F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x1F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG95_IN_SEL (BIT(6)) +#define GPIO_SIG95_IN_SEL_M (BIT(6)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 6 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 5 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC95_IN_SEL 0x0000001F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x1F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG96_IN_SEL (BIT(6)) +#define GPIO_SIG96_IN_SEL_M (BIT(6)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 6 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 5 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC96_IN_SEL 0x0000001F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x1F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG97_IN_SEL (BIT(6)) +#define GPIO_SIG97_IN_SEL_M (BIT(6)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 6 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 5 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC97_IN_SEL 0x0000001F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x1F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG98_IN_SEL (BIT(6)) +#define GPIO_SIG98_IN_SEL_M (BIT(6)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 6 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 5 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC98_IN_SEL 0x0000001F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x1F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG99_IN_SEL (BIT(6)) +#define GPIO_SIG99_IN_SEL_M (BIT(6)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 6 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 5 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC99_IN_SEL 0x0000001F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x1F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG100_IN_SEL (BIT(6)) +#define GPIO_SIG100_IN_SEL_M (BIT(6)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 6 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 5 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC100_IN_SEL 0x0000001F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x1F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG101_IN_SEL (BIT(6)) +#define GPIO_SIG101_IN_SEL_M (BIT(6)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 6 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 5 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC101_IN_SEL 0x0000001F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x1F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG102_IN_SEL (BIT(6)) +#define GPIO_SIG102_IN_SEL_M (BIT(6)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 6 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 5 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC102_IN_SEL 0x0000001F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x1F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG103_IN_SEL (BIT(6)) +#define GPIO_SIG103_IN_SEL_M (BIT(6)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 6 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 5 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC103_IN_SEL 0x0000001F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x1F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG104_IN_SEL (BIT(6)) +#define GPIO_SIG104_IN_SEL_M (BIT(6)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 6 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 5 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC104_IN_SEL 0x0000001F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x1F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG105_IN_SEL (BIT(6)) +#define GPIO_SIG105_IN_SEL_M (BIT(6)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 6 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 5 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC105_IN_SEL 0x0000001F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x1F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG106_IN_SEL (BIT(6)) +#define GPIO_SIG106_IN_SEL_M (BIT(6)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 6 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 5 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC106_IN_SEL 0x0000001F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x1F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG107_IN_SEL (BIT(6)) +#define GPIO_SIG107_IN_SEL_M (BIT(6)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 6 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 5 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC107_IN_SEL 0x0000001F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x1F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG108_IN_SEL (BIT(6)) +#define GPIO_SIG108_IN_SEL_M (BIT(6)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 6 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 5 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC108_IN_SEL 0x0000001F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x1F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG109_IN_SEL (BIT(6)) +#define GPIO_SIG109_IN_SEL_M (BIT(6)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 6 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 5 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC109_IN_SEL 0x0000001F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x1F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG110_IN_SEL (BIT(6)) +#define GPIO_SIG110_IN_SEL_M (BIT(6)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 6 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 5 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC110_IN_SEL 0x0000001F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x1F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG111_IN_SEL (BIT(6)) +#define GPIO_SIG111_IN_SEL_M (BIT(6)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 6 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 5 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC111_IN_SEL 0x0000001F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x1F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG112_IN_SEL (BIT(6)) +#define GPIO_SIG112_IN_SEL_M (BIT(6)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 6 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 5 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC112_IN_SEL 0x0000001F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x1F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG113_IN_SEL (BIT(6)) +#define GPIO_SIG113_IN_SEL_M (BIT(6)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 6 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 5 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC113_IN_SEL 0x0000001F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x1F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG114_IN_SEL (BIT(6)) +#define GPIO_SIG114_IN_SEL_M (BIT(6)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 6 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 5 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC114_IN_SEL 0x0000001F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x1F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG115_IN_SEL (BIT(6)) +#define GPIO_SIG115_IN_SEL_M (BIT(6)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 6 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 5 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC115_IN_SEL 0x0000001F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x1F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG116_IN_SEL (BIT(6)) +#define GPIO_SIG116_IN_SEL_M (BIT(6)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 6 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 5 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC116_IN_SEL 0x0000001F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x1F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG117_IN_SEL (BIT(6)) +#define GPIO_SIG117_IN_SEL_M (BIT(6)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 6 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 5 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC117_IN_SEL 0x0000001F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x1F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG118_IN_SEL (BIT(6)) +#define GPIO_SIG118_IN_SEL_M (BIT(6)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 6 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 5 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC118_IN_SEL 0x0000001F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x1F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG119_IN_SEL (BIT(6)) +#define GPIO_SIG119_IN_SEL_M (BIT(6)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 6 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 5 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC119_IN_SEL 0x0000001F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x1F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG120_IN_SEL (BIT(6)) +#define GPIO_SIG120_IN_SEL_M (BIT(6)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 6 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 5 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC120_IN_SEL 0x0000001F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x1F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG121_IN_SEL (BIT(6)) +#define GPIO_SIG121_IN_SEL_M (BIT(6)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 6 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 5 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC121_IN_SEL 0x0000001F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x1F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG122_IN_SEL (BIT(6)) +#define GPIO_SIG122_IN_SEL_M (BIT(6)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 6 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 5 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC122_IN_SEL 0x0000001F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x1F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG123_IN_SEL (BIT(6)) +#define GPIO_SIG123_IN_SEL_M (BIT(6)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 6 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 5 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC123_IN_SEL 0x0000001F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x1F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG124_IN_SEL (BIT(6)) +#define GPIO_SIG124_IN_SEL_M (BIT(6)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 6 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 5 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC124_IN_SEL 0x0000001F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x1F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG125_IN_SEL (BIT(6)) +#define GPIO_SIG125_IN_SEL_M (BIT(6)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 6 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 5 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC125_IN_SEL 0x0000001F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x1F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG126_IN_SEL (BIT(6)) +#define GPIO_SIG126_IN_SEL_M (BIT(6)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 6 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 5 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC126_IN_SEL 0x0000001F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x1F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_SIG127_IN_SEL (BIT(6)) +#define GPIO_SIG127_IN_SEL_M (BIT(6)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 6 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 5 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: .*/ +#define GPIO_FUNC127_IN_SEL 0x0000001F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x1F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 10 +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 9 +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC0_OUT_SEL 0x000000FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0xFF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 10 +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 9 +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC1_OUT_SEL 0x000000FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0xFF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55C) +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 10 +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 9 +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC2_OUT_SEL 0x000000FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0xFF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 10 +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 9 +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC3_OUT_SEL 0x000000FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0xFF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 10 +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 9 +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC4_OUT_SEL 0x000000FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0xFF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 10 +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 9 +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC5_OUT_SEL 0x000000FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0xFF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56C) +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 10 +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 9 +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC6_OUT_SEL 0x000000FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0xFF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 10 +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 9 +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC7_OUT_SEL 0x000000FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0xFF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 10 +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 9 +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC8_OUT_SEL 0x000000FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0xFF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 10 +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 9 +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC9_OUT_SEL 0x000000FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0xFF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57C) +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 10 +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 9 +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC10_OUT_SEL 0x000000FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0xFF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 10 +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 9 +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC11_OUT_SEL 0x000000FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0xFF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 10 +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 9 +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC12_OUT_SEL 0x000000FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0xFF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 10 +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 9 +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC13_OUT_SEL 0x000000FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0xFF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58C) +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 10 +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 9 +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC14_OUT_SEL 0x000000FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0xFF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 10 +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 9 +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC15_OUT_SEL 0x000000FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0xFF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 10 +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 9 +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC16_OUT_SEL 0x000000FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0xFF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 10 +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 9 +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC17_OUT_SEL 0x000000FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0xFF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59C) +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 10 +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 9 +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC18_OUT_SEL 0x000000FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0xFF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A0) +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 10 +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 9 +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC19_OUT_SEL 0x000000FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0xFF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A4) +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 10 +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 9 +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC20_OUT_SEL 0x000000FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0xFF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A8) +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 10 +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 9 +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC21_OUT_SEL 0x000000FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0xFF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5AC) +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 10 +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 9 +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC22_OUT_SEL 0x000000FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0xFF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B0) +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 10 +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 9 +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC23_OUT_SEL 0x000000FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0xFF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B4) +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 10 +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 9 +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC24_OUT_SEL 0x000000FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0xFF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B8) +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 10 +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 9 +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC25_OUT_SEL 0x000000FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0xFF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5BC) +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 10 +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 9 +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC26_OUT_SEL 0x000000FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0xFF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C0) +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 10 +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 9 +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC27_OUT_SEL 0x000000FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0xFF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C4) +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 10 +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 9 +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC28_OUT_SEL 0x000000FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0xFF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C8) +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 10 +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 9 +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: .*/ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: .*/ +#define GPIO_FUNC29_OUT_SEL 0x000000FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0xFF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) +/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (BIT(0)) +#define GPIO_CLK_EN_V 0x1 +#define GPIO_CLK_EN_S 0 + +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109090 ; */ +/*description: .*/ +#define GPIO_DATE 0x0FFFFFFF +#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) +#define GPIO_DATE_V 0xFFFFFFF +#define GPIO_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h b/components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h rename to components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h index a74e368e8c..f846afdec2 100644 --- a/components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_GPIO_SD_REG_H_ #define _SOC_GPIO_SD_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0) /* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ diff --git a/components/soc/esp32h2/include/rev2/soc/gpio_sig_map.h b/components/soc/esp32h2/include/rev2/soc/gpio_sig_map.h new file mode 100644 index 0000000000..a28ad30654 --- /dev/null +++ b/components/soc/esp32h2/include/rev2/soc/gpio_sig_map.h @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ + +#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_IDX 4 +#define SPICS0_OUT_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define EXT_ADC_START_IDX 45 +#define LEDC_LS_SIG_OUT0_IDX 45 +#define LEDC_LS_SIG_OUT1_IDX 46 +#define LEDC_LS_SIG_OUT2_IDX 47 +#define LEDC_LS_SIG_OUT3_IDX 48 +#define LEDC_LS_SIG_OUT4_IDX 49 +#define LEDC_LS_SIG_OUT5_IDX 50 +#define RMT_SIG_IN0_IDX 51 +#define RMT_SIG_OUT0_IDX 51 +#define RMT_SIG_IN1_IDX 52 +#define RMT_SIG_OUT1_IDX 52 +#define I2CEXT0_SCL_IN_IDX 53 +#define I2CEXT0_SCL_OUT_IDX 53 +#define I2CEXT0_SDA_IN_IDX 54 +#define I2CEXT0_SDA_OUT_IDX 54 +#define GPIO_SD0_OUT_IDX 55 +#define GPIO_SD1_OUT_IDX 56 +#define GPIO_SD2_OUT_IDX 57 +#define GPIO_SD3_OUT_IDX 58 +#define EVENT_MATRIX_IN0_IDX 59 +#define TASK_MATRIX_OUT0_IDX 59 +#define EVENT_MATRIX_IN1_IDX 60 +#define TASK_MATRIX_OUT1_IDX 60 +#define EVENT_MATRIX_IN2_IDX 61 +#define TASK_MATRIX_OUT2_IDX 61 +#define EVENT_MATRIX_IN3_IDX 62 +#define TASK_MATRIX_OUT3_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define FSPICS1_OUT_IDX 69 +#define FSPICS2_OUT_IDX 70 +#define FSPICS3_OUT_IDX 71 +#define FSPICS4_OUT_IDX 72 +#define FSPICS5_OUT_IDX 73 +#define TWAI_RX_IDX 74 +#define TWAI_TX_IDX 74 +#define TWAI_BUS_OFF_ON_IDX 75 +#define TWAI_CLKOUT_IDX 76 +#define PCMFSYNC_IN_IDX 77 +#define PCMFSYNC_OUT_IDX 77 +#define PCMCLK_IN_IDX 78 +#define PCMCLK_OUT_IDX 78 +#define PCMDIN_IDX 79 +#define PCMDOUT_IDX 79 +#define CO_EXT_PRIORITY_IN_IDX 80 +#define CO_EXT_PRIORITY_OUT_IDX 80 +#define CO_EXT_ACTIVE_IN_IDX 81 +#define CO_EXT_ACTIVE_OUT_IDX 81 +#define MODEM_COEX_GRANT1_IDX 87 +#define MODEM_COEX_GRANT2_IDX 88 +#define ANT_SEL0_IDX 89 +#define ANT_SEL1_IDX 90 +#define ANT_SEL2_IDX 91 +#define ANT_SEL3_IDX 92 +#define ANT_SEL4_IDX 93 +#define ANT_SEL5_IDX 94 +#define ANT_SEL6_IDX 95 +#define ANT_SEL7_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define SYNCERR_IDX 101 +#define SYNC_FOUND_IDX 102 +#define CH_IDX_IDX 103 +#define SYNC_WINDOW_IDX 104 +#define DATA_EN_IDX 105 +#define DATA_IDX 106 +#define PKT_TX_ON_IDX 107 +#define PKT_RX_ON_IDX 108 +#define TXRU_ON_IDX 109 +#define RXRU_ON_IDX 110 +#define LELC_ST3_IDX 111 +#define LELC_ST2_IDX 112 +#define LELC_ST1_IDX 113 +#define LELC_ST0_IDX 114 +#define CRCOK_IDX 115 +#define CLK_GPIO_IDX 116 +#define RADIO_START_IDX 117 +#define SEQUENCE_ON_IDX 118 +#define PUMP_CLK_IDX 119 +#define PUMP_XPD_IDX 120 +#define PUMP_DRV1_IDX 121 +#define PUMP_DRV0_IDX 122 +#define CLK_OUT_OUT1_IDX 123 +#define CLK_OUT_OUT2_IDX 124 +#define CLK_OUT_OUT3_IDX 125 +#define SPICS1_OUT_IDX 126 +#define USB_JTAG_TRST_IDX 127 +#define SIG_GPIO_OUT_IDX 128 +#define GPIO_MAP_DATE_IDX 0x2109090 +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h b/components/soc/esp32h2/include/rev2/soc/interrupt_core0_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h rename to components/soc/esp32h2/include/rev2/soc/interrupt_core0_reg.h index b5833d1af2..fe0d5f684a 100644 --- a/components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/interrupt_core0_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_INTERRUPT_CORE0_REG_H_ #define _SOC_INTERRUPT_CORE0_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE diff --git a/components/soc/esp32h2/include/soc/rev2/io_mux_reg.h b/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/io_mux_reg.h rename to components/soc/esp32h2/include/rev2/soc/io_mux_reg.h index cc79acc33d..9caa01cd19 100644 --- a/components/soc/esp32h2/include/soc/rev2/io_mux_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include "soc.h" +#include "soc/soc.h" /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ diff --git a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h b/components/soc/esp32h2/include/rev2/soc/rtc_cntl_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h rename to components/soc/esp32h2/include/rev2/soc/rtc_cntl_reg.h index 02d3012df6..9699fe654f 100644 --- a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/rtc_cntl_reg.h @@ -21,11 +21,11 @@ #define RTC_WDT_RESET_LENGTH_1600_NS 6 #define RTC_WDT_RESET_LENGTH_3200_NS 7 +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG diff --git a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h b/components/soc/esp32h2/include/rev2/soc/rtc_cntl_struct.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h rename to components/soc/esp32h2/include/rev2/soc/rtc_cntl_struct.h index ffd97153fa..67cf005ab0 100644 --- a/components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h +++ b/components/soc/esp32h2/include/rev2/soc/rtc_cntl_struct.h @@ -10,9 +10,8 @@ #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -typedef volatile struct { +typedef volatile struct rtc_cntl_dev_s{ union { struct { uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ diff --git a/components/soc/esp32h2/include/soc/rev2/sensitive_reg.h b/components/soc/esp32h2/include/rev2/soc/sensitive_reg.h similarity index 99% rename from components/soc/esp32h2/include/soc/rev2/sensitive_reg.h rename to components/soc/esp32h2/include/rev2/soc/sensitive_reg.h index 9a3e6bd81a..679c4c7857 100644 --- a/components/soc/esp32h2/include/soc/rev2/sensitive_reg.h +++ b/components/soc/esp32h2/include/rev2/soc/sensitive_reg.h @@ -6,11 +6,11 @@ #ifndef _SOC_SENSITIVE_REG_H_ #define _SOC_SENSITIVE_REG_H_ +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) /* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ diff --git a/components/soc/esp32h2/include/rev2/soc/soc_caps.h b/components/soc/esp32h2/include/rev2/soc/soc_caps.h new file mode 100644 index 0000000000..ea86ef39ec --- /dev/null +++ b/components/soc/esp32h2/include/rev2/soc/soc_caps.h @@ -0,0 +1,271 @@ +/* + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +#define SOC_CPU_CORES_NUM 1 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_TWAI_SUPPORTED 1 +#define SOC_BT_SUPPORTED 1 +#define SOC_DIG_SIGN_SUPPORTED 1 +#define SOC_HMAC_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_USB_SERIAL_JTAG_SUPPORTED 1 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1 +#define SOC_TEMP_SENSOR_SUPPORTED 1 + + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_PATT_LEN_MAX (16) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1 +//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (1) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_BREAKPOINTS_NUM 8 +#define SOC_CPU_WATCHPOINTS_NUM 8 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 + +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1) // Number of GDMA groups +#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group +#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C3 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1) +#define SOC_GPIO_PIN_COUNT (26) + +// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC +// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. +#define GPIO_SUPPORTS_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-C3 +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) +#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT 0 + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- SIGMA DELTA CAPS --------------------------------*/ +#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral +#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels + +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// Peripheral supports output given level during its "dummy phase" +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) + + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) + +/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ +#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 16384 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-H2 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_RTC_CLK (1) +#define SOC_UART_SUPPORT_XTAL_CLK (1) + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) +#define SOC_MAC_BB_PD_MEM_SIZE (192*4) + +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_BT_WAKEUP (1) + +#define SOC_PM_SUPPORT_CPU_PD (1) + +#define SOC_PM_SUPPORT_BT_PD (1) diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index eaa0f39a89..fb288fb4ef 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -146,19 +146,6 @@ typedef enum { RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL } rtc_xtal_freq_t; -#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 -/** - * @brief CPU frequency values - */ -typedef enum { - RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency - RTC_CPU_FREQ_80M = 1, //!< 80 MHz - RTC_CPU_FREQ_160M = 2, //!< 160 MHz - RTC_CPU_FREQ_240M = 3, //!< 240 MHz - RTC_CPU_FREQ_2M = 4, //!< 2 MHz -} rtc_cpu_freq_t; -#endif - /** * @brief CPU clock source */ diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index dbacea4ab0..fbafdf3a0e 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -934,7 +934,6 @@ components/esp_system/port/soc/esp32h2/apb_backup_dma.c components/esp_system/port/soc/esp32h2/cache_err_int.c components/esp_system/port/soc/esp32h2/cache_err_int.h components/esp_system/port/soc/esp32h2/reset_reason.c -components/esp_system/port/soc/esp32h2/system_internal.c components/esp_system/port/soc/esp32s2/cache_err_int.c components/esp_system/port/soc/esp32s2/cache_err_int.h components/esp_system/port/soc/esp32s2/reset_reason.c @@ -1948,7 +1947,6 @@ components/soc/esp32c3/sigmadelta_periph.c components/soc/esp32c3/spi_periph.c components/soc/esp32c3/uart_periph.c components/soc/esp32h2/adc_periph.c -components/soc/esp32h2/gpio_periph.c components/soc/esp32h2/gdma_periph.c components/soc/esp32h2/i2c_periph.c components/soc/esp32h2/i2s_periph.c @@ -1967,10 +1965,8 @@ components/soc/esp32h2/include/soc/efuse_struct.h components/soc/esp32h2/include/soc/extmem_reg.h components/soc/esp32h2/include/soc/fe_reg.h components/soc/esp32h2/include/soc/gpio_pins.h -components/soc/esp32h2/include/soc/gpio_reg.h components/soc/esp32h2/include/soc/gpio_sd_reg.h components/soc/esp32h2/include/soc/gpio_sd_struct.h -components/soc/esp32h2/include/soc/gpio_sig_map.h components/soc/esp32h2/include/soc/gpio_struct.h components/soc/esp32h2/include/soc/hwcrypto_reg.h components/soc/esp32h2/include/soc/i2c_reg.h