From 4c3ce9f21dba950df5d4ffdeb1b81909087eefdd Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Thu, 13 Oct 2022 18:23:42 +0800 Subject: [PATCH 1/2] esp_rom: fix esp32s3 rom ets_printf bug --- components/bootloader_support/src/bootloader_console.c | 6 +----- components/esp_rom/esp32s3/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32s3/esp_rom_caps.h | 1 + 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index d63e63a638..6f855f4da0 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -50,12 +50,8 @@ void bootloader_console_init(void) { const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM; -#if !ESP_ROM_SUPPORT_MULTIPLE_UART - /* esp_rom_install_channel_put is not available unless multiple UARTs are supported */ + // Install rom uart printf as console. esp_rom_install_uart_printf(); -#else - esp_rom_install_channel_putc(1, esp_rom_uart_putc); -#endif // Wait for UART FIFO to be empty. esp_rom_uart_tx_wait_idle(0); diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index 7383c90099..cf25cf3224 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -54,3 +54,7 @@ config ESP_ROM_HAS_LAYOUT_TABLE config ESP_ROM_HAS_SPI_FLASH bool default y + +config ESP_ROM_HAS_ETS_PRINTF_BUG + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index 88d85003a4..abebda6346 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -19,3 +19,4 @@ #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register From 8774db59f0a97aef1bddbe88ee5ee5f64db85207 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Fri, 14 Oct 2022 14:06:40 +0800 Subject: [PATCH 2/2] esp_rom: remove ESP_ROM_SUPPORT_MULTIPLE_UART --- components/bootloader_support/src/bootloader_console.c | 5 +---- components/esp_rom/esp32/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32/esp_rom_caps.h | 1 - components/esp_rom/esp32s2/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32s2/esp_rom_caps.h | 1 - components/esp_rom/esp32s3/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32s3/esp_rom_caps.h | 1 - 7 files changed, 1 insertion(+), 19 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 6f855f4da0..fe1486880f 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -60,10 +60,7 @@ void bootloader_console_init(void) // Some constants to make the following code less upper-case const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO; const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO; - // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code). -#if ESP_ROM_SUPPORT_MULTIPLE_UART - esp_rom_uart_set_as_console(uart_num); -#endif + // If console is attached to UART1 or if non-default pins are used, // need to reconfigure pins using GPIO matrix if (uart_num != 0 || diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index 4707ff484e..ed129cb84e 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index 1d19be8571..959075b29c 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -9,5 +9,4 @@ #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index 2b753e7e0d..870795370c 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -7,10 +7,6 @@ config ESP_ROM_HAS_CRC_LE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 1078ff8997..1032eef93a 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -7,5 +7,4 @@ #pragma once #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index cf25cf3224..298c2c1a07 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_UART_CLK_IS_XTAL bool default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index abebda6346..c76afc08c5 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -9,7 +9,6 @@ #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_USB_SERIAL_DEVICE_NUM (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.