diff --git a/components/esp_rom/include/esp32c3/rom/rtc.h b/components/esp_rom/include/esp32c3/rom/rtc.h
index 76ece7e819..2a7f6cb614 100644
--- a/components/esp_rom/include/esp32c3/rom/rtc.h
+++ b/components/esp_rom/include/esp32c3/rom/rtc.h
@@ -85,8 +85,7 @@ typedef enum {
     NO_MEAN                =  0,
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
     RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core*/
-    DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
+    DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core*/
     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
@@ -96,8 +95,13 @@ typedef enum {
     RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
     RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
     RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
-    TG1WDT_CPU_RESET       = 17,    /**<11, Time Group1 reset CPU*/
-    SUPER_WDT_RESET        = 18,    /**<11, super watchdog reset digital core and rtc module*/
+    TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
+    SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
+    GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
+    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core */
+    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core */
+    POWER_GLITCH_RESET     = 23,    /**<23, power glitch reset digital core and rtc module*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -112,7 +116,13 @@ _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RT
 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
+_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
+_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
+_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
+_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
+_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
+_Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
 
 typedef enum {
     NO_SLEEP        = 0,
diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h
index 76ece7e819..ad4f45c2ca 100644
--- a/components/esp_rom/include/esp32h2/rom/rtc.h
+++ b/components/esp_rom/include/esp32h2/rom/rtc.h
@@ -85,8 +85,7 @@ typedef enum {
     NO_MEAN                =  0,
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
     RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core*/
-    DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
+    DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core*/
     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
@@ -96,8 +95,14 @@ typedef enum {
     RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
     RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
     RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
-    TG1WDT_CPU_RESET       = 17,    /**<11, Time Group1 reset CPU*/
-    SUPER_WDT_RESET        = 18,    /**<11, super watchdog reset digital core and rtc module*/
+    TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
+    SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
+    GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
+    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core */
+    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core */
+    POWER_GLITCH_RESET     = 23,    /**<23, power glitch reset digital core and rtc module*/
+    JTAG_RESET             = 24,    /**<24, jtag reset CPU*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -112,7 +117,14 @@ _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RT
 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
+_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
+_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
+_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
+_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
+_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
+_Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
+_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG");
 
 typedef enum {
     NO_SLEEP        = 0,
diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h
index 09d2376ef3..d928c4dee4 100644
--- a/components/esp_rom/include/esp32s3/rom/rtc.h
+++ b/components/esp_rom/include/esp32s3/rom/rtc.h
@@ -92,6 +92,9 @@ typedef enum {
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
     GLITCH_RTC_RESET       = 19,    /**<19, glitch reset digital core and rtc module*/
     EFUSE_RESET            = 20,    /**<20, efuse reset digital core*/
+    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core */
+    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core */
+    POWER_GLITCH_RESET     = 23,    /**<23, power glitch reset digital core and rtc module*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -106,9 +109,13 @@ _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RT
 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
+_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
 _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
 _Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
+_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
+_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
+_Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
 
 typedef enum {
     NO_SLEEP        = 0,
diff --git a/components/soc/esp32c3/include/soc/reset_reasons.h b/components/soc/esp32c3/include/soc/reset_reasons.h
index 0bb99f5851..c624619bb3 100644
--- a/components/soc/esp32c3/include/soc/reset_reasons.h
+++ b/components/soc/esp32c3/include/soc/reset_reasons.h
@@ -52,6 +52,8 @@ typedef enum {
     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
     RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
     RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
+    RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core
+    RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core
     RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
 } soc_reset_reason_t;
 
diff --git a/components/soc/esp32h2/include/soc/reset_reasons.h b/components/soc/esp32h2/include/soc/reset_reasons.h
index 0bb99f5851..b11a6ee52a 100644
--- a/components/soc/esp32h2/include/soc/reset_reasons.h
+++ b/components/soc/esp32h2/include/soc/reset_reasons.h
@@ -52,7 +52,10 @@ typedef enum {
     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
     RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
     RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
+    RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core
+    RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core
     RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
+    RESET_REASON_CPU_JTAG        = 0x18, // JTAG resets the CPU
 } soc_reset_reason_t;
 
 
diff --git a/components/soc/esp32s3/include/soc/reset_reasons.h b/components/soc/esp32s3/include/soc/reset_reasons.h
index 6fc0a7391a..2c1c34e9fe 100644
--- a/components/soc/esp32s3/include/soc/reset_reasons.h
+++ b/components/soc/esp32s3/include/soc/reset_reasons.h
@@ -56,6 +56,8 @@ typedef enum {
     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
     RESET_REASON_SYS_CLK_GLITCH  = 0x13, // Glitch on clock resets the digital core and rtc module
     RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
+    RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core
+    RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core
     RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
 } soc_reset_reason_t;