espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-02 12:14:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/remove_psram_cs_clk_pin_settings_config_s2_s3_v4.3' into 'release/v4.3'

Browse Source 
psram: remove CS/CLK pin settings in kconfig on ESP32S2 (v4.3)

See merge request espressif/esp-idf!21048
This commit is contained in:
morris
2022-11-14 17:17:13 +08:00
parent 289a3311de 522cf49d33
commit 3bbb109eb2
6 changed files with 28 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
components/esp32s2/Kconfig
View File

@@ -143,22 +143,14 @@ menu "ESP32S2-specific"
default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0 default 0
menu "PSRAM clock and cs IO for ESP32S2" config SPIRAM_CLK_IO
depends on ESP32S2_SPIRAM_SUPPORT int
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30 default 30
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
config DEFAULT_PSRAM_CS_IO config SPIRAM_CS_IO
int "PSRAM CS IO number" int
range 0 33
default 26 default 26
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM" bool "Cache fetch instructions from SPI RAM"
default n default n

5
components/esp32s2/sdkconfig.rename Normal file
View File

@@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO

4
components/esp32s2/spiram_psram.c
View File

@@ -94,8 +94,8 @@ static const char* TAG = "psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design. // PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM

18
components/esp32s3/Kconfig
View File

@@ -194,22 +194,14 @@ menu "ESP32S3-Specific"
default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0 default 0
menu "PSRAM Clock and CS IO for ESP32S3" config SPIRAM_CLK_IO
depends on ESP32S3_SPIRAM_SUPPORT int
config DEFAULT_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 30 default 30
help
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
config DEFAULT_PSRAM_CS_IO config SPIRAM_CS_IO
int "PSRAM CS IO number" int
range 0 33
default 26 default 26
help
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS config SPIRAM_FETCH_INSTRUCTIONS
bool "Cache fetch instructions from SPI RAM" bool "Cache fetch instructions from SPI RAM"
default n default n

5
components/esp32s3/sdkconfig.rename Normal file
View File

@@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO

4
components/esp32s3/spiram_psram.c
View File

@@ -97,8 +97,8 @@ static const char* TAG = "psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design. // PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM