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Merge branch 'feat/h4_mp_compatibility_changes' into 'master'

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feat(h4mp): update compatible soc headers (part1)

See merge request espressif/esp-idf!41205
This commit is contained in:
Chen Ji Chang
2025-08-14 14:10:42 +08:00
parent 71d3492124 18420f8d3d
commit 3c60941aa0
20 changed files with 6135 additions and 640 deletions
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28
components/soc/esp32h4/register/soc/cache_reg.h
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@@ -254,7 +254,7 @@ extern "C" {
#define CACHE_L1_DCACHE_FREEZE_EN_S 16
/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
* The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
* will not stuck. 1: a miss-access will stuck.
* will stuck. 1: a miss-access will not stuck.
*/
#define CACHE_L1_DCACHE_FREEZE_MODE (BIT(17))
#define CACHE_L1_DCACHE_FREEZE_MODE_M (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
@@ -810,6 +810,14 @@ extern "C" {
#define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
#define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU
#define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3
/** CACHE_L1_ICACHE0_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
#define CACHE_L1_ICACHE0_PRELOAD_MODE (BIT(7))
#define CACHE_L1_ICACHE0_PRELOAD_MODE_M (CACHE_L1_ICACHE0_PRELOAD_MODE_V << CACHE_L1_ICACHE0_PRELOAD_MODE_S)
#define CACHE_L1_ICACHE0_PRELOAD_MODE_V 0x00000001U
#define CACHE_L1_ICACHE0_PRELOAD_MODE_S 7
/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
* L1 instruction Cache 0 preload address configure register
@@ -872,6 +880,14 @@ extern "C" {
#define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
#define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU
#define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3
/** CACHE_L1_ICACHE1_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
#define CACHE_L1_ICACHE1_PRELOAD_MODE (BIT(7))
#define CACHE_L1_ICACHE1_PRELOAD_MODE_M (CACHE_L1_ICACHE1_PRELOAD_MODE_V << CACHE_L1_ICACHE1_PRELOAD_MODE_S)
#define CACHE_L1_ICACHE1_PRELOAD_MODE_V 0x00000001U
#define CACHE_L1_ICACHE1_PRELOAD_MODE_S 7
/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
* L1 instruction Cache 1 preload address configure register
@@ -934,6 +950,14 @@ extern "C" {
#define CACHE_L1_DCACHE_PRELOAD_RGID_M (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
#define CACHE_L1_DCACHE_PRELOAD_RGID_V 0x0000000FU
#define CACHE_L1_DCACHE_PRELOAD_RGID_S 3
/** CACHE_L1_DCACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 dcache preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
#define CACHE_L1_DCACHE_PRELOAD_MODE (BIT(7))
#define CACHE_L1_DCACHE_PRELOAD_MODE_M (CACHE_L1_DCACHE_PRELOAD_MODE_V << CACHE_L1_DCACHE_PRELOAD_MODE_S)
#define CACHE_L1_DCACHE_PRELOAD_MODE_V 0x00000001U
#define CACHE_L1_DCACHE_PRELOAD_MODE_S 7
/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
* L1 data Cache preload address configure register
@@ -2575,7 +2599,7 @@ extern "C" {
* Version control register
*/
#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
/** CACHE_DATE : R/W; bitpos: [27:0]; default: 37765696;
/** CACHE_DATE : R/W; bitpos: [27:0]; default: 38810384;
* version control register. Note that this default value stored is the latest date
* when the hardware logic was updated.
*/

25
components/soc/esp32h4/register/soc/cache_struct.h
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@@ -251,7 +251,7 @@ typedef union {
uint32_t l1_dcache_freeze_en:1;
/** l1_dcache_freeze_mode : R/W; bitpos: [17]; default: 0;
* The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
* will not stuck. 1: a miss-access will stuck.
* will stuck. 1: a miss-access will not stuck.
*/
uint32_t l1_dcache_freeze_mode:1;
/** l1_dcache_freeze_done : RO; bitpos: [18]; default: 0;
@@ -768,7 +768,12 @@ typedef union {
* The bit is used to set the gid of l1 icache0 preload.
*/
uint32_t l1_icache0_preload_rgid:4;
uint32_t reserved_7:25;
/** l1_icache0_preload_mode : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
uint32_t l1_icache0_preload_mode:1;
uint32_t reserved_8:24;
};
uint32_t val;
} cache_l1_icache0_preload_ctrl_reg_t;
@@ -826,7 +831,12 @@ typedef union {
* The bit is used to set the gid of l1 icache1 preload.
*/
uint32_t l1_icache1_preload_rgid:4;
uint32_t reserved_7:25;
/** l1_icache1_preload_mode : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
uint32_t l1_icache1_preload_mode:1;
uint32_t reserved_8:24;
};
uint32_t val;
} cache_l1_icache1_preload_ctrl_reg_t;
@@ -884,7 +894,12 @@ typedef union {
* The bit is used to set the gid of l1 dcache preload.
*/
uint32_t l1_dcache_preload_rgid:4;
uint32_t reserved_7:25;
/** l1_dcache_preload_mode : R/W; bitpos: [7]; default: 0;
* Configures the mode of l1 dcache preload, 0: load data from next level memory, 1:
* not load data from next level memory.
*/
uint32_t l1_dcache_preload_mode:1;
uint32_t reserved_8:24;
};
uint32_t val;
} cache_l1_dcache_preload_ctrl_reg_t;
@@ -2415,7 +2430,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37765696;
/** date : R/W; bitpos: [27:0]; default: 38810384;
* version control register. Note that this default value stored is the latest date
* when the hardware logic was updated.
*/

1402
components/soc/esp32h4/register/soc/hp_mem_apm_reg.h Normal file
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578
components/soc/esp32h4/register/soc/hp_mem_apm_struct.h Normal file
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@@ -0,0 +1,578 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_mem_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t regionn_addr_start_l:12;
/** regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:7;
/** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, start address of region n.
*/
uint32_t regionn_addr_start_h:13;
};
uint32_t val;
} hp_mem_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
* Low 12 bit, end address of region n.
*/
uint32_t regionn_addr_end_l:12;
/** regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:7;
/** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
* High 13 bit, end address of region n.
*/
uint32_t regionn_addr_end_h:13;
};
uint32_t val;
} hp_mem_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} hp_mem_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_mem_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:16;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_mem_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:16;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_mem_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} hp_mem_apm_m3_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m3_apm_int_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_mem_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_mem_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37769360;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_mem_apm_date_reg_t;
typedef struct {
volatile hp_mem_apm_region_filter_en_reg_t region_filter_en;
volatile hp_mem_apm_regionn_addr_start_reg_t region0_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region0_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region0_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region1_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region1_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region1_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region2_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region2_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region2_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region3_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region3_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region3_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region4_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region4_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region4_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region5_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region5_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region5_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region6_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region6_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region6_attr;
volatile hp_mem_apm_regionn_addr_start_reg_t region7_addr_start;
volatile hp_mem_apm_regionn_addr_end_reg_t region7_addr_end;
volatile hp_mem_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile hp_mem_apm_func_ctrl_reg_t func_ctrl;
volatile hp_mem_apm_m0_status_reg_t m0_status;
volatile hp_mem_apm_m0_status_clr_reg_t m0_status_clr;
volatile hp_mem_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile hp_mem_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile hp_mem_apm_m1_status_reg_t m1_status;
volatile hp_mem_apm_m1_status_clr_reg_t m1_status_clr;
volatile hp_mem_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile hp_mem_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile hp_mem_apm_m2_status_reg_t m2_status;
volatile hp_mem_apm_m2_status_clr_reg_t m2_status_clr;
volatile hp_mem_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile hp_mem_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile hp_mem_apm_m3_status_reg_t m3_status;
volatile hp_mem_apm_m3_status_clr_reg_t m3_status_clr;
volatile hp_mem_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile hp_mem_apm_m3_exception_info1_reg_t m3_exception_info1;
uint32_t reserved_108[4];
volatile hp_mem_apm_int_en_reg_t int_en;
uint32_t reserved_11c[439];
volatile hp_mem_apm_clock_gate_reg_t clock_gate;
volatile hp_mem_apm_date_reg_t date;
} hp_mem_apm_dev_t;
extern hp_mem_apm_dev_t HP_MEM_APM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_mem_apm_dev_t) == 0x800, "Invalid size of hp_mem_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

53
components/soc/esp32h4/register/soc/hp_system_reg.h
View File

@@ -478,6 +478,57 @@ extern "C" {
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_S 8
/** HP_SYSTEM_PERI_PMS_INT_EN_REG register
* APM interrupt enable register
*/
#define HP_SYSTEM_PERI_PMS_INT_EN_REG (DR_REG_HP_SYSTEM_BASE + 0xa8)
/** HP_SYSTEM_HP_PERI_PMS_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures to enable hp peri pms interrupt.
* 0: disable
* 1: enable
*/
#define HP_SYSTEM_HP_PERI_PMS_INT_EN (BIT(0))
#define HP_SYSTEM_HP_PERI_PMS_INT_EN_M (HP_SYSTEM_HP_PERI_PMS_INT_EN_V << HP_SYSTEM_HP_PERI_PMS_INT_EN_S)
#define HP_SYSTEM_HP_PERI_PMS_INT_EN_V 0x00000001U
#define HP_SYSTEM_HP_PERI_PMS_INT_EN_S 0
/** HP_SYSTEM_CPU_PERI_PMS_INT_EN : R/W; bitpos: [1]; default: 0;
* Configures to enable cpu peri pms interrupt.
* 0: disable
* 1: enable
*/
#define HP_SYSTEM_CPU_PERI_PMS_INT_EN (BIT(1))
#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_M (HP_SYSTEM_CPU_PERI_PMS_INT_EN_V << HP_SYSTEM_CPU_PERI_PMS_INT_EN_S)
#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_S 1
/** HP_SYSTEM_MODEM_PERI_PMS_INT_EN : R/W; bitpos: [2]; default: 0;
* Configures to enable modem peri pms interrupt.
* 0: disable
* 1: enable
*/
#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN (BIT(2))
#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_M (HP_SYSTEM_MODEM_PERI_PMS_INT_EN_V << HP_SYSTEM_MODEM_PERI_PMS_INT_EN_S)
#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_S 2
/** HP_SYSTEM_CPU_WAKEUP_EVENT_REG register
* NA
*/
#define HP_SYSTEM_CPU_WAKEUP_EVENT_REG (DR_REG_HP_SYSTEM_BASE + 0xc0)
/** HP_SYSTEM_CPU0_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0;
* Configures the cpu0 to exit WFI mode
*/
#define HP_SYSTEM_CPU0_WAKEUP_EVENT (BIT(0))
#define HP_SYSTEM_CPU0_WAKEUP_EVENT_M (HP_SYSTEM_CPU0_WAKEUP_EVENT_V << HP_SYSTEM_CPU0_WAKEUP_EVENT_S)
#define HP_SYSTEM_CPU0_WAKEUP_EVENT_V 0x00000001U
#define HP_SYSTEM_CPU0_WAKEUP_EVENT_S 0
/** HP_SYSTEM_CPU1_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0;
* Configures the cpu1 to exit WFI mode
*/
#define HP_SYSTEM_CPU1_WAKEUP_EVENT (BIT(1))
#define HP_SYSTEM_CPU1_WAKEUP_EVENT_M (HP_SYSTEM_CPU1_WAKEUP_EVENT_V << HP_SYSTEM_CPU1_WAKEUP_EVENT_S)
#define HP_SYSTEM_CPU1_WAKEUP_EVENT_V 0x00000001U
#define HP_SYSTEM_CPU1_WAKEUP_EVENT_S 1
/** HP_SYSTEM_ID_REG register
* ID register
*/
@@ -506,7 +557,7 @@ extern "C" {
* Date control and version control register
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823056;
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 38813728;
* Version control register.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU

349
components/soc/esp32h4/register/soc/hp_system_struct.h
View File

@@ -11,213 +11,231 @@ extern "C" {
#endif
/** Group: Configuration Register */
/** Type of system_external_device_encrypt_decrypt_control register
/** Type of external_device_encrypt_decrypt_control register
* External device encryption/decryption configuration register
*/
typedef union {
struct {
/** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_spi_manual_encrypt:1;
/** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t system_enable_download_db_encrypt:1;
/** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_download_g0cb_decrypt:1;
/** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode.
* 0: Disable
* 1: Enable
*/
uint32_t system_enable_download_manual_encrypt:1;
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_system_external_device_encrypt_decrypt_control_reg_t;
/** Type of system_sdio_ctrl register
/** Type of sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1;
/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t system_dis_sdio_prob:1;
/** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1;
uint32_t dis_sdio_prob:1;
/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t system_sdio_win_access_en:1;
uint32_t sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_sdio_ctrl_reg_t;
/** Type of system_rom_table_lock register
/** Type of rom_table_lock register
* ROM-Table lock register
*/
typedef union {
struct {
/** system_rom_table_lock : R/W; bitpos: [0]; default: 0;
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE.
* 0: Unlock
* 1: Lock
*/
uint32_t system_rom_table_lock:1;
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rom_table_lock_reg_t;
/** Type of system_rom_table register
/** Type of rom_table register
* ROM-Table register
*/
typedef union {
struct {
/** system_rom_table : R/W; bitpos: [31:0]; default: 0;
/** rom_table : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
uint32_t system_rom_table:32;
uint32_t rom_table:32;
};
uint32_t val;
} hp_system_rom_table_reg_t;
/** Type of system_core_debug_runstall_conf register
/** Type of core_debug_runstall_conf register
* Core Debug RunStall configurion register
*/
typedef union {
struct {
/** system_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.
* 0: Disable
* 1: Enable
*/
uint32_t system_core_debug_runstall_enable:1;
/** system_core0_runstalled : RO; bitpos: [1]; default: 0;
uint32_t core_debug_runstall_enable:1;
/** core0_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core0. 1: stalled, 0:
* not stalled.
*/
uint32_t system_core0_runstalled:1;
/** system_core1_runstalled : RO; bitpos: [2]; default: 0;
uint32_t core0_runstalled:1;
/** core1_runstalled : RO; bitpos: [2]; default: 0;
* Software can read this field to get the runstall status of hp-core1. 1: stalled, 0:
* not stalled.
*/
uint32_t system_core1_runstalled:1;
uint32_t core1_runstalled:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_core_debug_runstall_conf_reg_t;
/** Type of system_sprom_ctrl register
/** Type of sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 80;
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 80;
* reserved
*/
uint32_t system_sprom_mem_aux_ctrl:32;
uint32_t sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprom_ctrl_reg_t;
/** Type of system_spram_ctrl register
/** Type of spram_ctrl register
* reserved
*/
typedef union {
struct {
/** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
uint32_t system_spram_mem_aux_ctrl:32;
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_spram_ctrl_reg_t;
/** Type of system_sprf_ctrl register
/** Type of sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320;
* reserved
*/
uint32_t system_sprf_mem_aux_ctrl:32;
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprf_ctrl_reg_t;
/** Type of system_bitscrambler_peri_sel register
/** Type of bitscrambler_peri_sel register
* reserved
*/
typedef union {
struct {
/** system_bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0;
/** bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0;
* select peri that will be connected to bitscrambler,dir : receive data from bs
*/
uint32_t system_bitscrambler_rx_sel:4;
/** system_bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0;
uint32_t bitscrambler_rx_sel:4;
/** bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0;
* select peri that will be connected to bitscrambler,dir : transfer data to peri
*/
uint32_t system_bitscrambler_tx_sel:4;
uint32_t bitscrambler_tx_sel:4;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_system_bitscrambler_peri_sel_reg_t;
/** Type of system_appcpu_boot_addr register
/** Type of appcpu_boot_addr register
* reserved
*/
typedef union {
struct {
/** system_appcpu_boot_addr : R/W; bitpos: [31:0]; default: 0;
/** appcpu_boot_addr : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t system_appcpu_boot_addr:32;
uint32_t appcpu_boot_addr:32;
};
uint32_t val;
} hp_system_appcpu_boot_addr_reg_t;
/** Type of system_axi_mst_pri register
/** Type of axi_mst_pri register
* AXI mst priority configuration register
*/
typedef union {
struct {
/** system_dma_priority : R/W; bitpos: [0]; default: 0;
/** dma_priority : R/W; bitpos: [0]; default: 0;
* AHB-DMA arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t system_dma_priority:1;
/** system_cache_priority : R/W; bitpos: [1]; default: 0;
uint32_t dma_priority:1;
/** cache_priority : R/W; bitpos: [1]; default: 0;
* CACHE arbitration priority for command channels between masters connected to
* ext_mem_DW_axi
*/
uint32_t system_cache_priority:1;
uint32_t cache_priority:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_axi_mst_pri_reg_t;
/** Type of system_rst_en register
/** Type of cpu_wakeup_event register
* NA
*/
typedef union {
struct {
/** cpu0_wakeup_event : R/W; bitpos: [0]; default: 0;
* Configures the cpu0 to exit WFI mode
*/
uint32_t cpu0_wakeup_event:1;
/** cpu1_wakeup_event : R/W; bitpos: [1]; default: 0;
* Configures the cpu1 to exit WFI mode
*/
uint32_t cpu1_wakeup_event:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_cpu_wakeup_event_reg_t;
/** Type of rst_en register
* PCR clock gating configure register
*/
typedef union {
struct {
/** system_hpsysreg_rst_en : R/W; bitpos: [0]; default: 0;
/** hpsysreg_rst_en : R/W; bitpos: [0]; default: 0;
* Set 0 to reset hp_system_reg module
*/
uint32_t system_hpsysreg_rst_en:1;
uint32_t hpsysreg_rst_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
@@ -225,111 +243,111 @@ typedef union {
/** Group: Timeout Register */
/** Type of system_cpu_peri_timeout_conf register
/** Type of cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
uint32_t system_cpu_peri_timeout_thres:16;
/** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
uint32_t system_cpu_peri_timeout_int_clear:1;
/** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t system_cpu_peri_timeout_protect_en:1;
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_cpu_peri_timeout_conf_reg_t;
/** Type of system_cpu_peri_timeout_addr register
/** Type of cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t system_cpu_peri_timeout_addr:32;
uint32_t cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_cpu_peri_timeout_addr_reg_t;
/** Type of system_cpu_peri_timeout_uid register
/** Type of cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t system_cpu_peri_timeout_uid:7;
uint32_t cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_cpu_peri_timeout_uid_reg_t;
/** Type of system_hp_peri_timeout_conf register
/** Type of hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
uint32_t system_hp_peri_timeout_thres:16;
/** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.
* 0: No effect
* 1: Clear timeout interrupt
*/
uint32_t system_hp_peri_timeout_int_clear:1;
/** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.
* 0: Disable
* 1: Enable
*/
uint32_t system_hp_peri_timeout_protect_en:1;
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_hp_peri_timeout_conf_reg_t;
/** Type of system_hp_peri_timeout_addr register
/** Type of hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t system_hp_peri_timeout_addr:32;
uint32_t hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_hp_peri_timeout_addr_reg_t;
/** Type of system_hp_peri_timeout_uid register
/** Type of hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t system_hp_peri_timeout_uid:7;
uint32_t hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
@@ -337,150 +355,178 @@ typedef union {
/** Group: PMS Register */
/** Type of system_cpu_peri_pms_conf register
/** Type of cpu_peri_pms_conf register
* CPU Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_cpu_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
/** cpu_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear cpu peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_cpu_peri_pms_exception_clr:1;
uint32_t cpu_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_cpu_peri_pms_conf_reg_t;
/** Type of system_cpu_peri_pms_exception_info register
/** Type of cpu_peri_pms_exception_info register
* CPU Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_cpu_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
/** cpu_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the cpu peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_cpu_peri_pms_exception_det:1;
/** system_cpu_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
uint32_t cpu_peri_pms_exception_det:1;
/** cpu_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when cpu peripheral pms has been triggered.
*/
uint32_t system_cpu_peri_pms_exception_id:5;
/** system_cpu_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
uint32_t cpu_peri_pms_exception_id:5;
/** cpu_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when cpu peripheral pms has been triggered.
*/
uint32_t system_cpu_peri_pms_exception_mode:2;
/** system_cpu_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
uint32_t cpu_peri_pms_exception_mode:2;
/** cpu_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when cpu peripheral pms has been
* triggered.
*/
uint32_t system_cpu_peri_pms_exception_addr:24;
uint32_t cpu_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_cpu_peri_pms_exception_info_reg_t;
/** Type of system_hp_peri_pms_conf register
/** Type of hp_peri_pms_conf register
* HP Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_hp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
/** hp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear hp peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_hp_peri_pms_exception_clr:1;
uint32_t hp_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_hp_peri_pms_conf_reg_t;
/** Type of system_hp_peri_pms_exception_info register
/** Type of hp_peri_pms_exception_info register
* HP Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_hp_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
/** hp_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the hp peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_hp_peri_pms_exception_det:1;
/** system_hp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
uint32_t hp_peri_pms_exception_det:1;
/** hp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when hp peripheral pms has been triggered.
*/
uint32_t system_hp_peri_pms_exception_id:5;
/** system_hp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
uint32_t hp_peri_pms_exception_id:5;
/** hp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when hp peripheral pms has been triggered.
*/
uint32_t system_hp_peri_pms_exception_mode:2;
/** system_hp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
uint32_t hp_peri_pms_exception_mode:2;
/** hp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when hp peripheral pms has been
* triggered.
*/
uint32_t system_hp_peri_pms_exception_addr:24;
uint32_t hp_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_hp_peri_pms_exception_info_reg_t;
/** Type of system_modem_peri_pms_conf register
/** Type of modem_peri_pms_conf register
* MODEM Peripherals PMS configuration register
*/
typedef union {
struct {
/** system_modem_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
/** modem_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear modem peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t system_modem_peri_pms_exception_clr:1;
uint32_t modem_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_modem_peri_pms_conf_reg_t;
/** Type of system_modem_peri_pms_exception_info register
/** Type of modem_peri_pms_exception_info register
* MODEM Peripherals PMS exception info record register
*/
typedef union {
struct {
/** system_modem_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
/** modem_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the modem peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t system_modem_peri_pms_exception_det:1;
/** system_modem_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
uint32_t modem_peri_pms_exception_det:1;
/** modem_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when modem peripheral pms has been triggered.
*/
uint32_t system_modem_peri_pms_exception_id:5;
/** system_modem_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
uint32_t modem_peri_pms_exception_id:5;
/** modem_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when modem peripheral pms has been triggered.
*/
uint32_t system_modem_peri_pms_exception_mode:2;
/** system_modem_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
uint32_t modem_peri_pms_exception_mode:2;
/** modem_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when modem peripheral pms has been
* triggered.
*/
uint32_t system_modem_peri_pms_exception_addr:24;
uint32_t modem_peri_pms_exception_addr:24;
};
uint32_t val;
} hp_system_modem_peri_pms_exception_info_reg_t;
/** Type of peri_pms_int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** hp_peri_pms_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable hp peri pms interrupt.
* 0: disable
* 1: enable
*/
uint32_t hp_peri_pms_int_en:1;
/** cpu_peri_pms_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable cpu peri pms interrupt.
* 0: disable
* 1: enable
*/
uint32_t cpu_peri_pms_int_en:1;
/** modem_peri_pms_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable modem peri pms interrupt.
* 0: disable
* 1: enable
*/
uint32_t modem_peri_pms_int_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_peri_pms_int_en_reg_t;
/** Group: ID Register */
/** Type of system_id register
/** Type of id register
* ID register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** system_rom_id : RO; bitpos: [27:12]; default: 0;
/** rom_id : RO; bitpos: [27:12]; default: 0;
* Represents the ROM ID of chip
*/
uint32_t system_rom_id:16;
uint32_t rom_id:16;
uint32_t reserved_28:4;
};
uint32_t val;
@@ -488,15 +534,15 @@ typedef union {
/** Group: Version Register */
/** Type of system_date register
/** Type of date register
* Date control and version control register
*/
typedef union {
struct {
/** system_date : R/W; bitpos: [27:0]; default: 37823056;
/** date : R/W; bitpos: [27:0]; default: 38813728;
* Version control register.
*/
uint32_t system_date:28;
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
@@ -504,47 +550,50 @@ typedef union {
typedef struct {
volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control;
volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
uint32_t reserved_004[2];
volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid;
volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
uint32_t reserved_024[3];
volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl;
volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
uint32_t reserved_034;
volatile hp_system_rom_table_lock_reg_t system_rom_table_lock;
volatile hp_system_rom_table_reg_t system_rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf;
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
volatile hp_system_rom_table_reg_t rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
uint32_t reserved_044[11];
volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t system_spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl;
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
uint32_t reserved_07c;
volatile hp_system_bitscrambler_peri_sel_reg_t system_bitscrambler_peri_sel;
volatile hp_system_appcpu_boot_addr_reg_t system_appcpu_boot_addr;
volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri;
volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
volatile hp_system_appcpu_boot_addr_reg_t appcpu_boot_addr;
volatile hp_system_axi_mst_pri_reg_t axi_mst_pri;
uint32_t reserved_08c;
volatile hp_system_cpu_peri_pms_conf_reg_t system_cpu_peri_pms_conf;
volatile hp_system_cpu_peri_pms_exception_info_reg_t system_cpu_peri_pms_exception_info;
volatile hp_system_hp_peri_pms_conf_reg_t system_hp_peri_pms_conf;
volatile hp_system_hp_peri_pms_exception_info_reg_t system_hp_peri_pms_exception_info;
volatile hp_system_modem_peri_pms_conf_reg_t system_modem_peri_pms_conf;
volatile hp_system_modem_peri_pms_exception_info_reg_t system_modem_peri_pms_exception_info;
uint32_t reserved_0a8[205];
volatile hp_system_id_reg_t system_id;
volatile hp_system_cpu_peri_pms_conf_reg_t cpu_peri_pms_conf;
volatile hp_system_cpu_peri_pms_exception_info_reg_t cpu_peri_pms_exception_info;
volatile hp_system_hp_peri_pms_conf_reg_t hp_peri_pms_conf;
volatile hp_system_hp_peri_pms_exception_info_reg_t hp_peri_pms_exception_info;
volatile hp_system_modem_peri_pms_conf_reg_t modem_peri_pms_conf;
volatile hp_system_modem_peri_pms_exception_info_reg_t modem_peri_pms_exception_info;
volatile hp_system_peri_pms_int_en_reg_t peri_pms_int_en;
uint32_t reserved_0ac[5];
volatile hp_system_cpu_wakeup_event_reg_t cpu_wakeup_event;
uint32_t reserved_0c4[198];
volatile hp_system_id_reg_t id;
uint32_t reserved_3e0[4];
volatile hp_system_rst_en_reg_t system_rst_en;
volatile hp_system_rst_en_reg_t rst_en;
uint32_t reserved_3f4[2];
volatile hp_system_date_reg_t system_date;
} hp_dev_t;
volatile hp_system_date_reg_t date;
} hp_system_dev_t;
extern hp_dev_t HP_SYSTEM;
extern hp_system_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_dev_t) == 0x400, "Invalid size of hp_dev_t structure");
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
#endif
#ifdef __cplusplus

79
components/soc/esp32h4/register/soc/lp_aon_reg.h
View File

@@ -150,7 +150,7 @@ extern "C" {
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~31 hold enable,when io in hold status, all io configure and output
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
@@ -160,13 +160,10 @@ extern "C" {
/** LP_AON_GPIO_HOLD1_REG register
* reserved
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
@@ -248,6 +245,13 @@ extern "C" {
* configure hp iomux reset bypass
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_PULL_LDO_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_PULL_LDO_EN (BIT(27))
#define LP_AON_IO_MUX_PULL_LDO_EN_M (LP_AON_IO_MUX_PULL_LDO_EN_V << LP_AON_IO_MUX_PULL_LDO_EN_S)
#define LP_AON_IO_MUX_PULL_LDO_EN_V 0x00000001U
#define LP_AON_IO_MUX_PULL_LDO_EN_S 27
/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
@@ -608,45 +612,6 @@ extern "C" {
#define LP_AON_IO_LDO_ADJUST_SW_EN_V 0x00000001U
#define LP_AON_IO_LDO_ADJUST_SW_EN_S 31
/** LP_AON_LP_GPIO_SECURITY_REG register
* need des
*/
#define LP_AON_LP_GPIO_SECURITY_REG (DR_REG_LP_AON_BASE + 0x8c)
/** LP_AON_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0;
* This field decides whether lp_gpio_config can be locked, or not. 0 (default):
* unlocked. 1: locked.
*/
#define LP_AON_LP_GPIO_LOCK 0x0000003FU
#define LP_AON_LP_GPIO_LOCK_M (LP_AON_LP_GPIO_LOCK_V << LP_AON_LP_GPIO_LOCK_S)
#define LP_AON_LP_GPIO_LOCK_V 0x0000003FU
#define LP_AON_LP_GPIO_LOCK_S 0
/** LP_AON_HP_GPIO_SECURITY_1_REG register
* need des
*/
#define LP_AON_HP_GPIO_SECURITY_1_REG (DR_REG_LP_AON_BASE + 0x90)
/** LP_AON_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0;
* This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_AON_HP_GPIO_LOCK_P1 0xFFFFFFFFU
#define LP_AON_HP_GPIO_LOCK_P1_M (LP_AON_HP_GPIO_LOCK_P1_V << LP_AON_HP_GPIO_LOCK_P1_S)
#define LP_AON_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU
#define LP_AON_HP_GPIO_LOCK_P1_S 0
/** LP_AON_HP_GPIO_SECURITY_2_REG register
* need des
*/
#define LP_AON_HP_GPIO_SECURITY_2_REG (DR_REG_LP_AON_BASE + 0x94)
/** LP_AON_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0;
* This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_AON_HP_GPIO_LOCK_P2 0x000000FFU
#define LP_AON_HP_GPIO_LOCK_P2_M (LP_AON_HP_GPIO_LOCK_P2_V << LP_AON_HP_GPIO_LOCK_P2_S)
#define LP_AON_HP_GPIO_LOCK_P2_V 0x000000FFU
#define LP_AON_HP_GPIO_LOCK_P2_S 0
/** LP_AON_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
@@ -674,11 +639,37 @@ extern "C" {
#define LP_AON_ICACHE1_USAGE_V 0x00000001U
#define LP_AON_ICACHE1_USAGE_S 1
/** LP_AON_PUF_CONF_REG register
* PUF mem control config register
*/
#define LP_AON_PUF_CONF_REG (DR_REG_LP_AON_BASE + 0x19c)
/** LP_AON_PUF_SW : R/W; bitpos: [0]; default: 1;
* puf mem power switch control signal
*/
#define LP_AON_PUF_SW (BIT(0))
#define LP_AON_PUF_SW_M (LP_AON_PUF_SW_V << LP_AON_PUF_SW_S)
#define LP_AON_PUF_SW_V 0x00000001U
#define LP_AON_PUF_SW_S 0
/** LP_AON_PUF_ISO_EN : R/W; bitpos: [1]; default: 0;
* iso enable signal for puf mem
*/
#define LP_AON_PUF_ISO_EN (BIT(1))
#define LP_AON_PUF_ISO_EN_M (LP_AON_PUF_ISO_EN_V << LP_AON_PUF_ISO_EN_S)
#define LP_AON_PUF_ISO_EN_V 0x00000001U
#define LP_AON_PUF_ISO_EN_S 1
/** LP_AON_PUF_MEM_DISCHARGE : R/W; bitpos: [2]; default: 0;
* discharge signal for puf mem
*/
#define LP_AON_PUF_MEM_DISCHARGE (BIT(2))
#define LP_AON_PUF_MEM_DISCHARGE_M (LP_AON_PUF_MEM_DISCHARGE_V << LP_AON_PUF_MEM_DISCHARGE_S)
#define LP_AON_PUF_MEM_DISCHARGE_V 0x00000001U
#define LP_AON_PUF_MEM_DISCHARGE_S 2
/** LP_AON_DATE_REG register
* reserved
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823056;
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352;
* version register
*/
#define LP_AON_DATE 0x7FFFFFFFU

86
components/soc/esp32h4/register/soc/lp_aon_struct.h
View File

@@ -163,7 +163,7 @@ typedef union {
typedef union {
struct {
/** aon_gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~31 hold enable,when io in hold status, all io configure and output
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
uint32_t gpio_hold0:32;
@@ -178,7 +178,6 @@ typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t gpio_hold1:32;
};
@@ -251,7 +250,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:28;
uint32_t reserved_0:27;
/** aon_io_mux_pull_ldo_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t aon_io_mux_pull_ldo_en:1;
/** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
@@ -546,50 +549,6 @@ typedef union {
uint32_t val;
} lp_aon_io_ldo_cfg_reg_t;
/** Type of aon_lp_gpio_security register
* need des
*/
typedef union {
struct {
/** aon_lp_gpio_lock : R/W; bitpos: [5:0]; default: 0;
* This field decides whether lp_gpio_config can be locked, or not. 0 (default):
* unlocked. 1: locked.
*/
uint32_t aon_lp_gpio_lock:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_aon_lp_gpio_security_reg_t;
/** Type of aon_hp_gpio_security_1 register
* need des
*/
typedef union {
struct {
/** aon_hp_gpio_lock_p1 : R/W; bitpos: [31:0]; default: 0;
* This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
uint32_t aon_hp_gpio_lock_p1:32;
};
uint32_t val;
} lp_aon_hp_gpio_security_1_reg_t;
/** Type of aon_hp_gpio_security_2 register
* need des
*/
typedef union {
struct {
/** aon_hp_gpio_lock_p2 : R/W; bitpos: [7:0]; default: 0;
* This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
uint32_t aon_hp_gpio_lock_p2:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_hp_gpio_security_2_reg_t;
/** Type of aon_sram_usage_conf register
* HP memory usage configuration register
*/
@@ -616,12 +575,34 @@ typedef union {
uint32_t val;
} lp_aon_sram_usage_conf_reg_t;
/** Type of puf_conf register
* PUF mem control config register
*/
typedef union {
struct {
/** puf_sw : R/W; bitpos: [0]; default: 1;
* puf mem power switch control signal
*/
uint32_t puf_sw:1;
/** puf_iso_en : R/W; bitpos: [1]; default: 0;
* iso enable signal for puf mem
*/
uint32_t puf_iso_en:1;
/** puf_mem_discharge : R/W; bitpos: [2]; default: 0;
* discharge signal for puf mem
*/
uint32_t puf_mem_discharge:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_aon_puf_conf_reg_t;
/** Type of aon_date register
* reserved
*/
typedef union {
struct {
/** aon_date : R/W; bitpos: [30:0]; default: 37823056;
/** aon_date : R/W; bitpos: [30:0]; default: 38814352;
* version register
*/
uint32_t aon_date:31;
@@ -662,12 +643,11 @@ typedef struct {
volatile lp_aon_mem_ctrl_reg_t mem_ctrl;
volatile lp_aon_hp_mem_ctrl_reg_t hp_mem_ctrl;
volatile lp_aon_io_ldo_cfg_reg_t io_ldo_cfg;
uint32_t reserved_088;
volatile lp_aon_lp_gpio_security_reg_t lp_gpio_security;
volatile lp_aon_hp_gpio_security_1_reg_t hp_gpio_security_1;
volatile lp_aon_hp_gpio_security_2_reg_t hp_gpio_security_2;
uint32_t reserved_088[4];
volatile lp_aon_sram_usage_conf_reg_t sram_usage_conf;
uint32_t reserved_09c[216];
uint32_t reserved_09c[64];
volatile lp_aon_puf_conf_reg_t puf_conf;
uint32_t reserved_1a0[151];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;

77
components/soc/esp32h4/register/soc/lp_tee_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** LP_TEE_TRNG_CTRL_REG register
* trng read/write control register
*/
#define LP_TEE_TRNG_CTRL_REG (DR_REG_LP_BASE + 0x0)
#define LP_TEE_TRNG_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_READ_TEE_TRNG : R/W; bitpos: [0]; default: 1;
* Configures trng registers read permission in tee mode.
* 0: can not be read
@@ -91,7 +91,7 @@ extern "C" {
/** LP_TEE_EFUSE_CTRL_REG register
* efuse read/write control register
*/
#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_BASE + 0x4)
#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1;
* Configures efuse registers read permission in tee mode.
* 0: can not be read
@@ -168,7 +168,7 @@ extern "C" {
/** LP_TEE_PMU_CTRL_REG register
* pmu read/write control register
*/
#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_BASE + 0x8)
#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8)
/** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1;
* Configures pmu registers read permission in tee mode.
* 0: can not be read
@@ -245,7 +245,7 @@ extern "C" {
/** LP_TEE_CLKRST_CTRL_REG register
* clkrst read/write control register
*/
#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_BASE + 0xc)
#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc)
/** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1;
* Configures clkrst registers read permission in tee mode.
* 0: can not be read
@@ -322,7 +322,7 @@ extern "C" {
/** LP_TEE_LP_AON_CTRL_CTRL_REG register
* lp_aon_ctrl read/write control register
*/
#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_BASE + 0x10)
#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10)
/** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1;
* Configures lp_aon_ctrl registers read permission in tee mode.
* 0: can not be read
@@ -399,7 +399,7 @@ extern "C" {
/** LP_TEE_LP_TIMER_CTRL_REG register
* lp_timer read/write control register
*/
#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x14)
#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14)
/** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1;
* Configures lp_timer registers read permission in tee mode.
* 0: can not be read
@@ -476,7 +476,7 @@ extern "C" {
/** LP_TEE_LP_WDT_CTRL_REG register
* lp_wdt read/write control register
*/
#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_BASE + 0x18)
#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18)
/** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1;
* Configures lp_wdt registers read permission in tee mode.
* 0: can not be read
@@ -553,7 +553,7 @@ extern "C" {
/** LP_TEE_LPPERI_CTRL_REG register
* lpperi read/write control register
*/
#define LP_TEE_LPPERI_CTRL_REG (DR_REG_LP_BASE + 0x1c)
#define LP_TEE_LPPERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c)
/** LP_TEE_READ_TEE_LPPERI : R/W; bitpos: [0]; default: 1;
* Configures lpperi registers read permission in tee mode.
* 0: can not be read
@@ -630,7 +630,7 @@ extern "C" {
/** LP_TEE_LP_ANA_PERI_CTRL_REG register
* lp_ana_peri read/write control register
*/
#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_BASE + 0x20)
#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20)
/** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1;
* Configures lp_ana_peri registers read permission in tee mode.
* 0: can not be read
@@ -707,7 +707,7 @@ extern "C" {
/** LP_TEE_LP_TOUCH_CTRL_REG register
* lp_touch read/write control register
*/
#define LP_TEE_LP_TOUCH_CTRL_REG (DR_REG_LP_BASE + 0x24)
#define LP_TEE_LP_TOUCH_CTRL_REG (DR_REG_LP_TEE_BASE + 0x24)
/** LP_TEE_READ_TEE_LP_TOUCH : R/W; bitpos: [0]; default: 1;
* Configures lp_touch registers read permission in tee mode.
* 0: can not be read
@@ -784,7 +784,7 @@ extern "C" {
/** LP_TEE_TOUCH_AON_CTRL_REG register
* touch_aon read/write control register
*/
#define LP_TEE_TOUCH_AON_CTRL_REG (DR_REG_LP_BASE + 0x28)
#define LP_TEE_TOUCH_AON_CTRL_REG (DR_REG_LP_TEE_BASE + 0x28)
/** LP_TEE_READ_TEE_TOUCH_AON : R/W; bitpos: [0]; default: 1;
* Configures touch_aon registers read permission in tee mode.
* 0: can not be read
@@ -861,7 +861,7 @@ extern "C" {
/** LP_TEE_LP_IO_CTRL_REG register
* lp_io read/write control register
*/
#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_BASE + 0x2c)
#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c)
/** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1;
* Configures lp_io registers read permission in tee mode.
* 0: can not be read
@@ -938,7 +938,7 @@ extern "C" {
/** LP_TEE_LP_BLE_TIMER_CTRL_REG register
* lp_ble_timer read/write control register
*/
#define LP_TEE_LP_BLE_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x30)
#define LP_TEE_LP_BLE_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x30)
/** LP_TEE_READ_TEE_LP_BLE_TIMER : R/W; bitpos: [0]; default: 1;
* Configures lp_ble_timer registers read permission in tee mode.
* 0: can not be read
@@ -1015,7 +1015,7 @@ extern "C" {
/** LP_TEE_LP_TEE_CTRL_REG register
* lp_tee read/write control register
*/
#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_BASE + 0x34)
#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34)
/** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1;
* Configures lp_tee registers read permission in tee mode.
* 0: can not be read
@@ -1092,7 +1092,7 @@ extern "C" {
/** LP_TEE_HUK_CTRL_REG register
* lp_tee read/write control register
*/
#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_BASE + 0x38)
#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38)
/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1;
* Configures huk registers read permission in tee mode.
* 0: can not be read
@@ -1166,10 +1166,49 @@ extern "C" {
#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U
#define LP_TEE_WRITE_REE2_HUK_S 7
/** LP_TEE_LP_GPIO_SECURITY_REG register
* need des
*/
#define LP_TEE_LP_GPIO_SECURITY_REG (DR_REG_LP_TEE_BASE + 0xe4)
/** LP_TEE_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0;
* This field decides whether lp_gpio_config can be locked, or not. 0 (default):
* unlocked. 1: locked.
*/
#define LP_TEE_LP_GPIO_LOCK 0x0000003FU
#define LP_TEE_LP_GPIO_LOCK_M (LP_TEE_LP_GPIO_LOCK_V << LP_TEE_LP_GPIO_LOCK_S)
#define LP_TEE_LP_GPIO_LOCK_V 0x0000003FU
#define LP_TEE_LP_GPIO_LOCK_S 0
/** LP_TEE_HP_GPIO_SECURITY_1_REG register
* need des
*/
#define LP_TEE_HP_GPIO_SECURITY_1_REG (DR_REG_LP_TEE_BASE + 0xe8)
/** LP_TEE_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0;
* This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_TEE_HP_GPIO_LOCK_P1 0xFFFFFFFFU
#define LP_TEE_HP_GPIO_LOCK_P1_M (LP_TEE_HP_GPIO_LOCK_P1_V << LP_TEE_HP_GPIO_LOCK_P1_S)
#define LP_TEE_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU
#define LP_TEE_HP_GPIO_LOCK_P1_S 0
/** LP_TEE_HP_GPIO_SECURITY_2_REG register
* need des
*/
#define LP_TEE_HP_GPIO_SECURITY_2_REG (DR_REG_LP_TEE_BASE + 0xec)
/** LP_TEE_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0;
* This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_TEE_HP_GPIO_LOCK_P2 0x000000FFU
#define LP_TEE_HP_GPIO_LOCK_P2_M (LP_TEE_HP_GPIO_LOCK_P2_V << LP_TEE_HP_GPIO_LOCK_P2_S)
#define LP_TEE_HP_GPIO_LOCK_P2_V 0x000000FFU
#define LP_TEE_HP_GPIO_LOCK_P2_S 0
/** LP_TEE_BUS_ERR_CONF_REG register
* Clock gating register
*/
#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_BASE + 0xf0)
#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0)
/** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
@@ -1183,7 +1222,7 @@ extern "C" {
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xf8)
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
@@ -1197,8 +1236,8 @@ extern "C" {
/** LP_TEE_DATE_REG register
* Version control register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_BASE + 0xfc)
/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 37818640;
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 38813840;
* Version control register
*/
#define LP_TEE_DATE 0x0FFFFFFFU

616
components/soc/esp32h4/register/soc/lp_tee_struct.h
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File diff suppressed because it is too large Load Diff

16
components/soc/esp32h4/register/soc/lpperi_reg.h
View File

@@ -179,6 +179,20 @@ extern "C" {
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S 8
/** LPPERI_PERI_PMS_INT_EN_REG register
* APM interrupt enable register
*/
#define LPPERI_PERI_PMS_INT_EN_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_PMS_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures to enable lp peri pms interrupt.
* 0: disable
* 1: enable
*/
#define LPPERI_LP_PERI_PMS_INT_EN (BIT(0))
#define LPPERI_LP_PERI_PMS_INT_EN_M (LPPERI_LP_PERI_PMS_INT_EN_V << LPPERI_LP_PERI_PMS_INT_EN_S)
#define LPPERI_LP_PERI_PMS_INT_EN_V 0x00000001U
#define LPPERI_LP_PERI_PMS_INT_EN_S 0
/** LPPERI_INTERRUPT_SOURCE_REG register
* record the lp cpu interrupt
*/
@@ -195,7 +209,7 @@ extern "C" {
* version register
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37819136;
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 38813744;
* version register
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU

21
components/soc/esp32h4/register/soc/lpperi_struct.h
View File

@@ -167,6 +167,22 @@ typedef union {
uint32_t val;
} lpperi_lp_peri_pms_exception_info_reg_t;
/** Type of peri_pms_int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** lp_peri_pms_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable lp peri pms interrupt.
* 0: disable
* 1: enable
*/
uint32_t lp_peri_pms_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lpperi_peri_pms_int_en_reg_t;
/** Group: Version register */
/** Type of date register
@@ -174,7 +190,7 @@ typedef union {
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 37819136;
/** lpperi_date : R/W; bitpos: [30:0]; default: 38813744;
* version register
*/
uint32_t lpperi_date:31;
@@ -193,7 +209,8 @@ typedef struct {
uint32_t reserved_008[2];
volatile lpperi_lp_peri_pms_conf_reg_t lp_peri_pms_conf;
volatile lpperi_lp_peri_pms_exception_info_reg_t lp_peri_pms_exception_info;
uint32_t reserved_018[2];
volatile lpperi_peri_pms_int_en_reg_t peri_pms_int_en;
uint32_t reserved_01c;
volatile lpperi_interrupt_source_reg_t interrupt_source;
uint32_t reserved_024[246];
volatile lpperi_date_reg_t date;

27
components/soc/esp32h4/register/soc/pmu_reg.h
View File

@@ -476,7 +476,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16;
* need_des
*/
#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU
@@ -940,7 +940,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16;
* need_des
*/
#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU
@@ -2476,7 +2476,7 @@ extern "C" {
* need_des
*/
#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130)
/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 384;
* need_des
*/
#define PMU_WAIT_XTL_STABLE 0x0000FFFFU
@@ -3742,11 +3742,30 @@ extern "C" {
#define PMU_TOUCH_FORCE_DONE_V 0x00000001U
#define PMU_TOUCH_FORCE_DONE_S 31
/** PMU_BLE_BANDGAP_CTRL_REG register
* need_des
*/
#define PMU_BLE_BANDGAP_CTRL_REG (DR_REG_PMU_BASE + 0x1c4)
/** PMU_EXT_OCODE : R/W; bitpos: [30:23]; default: 120;
* need_des
*/
#define PMU_EXT_OCODE 0x000000FFU
#define PMU_EXT_OCODE_M (PMU_EXT_OCODE_V << PMU_EXT_OCODE_S)
#define PMU_EXT_OCODE_V 0x000000FFU
#define PMU_EXT_OCODE_S 23
/** PMU_EXT_FORCE_OCODE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_EXT_FORCE_OCODE (BIT(31))
#define PMU_EXT_FORCE_OCODE_M (PMU_EXT_FORCE_OCODE_V << PMU_EXT_FORCE_OCODE_S)
#define PMU_EXT_FORCE_OCODE_V 0x00000001U
#define PMU_EXT_FORCE_OCODE_S 31
/** PMU_DATE_REG register
* need_des
*/
#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37818464;
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38814336;
* need_des
*/
#define PMU_PMU_DATE 0x7FFFFFFFU

3001
components/soc/esp32h4/register/soc/pmu_struct_mp.h Normal file
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File diff suppressed because it is too large Load Diff

186
components/soc/esp32h4/register/soc/spi_mem_c_reg.h
View File

@@ -1321,6 +1321,29 @@ extern "C" {
#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S)
#define SPI_FMEM_PMS0_ECC_V 0x00000001U
#define SPI_FMEM_PMS0_ECC_S 2
/** SPI_FMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR (BIT(3))
#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS0_NONSECURE_RD_ATTR_S)
#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_S 3
/** SPI_FMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR (BIT(4))
#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS0_NONSECURE_WR_ATTR_S)
#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_S 4
/** SPI_FMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and
* SPI_FMEM_PMS0_SIZE_REG.
*/
#define SPI_FMEM_PMS0_NONSECURE_ECC (BIT(5))
#define SPI_FMEM_PMS0_NONSECURE_ECC_M (SPI_FMEM_PMS0_NONSECURE_ECC_V << SPI_FMEM_PMS0_NONSECURE_ECC_S)
#define SPI_FMEM_PMS0_NONSECURE_ECC_V 0x00000001U
#define SPI_FMEM_PMS0_NONSECURE_ECC_S 5
/** SPI_FMEM_PMS1_ATTR_REG register
* SPI1 flash PMS section 1 attribute register
@@ -1349,6 +1372,29 @@ extern "C" {
#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S)
#define SPI_FMEM_PMS1_ECC_V 0x00000001U
#define SPI_FMEM_PMS1_ECC_S 2
/** SPI_FMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR (BIT(3))
#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS1_NONSECURE_RD_ATTR_S)
#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_S 3
/** SPI_FMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR (BIT(4))
#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS1_NONSECURE_WR_ATTR_S)
#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_S 4
/** SPI_FMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and
* SPI_FMEM_PMS1_SIZE_REG.
*/
#define SPI_FMEM_PMS1_NONSECURE_ECC (BIT(5))
#define SPI_FMEM_PMS1_NONSECURE_ECC_M (SPI_FMEM_PMS1_NONSECURE_ECC_V << SPI_FMEM_PMS1_NONSECURE_ECC_S)
#define SPI_FMEM_PMS1_NONSECURE_ECC_V 0x00000001U
#define SPI_FMEM_PMS1_NONSECURE_ECC_S 5
/** SPI_FMEM_PMS2_ATTR_REG register
* SPI1 flash PMS section 2 attribute register
@@ -1377,6 +1423,29 @@ extern "C" {
#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S)
#define SPI_FMEM_PMS2_ECC_V 0x00000001U
#define SPI_FMEM_PMS2_ECC_S 2
/** SPI_FMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR (BIT(3))
#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS2_NONSECURE_RD_ATTR_S)
#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_S 3
/** SPI_FMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR (BIT(4))
#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS2_NONSECURE_WR_ATTR_S)
#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_S 4
/** SPI_FMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and
* SPI_FMEM_PMS2_SIZE_REG.
*/
#define SPI_FMEM_PMS2_NONSECURE_ECC (BIT(5))
#define SPI_FMEM_PMS2_NONSECURE_ECC_M (SPI_FMEM_PMS2_NONSECURE_ECC_V << SPI_FMEM_PMS2_NONSECURE_ECC_S)
#define SPI_FMEM_PMS2_NONSECURE_ECC_V 0x00000001U
#define SPI_FMEM_PMS2_NONSECURE_ECC_S 5
/** SPI_FMEM_PMS3_ATTR_REG register
* SPI1 flash PMS section 3 attribute register
@@ -1405,6 +1474,29 @@ extern "C" {
#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S)
#define SPI_FMEM_PMS3_ECC_V 0x00000001U
#define SPI_FMEM_PMS3_ECC_S 2
/** SPI_FMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR (BIT(3))
#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS3_NONSECURE_RD_ATTR_S)
#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_S 3
/** SPI_FMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed.
*/
#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR (BIT(4))
#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS3_NONSECURE_WR_ATTR_S)
#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_S 4
/** SPI_FMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and
* SPI_FMEM_PMS3_SIZE_REG.
*/
#define SPI_FMEM_PMS3_NONSECURE_ECC (BIT(5))
#define SPI_FMEM_PMS3_NONSECURE_ECC_M (SPI_FMEM_PMS3_NONSECURE_ECC_V << SPI_FMEM_PMS3_NONSECURE_ECC_S)
#define SPI_FMEM_PMS3_NONSECURE_ECC_V 0x00000001U
#define SPI_FMEM_PMS3_NONSECURE_ECC_S 5
/** SPI_FMEM_PMS0_ADDR_REG register
* SPI1 flash PMS section 0 start address register
@@ -1533,6 +1625,29 @@ extern "C" {
#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S)
#define SPI_SMEM_PMS0_ECC_V 0x00000001U
#define SPI_SMEM_PMS0_ECC_S 2
/** SPI_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3))
#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS0_NONSECURE_RD_ATTR_S)
#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_S 3
/** SPI_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4))
#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS0_NONSECURE_WR_ATTR_S)
#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_S 4
/** SPI_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section 0 is configured by registers
* SPI_SMEM_PMS0_ADDR_REG and SPI_SMEM_PMS0_SIZE_REG.
*/
#define SPI_SMEM_PMS0_NONSECURE_ECC (BIT(5))
#define SPI_SMEM_PMS0_NONSECURE_ECC_M (SPI_SMEM_PMS0_NONSECURE_ECC_V << SPI_SMEM_PMS0_NONSECURE_ECC_S)
#define SPI_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U
#define SPI_SMEM_PMS0_NONSECURE_ECC_S 5
/** SPI_SMEM_PMS1_ATTR_REG register
* SPI1 external RAM PMS section 1 attribute register
@@ -1561,6 +1676,29 @@ extern "C" {
#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S)
#define SPI_SMEM_PMS1_ECC_V 0x00000001U
#define SPI_SMEM_PMS1_ECC_S 2
/** SPI_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3))
#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS1_NONSECURE_RD_ATTR_S)
#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_S 3
/** SPI_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4))
#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS1_NONSECURE_WR_ATTR_S)
#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_S 4
/** SPI_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section 1 is configured by registers
* SPI_SMEM_PMS1_ADDR_REG and SPI_SMEM_PMS1_SIZE_REG.
*/
#define SPI_SMEM_PMS1_NONSECURE_ECC (BIT(5))
#define SPI_SMEM_PMS1_NONSECURE_ECC_M (SPI_SMEM_PMS1_NONSECURE_ECC_V << SPI_SMEM_PMS1_NONSECURE_ECC_S)
#define SPI_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U
#define SPI_SMEM_PMS1_NONSECURE_ECC_S 5
/** SPI_SMEM_PMS2_ATTR_REG register
* SPI1 external RAM PMS section 2 attribute register
@@ -1589,6 +1727,29 @@ extern "C" {
#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S)
#define SPI_SMEM_PMS2_ECC_V 0x00000001U
#define SPI_SMEM_PMS2_ECC_S 2
/** SPI_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3))
#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS2_NONSECURE_RD_ATTR_S)
#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_S 3
/** SPI_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4))
#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS2_NONSECURE_WR_ATTR_S)
#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_S 4
/** SPI_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section 2 is configured by registers
* SPI_SMEM_PMS2_ADDR_REG and SPI_SMEM_PMS2_SIZE_REG.
*/
#define SPI_SMEM_PMS2_NONSECURE_ECC (BIT(5))
#define SPI_SMEM_PMS2_NONSECURE_ECC_M (SPI_SMEM_PMS2_NONSECURE_ECC_V << SPI_SMEM_PMS2_NONSECURE_ECC_S)
#define SPI_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U
#define SPI_SMEM_PMS2_NONSECURE_ECC_S 5
/** SPI_SMEM_PMS3_ATTR_REG register
* SPI1 external RAM PMS section 3 attribute register
@@ -1617,6 +1778,29 @@ extern "C" {
#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S)
#define SPI_SMEM_PMS3_ECC_V 0x00000001U
#define SPI_SMEM_PMS3_ECC_S 2
/** SPI_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3))
#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS3_NONSECURE_RD_ATTR_S)
#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U
#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_S 3
/** SPI_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed.
*/
#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4))
#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS3_NONSECURE_WR_ATTR_S)
#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U
#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_S 4
/** SPI_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section 3 is configured by registers
* SPI_SMEM_PMS3_ADDR_REG and SPI_SMEM_PMS3_SIZE_REG.
*/
#define SPI_SMEM_PMS3_NONSECURE_ECC (BIT(5))
#define SPI_SMEM_PMS3_NONSECURE_ECC_M (SPI_SMEM_PMS3_NONSECURE_ECC_V << SPI_SMEM_PMS3_NONSECURE_ECC_S)
#define SPI_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U
#define SPI_SMEM_PMS3_NONSECURE_ECC_S 5
/** SPI_SMEM_PMS0_ADDR_REG register
* SPI1 external RAM PMS section 0 start address register
@@ -3566,7 +3750,7 @@ extern "C" {
* SPI0 version control register
*/
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512;
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 38813840;
* SPI0 register version.
*/
#define SPI_MEM_DATE 0x0FFFFFFFU

34
components/soc/esp32h4/register/soc/spi_mem_c_struct.h
View File

@@ -1174,7 +1174,21 @@ typedef union {
* SPI_FMEM_PMSn_SIZE_REG.
*/
uint32_t fmem_pmsn_ecc:1;
uint32_t reserved_3:29;
/** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1;
* 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_nonsecure_rd_attr:1;
/** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1;
* 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed.
*/
uint32_t fmem_pmsn_nonsecure_wr_attr:1;
/** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0;
* SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it.
* The flash PMS section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and
* SPI_FMEM_PMSn_SIZE_REG.
*/
uint32_t fmem_pmsn_nonsecure_ecc:1;
uint32_t reserved_6:26;
};
uint32_t val;
} spi_fmem_pmsn_attr_reg_t;
@@ -1227,7 +1241,21 @@ typedef union {
* SPI_SMEM_PMSn_SIZE_REG.
*/
uint32_t smem_pmsn_ecc:1;
uint32_t reserved_3:29;
/** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1;
* 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed.
*/
uint32_t smem_pmsn_nonsecure_rd_attr:1;
/** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1;
* 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed.
*/
uint32_t smem_pmsn_nonsecure_wr_attr:1;
/** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0;
* SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable
* it. The external RAM PMS section n is configured by registers
* SPI_SMEM_PMSn_ADDR_REG and SPI_SMEM_PMSn_SIZE_REG.
*/
uint32_t smem_pmsn_nonsecure_ecc:1;
uint32_t reserved_6:26;
};
uint32_t val;
} spi_smem_pmsn_attr_reg_t;
@@ -2679,7 +2707,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37822512;
/** date : R/W; bitpos: [27:0]; default: 38813840;
* SPI0 register version.
*/
uint32_t date:28;

137
components/soc/esp32h4/register/soc/touch_aon_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG register
* need_des
*/
#define TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG (DR_REG_TOUCH_BASE + 0x0)
#define TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG (DR_REG_TOUCH_AON_BASE + 0x0)
/** TOUCH_AON_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
* need_des
*/
@@ -40,7 +40,7 @@ extern "C" {
/** TOUCH_AON_SCAN_CTRL1_REG register
* need_des
*/
#define TOUCH_AON_SCAN_CTRL1_REG (DR_REG_TOUCH_BASE + 0x4)
#define TOUCH_AON_SCAN_CTRL1_REG (DR_REG_TOUCH_AON_BASE + 0x4)
/** TOUCH_AON_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
@@ -73,7 +73,14 @@ extern "C" {
/** TOUCH_AON_SCAN_CTRL2_REG register
* need_des
*/
#define TOUCH_AON_SCAN_CTRL2_REG (DR_REG_TOUCH_BASE + 0x8)
#define TOUCH_AON_SCAN_CTRL2_REG (DR_REG_TOUCH_AON_BASE + 0x8)
/** TOUCH_AON_FREQ_SCAN_CNT_RISE : R/W; bitpos: [1:0]; default: 1;
* need_des
*/
#define TOUCH_AON_FREQ_SCAN_CNT_RISE 0x00000003U
#define TOUCH_AON_FREQ_SCAN_CNT_RISE_M (TOUCH_AON_FREQ_SCAN_CNT_RISE_V << TOUCH_AON_FREQ_SCAN_CNT_RISE_S)
#define TOUCH_AON_FREQ_SCAN_CNT_RISE_V 0x00000003U
#define TOUCH_AON_FREQ_SCAN_CNT_RISE_S 0
/** TOUCH_AON_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535;
* need_des
*/
@@ -113,7 +120,7 @@ extern "C" {
/** TOUCH_AON_WORK_REG register
* need_des
*/
#define TOUCH_AON_WORK_REG (DR_REG_TOUCH_BASE + 0xc)
#define TOUCH_AON_WORK_REG (DR_REG_TOUCH_AON_BASE + 0xc)
/** TOUCH_AON_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0;
* need_des
*/
@@ -160,7 +167,7 @@ extern "C" {
/** TOUCH_AON_WORK_MEAS_NUM_REG register
* need_des
*/
#define TOUCH_AON_WORK_MEAS_NUM_REG (DR_REG_TOUCH_BASE + 0x10)
#define TOUCH_AON_WORK_MEAS_NUM_REG (DR_REG_TOUCH_AON_BASE + 0x10)
/** TOUCH_AON_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
* need_des
*/
@@ -186,7 +193,7 @@ extern "C" {
/** TOUCH_AON_FILTER1_REG register
* need_des
*/
#define TOUCH_AON_FILTER1_REG (DR_REG_TOUCH_BASE + 0x14)
#define TOUCH_AON_FILTER1_REG (DR_REG_TOUCH_AON_BASE + 0x14)
/** TOUCH_AON_TOUCH_NN_DISUPDATE_BENCHMARK_EN : R/W; bitpos: [0]; default: 0;
* Reserved
*/
@@ -268,7 +275,7 @@ extern "C" {
/** TOUCH_AON_FILTER2_REG register
* need_des
*/
#define TOUCH_AON_FILTER2_REG (DR_REG_TOUCH_BASE + 0x18)
#define TOUCH_AON_FILTER2_REG (DR_REG_TOUCH_AON_BASE + 0x18)
/** TOUCH_AON_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383;
* need_des
*/
@@ -294,7 +301,7 @@ extern "C" {
/** TOUCH_AON_FILTER3_REG register
* need_des
*/
#define TOUCH_AON_FILTER3_REG (DR_REG_TOUCH_BASE + 0x1c)
#define TOUCH_AON_FILTER3_REG (DR_REG_TOUCH_AON_BASE + 0x1c)
/** TOUCH_AON_TOUCH_BENCHMARK_SW : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
@@ -327,7 +334,7 @@ extern "C" {
/** TOUCH_AON_SLP0_REG register
* need_des
*/
#define TOUCH_AON_SLP0_REG (DR_REG_TOUCH_BASE + 0x20)
#define TOUCH_AON_SLP0_REG (DR_REG_TOUCH_AON_BASE + 0x20)
/** TOUCH_AON_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
@@ -353,7 +360,7 @@ extern "C" {
/** TOUCH_AON_SLP1_REG register
* need_des
*/
#define TOUCH_AON_SLP1_REG (DR_REG_TOUCH_BASE + 0x24)
#define TOUCH_AON_SLP1_REG (DR_REG_TOUCH_AON_BASE + 0x24)
/** TOUCH_AON_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
@@ -372,7 +379,7 @@ extern "C" {
/** TOUCH_AON_CLR_REG register
* need_des
*/
#define TOUCH_AON_CLR_REG (DR_REG_TOUCH_BASE + 0x28)
#define TOUCH_AON_CLR_REG (DR_REG_TOUCH_AON_BASE + 0x28)
/** TOUCH_AON_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0;
* need_des
*/
@@ -391,7 +398,7 @@ extern "C" {
/** TOUCH_AON_APPROACH_REG register
* need_des
*/
#define TOUCH_AON_APPROACH_REG (DR_REG_TOUCH_BASE + 0x2c)
#define TOUCH_AON_APPROACH_REG (DR_REG_TOUCH_AON_BASE + 0x2c)
/** TOUCH_AON_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15;
* need_des
*/
@@ -424,7 +431,7 @@ extern "C" {
/** TOUCH_AON_FREQ0_SCAN_PARA_REG register
* need_des
*/
#define TOUCH_AON_FREQ0_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x30)
#define TOUCH_AON_FREQ0_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x30)
/** TOUCH_AON_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
* need_des
*/
@@ -471,7 +478,7 @@ extern "C" {
/** TOUCH_AON_FREQ1_SCAN_PARA_REG register
* need_des
*/
#define TOUCH_AON_FREQ1_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x34)
#define TOUCH_AON_FREQ1_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x34)
/** TOUCH_AON_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
* need_des
*/
@@ -518,7 +525,7 @@ extern "C" {
/** TOUCH_AON_FREQ2_SCAN_PARA_REG register
* need_des
*/
#define TOUCH_AON_FREQ2_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x38)
#define TOUCH_AON_FREQ2_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x38)
/** TOUCH_AON_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
* need_des
*/
@@ -565,7 +572,7 @@ extern "C" {
/** TOUCH_AON_ANA_PARA_REG register
* need_des
*/
#define TOUCH_AON_ANA_PARA_REG (DR_REG_TOUCH_BASE + 0x3c)
#define TOUCH_AON_ANA_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x3c)
/** TOUCH_AON_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0;
* need_des
*/
@@ -591,7 +598,7 @@ extern "C" {
/** TOUCH_AON_MUX0_REG register
* need_des
*/
#define TOUCH_AON_MUX0_REG (DR_REG_TOUCH_BASE + 0x40)
#define TOUCH_AON_MUX0_REG (DR_REG_TOUCH_AON_BASE + 0x40)
/** TOUCH_AON_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0;
* need_des
*/
@@ -652,7 +659,7 @@ extern "C" {
/** TOUCH_AON_MUX1_REG register
* need_des
*/
#define TOUCH_AON_MUX1_REG (DR_REG_TOUCH_BASE + 0x44)
#define TOUCH_AON_MUX1_REG (DR_REG_TOUCH_AON_BASE + 0x44)
/** TOUCH_AON_TOUCH_START : R/W; bitpos: [14:0]; default: 0;
* need_des
*/
@@ -671,7 +678,7 @@ extern "C" {
/** TOUCH_AON_PAD0_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD0_TH0_REG (DR_REG_TOUCH_BASE + 0x48)
#define TOUCH_AON_PAD0_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x48)
/** TOUCH_AON_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -683,7 +690,7 @@ extern "C" {
/** TOUCH_AON_PAD0_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD0_TH1_REG (DR_REG_TOUCH_BASE + 0x4c)
#define TOUCH_AON_PAD0_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x4c)
/** TOUCH_AON_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -695,7 +702,7 @@ extern "C" {
/** TOUCH_AON_PAD0_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD0_TH2_REG (DR_REG_TOUCH_BASE + 0x50)
#define TOUCH_AON_PAD0_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x50)
/** TOUCH_AON_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -707,7 +714,7 @@ extern "C" {
/** TOUCH_AON_PAD1_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD1_TH0_REG (DR_REG_TOUCH_BASE + 0x54)
#define TOUCH_AON_PAD1_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x54)
/** TOUCH_AON_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -719,7 +726,7 @@ extern "C" {
/** TOUCH_AON_PAD1_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD1_TH1_REG (DR_REG_TOUCH_BASE + 0x58)
#define TOUCH_AON_PAD1_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x58)
/** TOUCH_AON_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -731,7 +738,7 @@ extern "C" {
/** TOUCH_AON_PAD1_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD1_TH2_REG (DR_REG_TOUCH_BASE + 0x5c)
#define TOUCH_AON_PAD1_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x5c)
/** TOUCH_AON_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -743,7 +750,7 @@ extern "C" {
/** TOUCH_AON_PAD2_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD2_TH0_REG (DR_REG_TOUCH_BASE + 0x60)
#define TOUCH_AON_PAD2_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x60)
/** TOUCH_AON_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -755,7 +762,7 @@ extern "C" {
/** TOUCH_AON_PAD2_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD2_TH1_REG (DR_REG_TOUCH_BASE + 0x64)
#define TOUCH_AON_PAD2_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x64)
/** TOUCH_AON_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -767,7 +774,7 @@ extern "C" {
/** TOUCH_AON_PAD2_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD2_TH2_REG (DR_REG_TOUCH_BASE + 0x68)
#define TOUCH_AON_PAD2_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x68)
/** TOUCH_AON_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -779,7 +786,7 @@ extern "C" {
/** TOUCH_AON_PAD3_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD3_TH0_REG (DR_REG_TOUCH_BASE + 0x6c)
#define TOUCH_AON_PAD3_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x6c)
/** TOUCH_AON_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -791,7 +798,7 @@ extern "C" {
/** TOUCH_AON_PAD3_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD3_TH1_REG (DR_REG_TOUCH_BASE + 0x70)
#define TOUCH_AON_PAD3_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x70)
/** TOUCH_AON_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -803,7 +810,7 @@ extern "C" {
/** TOUCH_AON_PAD3_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD3_TH2_REG (DR_REG_TOUCH_BASE + 0x74)
#define TOUCH_AON_PAD3_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x74)
/** TOUCH_AON_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -815,7 +822,7 @@ extern "C" {
/** TOUCH_AON_PAD4_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD4_TH0_REG (DR_REG_TOUCH_BASE + 0x78)
#define TOUCH_AON_PAD4_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x78)
/** TOUCH_AON_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -827,7 +834,7 @@ extern "C" {
/** TOUCH_AON_PAD4_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD4_TH1_REG (DR_REG_TOUCH_BASE + 0x7c)
#define TOUCH_AON_PAD4_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x7c)
/** TOUCH_AON_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -839,7 +846,7 @@ extern "C" {
/** TOUCH_AON_PAD4_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD4_TH2_REG (DR_REG_TOUCH_BASE + 0x80)
#define TOUCH_AON_PAD4_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x80)
/** TOUCH_AON_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -851,7 +858,7 @@ extern "C" {
/** TOUCH_AON_PAD5_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD5_TH0_REG (DR_REG_TOUCH_BASE + 0x84)
#define TOUCH_AON_PAD5_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x84)
/** TOUCH_AON_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -863,7 +870,7 @@ extern "C" {
/** TOUCH_AON_PAD5_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD5_TH1_REG (DR_REG_TOUCH_BASE + 0x88)
#define TOUCH_AON_PAD5_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x88)
/** TOUCH_AON_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -875,7 +882,7 @@ extern "C" {
/** TOUCH_AON_PAD5_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD5_TH2_REG (DR_REG_TOUCH_BASE + 0x8c)
#define TOUCH_AON_PAD5_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x8c)
/** TOUCH_AON_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -887,7 +894,7 @@ extern "C" {
/** TOUCH_AON_PAD6_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD6_TH0_REG (DR_REG_TOUCH_BASE + 0x90)
#define TOUCH_AON_PAD6_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x90)
/** TOUCH_AON_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -899,7 +906,7 @@ extern "C" {
/** TOUCH_AON_PAD6_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD6_TH1_REG (DR_REG_TOUCH_BASE + 0x94)
#define TOUCH_AON_PAD6_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x94)
/** TOUCH_AON_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -911,7 +918,7 @@ extern "C" {
/** TOUCH_AON_PAD6_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD6_TH2_REG (DR_REG_TOUCH_BASE + 0x98)
#define TOUCH_AON_PAD6_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x98)
/** TOUCH_AON_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -923,7 +930,7 @@ extern "C" {
/** TOUCH_AON_PAD7_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD7_TH0_REG (DR_REG_TOUCH_BASE + 0x9c)
#define TOUCH_AON_PAD7_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x9c)
/** TOUCH_AON_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -935,7 +942,7 @@ extern "C" {
/** TOUCH_AON_PAD7_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD7_TH1_REG (DR_REG_TOUCH_BASE + 0xa0)
#define TOUCH_AON_PAD7_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xa0)
/** TOUCH_AON_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -947,7 +954,7 @@ extern "C" {
/** TOUCH_AON_PAD7_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD7_TH2_REG (DR_REG_TOUCH_BASE + 0xa4)
#define TOUCH_AON_PAD7_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xa4)
/** TOUCH_AON_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -959,7 +966,7 @@ extern "C" {
/** TOUCH_AON_PAD8_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD8_TH0_REG (DR_REG_TOUCH_BASE + 0xa8)
#define TOUCH_AON_PAD8_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xa8)
/** TOUCH_AON_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -971,7 +978,7 @@ extern "C" {
/** TOUCH_AON_PAD8_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD8_TH1_REG (DR_REG_TOUCH_BASE + 0xac)
#define TOUCH_AON_PAD8_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xac)
/** TOUCH_AON_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -983,7 +990,7 @@ extern "C" {
/** TOUCH_AON_PAD8_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD8_TH2_REG (DR_REG_TOUCH_BASE + 0xb0)
#define TOUCH_AON_PAD8_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xb0)
/** TOUCH_AON_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -995,7 +1002,7 @@ extern "C" {
/** TOUCH_AON_PAD9_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD9_TH0_REG (DR_REG_TOUCH_BASE + 0xb4)
#define TOUCH_AON_PAD9_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xb4)
/** TOUCH_AON_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1007,7 +1014,7 @@ extern "C" {
/** TOUCH_AON_PAD9_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD9_TH1_REG (DR_REG_TOUCH_BASE + 0xb8)
#define TOUCH_AON_PAD9_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xb8)
/** TOUCH_AON_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1019,7 +1026,7 @@ extern "C" {
/** TOUCH_AON_PAD9_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD9_TH2_REG (DR_REG_TOUCH_BASE + 0xbc)
#define TOUCH_AON_PAD9_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xbc)
/** TOUCH_AON_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1031,7 +1038,7 @@ extern "C" {
/** TOUCH_AON_PAD10_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD10_TH0_REG (DR_REG_TOUCH_BASE + 0xc0)
#define TOUCH_AON_PAD10_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xc0)
/** TOUCH_AON_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1043,7 +1050,7 @@ extern "C" {
/** TOUCH_AON_PAD10_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD10_TH1_REG (DR_REG_TOUCH_BASE + 0xc4)
#define TOUCH_AON_PAD10_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xc4)
/** TOUCH_AON_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1055,7 +1062,7 @@ extern "C" {
/** TOUCH_AON_PAD10_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD10_TH2_REG (DR_REG_TOUCH_BASE + 0xc8)
#define TOUCH_AON_PAD10_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xc8)
/** TOUCH_AON_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1067,7 +1074,7 @@ extern "C" {
/** TOUCH_AON_PAD11_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD11_TH0_REG (DR_REG_TOUCH_BASE + 0xcc)
#define TOUCH_AON_PAD11_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xcc)
/** TOUCH_AON_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1079,7 +1086,7 @@ extern "C" {
/** TOUCH_AON_PAD11_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD11_TH1_REG (DR_REG_TOUCH_BASE + 0xd0)
#define TOUCH_AON_PAD11_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xd0)
/** TOUCH_AON_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1091,7 +1098,7 @@ extern "C" {
/** TOUCH_AON_PAD11_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD11_TH2_REG (DR_REG_TOUCH_BASE + 0xd4)
#define TOUCH_AON_PAD11_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xd4)
/** TOUCH_AON_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1103,7 +1110,7 @@ extern "C" {
/** TOUCH_AON_PAD12_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD12_TH0_REG (DR_REG_TOUCH_BASE + 0xd8)
#define TOUCH_AON_PAD12_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xd8)
/** TOUCH_AON_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1115,7 +1122,7 @@ extern "C" {
/** TOUCH_AON_PAD12_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD12_TH1_REG (DR_REG_TOUCH_BASE + 0xdc)
#define TOUCH_AON_PAD12_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xdc)
/** TOUCH_AON_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1127,7 +1134,7 @@ extern "C" {
/** TOUCH_AON_PAD12_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD12_TH2_REG (DR_REG_TOUCH_BASE + 0xe0)
#define TOUCH_AON_PAD12_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xe0)
/** TOUCH_AON_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1139,7 +1146,7 @@ extern "C" {
/** TOUCH_AON_PAD13_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD13_TH0_REG (DR_REG_TOUCH_BASE + 0xe4)
#define TOUCH_AON_PAD13_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xe4)
/** TOUCH_AON_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1151,7 +1158,7 @@ extern "C" {
/** TOUCH_AON_PAD13_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD13_TH1_REG (DR_REG_TOUCH_BASE + 0xe8)
#define TOUCH_AON_PAD13_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xe8)
/** TOUCH_AON_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1163,7 +1170,7 @@ extern "C" {
/** TOUCH_AON_PAD13_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD13_TH2_REG (DR_REG_TOUCH_BASE + 0xec)
#define TOUCH_AON_PAD13_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xec)
/** TOUCH_AON_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1175,7 +1182,7 @@ extern "C" {
/** TOUCH_AON_PAD14_TH0_REG register
* need_des
*/
#define TOUCH_AON_PAD14_TH0_REG (DR_REG_TOUCH_BASE + 0xf0)
#define TOUCH_AON_PAD14_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xf0)
/** TOUCH_AON_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1187,7 +1194,7 @@ extern "C" {
/** TOUCH_AON_PAD14_TH1_REG register
* need_des
*/
#define TOUCH_AON_PAD14_TH1_REG (DR_REG_TOUCH_BASE + 0xf4)
#define TOUCH_AON_PAD14_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xf4)
/** TOUCH_AON_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1199,7 +1206,7 @@ extern "C" {
/** TOUCH_AON_PAD14_TH2_REG register
* need_des
*/
#define TOUCH_AON_PAD14_TH2_REG (DR_REG_TOUCH_BASE + 0xf8)
#define TOUCH_AON_PAD14_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xf8)
/** TOUCH_AON_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0;
* Reserved
*/
@@ -1211,8 +1218,8 @@ extern "C" {
/** TOUCH_AON_DATE_REG register
* need_des
*/
#define TOUCH_AON_DATE_REG (DR_REG_TOUCH_BASE + 0xfc)
/** TOUCH_AON_DATE : R/W; bitpos: [30:0]; default: 2360864;
#define TOUCH_AON_DATE_REG (DR_REG_TOUCH_AON_BASE + 0xfc)
/** TOUCH_AON_DATE : R/W; bitpos: [30:0]; default: 38813808;
* need_des
*/
#define TOUCH_AON_DATE 0x7FFFFFFFU

8
components/soc/esp32h4/register/soc/touch_aon_struct.h
View File

@@ -63,7 +63,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** freq_scan_cnt_rise : R/W; bitpos: [1:0]; default: 1;
* need_des
*/
uint32_t freq_scan_cnt_rise:2;
uint32_t reserved_2:4;
/** aon_touch_timeout_num : R/W; bitpos: [21:6]; default: 65535;
* need_des
*/
@@ -1149,7 +1153,7 @@ typedef union {
*/
typedef union {
struct {
/** aon_date : R/W; bitpos: [30:0]; default: 2360864;
/** date : R/W; bitpos: [30:0]; default: 38813808;
* need_des
*/
uint32_t aon_date:31;

28
components/soc/esp32h4/register/soc/touch_reg.h
View File

@@ -57,6 +57,13 @@ extern "C" {
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5
/** TOUCH_BASELINE_UPDATE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* need_des
*/
#define TOUCH_BASELINE_UPDATE_INT_RAW (BIT(6))
#define TOUCH_BASELINE_UPDATE_INT_RAW_M (TOUCH_BASELINE_UPDATE_INT_RAW_V << TOUCH_BASELINE_UPDATE_INT_RAW_S)
#define TOUCH_BASELINE_UPDATE_INT_RAW_V 0x00000001U
#define TOUCH_BASELINE_UPDATE_INT_RAW_S 6
/** TOUCH_INT_ST_REG register
* need_des
@@ -104,6 +111,13 @@ extern "C" {
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_M (TOUCH_APPROACH_LOOP_DONE_INT_ST_V << TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5
/** TOUCH_BASELINE_UPDATE_INT_ST : RO; bitpos: [6]; default: 0;
* need_des
*/
#define TOUCH_BASELINE_UPDATE_INT_ST (BIT(6))
#define TOUCH_BASELINE_UPDATE_INT_ST_M (TOUCH_BASELINE_UPDATE_INT_ST_V << TOUCH_BASELINE_UPDATE_INT_ST_S)
#define TOUCH_BASELINE_UPDATE_INT_ST_V 0x00000001U
#define TOUCH_BASELINE_UPDATE_INT_ST_S 6
/** TOUCH_INT_ENA_REG register
* need_des
@@ -151,6 +165,13 @@ extern "C" {
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5
/** TOUCH_BASELINE_UPDATE_INT_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define TOUCH_BASELINE_UPDATE_INT_ENA (BIT(6))
#define TOUCH_BASELINE_UPDATE_INT_ENA_M (TOUCH_BASELINE_UPDATE_INT_ENA_V << TOUCH_BASELINE_UPDATE_INT_ENA_S)
#define TOUCH_BASELINE_UPDATE_INT_ENA_V 0x00000001U
#define TOUCH_BASELINE_UPDATE_INT_ENA_S 6
/** TOUCH_INT_CLR_REG register
* need_des
@@ -198,6 +219,13 @@ extern "C" {
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U
#define TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5
/** TOUCH_BASELINE_UPDATE_INT_CLR : WT; bitpos: [6]; default: 0;
* need_des
*/
#define TOUCH_BASELINE_UPDATE_INT_CLR (BIT(6))
#define TOUCH_BASELINE_UPDATE_INT_CLR_M (TOUCH_BASELINE_UPDATE_INT_CLR_V << TOUCH_BASELINE_UPDATE_INT_CLR_S)
#define TOUCH_BASELINE_UPDATE_INT_CLR_V 0x00000001U
#define TOUCH_BASELINE_UPDATE_INT_CLR_S 6
/** TOUCH_CHN_STATUS_REG register
* need_des

24
components/soc/esp32h4/register/soc/touch_struct.h
View File

@@ -40,7 +40,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_raw:1;
uint32_t reserved_6:26;
/** baseline_update_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* need_des
*/
uint32_t baseline_update_int_raw:1;
uint32_t reserved_7:25;
};
uint32_t val;
} touch_int_raw_reg_t;
@@ -74,7 +78,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_st:1;
uint32_t reserved_6:26;
/** baseline_update_int_st : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t baseline_update_int_st:1;
uint32_t reserved_7:25;
};
uint32_t val;
} touch_int_st_reg_t;
@@ -108,7 +116,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_ena:1;
uint32_t reserved_6:26;
/** baseline_update_int_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t baseline_update_int_ena:1;
uint32_t reserved_7:25;
};
uint32_t val;
} touch_int_ena_reg_t;
@@ -142,7 +154,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_clr:1;
uint32_t reserved_6:26;
/** baseline_update_int_clr : WT; bitpos: [6]; default: 0;
* need_des
*/
uint32_t baseline_update_int_clr:1;
uint32_t reserved_7:25;
};
uint32_t val;
} touch_int_clr_reg_t;