diff --git a/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c b/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c index 282c798adb..e488c1d2b2 100644 --- a/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c +++ b/components/esp_driver_twai/test_apps/twaifd_test/main/test_twaifd.c @@ -121,7 +121,7 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]") twai_onchip_node_config_t node_config = { .io_cfg.tx = TEST_TX_GPIO, .io_cfg.rx = TEST_TX_GPIO, // Using same pin for test without transceiver - .bit_timing.bitrate = 1000000, + .bit_timing.bitrate = 20000, .data_timing.bitrate = 4000000, .data_timing.ssp_permill = 700, // ssp 70.0% .tx_queue_depth = TEST_TWAI_QUEUE_DEPTH, @@ -130,14 +130,14 @@ TEST_CASE("twai transmit stop resume (loopback)", "[TWAI]") }; TEST_ESP_OK(twai_new_node_onchip(&node_config, &node_hdl)); - // reconfig fd timing to 48M/(12+5+6+1)=2MHz, ssp=20/(12+5+6+1)=83% + // reconfig fd timing to 80M/(4+3+2+1)=8MHz, ssp=8/(4+3+2+1)=80% twai_timing_advanced_config_t timing_fd = { .brp = 1, - .prop_seg = 12, - .tseg_1 = 5, - .tseg_2 = 6, - .sjw = 3, - .ssp_offset = 20, + .prop_seg = 4, + .tseg_1 = 3, + .tseg_2 = 2, + .sjw = 2, + .ssp_offset = 8, }; TEST_ESP_OK(twai_node_reconfig_timing(node_hdl, NULL, &timing_fd)); diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index 30f0ac56f6..6db46ddcca 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -698,13 +698,14 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) *----------------------------------------------------------------------------*/ /** * Set the standard clock mode for master. + * This config take effect only when SPI_CLK (pre-div before periph) div >=2 * * @param hw Beginning address of the peripheral registers. * @param enable_std True for std timing, False for half cycle delay sampling. */ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point) { - //This is not supported + hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1); } /** @@ -712,7 +713,7 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_ */ static inline bool spi_ll_master_is_rx_std_sample_supported(void) { - return false; + return true; } /** diff --git a/components/hal/esp32c5/include/hal/twaifd_ll.h b/components/hal/esp32c5/include/hal/twaifd_ll.h index e742e9634b..6fbd9bc0fc 100644 --- a/components/hal/esp32c5/include/hal/twaifd_ll.h +++ b/components/hal/esp32c5/include/hal/twaifd_ll.h @@ -92,7 +92,7 @@ static inline void twaifd_ll_reset_register(uint8_t twai_id) */ static inline void twaifd_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t clk_src) { - PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_RC_FAST) ? 1 : 0; + PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_XTAL) ? 0 : 1; } /** diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 902fae9407..04341d8d63 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -422,15 +422,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of TWAI */ -#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M} /** * @brief TWAI clock source */ typedef enum { TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TWAI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ + TWAI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as the default clock choice */ } soc_periph_twai_clk_src_t; //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 0d99d51a1e..b69113df54 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -21,7 +21,6 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 #define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5 #define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5 #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 diff --git a/components/soc/esp32c5/register/soc/pcr_reg.h b/components/soc/esp32c5/register/soc/pcr_reg.h index e9e7316b2a..e535f0e79c 100644 --- a/components/soc/esp32c5/register/soc/pcr_reg.h +++ b/components/soc/esp32c5/register/soc/pcr_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,7 @@ extern "C" { #define PCR_UART0_CLK_EN_V 0x00000001U #define PCR_UART0_CLK_EN_S 0 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ #define PCR_UART0_RST_EN (BIT(1)) #define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) @@ -63,10 +63,10 @@ extern "C" { #define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART0_SCLK_DIV_NUM_S 12 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART0_SCLK_SEL 0x00000003U #define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) @@ -111,7 +111,7 @@ extern "C" { #define PCR_UART1_CLK_EN_V 0x00000001U #define PCR_UART1_CLK_EN_S 0 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ #define PCR_UART1_RST_EN (BIT(1)) #define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) @@ -151,10 +151,10 @@ extern "C" { #define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART1_SCLK_DIV_NUM_S 12 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART1_SCLK_SEL 0x00000003U #define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) @@ -199,7 +199,7 @@ extern "C" { #define PCR_MSPI_CLK_EN_V 0x00000001U #define PCR_MSPI_CLK_EN_S 0 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ #define PCR_MSPI_RST_EN (BIT(1)) #define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) @@ -226,7 +226,7 @@ extern "C" { #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only available when the clock-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ #define PCR_MSPI_FAST_DIV_NUM 0x000000FFU @@ -234,10 +234,10 @@ extern "C" { #define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU #define PCR_MSPI_FAST_DIV_NUM_S 0 /** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_MSPI_FUNC_CLK_SEL 0x00000003U #define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) @@ -251,7 +251,7 @@ extern "C" { #define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U #define PCR_MSPI_FUNC_CLK_EN_S 10 /** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ #define PCR_MSPI_AXI_RST_EN (BIT(11)) #define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) @@ -270,7 +270,7 @@ extern "C" { #define PCR_I2C_CLK_EN_V 0x00000001U #define PCR_I2C_CLK_EN_S 0 /** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ #define PCR_I2C_RST_EN (BIT(1)) #define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) @@ -303,9 +303,9 @@ extern "C" { #define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU #define PCR_I2C_SCLK_DIV_NUM_S 12 /** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_I2C_SCLK_SEL (BIT(20)) #define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) @@ -331,7 +331,7 @@ extern "C" { #define PCR_TWAI0_CLK_EN_V 0x00000001U #define PCR_TWAI0_CLK_EN_S 0 /** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai0 module + * Set 1 to reset twai0 module */ #define PCR_TWAI0_RST_EN (BIT(1)) #define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) @@ -350,9 +350,9 @@ extern "C" { */ #define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) /** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI0. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ #define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) #define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) @@ -378,7 +378,7 @@ extern "C" { #define PCR_TWAI1_CLK_EN_V 0x00000001U #define PCR_TWAI1_CLK_EN_S 0 /** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai1 module + * Set 1 to reset twai1 module */ #define PCR_TWAI1_RST_EN (BIT(1)) #define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) @@ -397,9 +397,9 @@ extern "C" { */ #define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34) /** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI1. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ #define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) #define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) @@ -425,7 +425,7 @@ extern "C" { #define PCR_UHCI_CLK_EN_V 0x00000001U #define PCR_UHCI_CLK_EN_S 0 /** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module + * Set 1 to reset uhci module */ #define PCR_UHCI_RST_EN (BIT(1)) #define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) @@ -451,7 +451,7 @@ extern "C" { #define PCR_RMT_CLK_EN_V 0x00000001U #define PCR_RMT_CLK_EN_S 0 /** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module + * Set 1 to reset rmt module */ #define PCR_RMT_RST_EN (BIT(1)) #define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) @@ -484,10 +484,10 @@ extern "C" { #define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU #define PCR_RMT_SCLK_DIV_NUM_S 12 /** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; - * Configures the clock source of RMT.\\ - * 0: XTAL_CLK\\ - * 1 (default): RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_RMT_SCLK_SEL 0x00000003U #define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) @@ -532,7 +532,7 @@ extern "C" { #define PCR_LEDC_CLK_EN_V 0x00000001U #define PCR_LEDC_CLK_EN_S 0 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ #define PCR_LEDC_RST_EN (BIT(1)) #define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) @@ -551,10 +551,10 @@ extern "C" { */ #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) @@ -599,7 +599,7 @@ extern "C" { #define PCR_TG0_CLK_EN_V 0x00000001U #define PCR_TG0_CLK_EN_S 0 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ #define PCR_TG0_RST_EN (BIT(1)) #define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) @@ -632,10 +632,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_TIMER_CLK_SEL 0x00000003U #define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) @@ -654,10 +654,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_WDT_CLK_SEL 0x00000003U #define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) @@ -683,7 +683,7 @@ extern "C" { #define PCR_TG1_CLK_EN_V 0x00000001U #define PCR_TG1_CLK_EN_S 0 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ #define PCR_TG1_RST_EN (BIT(1)) #define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) @@ -716,10 +716,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x64) /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_TIMER_CLK_SEL 0x00000003U #define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) @@ -738,10 +738,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_WDT_CLK_SEL 0x00000003U #define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) @@ -767,7 +767,7 @@ extern "C" { #define PCR_SYSTIMER_CLK_EN_V 0x00000001U #define PCR_SYSTIMER_CLK_EN_S 0 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ #define PCR_SYSTIMER_RST_EN (BIT(1)) #define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) @@ -786,9 +786,9 @@ extern "C" { */ #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x70) /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) #define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) @@ -814,7 +814,7 @@ extern "C" { #define PCR_I2S_CLK_EN_V 0x00000001U #define PCR_I2S_CLK_EN_S 0 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ #define PCR_I2S_RST_EN (BIT(1)) #define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) @@ -850,11 +850,11 @@ extern "C" { #define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_TX_CLKM_DIV_NUM_S 12 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_TX_CLKM_SEL 0x00000003U #define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) @@ -917,11 +917,11 @@ extern "C" { #define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_RX_CLKM_DIV_NUM_S 12 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_RX_CLKM_SEL 0x00000003U #define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) @@ -935,9 +935,9 @@ extern "C" { #define PCR_I2S_RX_CLKM_EN_V 0x00000001U #define PCR_I2S_RX_CLKM_EN_S 22 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ #define PCR_I2S_MCLK_SEL (BIT(23)) #define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) @@ -993,7 +993,7 @@ extern "C" { #define PCR_SARADC_CLK_EN_V 0x00000001U #define PCR_SARADC_CLK_EN_S 0 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ #define PCR_SARADC_RST_EN (BIT(1)) #define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) @@ -1007,7 +1007,7 @@ extern "C" { #define PCR_SARADC_REG_CLK_EN_V 0x00000001U #define PCR_SARADC_REG_CLK_EN_S 2 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ #define PCR_SARADC_REG_RST_EN (BIT(3)) #define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) @@ -1040,10 +1040,10 @@ extern "C" { #define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SARADC_CLKM_DIV_NUM_S 12 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_SARADC_CLKM_SEL 0x00000003U #define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) @@ -1062,9 +1062,9 @@ extern "C" { */ #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x90) /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_TSENS_CLK_SEL (BIT(20)) #define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) @@ -1078,7 +1078,7 @@ extern "C" { #define PCR_TSENS_CLK_EN_V 0x00000001U #define PCR_TSENS_CLK_EN_S 22 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ #define PCR_TSENS_RST_EN (BIT(23)) #define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) @@ -1097,7 +1097,7 @@ extern "C" { #define PCR_USB_DEVICE_CLK_EN_V 0x00000001U #define PCR_USB_DEVICE_CLK_EN_S 0 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ #define PCR_USB_DEVICE_RST_EN (BIT(1)) #define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) @@ -1123,7 +1123,7 @@ extern "C" { #define PCR_INTMTX_CLK_EN_V 0x00000001U #define PCR_INTMTX_CLK_EN_S 0 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ #define PCR_INTMTX_RST_EN (BIT(1)) #define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) @@ -1149,7 +1149,7 @@ extern "C" { #define PCR_PCNT_CLK_EN_V 0x00000001U #define PCR_PCNT_CLK_EN_S 0 /** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module + * Set 1 to reset pcnt module */ #define PCR_PCNT_RST_EN (BIT(1)) #define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) @@ -1175,7 +1175,7 @@ extern "C" { #define PCR_ETM_CLK_EN_V 0x00000001U #define PCR_ETM_CLK_EN_S 0 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ #define PCR_ETM_RST_EN (BIT(1)) #define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) @@ -1201,7 +1201,7 @@ extern "C" { #define PCR_PWM_CLK_EN_V 0x00000001U #define PCR_PWM_CLK_EN_S 0 /** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module + * Set 1 to reset pwm module */ #define PCR_PWM_RST_EN (BIT(1)) #define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) @@ -1227,10 +1227,10 @@ extern "C" { #define PCR_PWM_DIV_NUM_V 0x000000FFU #define PCR_PWM_DIV_NUM_S 12 /** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of MCPWM.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures the clock source of MCPWM. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ #define PCR_PWM_CLKM_SEL 0x00000003U #define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) @@ -1256,7 +1256,7 @@ extern "C" { #define PCR_PARL_CLK_EN_V 0x00000001U #define PCR_PARL_CLK_EN_S 0 /** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg + * Set 1 to reset parl apb reg */ #define PCR_PARL_RST_EN (BIT(1)) #define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) @@ -1282,11 +1282,11 @@ extern "C" { #define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU #define PCR_PARL_CLK_RX_DIV_NUM_S 0 /** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ #define PCR_PARL_CLK_RX_SEL 0x00000003U #define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) @@ -1300,7 +1300,7 @@ extern "C" { #define PCR_PARL_CLK_RX_EN_V 0x00000001U #define PCR_PARL_CLK_RX_EN_S 18 /** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module + * Set 1 to reset parl rx module */ #define PCR_PARL_RX_RST_EN (BIT(19)) #define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) @@ -1319,11 +1319,11 @@ extern "C" { #define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU #define PCR_PARL_CLK_TX_DIV_NUM_S 0 /** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ #define PCR_PARL_CLK_TX_SEL 0x00000003U #define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) @@ -1337,7 +1337,7 @@ extern "C" { #define PCR_PARL_CLK_TX_EN_V 0x00000001U #define PCR_PARL_CLK_TX_EN_S 18 /** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module + * Set 1 to reset parl tx module */ #define PCR_PARL_TX_RST_EN (BIT(19)) #define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) @@ -1356,7 +1356,7 @@ extern "C" { #define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U #define PCR_PVT_MONITOR_CLK_EN_S 0 /** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module + * Set 1 to reset all pvt monitor module */ #define PCR_PVT_MONITOR_RST_EN (BIT(1)) #define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) @@ -1396,9 +1396,9 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) @@ -1424,7 +1424,7 @@ extern "C" { #define PCR_GDMA_CLK_EN_V 0x00000001U #define PCR_GDMA_CLK_EN_S 0 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ #define PCR_GDMA_RST_EN (BIT(1)) #define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) @@ -1443,7 +1443,7 @@ extern "C" { #define PCR_SPI2_CLK_EN_V 0x00000001U #define PCR_SPI2_CLK_EN_S 0 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ #define PCR_SPI2_RST_EN (BIT(1)) #define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) @@ -1469,11 +1469,11 @@ extern "C" { #define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SPI2_CLKM_DIV_NUM_S 12 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ - * 3: PLL_F120M_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + * 3: PLL_F120M_CLK */ #define PCR_SPI2_CLKM_SEL 0x00000003U #define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) @@ -1499,7 +1499,7 @@ extern "C" { #define PCR_AES_CLK_EN_V 0x00000001U #define PCR_AES_CLK_EN_S 0 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ #define PCR_AES_RST_EN (BIT(1)) #define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) @@ -1525,7 +1525,7 @@ extern "C" { #define PCR_SHA_CLK_EN_V 0x00000001U #define PCR_SHA_CLK_EN_S 0 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ #define PCR_SHA_RST_EN (BIT(1)) #define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) @@ -1551,7 +1551,7 @@ extern "C" { #define PCR_RSA_CLK_EN_V 0x00000001U #define PCR_RSA_CLK_EN_S 0 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ #define PCR_RSA_RST_EN (BIT(1)) #define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) @@ -1603,7 +1603,7 @@ extern "C" { #define PCR_ECC_CLK_EN_V 0x00000001U #define PCR_ECC_CLK_EN_S 0 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ #define PCR_ECC_RST_EN (BIT(1)) #define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) @@ -1655,7 +1655,7 @@ extern "C" { #define PCR_DS_CLK_EN_V 0x00000001U #define PCR_DS_CLK_EN_S 0 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ #define PCR_DS_RST_EN (BIT(1)) #define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) @@ -1681,7 +1681,7 @@ extern "C" { #define PCR_HMAC_CLK_EN_V 0x00000001U #define PCR_HMAC_CLK_EN_S 0 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ #define PCR_HMAC_RST_EN (BIT(1)) #define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) @@ -1707,7 +1707,7 @@ extern "C" { #define PCR_ECDSA_CLK_EN_V 0x00000001U #define PCR_ECDSA_CLK_EN_S 0 /** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ #define PCR_ECDSA_RST_EN (BIT(1)) #define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) @@ -1733,7 +1733,7 @@ extern "C" { #define PCR_IOMUX_CLK_EN_V 0x00000001U #define PCR_IOMUX_CLK_EN_S 0 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ #define PCR_IOMUX_RST_EN (BIT(1)) #define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) @@ -1745,10 +1745,10 @@ extern "C" { */ #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xf4) /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U #define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) @@ -1774,7 +1774,7 @@ extern "C" { #define PCR_REGDMA_CLK_EN_V 0x00000001U #define PCR_REGDMA_CLK_EN_S 0 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ #define PCR_REGDMA_RST_EN (BIT(1)) #define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) @@ -1793,7 +1793,7 @@ extern "C" { #define PCR_TRACE_CLK_EN_V 0x00000001U #define PCR_TRACE_CLK_EN_S 0 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ #define PCR_TRACE_RST_EN (BIT(1)) #define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) @@ -1812,7 +1812,7 @@ extern "C" { #define PCR_ASSIST_CLK_EN_V 0x00000001U #define PCR_ASSIST_CLK_EN_S 0 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ #define PCR_ASSIST_RST_EN (BIT(1)) #define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) @@ -1831,7 +1831,7 @@ extern "C" { #define PCR_CACHE_CLK_EN_V 0x00000001U #define PCR_CACHE_CLK_EN_S 0 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ #define PCR_CACHE_RST_EN (BIT(1)) #define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) @@ -1884,14 +1884,14 @@ extern "C" { */ #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ #define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) #define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) #define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U #define PCR_CPU_TIMEOUT_RST_EN_S 1 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ #define PCR_HP_TIMEOUT_RST_EN (BIT(2)) #define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) @@ -1902,12 +1902,27 @@ extern "C" { * SYSCLK configuration register */ #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ - * 2: PLL_F240M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK */ #define PCR_SOC_CLK_SEL 0x00000003U #define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) @@ -1933,20 +1948,6 @@ extern "C" { * CPU_WAITI configuration register */ #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) -/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_CPUPERIOD_SEL 0x00000003U -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003U -#define PCR_CPUPERIOD_SEL_S 0 -/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001U -#define PCR_PLL_FREQ_SEL_S 2 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1968,7 +1969,7 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1982,7 +1983,7 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -2010,7 +2011,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -2042,7 +2043,7 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close, + * This field is used to open 240 MHz clock (div2 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_240M_CLK_EN (BIT(0)) @@ -2050,7 +2051,7 @@ extern "C" { #define PCR_PLL_240M_CLK_EN_V 0x00000001U #define PCR_PLL_240M_CLK_EN_S 0 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) @@ -2058,7 +2059,7 @@ extern "C" { #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) @@ -2066,7 +2067,7 @@ extern "C" { #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) @@ -2074,7 +2075,7 @@ extern "C" { #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_60M_CLK_EN (BIT(4)) @@ -2082,7 +2083,7 @@ extern "C" { #define PCR_PLL_60M_CLK_EN_V 0x00000001U #define PCR_PLL_60M_CLK_EN_S 4 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(5)) @@ -2090,7 +2091,7 @@ extern "C" { #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 5 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(6)) @@ -2098,7 +2099,7 @@ extern "C" { #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 6 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(7)) @@ -2106,7 +2107,7 @@ extern "C" { #define PCR_PLL_20M_CLK_EN_V 0x00000001U #define PCR_PLL_20M_CLK_EN_S 7 /** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) driven from SPLL. 0: close, + * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_12M_CLK_EN (BIT(8)) @@ -2201,12 +2202,12 @@ extern "C" { */ #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) /** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ #define PCR_32K_SEL 0x00000007U #define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) @@ -2281,59 +2282,33 @@ extern "C" { #define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) /** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_SEC_CLK_SEL 0x00000003U #define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) #define PCR_SEC_CLK_SEL_V 0x00000003U #define PCR_SEC_CLK_SEL_S 0 /** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ #define PCR_SEC_RST_EN (BIT(2)) #define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) #define PCR_SEC_RST_EN_V 0x00000001U #define PCR_SEC_RST_EN_S 2 -/** PCR_ADC_DAC_INV_PHASE_CONF_REG register - * xxxx - */ -#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140) -/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; - * xxxx - */ -#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 -/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; - * xxxx - */ -#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 -/** PCR_CLK_PWDET_ADC_INV_PHASE_ENA : R/W; bitpos: [2]; default: 0; - * xxxx - */ -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA (BIT(2)) -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_M (PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V << PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S 2 - /** PCR_BUS_CLK_UPDATE_REG register * Configuration register for applying updated high-performance system clock sources */ #define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x144) /** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ #define PCR_BUS_CLOCK_UPDATE (BIT(0)) #define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) @@ -2345,41 +2320,20 @@ extern "C" { */ #define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x148) /** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ #define PCR_SAR2_CLK_DIV_NUM 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) #define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_S 0 /** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ #define PCR_SAR1_CLK_DIV_NUM 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) #define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_S 8 -/** PCR_PWDET_SAR_CLK_CONF_REG register - * xxxx - */ -#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x14c) -/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) -#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 -/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_EN (BIT(8)) -#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) -#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U -#define PCR_PWDET_SAR_CLK_EN_S 8 - /** PCR_BS_CONF_REG register * BS configuration register */ @@ -2392,7 +2346,7 @@ extern "C" { #define PCR_BS_CLK_EN_V 0x00000001U #define PCR_BS_CLK_EN_S 0 /** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset bs module + * Set 1 to reset bs module */ #define PCR_BS_RST_EN (BIT(1)) #define PCR_BS_RST_EN_M (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S) @@ -2404,14 +2358,14 @@ extern "C" { */ #define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x154) /** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset bs tx module + * Set 1 to reset bs tx module */ #define PCR_BS_TX_RST_EN (BIT(23)) #define PCR_BS_TX_RST_EN_M (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S) #define PCR_BS_TX_RST_EN_V 0x00000001U #define PCR_BS_TX_RST_EN_S 23 /** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0; - * Set 0 to reset bs rx module + * Set 1 to reset bs rx module */ #define PCR_BS_RX_RST_EN (BIT(24)) #define PCR_BS_RX_RST_EN_M (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S) @@ -2442,14 +2396,14 @@ extern "C" { */ #define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x15c) /** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ #define PCR_TG0_WDT_RST_EN (BIT(0)) #define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) #define PCR_TG0_WDT_RST_EN_V 0x00000001U #define PCR_TG0_WDT_RST_EN_S 0 /** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ #define PCR_TG1_WDT_RST_EN (BIT(1)) #define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) @@ -2461,14 +2415,14 @@ extern "C" { */ #define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x160) /** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ #define PCR_TG0_XTAL_RST_EN (BIT(0)) #define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) #define PCR_TG0_XTAL_RST_EN_V 0x00000001U #define PCR_TG0_XTAL_RST_EN_S 0 /** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ #define PCR_TG1_XTAL_RST_EN (BIT(1)) #define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) @@ -2494,7 +2448,7 @@ extern "C" { #define PCR_KM_CLK_EN_V 0x00000001U #define PCR_KM_CLK_EN_S 0 /** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset km module + * Set 1 to reset km module */ #define PCR_KM_RST_EN (BIT(1)) #define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) @@ -2539,7 +2493,7 @@ extern "C" { #define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 /** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ #define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) @@ -2565,7 +2519,7 @@ extern "C" { #define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 /** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ #define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) @@ -2623,6 +2577,25 @@ extern "C" { #define PCR_HPCORE_0_MEM_FORCE_PD_V 0x00000001U #define PCR_HPCORE_0_MEM_FORCE_PD_S 2 +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x17c) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + /** PCR_FPGA_DEBUG_REG register * fpga debug register */ @@ -2651,7 +2624,7 @@ extern "C" { * Date register. */ #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) -/** PCR_DATE : R/W; bitpos: [27:0]; default: 36774528; +/** PCR_DATE : R/W; bitpos: [27:0]; default: 2363425; * PCR version information. */ #define PCR_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/pcr_struct.h b/components/soc/esp32c5/register/soc/pcr_struct.h index 299a2da15b..fddb127f87 100644 --- a/components/soc/esp32c5/register/soc/pcr_struct.h +++ b/components/soc/esp32c5/register/soc/pcr_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ typedef union { */ uint32_t uart0_clk_en:1; /** uart0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ uint32_t uart0_rst_en:1; /** uart0_ready : RO; bitpos: [2]; default: 1; @@ -51,10 +51,10 @@ typedef union { */ uint32_t uart0_sclk_div_num:8; /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart0_sclk_sel:2; /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; @@ -95,7 +95,7 @@ typedef union { */ uint32_t uart1_clk_en:1; /** uart1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ uint32_t uart1_rst_en:1; /** uart1_ready : RO; bitpos: [2]; default: 1; @@ -125,10 +125,10 @@ typedef union { */ uint32_t uart1_sclk_div_num:8; /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart1_sclk_sel:2; /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; @@ -169,7 +169,7 @@ typedef union { */ uint32_t mspi_clk_en:1; /** mspi_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ uint32_t mspi_rst_en:1; /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; @@ -197,10 +197,10 @@ typedef union { */ uint32_t mspi_fast_div_num:8; /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t mspi_func_clk_sel:2; /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; @@ -208,7 +208,7 @@ typedef union { */ uint32_t mspi_func_clk_en:1; /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ uint32_t mspi_axi_rst_en:1; uint32_t reserved_12:20; @@ -226,7 +226,7 @@ typedef union { */ uint32_t i2c_clk_en:1; /** i2c_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ uint32_t i2c_rst_en:1; uint32_t reserved_2:30; @@ -252,9 +252,9 @@ typedef union { */ uint32_t i2c_sclk_div_num:8; /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t i2c_sclk_sel:1; uint32_t reserved_21:1; @@ -277,7 +277,7 @@ typedef union { */ uint32_t twai_clk_en:1; /** twai_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai module + * Set 1 to reset twai module */ uint32_t twai_rst_en:1; /** twai_ready : RO; bitpos: [2]; default: 1; @@ -296,9 +296,9 @@ typedef union { struct { uint32_t reserved_0:20; /** twai_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of TWAI. + * 0 (default): XTAL_CLK + * 1: PLL_F80M_CLK */ uint32_t twai_func_clk_sel:1; uint32_t reserved_21:1; @@ -321,7 +321,7 @@ typedef union { */ uint32_t uhci_clk_en:1; /** uhci_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module + * Set 1 to reset uhci module */ uint32_t uhci_rst_en:1; /** uhci_ready : RO; bitpos: [2]; default: 1; @@ -343,7 +343,7 @@ typedef union { */ uint32_t rmt_clk_en:1; /** rmt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module + * Set 1 to reset rmt module */ uint32_t rmt_rst_en:1; uint32_t reserved_2:30; @@ -369,10 +369,10 @@ typedef union { */ uint32_t rmt_sclk_div_num:8; /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; - * Configures the clock source of RMT.\\ - * 0: XTAL_CLK\\ - * 1 (default): RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of RMT. + * 0: XTAL_CLK + * 1 (default): RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t rmt_sclk_sel:2; /** rmt_sclk_en : R/W; bitpos: [22]; default: 0; @@ -413,7 +413,7 @@ typedef union { */ uint32_t ledc_clk_en:1; /** ledc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ uint32_t ledc_rst_en:1; /** ledc_ready : RO; bitpos: [2]; default: 1; @@ -432,10 +432,10 @@ typedef union { struct { uint32_t reserved_0:20; /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 0; @@ -476,7 +476,7 @@ typedef union { */ uint32_t tg0_clk_en:1; /** tg0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ uint32_t tg0_rst_en:1; /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; @@ -503,10 +503,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_timer_clk_sel:2; /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -525,10 +525,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_wdt_clk_sel:2; /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -550,7 +550,7 @@ typedef union { */ uint32_t tg1_clk_en:1; /** tg1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ uint32_t tg1_rst_en:1; /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; @@ -577,10 +577,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_timer_clk_sel:2; /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -599,10 +599,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_wdt_clk_sel:2; /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -624,7 +624,7 @@ typedef union { */ uint32_t systimer_clk_en:1; /** systimer_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ uint32_t systimer_rst_en:1; /** systimer_ready : RO; bitpos: [2]; default: 1; @@ -643,9 +643,9 @@ typedef union { struct { uint32_t reserved_0:20; /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t systimer_func_clk_sel:1; uint32_t reserved_21:1; @@ -668,7 +668,7 @@ typedef union { */ uint32_t i2s_clk_en:1; /** i2s_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ uint32_t i2s_rst_en:1; /** i2s_rx_ready : RO; bitpos: [2]; default: 1; @@ -698,11 +698,11 @@ typedef union { */ uint32_t i2s_tx_clkm_div_num:8; /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_tx_clkm_sel:2; /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 0; @@ -755,11 +755,11 @@ typedef union { */ uint32_t i2s_rx_clkm_div_num:8; /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F240M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F240M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_rx_clkm_sel:2; /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 0; @@ -767,9 +767,9 @@ typedef union { */ uint32_t i2s_rx_clkm_en:1; /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ uint32_t i2s_mclk_sel:1; uint32_t reserved_24:8; @@ -817,7 +817,7 @@ typedef union { */ uint32_t saradc_clk_en:1; /** saradc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ uint32_t saradc_rst_en:1; /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 0; @@ -825,7 +825,7 @@ typedef union { */ uint32_t saradc_reg_clk_en:1; /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ uint32_t saradc_reg_rst_en:1; uint32_t reserved_4:28; @@ -851,10 +851,10 @@ typedef union { */ uint32_t saradc_clkm_div_num:8; /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t saradc_clkm_sel:2; /** saradc_clkm_en : R/W; bitpos: [22]; default: 0; @@ -873,9 +873,9 @@ typedef union { struct { uint32_t reserved_0:20; /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t tsens_clk_sel:1; uint32_t reserved_21:1; @@ -884,7 +884,7 @@ typedef union { */ uint32_t tsens_clk_en:1; /** tsens_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ uint32_t tsens_rst_en:1; uint32_t reserved_24:8; @@ -902,7 +902,7 @@ typedef union { */ uint32_t usb_device_clk_en:1; /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ uint32_t usb_device_rst_en:1; /** usb_device_ready : RO; bitpos: [2]; default: 1; @@ -924,7 +924,7 @@ typedef union { */ uint32_t intmtx_clk_en:1; /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ uint32_t intmtx_rst_en:1; /** intmtx_ready : RO; bitpos: [2]; default: 1; @@ -946,7 +946,7 @@ typedef union { */ uint32_t pcnt_clk_en:1; /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module + * Set 1 to reset pcnt module */ uint32_t pcnt_rst_en:1; /** pcnt_ready : RO; bitpos: [2]; default: 1; @@ -968,7 +968,7 @@ typedef union { */ uint32_t etm_clk_en:1; /** etm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ uint32_t etm_rst_en:1; /** etm_ready : RO; bitpos: [2]; default: 1; @@ -990,7 +990,7 @@ typedef union { */ uint32_t pwm_clk_en:1; /** pwm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module + * Set 1 to reset pwm module */ uint32_t pwm_rst_en:1; /** pwm_ready : RO; bitpos: [2]; default: 1; @@ -1013,10 +1013,10 @@ typedef union { */ uint32_t pwm_div_num:8; /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of MCPWM.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures the clock source of MCPWM. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ uint32_t pwm_clkm_sel:2; /** pwm_clkm_en : R/W; bitpos: [22]; default: 0; @@ -1038,7 +1038,7 @@ typedef union { */ uint32_t parl_clk_en:1; /** parl_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg + * Set 1 to reset parl apb reg */ uint32_t parl_rst_en:1; /** parl_ready : RO; bitpos: [2]; default: 1; @@ -1060,11 +1060,11 @@ typedef union { */ uint32_t parl_clk_rx_div_num:16; /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ uint32_t parl_clk_rx_sel:2; /** parl_clk_rx_en : R/W; bitpos: [18]; default: 0; @@ -1072,7 +1072,7 @@ typedef union { */ uint32_t parl_clk_rx_en:1; /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module + * Set 1 to reset parl rx module */ uint32_t parl_rx_rst_en:1; uint32_t reserved_20:12; @@ -1090,11 +1090,11 @@ typedef union { */ uint32_t parl_clk_tx_div_num:16; /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; - * Configures the clock source of Paraller IO RX\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F240M_CLK\\ - * 3: Use the clock from chip pin\\ + * Configures the clock source of Paraller IO RX + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F240M_CLK + * 3: Use the clock from chip pin */ uint32_t parl_clk_tx_sel:2; /** parl_clk_tx_en : R/W; bitpos: [18]; default: 0; @@ -1102,7 +1102,7 @@ typedef union { */ uint32_t parl_clk_tx_en:1; /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module + * Set 1 to reset parl tx module */ uint32_t parl_tx_rst_en:1; uint32_t reserved_20:12; @@ -1120,7 +1120,7 @@ typedef union { */ uint32_t pvt_monitor_clk_en:1; /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module + * Set 1 to reset all pvt monitor module */ uint32_t pvt_monitor_rst_en:1; /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; @@ -1151,9 +1151,9 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ uint32_t pvt_monitor_func_clk_sel:1; uint32_t reserved_21:1; @@ -1176,7 +1176,7 @@ typedef union { */ uint32_t gdma_clk_en:1; /** gdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ uint32_t gdma_rst_en:1; uint32_t reserved_2:30; @@ -1194,7 +1194,7 @@ typedef union { */ uint32_t spi2_clk_en:1; /** spi2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ uint32_t spi2_rst_en:1; /** spi2_ready : RO; bitpos: [2]; default: 1; @@ -1217,11 +1217,11 @@ typedef union { */ uint32_t spi2_clkm_div_num:8; /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ - * 3: PLL_F120M_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK + * 3: PLL_F120M_CLK */ uint32_t spi2_clkm_sel:2; /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; @@ -1243,7 +1243,7 @@ typedef union { */ uint32_t aes_clk_en:1; /** aes_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ uint32_t aes_rst_en:1; /** aes_ready : RO; bitpos: [2]; default: 1; @@ -1265,7 +1265,7 @@ typedef union { */ uint32_t sha_clk_en:1; /** sha_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ uint32_t sha_rst_en:1; /** sha_ready : RO; bitpos: [2]; default: 1; @@ -1287,7 +1287,7 @@ typedef union { */ uint32_t rsa_clk_en:1; /** rsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ uint32_t rsa_rst_en:1; /** rsa_ready : RO; bitpos: [2]; default: 1; @@ -1331,7 +1331,7 @@ typedef union { */ uint32_t ecc_clk_en:1; /** ecc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ uint32_t ecc_rst_en:1; /** ecc_ready : RO; bitpos: [2]; default: 1; @@ -1375,7 +1375,7 @@ typedef union { */ uint32_t ds_clk_en:1; /** ds_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ uint32_t ds_rst_en:1; /** ds_ready : RO; bitpos: [2]; default: 1; @@ -1397,7 +1397,7 @@ typedef union { */ uint32_t hmac_clk_en:1; /** hmac_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ uint32_t hmac_rst_en:1; /** hmac_ready : RO; bitpos: [2]; default: 1; @@ -1419,7 +1419,7 @@ typedef union { */ uint32_t ecdsa_clk_en:1; /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ uint32_t ecdsa_rst_en:1; /** ecdsa_ready : RO; bitpos: [2]; default: 1; @@ -1441,7 +1441,7 @@ typedef union { */ uint32_t iomux_clk_en:1; /** iomux_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ uint32_t iomux_rst_en:1; uint32_t reserved_2:30; @@ -1456,10 +1456,10 @@ typedef union { struct { uint32_t reserved_0:20; /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t iomux_func_clk_sel:2; /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; @@ -1481,7 +1481,7 @@ typedef union { */ uint32_t regdma_clk_en:1; /** regdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ uint32_t regdma_rst_en:1; uint32_t reserved_2:30; @@ -1499,7 +1499,7 @@ typedef union { */ uint32_t trace_clk_en:1; /** trace_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ uint32_t trace_rst_en:1; uint32_t reserved_2:30; @@ -1517,7 +1517,7 @@ typedef union { */ uint32_t assist_clk_en:1; /** assist_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ uint32_t assist_rst_en:1; uint32_t reserved_2:30; @@ -1535,7 +1535,7 @@ typedef union { */ uint32_t cache_clk_en:1; /** cache_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ uint32_t cache_rst_en:1; /** cache_pu_en : R/W; bitpos: [2]; default: 1; @@ -1581,11 +1581,11 @@ typedef union { struct { uint32_t reserved_0:1; /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ uint32_t cpu_timeout_rst_en:1; /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ uint32_t hp_timeout_rst_en:1; uint32_t reserved_3:29; @@ -1598,13 +1598,21 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:16; + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ - * 2: PLL_F240M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK + * 2: PLL_F240M_CLK */ uint32_t soc_clk_sel:2; uint32_t reserved_18:6; @@ -1626,14 +1634,7 @@ typedef union { */ typedef union { struct { - /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t cpuperiod_sel:2; - /** pll_freq_sel : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t pll_freq_sel:1; + uint32_t reserved_0:3; /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1821,12 +1822,12 @@ typedef union { typedef union { struct { /** 32k_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ uint32_t clk_32k_sel:3; uint32_t reserved_3:5; @@ -1895,14 +1896,14 @@ typedef union { struct { /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t sec_clk_sel:2; /** sec_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ uint32_t sec_rst_en:1; uint32_t reserved_3:29; @@ -1910,28 +1911,6 @@ typedef union { uint32_t val; } pcr_sec_conf_reg_t; -/** Type of adc_dac_inv_phase_conf register - * xxxx - */ -typedef union { - struct { - /** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; - * xxxx - */ - uint32_t clk_rx_adc_inv_phase_ena:1; - /** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0; - * xxxx - */ - uint32_t clk_tx_dac_inv_phase_ena:1; - /** clk_pwdet_adc_inv_phase_ena : R/W; bitpos: [2]; default: 0; - * xxxx - */ - uint32_t clk_pwdet_adc_inv_phase_ena:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_adc_dac_inv_phase_conf_reg_t; - /** Type of bus_clk_update register * Configuration register for applying updated high-performance system clock sources */ @@ -1939,10 +1918,10 @@ typedef union { struct { /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ uint32_t bus_clock_update:1; uint32_t reserved_1:31; @@ -1956,13 +1935,11 @@ typedef union { typedef union { struct { /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ uint32_t sar2_clk_div_num:8; /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ uint32_t sar1_clk_div_num:8; uint32_t reserved_16:16; @@ -1970,24 +1947,6 @@ typedef union { uint32_t val; } pcr_sar_clk_div_reg_t; -/** Type of pwdet_sar_clk_conf register - * xxxx - */ -typedef union { - struct { - /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ - uint32_t pwdet_sar_clk_div_num:8; - /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; - * xxxx - */ - uint32_t pwdet_sar_clk_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} pcr_pwdet_sar_clk_conf_reg_t; - /** Type of bs_conf register * BS configuration register */ @@ -1998,7 +1957,7 @@ typedef union { */ uint32_t bs_clk_en:1; /** bs_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset bs module + * Set 1 to reset bs module */ uint32_t bs_rst_en:1; uint32_t reserved_2:30; @@ -2013,11 +1972,11 @@ typedef union { struct { uint32_t reserved_0:23; /** bs_tx_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset bs tx module + * Set 1 to reset bs tx module */ uint32_t bs_tx_rst_en:1; /** bs_rx_rst_en : R/W; bitpos: [24]; default: 0; - * Set 0 to reset bs rx module + * Set 1 to reset bs rx module */ uint32_t bs_rx_rst_en:1; uint32_t reserved_25:7; @@ -2050,11 +2009,11 @@ typedef union { typedef union { struct { /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ uint32_t tg0_wdt_rst_en:1; /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ uint32_t tg1_wdt_rst_en:1; uint32_t reserved_2:30; @@ -2068,11 +2027,11 @@ typedef union { typedef union { struct { /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ uint32_t tg0_xtal_rst_en:1; /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ uint32_t tg1_xtal_rst_en:1; /** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1; @@ -2094,7 +2053,7 @@ typedef union { */ uint32_t km_clk_en:1; /** km_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset km module + * Set 1 to reset km module */ uint32_t km_rst_en:1; /** km_ready : RO; bitpos: [2]; default: 1; @@ -2135,7 +2094,7 @@ typedef union { */ uint32_t tcm_mem_monitor_clk_en:1; /** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ uint32_t tcm_mem_monitor_rst_en:1; /** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -2157,7 +2116,7 @@ typedef union { */ uint32_t psram_mem_monitor_clk_en:1; /** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ uint32_t psram_mem_monitor_rst_en:1; /** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -2212,6 +2171,24 @@ typedef union { uint32_t val; } pcr_hpcore_0_pd_ctrl_reg_t; +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register + */ +typedef union { + struct { + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable sdio_slave clock + */ + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sdio_slave_conf_reg_t; + /** Type of clock_gate register * PCR clock gating configure register */ @@ -2268,7 +2245,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774528; + /** date : R/W; bitpos: [27:0]; default: 2363425; * PCR version information. */ uint32_t date:28; @@ -2370,10 +2347,10 @@ typedef struct { volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; volatile pcr_sec_conf_reg_t sec_conf; - volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf; + uint32_t reserved_140; volatile pcr_bus_clk_update_reg_t bus_clk_update; volatile pcr_sar_clk_div_reg_t sar_clk_div; - volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + uint32_t reserved_14c; volatile pcr_bs_conf_reg_t bs_conf; volatile pcr_bs_func_conf_reg_t bs_func_conf; volatile pcr_bs_pd_ctrl_reg_t bs_pd_ctrl; @@ -2385,7 +2362,8 @@ typedef struct { volatile pcr_psram_mem_monitor_conf_reg_t psram_mem_monitor_conf; volatile pcr_reset_event_bypass_reg_t reset_event_bypass; volatile pcr_hpcore_0_pd_ctrl_reg_t hpcore_0_pd_ctrl; - uint32_t reserved_17c[926]; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + uint32_t reserved_180[925]; volatile pcr_fpga_debug_reg_t fpga_debug; volatile pcr_clock_gate_reg_t clock_gate; volatile pcr_date_reg_t date; diff --git a/components/soc/esp32c5/register/soc/spi_reg.h b/components/soc/esp32c5/register/soc/spi_reg.h index cce0834349..4ace6f9957 100644 --- a/components/soc/esp32c5/register/soc/spi_reg.h +++ b/components/soc/esp32c5/register/soc/spi_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,13 +11,15 @@ extern "C" { #endif +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5 + /** SPI_CMD_REG register * Command control register */ #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ #define SPI_CONF_BITLEN 0x0003FFFFU @@ -26,9 +28,9 @@ extern "C" { #define SPI_CONF_BITLEN_S 0 /** SPI_UPDATE : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ #define SPI_UPDATE (BIT(23)) @@ -36,9 +38,9 @@ extern "C" { #define SPI_UPDATE_V 0x00000001U #define SPI_UPDATE_S 23 /** SPI_USR : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -65,9 +67,9 @@ extern "C" { */ #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ #define SPI_DUMMY_OUT (BIT(3)) @@ -75,9 +77,9 @@ extern "C" { #define SPI_DUMMY_OUT_V 0x00000001U #define SPI_DUMMY_OUT_S 3 /** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_DUAL (BIT(5)) @@ -85,9 +87,9 @@ extern "C" { #define SPI_FADDR_DUAL_V 0x00000001U #define SPI_FADDR_DUAL_S 5 /** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_QUAD (BIT(6)) @@ -95,9 +97,9 @@ extern "C" { #define SPI_FADDR_QUAD_V 0x00000001U #define SPI_FADDR_QUAD_S 6 /** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_OCT (BIT(7)) @@ -105,9 +107,9 @@ extern "C" { #define SPI_FADDR_OCT_V 0x00000001U #define SPI_FADDR_OCT_S 7 /** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_DUAL (BIT(8)) @@ -115,9 +117,9 @@ extern "C" { #define SPI_FCMD_DUAL_V 0x00000001U #define SPI_FCMD_DUAL_S 8 /** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_QUAD (BIT(9)) @@ -125,9 +127,9 @@ extern "C" { #define SPI_FCMD_QUAD_V 0x00000001U #define SPI_FCMD_QUAD_S 9 /** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_OCT (BIT(10)) @@ -136,9 +138,9 @@ extern "C" { #define SPI_FCMD_OCT_S 10 /** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_DUAL (BIT(14)) @@ -147,9 +149,9 @@ extern "C" { #define SPI_FREAD_DUAL_S 14 /** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_QUAD (BIT(15)) @@ -158,9 +160,9 @@ extern "C" { #define SPI_FREAD_QUAD_S 15 /** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_OCT (BIT(16)) @@ -168,9 +170,9 @@ extern "C" { #define SPI_FREAD_OCT_V 0x00000001U #define SPI_FREAD_OCT_S 16 /** SPI_Q_POL : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_Q_POL (BIT(18)) @@ -178,9 +180,9 @@ extern "C" { #define SPI_Q_POL_V 0x00000001U #define SPI_Q_POL_S 18 /** SPI_D_POL : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_D_POL (BIT(19)) @@ -188,9 +190,9 @@ extern "C" { #define SPI_D_POL_V 0x00000001U #define SPI_D_POL_S 19 /** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_HOLD_POL (BIT(20)) @@ -198,9 +200,9 @@ extern "C" { #define SPI_HOLD_POL_V 0x00000001U #define SPI_HOLD_POL_S 20 /** SPI_WP_POL : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_WP_POL (BIT(21)) @@ -208,9 +210,9 @@ extern "C" { #define SPI_WP_POL_V 0x00000001U #define SPI_WP_POL_S 21 /** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_RD_BIT_ORDER 0x00000003U @@ -219,9 +221,9 @@ extern "C" { #define SPI_RD_BIT_ORDER_S 23 /** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_WR_BIT_ORDER 0x00000003U @@ -245,7 +247,7 @@ extern "C" { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ #define SPI_CLKCNT_H 0x0000003FU @@ -255,7 +257,7 @@ extern "C" { /** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ #define SPI_CLKCNT_N 0x0000003FU @@ -270,10 +272,21 @@ extern "C" { #define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EDGE_SEL : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ +#define SPI_CLK_EDGE_SEL (BIT(30)) +#define SPI_CLK_EDGE_SEL_M (SPI_CLK_EDGE_SEL_V << SPI_CLK_EDGE_SEL_S) +#define SPI_CLK_EDGE_SEL_V 0x00000001U +#define SPI_CLK_EDGE_SEL_S 30 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -286,9 +299,9 @@ extern "C" { */ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_DOUTDIN (BIT(0)) @@ -296,9 +309,9 @@ extern "C" { #define SPI_DOUTDIN_V 0x00000001U #define SPI_DOUTDIN_S 0 /** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -315,18 +328,18 @@ extern "C" { #define SPI_OPI_MODE_V 0x00000001U #define SPI_OPI_MODE_S 4 /** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ #define SPI_TSCK_I_EDGE (BIT(5)) #define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) #define SPI_TSCK_I_EDGE_V 0x00000001U #define SPI_TSCK_I_EDGE_S 5 /** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_HOLD (BIT(6)) @@ -334,9 +347,9 @@ extern "C" { #define SPI_CS_HOLD_V 0x00000001U #define SPI_CS_HOLD_S 6 /** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_CS_SETUP (BIT(7)) @@ -344,9 +357,9 @@ extern "C" { #define SPI_CS_SETUP_V 0x00000001U #define SPI_CS_SETUP_S 7 /** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ #define SPI_RSCK_I_EDGE (BIT(8)) #define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) @@ -354,8 +367,7 @@ extern "C" { #define SPI_RSCK_I_EDGE_S 8 /** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ #define SPI_CK_OUT_EDGE (BIT(9)) #define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) @@ -363,9 +375,9 @@ extern "C" { #define SPI_CK_OUT_EDGE_S 9 /** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_DUAL (BIT(12)) @@ -374,9 +386,9 @@ extern "C" { #define SPI_FWRITE_DUAL_S 12 /** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_QUAD (BIT(13)) @@ -393,11 +405,11 @@ extern "C" { #define SPI_FWRITE_OCT_S 14 /** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ #define SPI_USR_CONF_NXT (BIT(15)) @@ -406,9 +418,9 @@ extern "C" { #define SPI_USR_CONF_NXT_S 15 /** SPI_SIO : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_SIO (BIT(17)) @@ -417,9 +429,9 @@ extern "C" { #define SPI_SIO_S 17 /** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO_HIGHPART (BIT(24)) @@ -428,9 +440,9 @@ extern "C" { #define SPI_USR_MISO_HIGHPART_S 24 /** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI_HIGHPART (BIT(25)) @@ -438,9 +450,9 @@ extern "C" { #define SPI_USR_MOSI_HIGHPART_V 0x00000001U #define SPI_USR_MOSI_HIGHPART_S 25 /** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ #define SPI_USR_DUMMY_IDLE (BIT(26)) @@ -448,9 +460,9 @@ extern "C" { #define SPI_USR_DUMMY_IDLE_V 0x00000001U #define SPI_USR_DUMMY_IDLE_S 26 /** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI (BIT(27)) @@ -458,9 +470,9 @@ extern "C" { #define SPI_USR_MOSI_V 0x00000001U #define SPI_USR_MOSI_S 27 /** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO (BIT(28)) @@ -468,9 +480,9 @@ extern "C" { #define SPI_USR_MISO_V 0x00000001U #define SPI_USR_MISO_S 28 /** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_DUMMY (BIT(29)) @@ -478,9 +490,9 @@ extern "C" { #define SPI_USR_DUMMY_V 0x00000001U #define SPI_USR_DUMMY_S 29 /** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_ADDR (BIT(30)) @@ -488,9 +500,9 @@ extern "C" { #define SPI_USR_ADDR_V 0x00000001U #define SPI_USR_ADDR_S 30 /** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_COMMAND (BIT(31)) @@ -504,7 +516,7 @@ extern "C" { #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ #define SPI_USR_DUMMY_CYCLELEN 0x000000FFU @@ -513,9 +525,9 @@ extern "C" { #define SPI_USR_DUMMY_CYCLELEN_S 0 /** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_WFULL_ERR_END_EN (BIT(16)) #define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) @@ -523,7 +535,7 @@ extern "C" { #define SPI_MST_WFULL_ERR_END_EN_S 16 /** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ @@ -533,7 +545,7 @@ extern "C" { #define SPI_CS_SETUP_TIME_S 17 /** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ #define SPI_CS_HOLD_TIME 0x0000001FU @@ -563,9 +575,9 @@ extern "C" { #define SPI_USR_COMMAND_VALUE_S 0 /** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) @@ -600,9 +612,9 @@ extern "C" { */ #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS0_DIS (BIT(0)) @@ -610,9 +622,9 @@ extern "C" { #define SPI_CS0_DIS_V 0x00000001U #define SPI_CS0_DIS_S 0 /** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS1_DIS (BIT(1)) @@ -620,9 +632,9 @@ extern "C" { #define SPI_CS1_DIS_V 0x00000001U #define SPI_CS1_DIS_S 1 /** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS2_DIS (BIT(2)) @@ -630,9 +642,9 @@ extern "C" { #define SPI_CS2_DIS_V 0x00000001U #define SPI_CS2_DIS_S 2 /** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS3_DIS (BIT(3)) @@ -640,9 +652,9 @@ extern "C" { #define SPI_CS3_DIS_V 0x00000001U #define SPI_CS3_DIS_S 3 /** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS4_DIS (BIT(4)) @@ -650,9 +662,9 @@ extern "C" { #define SPI_CS4_DIS_V 0x00000001U #define SPI_CS4_DIS_S 4 /** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS5_DIS (BIT(5)) @@ -660,9 +672,9 @@ extern "C" { #define SPI_CS5_DIS_V 0x00000001U #define SPI_CS5_DIS_S 5 /** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ #define SPI_CK_DIS (BIT(6)) @@ -670,9 +682,9 @@ extern "C" { #define SPI_CK_DIS_V 0x00000001U #define SPI_CK_DIS_S 6 /** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ #define SPI_MASTER_CS_POL 0x0000003FU @@ -715,9 +727,9 @@ extern "C" { #define SPI_CMD_DTR_EN_V 0x00000001U #define SPI_CMD_DTR_EN_S 19 /** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ #define SPI_SLAVE_CS_POL (BIT(23)) @@ -732,9 +744,9 @@ extern "C" { #define SPI_DQS_IDLE_EDGE_V 0x00000001U #define SPI_DQS_IDLE_EDGE_S 24 /** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_CK_IDLE_EDGE (BIT(29)) @@ -742,9 +754,9 @@ extern "C" { #define SPI_CK_IDLE_EDGE_V 0x00000001U #define SPI_CK_IDLE_EDGE_S 29 /** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_KEEP_ACTIVE (BIT(30)) @@ -765,13 +777,13 @@ extern "C" { */ #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN0_MODE 0x00000003U @@ -779,13 +791,13 @@ extern "C" { #define SPI_DIN0_MODE_V 0x00000003U #define SPI_DIN0_MODE_S 0 /** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN1_MODE 0x00000003U @@ -793,13 +805,13 @@ extern "C" { #define SPI_DIN1_MODE_V 0x00000003U #define SPI_DIN1_MODE_S 2 /** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN2_MODE 0x00000003U @@ -807,13 +819,13 @@ extern "C" { #define SPI_DIN2_MODE_V 0x00000003U #define SPI_DIN2_MODE_S 4 /** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -859,9 +871,9 @@ extern "C" { #define SPI_DIN7_MODE_S 14 /** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_TIMING_HCLK_ACTIVE (BIT(16)) @@ -874,11 +886,11 @@ extern "C" { */ #define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN0_NUM 0x00000003U @@ -886,11 +898,11 @@ extern "C" { #define SPI_DIN0_NUM_V 0x00000003U #define SPI_DIN0_NUM_S 0 /** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN1_NUM 0x00000003U @@ -898,12 +910,11 @@ extern "C" { #define SPI_DIN1_NUM_V 0x00000003U #define SPI_DIN1_NUM_S 2 /** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN2_NUM 0x00000003U @@ -911,12 +922,11 @@ extern "C" { #define SPI_DIN2_NUM_V 0x00000003U #define SPI_DIN2_NUM_S 4 /** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN3_NUM 0x00000003U @@ -961,9 +971,9 @@ extern "C" { */ #define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT0_MODE (BIT(0)) @@ -971,9 +981,9 @@ extern "C" { #define SPI_DOUT0_MODE_V 0x00000001U #define SPI_DOUT0_MODE_S 0 /** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT1_MODE (BIT(1)) @@ -981,9 +991,9 @@ extern "C" { #define SPI_DOUT1_MODE_V 0x00000001U #define SPI_DOUT1_MODE_S 1 /** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT2_MODE (BIT(2)) @@ -991,9 +1001,9 @@ extern "C" { #define SPI_DOUT2_MODE_V 0x00000001U #define SPI_DOUT2_MODE_S 2 /** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT3_MODE (BIT(3)) @@ -1051,18 +1061,18 @@ extern "C" { */ #define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) #define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) #define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U #define SPI_DMA_OUTFIFO_EMPTY_S 0 /** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_INFIFO_FULL (BIT(1)) #define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) @@ -1070,9 +1080,9 @@ extern "C" { #define SPI_DMA_INFIFO_FULL_S 1 /** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ #define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) #define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) @@ -1080,10 +1090,10 @@ extern "C" { #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 /** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -1095,12 +1105,11 @@ extern "C" { #define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 /** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -1120,29 +1129,27 @@ extern "C" { #define SPI_RX_EOF_EN_V 0x00000001U #define SPI_RX_EOF_EN_S 21 /** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_RX_ENA (BIT(27)) #define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) #define SPI_DMA_RX_ENA_V 0x00000001U #define SPI_DMA_RX_ENA_S 27 /** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_TX_ENA (BIT(28)) #define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) #define SPI_DMA_TX_ENA_V 0x00000001U #define SPI_DMA_TX_ENA_S 28 /** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ #define SPI_RX_AFIFO_RST (BIT(29)) @@ -1150,11 +1157,9 @@ extern "C" { #define SPI_RX_AFIFO_RST_V 0x00000001U #define SPI_RX_AFIFO_RST_S 29 /** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ #define SPI_BUF_AFIFO_RST (BIT(30)) @@ -1162,11 +1167,9 @@ extern "C" { #define SPI_BUF_AFIFO_RST_V 0x00000001U #define SPI_BUF_AFIFO_RST_S 30 /** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ #define SPI_DMA_AFIFO_RST (BIT(31)) @@ -2135,11 +2138,11 @@ extern "C" { */ #define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U @@ -2147,20 +2150,18 @@ extern "C" { #define SPI_CLK_MODE_V 0x00000003U #define SPI_CLK_MODE_S 0 /** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ #define SPI_CLK_MODE_13 (BIT(2)) #define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) #define SPI_CLK_MODE_13_V 0x00000001U #define SPI_CLK_MODE_13_S 2 /** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ #define SPI_RSCK_DATA_OUT (BIT(3)) #define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) @@ -2168,9 +2169,9 @@ extern "C" { #define SPI_RSCK_DATA_OUT_S 3 /** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) #define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) @@ -2178,9 +2179,9 @@ extern "C" { #define SPI_SLV_RDDMA_BITLEN_EN_S 8 /** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) #define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) @@ -2188,9 +2189,9 @@ extern "C" { #define SPI_SLV_WRDMA_BITLEN_EN_S 9 /** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) #define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) @@ -2198,9 +2199,9 @@ extern "C" { #define SPI_SLV_RDBUF_BITLEN_EN_S 10 /** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) #define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) @@ -2223,19 +2224,18 @@ extern "C" { #define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU #define SPI_DMA_SEG_MAGIC_VALUE_S 22 /** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ #define SPI_SLAVE_MODE (BIT(26)) #define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) #define SPI_SLAVE_MODE_V 0x00000001U #define SPI_SLAVE_MODE_S 26 /** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ #define SPI_SOFT_RESET (BIT(27)) @@ -2244,10 +2244,10 @@ extern "C" { #define SPI_SOFT_RESET_S 27 /** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ #define SPI_USR_CONF (BIT(28)) #define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) @@ -2255,9 +2255,9 @@ extern "C" { #define SPI_USR_CONF_S 28 /** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ #define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) #define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) @@ -2295,9 +2295,9 @@ extern "C" { */ #define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ #define SPI_CLK_EN (BIT(0)) #define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) @@ -2323,7 +2323,7 @@ extern "C" { * Version control */ #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) -/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; +/** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ #define SPI_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/spi_struct.h b/components/soc/esp32c5/register/soc/spi_struct.h index c5625f0968..0a50d5964b 100644 --- a/components/soc/esp32c5/register/soc/spi_struct.h +++ b/components/soc/esp32c5/register/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,23 +18,23 @@ typedef union { struct { /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ uint32_t conf_bitlen:18; uint32_t reserved_18:5; /** update : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ uint32_t update:1; /** usr : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -64,17 +64,17 @@ typedef union { typedef union { struct { /** doutdin : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t doutdin:1; uint32_t reserved_1:2; /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -85,51 +85,50 @@ typedef union { */ uint32_t opi_mode:1; /** tsck_i_edge : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ uint32_t tsck_i_edge:1; /** cs_hold : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_hold:1; /** cs_setup : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t cs_setup:1; /** rsck_i_edge : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ uint32_t rsck_i_edge:1; /** ck_out_edge : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; /** fwrite_dual : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_dual:1; /** fwrite_quad : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_quad:1; @@ -140,79 +139,79 @@ typedef union { uint32_t fwrite_oct:1; /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ uint32_t usr_conf_nxt:1; uint32_t reserved_16:1; /** sio : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t sio:1; uint32_t reserved_18:6; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi_highpart:1; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ uint32_t usr_dummy_idle:1; /** usr_mosi : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi:1; /** usr_miso : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso:1; /** usr_dummy : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_dummy:1; /** usr_addr : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_addr:1; /** usr_command : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_command:1; @@ -227,28 +226,28 @@ typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ uint32_t usr_dummy_cyclelen:8; uint32_t reserved_8:8; /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_wfull_err_end_en:1; /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ uint32_t cs_setup_time:5; /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ uint32_t cs_hold_time:5; @@ -274,9 +273,9 @@ typedef union { uint32_t reserved_16:11; /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_rempty_err_end_en:1; /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; @@ -297,122 +296,122 @@ typedef union { struct { uint32_t reserved_0:3; /** dummy_out : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ uint32_t dummy_out:1; uint32_t reserved_4:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_dual:1; /** faddr_quad : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_quad:1; /** faddr_oct : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_oct:1; /** fcmd_dual : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_dual:1; /** fcmd_quad : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_quad:1; /** fcmd_oct : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_oct:1; uint32_t reserved_11:3; /** fread_dual : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_dual:1; /** fread_quad : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_quad:1; /** fread_oct : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_oct:1; uint32_t reserved_17:1; /** q_pol : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t q_pol:1; /** d_pol : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t d_pol:1; /** hold_pol : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t hold_pol:1; /** wp_pol : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t wp_pol:1; uint32_t reserved_22:1; /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t rd_bit_order:2; /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t wr_bit_order:2; @@ -444,58 +443,58 @@ typedef union { typedef union { struct { /** cs0_dis : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs0_dis:1; /** cs1_dis : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs1_dis:1; /** cs2_dis : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs2_dis:1; /** cs3_dis : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs3_dis:1; /** cs4_dis : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs4_dis:1; /** cs5_dis : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs5_dis:1; /** ck_dis : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ uint32_t ck_dis:1; /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ uint32_t master_cs_pol:6; @@ -525,9 +524,9 @@ typedef union { uint32_t cmd_dtr_en:1; uint32_t reserved_20:3; /** slave_cs_pol : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ uint32_t slave_cs_pol:1; @@ -537,16 +536,16 @@ typedef union { uint32_t dqs_idle_edge:1; uint32_t reserved_25:4; /** ck_idle_edge : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t ck_idle_edge:1; /** cs_keep_active : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_keep_active:1; @@ -565,31 +564,31 @@ typedef union { typedef union { struct { /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ uint32_t dma_outfifo_empty:1; /** dma_infifo_full : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ uint32_t dma_infifo_full:1; uint32_t reserved_2:16; /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ uint32_t dma_slv_seg_trans_en:1; /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -598,12 +597,11 @@ typedef union { uint32_t slv_rx_seg_trans_clr_en:1; /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -618,41 +616,35 @@ typedef union { uint32_t rx_eof_en:1; uint32_t reserved_22:5; /** dma_rx_ena : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_rx_ena:1; /** dma_tx_ena : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_tx_ena:1; /** rx_afifo_rst : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ uint32_t rx_afifo_rst:1; /** buf_afifo_rst : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ uint32_t buf_afifo_rst:1; /** dma_afifo_rst : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ uint32_t dma_afifo_rst:1; @@ -666,55 +658,53 @@ typedef union { typedef union { struct { /** clk_mode : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ uint32_t clk_mode_13:1; /** rsck_data_out : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ uint32_t rsck_data_out:1; uint32_t reserved_4:4; /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rddma_bitlen_en:1; /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrdma_bitlen_en:1; /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rdbuf_bitlen_en:1; /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrbuf_bitlen_en:1; /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; @@ -729,32 +719,31 @@ typedef union { */ uint32_t dma_seg_magic_value:4; /** slave_mode : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ uint32_t slave_mode:1; /** soft_reset : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ uint32_t soft_reset:1; /** usr_conf : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ uint32_t usr_conf:1; /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ uint32_t mst_fd_wait_dma_tx_data:1; uint32_t reserved_30:2; @@ -799,14 +788,14 @@ typedef union { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ uint32_t clkcnt_h:6; /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ uint32_t clkcnt_n:6; @@ -815,11 +804,19 @@ typedef union { * Can be configured in CONF state. */ uint32_t clkdiv_pre:4; - uint32_t reserved_22:9; + uint32_t reserved_22:8; + /** clk_edge_sel : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ + uint32_t clk_edge_sel:1; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; @@ -833,9 +830,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; /** mst_clk_active : R/W; bitpos: [1]; default: 0; @@ -860,46 +857,46 @@ typedef union { typedef union { struct { /** din0_mode : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din0_mode:2; /** din1_mode : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din1_mode:2; /** din2_mode : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din2_mode:2; /** din3_mode : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -930,9 +927,9 @@ typedef union { uint32_t din7_mode:2; /** timing_hclk_active : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t timing_hclk_active:1; @@ -947,40 +944,38 @@ typedef union { typedef union { struct { /** din0_num : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din0_num:2; /** din1_num : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din1_num:2; /** din2_num : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din2_num:2; /** din3_num : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din3_num:2; @@ -1015,30 +1010,30 @@ typedef union { typedef union { struct { /** dout0_mode : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout0_mode:1; /** dout1_mode : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout1_mode:1; /** dout2_mode : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout2_mode:1; /** dout3_mode : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout3_mode:1; @@ -1574,7 +1569,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36716931; + /** date : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ uint32_t date:28; @@ -1601,7 +1596,7 @@ typedef struct { volatile spi_dma_int_ena_reg_t dma_int_ena; volatile spi_dma_int_clr_reg_t dma_int_clr; volatile spi_dma_int_raw_reg_t dma_int_raw; - volatile spi_dma_int_st_reg_t dma_int_sta; + volatile spi_dma_int_st_reg_t dma_int_st; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; volatile spi_wn_reg_t data_buf[16]; diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt index fb8fb4bcc9..921ec9af28 100644 --- a/docs/docs_not_updated/esp32c5.txt +++ b/docs/docs_not_updated/esp32c5.txt @@ -23,7 +23,6 @@ api-reference/storage/fatfsgen.rst api-reference/storage/index.rst api-reference/storage/nvs_partition_parse.rst api-reference/peripherals/twai.rst -api-reference/peripherals/spi_features.rst api-reference/peripherals/touch_pad.rst api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/index.rst