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Merge branch 'refactor/make_mspi_hal_independent' into 'master'

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refactor(mspi): Make mspi hal layer independent

See merge request espressif/esp-idf!42035
This commit is contained in:
C.S.M
2025-09-28 22:23:59 +08:00
parent f54c09e81e b145ede835
commit 3e4e6918fd
91 changed files with 292 additions and 308 deletions
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1
components/esp_common/CMakeLists.txt
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@@ -32,6 +32,7 @@ set(optional_reqs ulp
soc
esp-tls
esp_https_ota
esp_hal_mspi
esp_hw_support)
idf_build_get_property(build_components BUILD_COMPONENTS)

2
components/esp_common/src/esp_err_to_name.c
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@@ -618,7 +618,7 @@ static const esp_err_msg_t esp_err_msg_table[] = {
# ifdef ESP_ERR_FLASH_OP_TIMEOUT
ERR_TBL_IT(ESP_ERR_FLASH_OP_TIMEOUT), /* 24578 0x6002 */
# endif
// components/hal/include/hal/esp_flash_err.h
// components/esp_hal_mspi/include/hal/esp_flash_err.h
# ifdef ESP_ERR_FLASH_NOT_INITIALISED
ERR_TBL_IT(ESP_ERR_FLASH_NOT_INITIALISED), /* 24579 0x6003 */
# endif

29
components/esp_hal_mspi/CMakeLists.txt Normal file
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@@ -0,0 +1,29 @@
idf_build_get_property(target IDF_TARGET)
idf_build_get_property(esp_tee_build ESP_TEE_BUILD)
set(srcs)
set(includes "include" "${target}/include")
if(esp_tee_build)
if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
list(APPEND srcs "spi_flash_hal.c")
endif()
elseif(NOT BOOTLOADER_BUILD)
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
if(CONFIG_SOC_SPI_FLASH_SUPPORTED)
list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c")
endif()
if(CONFIG_SOC_FLASH_ENC_SUPPORTED)
list(APPEND srcs "spi_flash_encrypt_hal_iram.c")
endif()
endif()
if(CONFIG_SOC_GPSPI_SUPPORTED AND NOT CONFIG_IDF_TARGET_ESP32)
list(APPEND srcs "spi_flash_hal_gpspi.c")
endif()
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)

9
components/esp_hal_mspi/README.md Normal file
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@@ -0,0 +1,9 @@
# `esp_hal_mspi`
⚠️ This HAL component is still under heavy development at the moment, so we don't guarantee the stability and backward-compatibility among versions.
The `esp_hal_mspi` component provides a **Hardware Abstraction Layer** of mspi for all targets supported by ESP-IDF.
In a broad sense, the HAL layer consists of two sub-layers: HAL (upper) and Low-Level(bottom). The HAL layer defines the steps and data that is required to operate a peripheral (e.g. initialization, start and stop). The low-level is a translation layer above the register files under the `soc` component, it only covers general conceptions to register configurations.
The functions in this file mainly provide hardware abstraction for IDF peripheral drivers. For advanced developers, the HAL layer functions can also be directly used to assist in implementing their own drivers. However, it needs to be mentioned again that the interfaces here do not guarantee stability.

0
components/hal/esp32/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32/include/hal/mspi_ll.h
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2
components/hal/esp32/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32/include/hal/spi_flash_encrypted_ll.h
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@@ -54,7 +54,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(!(REG_READ(FLASH_ENCRYPTION_DONE_REG) & BIT(0))) {
while (!(REG_READ(FLASH_ENCRYPTION_DONE_REG) & BIT(0))) {
}
}

6
components/hal/esp32/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32/include/hal/spi_flash_ll.h
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@@ -247,7 +247,7 @@ static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl;
typeof(dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val = ctrl.val & ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
ctrl.val = ctrl.val | SPI_FASTRD_MODE_M;
@@ -402,7 +402,7 @@ static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
static inline void spi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.hold_time = hold_n;
dev->user.cs_hold = (hold_n > 0? 1: 0);
dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
}
static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
@@ -441,7 +441,7 @@ static inline uint32_t spi_flash_ll_calculate_clock_reg(uint8_t host_id, uint8_t
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12));
}
return div_parameter;
}

0
components/hal/esp32c2/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h
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0
components/hal/esp32c2/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32c2/include/hal/mspi_ll.h
View File

7
components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32c2/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -114,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(XTS_AES_STATE_REG) == 0x1) {
while (REG_READ(XTS_AES_STATE_REG) == 0x1) {
}
}
@@ -124,7 +123,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(XTS_AES_RELEASE_REG, 1);
while(REG_READ(XTS_AES_STATE_REG) != 0x3) {
while (REG_READ(XTS_AES_STATE_REG) != 0x3) {
}
}

1
components/hal/esp32c2/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32c2/include/hal/spi_flash_ll.h
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@@ -36,7 +36,6 @@ extern "C" {
dev_id; \
})
typedef union {
gpspi_flash_ll_clock_reg_t gpspi;
spimem_flash_ll_clock_reg_t spimem;

1
components/hal/esp32c2/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32c2/include/hal/spimem_flash_ll.h
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@@ -363,7 +363,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32c3/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h
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0
components/hal/esp32c3/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32c3/include/hal/mspi_ll.h
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7
components/hal/esp32c2/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32c3/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -114,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(XTS_AES_STATE_REG) == 0x1) {
while (REG_READ(XTS_AES_STATE_REG) == 0x1) {
}
}
@@ -124,7 +123,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(XTS_AES_RELEASE_REG, 1);
while(REG_READ(XTS_AES_STATE_REG) != 0x3) {
while (REG_READ(XTS_AES_STATE_REG) != 0x3) {
}
}

2
components/hal/esp32c3/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32c3/include/hal/spi_flash_ll.h
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@@ -36,7 +36,6 @@ extern "C" {
dev_id; \
})
typedef union {
gpspi_flash_ll_clock_reg_t gpspi;
spimem_flash_ll_clock_reg_t spimem;
@@ -99,7 +98,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32c3/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32c3/include/hal/spimem_flash_ll.h
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@@ -365,7 +365,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32c5/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32c5/include/hal/gpspi_flash_ll.h
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44
components/hal/esp32c5/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h
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@@ -52,17 +52,17 @@ static inline __attribute__((always_inline)) void mspi_timing_ll_set_core_clock(
HAL_ASSERT(mspi_id == 0);
uint32_t divider = 0;
switch (core_clk_mhz) {
case 80:
divider = 6;
break;
case 120:
divider = 4;
break;
case 240:
divider = 2;
break;
default:
HAL_ASSERT(false);
case 80:
divider = 6;
break;
case 120:
divider = 4;
break;
case 240:
divider = 2;
break;
default:
HAL_ASSERT(false);
}
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
@@ -106,7 +106,7 @@ static inline uint32_t mspi_timing_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -189,8 +189,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_mode(uint8_t mspi_id, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(mspi_id)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_DIN_MODE_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -205,8 +205,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_num(uint8_t mspi_id, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(mspi_id)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_DIN_NUM_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -373,8 +373,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_mode(uint8_t mspi_id, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_MODE_REG(mspi_id)) & (~(SPI_SMEM_DIN0_MODE_M | SPI_SMEM_DIN1_MODE_M | SPI_SMEM_DIN2_MODE_M | SPI_SMEM_DIN3_MODE_M | SPI_SMEM_DIN4_MODE_M | SPI_SMEM_DIN5_MODE_M | SPI_SMEM_DIN6_MODE_M | SPI_SMEM_DIN7_MODE_M | SPI_SMEM_DINS_MODE_M)))
| (din_mode << SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_SMEM_DINS_MODE_S);
| (din_mode << SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_SMEM_DINS_MODE_S);
REG_WRITE(SPI_SMEM_DIN_MODE_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -389,8 +389,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_num(uint8_t mspi_id, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_NUM_REG(mspi_id)) & (~(SPI_SMEM_DIN0_NUM_M | SPI_SMEM_DIN1_NUM_M | SPI_SMEM_DIN2_NUM_M | SPI_SMEM_DIN3_NUM_M | SPI_SMEM_DIN4_NUM_M | SPI_SMEM_DIN5_NUM_M | SPI_SMEM_DIN6_NUM_M | SPI_SMEM_DIN7_NUM_M | SPI_SMEM_DINS_NUM_M)))
| (din_num << SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_SMEM_DINS_NUM_S);
| (din_num << SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_SMEM_DINS_NUM_S);
REG_WRITE(SPI_SMEM_DIN_NUM_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -407,11 +407,11 @@ static inline void mspi_timing_ll_set_psram_extra_dummy(uint8_t mspi_id, uint8_t
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
}
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}

6
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h → components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h
View File

@@ -153,7 +153,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -166,7 +166,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
typeof(SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
mem_cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
@@ -355,7 +355,7 @@ static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
switch (reg_val) {
case 0:
page_size = 256;
break;

7
components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32c5/include/hal/spi_flash_encrypted_ll.h
View File

@@ -27,8 +27,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -115,7 +114,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
}
}
@@ -125,7 +124,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
}
}

1
components/hal/esp32c5/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32c5/include/hal/spi_flash_ll.h
View File

@@ -104,7 +104,6 @@ typedef union {
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enale) spimem_flash_ll_wb_mode_enable((spi_mem_dev_t*)dev, wb_mode_enale)
#endif
#ifdef __cplusplus

1
components/hal/esp32c5/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32c5/include/hal/spimem_flash_ll.h
View File

@@ -386,7 +386,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32c6/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32c6/include/hal/gpspi_flash_ll.h
View File

0
components/hal/esp32c6/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32c6/include/hal/mspi_ll.h
View File

7
components/hal/esp32c6/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32c6/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -114,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
}
}
@@ -124,7 +123,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
}
}

1
components/hal/esp32c6/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32c6/include/hal/spi_flash_ll.h
View File

@@ -100,7 +100,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32c6/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32c6/include/hal/spimem_flash_ll.h
View File

@@ -366,7 +366,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32c61/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32c61/include/hal/gpspi_flash_ll.h
View File

40
components/hal/esp32c61/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h
View File

@@ -76,14 +76,14 @@ static inline __attribute__((always_inline)) void mspi_timing_ll_set_core_clock(
HAL_ASSERT(mspi_id == 0);
uint32_t divider = 0;
switch (core_clk_mhz) {
case 80:
divider = 6;
break;
case 120:
divider = 4;
break;
default:
HAL_ASSERT(false);
case 80:
divider = 6;
break;
case 120:
divider = 4;
break;
default:
HAL_ASSERT(false);
}
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
@@ -100,7 +100,6 @@ static inline __attribute__((always_inline)) void mspi_timing_ll_enable_core_clo
PCR.mspi_conf.mspi_clk_en = enable;
}
/**
* Reset the MSPI clock
*/
@@ -128,7 +127,7 @@ static inline uint32_t mspi_timing_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -186,8 +185,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_mode(uint8_t mspi_id, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(mspi_id)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_DIN_MODE_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -202,8 +201,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_num(uint8_t mspi_id, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(mspi_id)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_DIN_NUM_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -370,8 +369,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_mode(uint8_t mspi_id, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_MODE_REG(mspi_id)) & (~(SPI_SMEM_DIN0_MODE_M | SPI_SMEM_DIN1_MODE_M | SPI_SMEM_DIN2_MODE_M | SPI_SMEM_DIN3_MODE_M | SPI_SMEM_DIN4_MODE_M | SPI_SMEM_DIN5_MODE_M | SPI_SMEM_DIN6_MODE_M | SPI_SMEM_DIN7_MODE_M | SPI_SMEM_DINS_MODE_M)))
| (din_mode << SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_SMEM_DINS_MODE_S);
| (din_mode << SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_SMEM_DINS_MODE_S);
REG_WRITE(SPI_SMEM_DIN_MODE_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -386,8 +385,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_num(uint8_t mspi_id, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_SMEM_DIN_NUM_REG(mspi_id)) & (~(SPI_SMEM_DIN0_NUM_M | SPI_SMEM_DIN1_NUM_M | SPI_SMEM_DIN2_NUM_M | SPI_SMEM_DIN3_NUM_M | SPI_SMEM_DIN4_NUM_M | SPI_SMEM_DIN5_NUM_M | SPI_SMEM_DIN6_NUM_M | SPI_SMEM_DIN7_NUM_M | SPI_SMEM_DINS_NUM_M)))
| (din_num << SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_SMEM_DINS_NUM_S);
| (din_num << SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_SMEM_DINS_NUM_S);
REG_WRITE(SPI_SMEM_DIN_NUM_REG(mspi_id), reg_val);
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -404,11 +403,11 @@ static inline void mspi_timing_ll_set_psram_extra_dummy(uint8_t mspi_id, uint8_t
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
}
REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(MSPI_TIMING_LL_MSPI_ID_0), SPI_MEM_TIMING_CALI_UPDATE);
}
@@ -427,7 +426,6 @@ static inline void mspi_timing_ll_get_psram_dummy(uint8_t mspi_id, int *usr_rdum
*extra_dummy = REG_GET_FIELD(SPI_SMEM_TIMING_CALI_REG(mspi_id), SPI_SMEM_EXTRA_DUMMY_CYCLELEN);
}
#ifdef __cplusplus
}
#endif

6
components/hal/esp32c61/include/hal/psram_ctrlr_ll.h → components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h
View File

@@ -153,7 +153,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -166,7 +166,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
typeof(SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
mem_cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
@@ -355,7 +355,7 @@ static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
switch (reg_val) {
case 0:
page_size = 256;
break;

7
components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32c61/include/hal/spi_flash_encrypted_ll.h
View File

@@ -27,8 +27,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -115,7 +114,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
}
}
@@ -125,7 +124,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
}
}

1
components/hal/esp32c61/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32c61/include/hal/spi_flash_ll.h
View File

@@ -102,7 +102,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32c61/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32c61/include/hal/spimem_flash_ll.h
View File

@@ -379,7 +379,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32h2/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32h2/include/hal/gpspi_flash_ll.h
View File

0
components/hal/esp32h2/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32h2/include/hal/mspi_ll.h
View File

7
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32h2/include/hal/spi_flash_encrypted_ll.h
View File

@@ -30,8 +30,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -118,7 +117,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
}
}
@@ -128,7 +127,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
}
}

1
components/hal/esp32h2/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32h2/include/hal/spi_flash_ll.h
View File

@@ -100,7 +100,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32h2/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32h2/include/hal/spimem_flash_ll.h
View File

@@ -367,7 +367,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32h21/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32h21/include/hal/gpspi_flash_ll.h
View File

0
components/hal/esp32h21/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h
View File

7
components/hal/esp32h21/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32h21/include/hal/spi_flash_encrypted_ll.h
View File

@@ -27,8 +27,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -115,7 +114,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
}
}
@@ -125,7 +124,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
while (REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
}
}

1
components/hal/esp32h21/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32h21/include/hal/spi_flash_ll.h
View File

@@ -96,7 +96,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

8
components/hal/esp32h21/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32h21/include/hal/spimem_flash_ll.h
View File

@@ -367,7 +367,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.
@@ -415,7 +414,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
*/
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {};
typeof(dev->user) user = {};
user.usr_mosi = 0;
user.usr_miso = 1;
user.usr_addr = 1;
@@ -446,7 +445,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl;
typeof(dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
@@ -655,7 +654,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -725,7 +724,6 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
dev->user2.val = user2_reg;
}
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE

0
components/hal/esp32h4/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32h4/include/hal/gpspi_flash_ll.h
View File

0
components/hal/esp32h4/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h
View File

6
components/hal/esp32h4/include/hal/psram_ctrlr_ll.h → components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h
View File

@@ -153,7 +153,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -166,7 +166,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
typeof(SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
mem_cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
@@ -355,7 +355,7 @@ static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
switch (reg_val) {
case 0:
page_size = 256;
break;

7
components/hal/esp32h4/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32h4/include/hal/spi_flash_encrypted_ll.h
View File

@@ -28,8 +28,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -116,7 +115,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
}
}
@@ -126,7 +125,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
while (REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
}
}

0
components/hal/esp32h4/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32h4/include/hal/spi_flash_ll.h
View File

8
components/hal/esp32h4/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32h4/include/hal/spimem_flash_ll.h
View File

@@ -365,7 +365,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.
@@ -413,7 +412,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
*/
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {};
typeof(dev->user) user = {};
user.usr_mosi = 0;
user.usr_miso = 1;
user.usr_addr = 1;
@@ -444,7 +443,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl;
typeof(dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
@@ -654,7 +653,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}
@@ -724,7 +723,6 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
dev->user2.val = user2_reg;
}
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE

0
components/hal/esp32p4/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32p4/include/hal/gpspi_flash_ll.h
View File

44
components/hal/esp32p4/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h
View File

@@ -128,8 +128,8 @@ typedef enum {
__attribute__((always_inline))
static inline void _mspi_timing_ll_reset_mspi(void)
{
REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
@@ -225,7 +225,6 @@ static inline void mspi_timing_ll_enable_dqs(bool en)
}
}
/**
* Set all MSPI pin drive
*
@@ -366,7 +365,6 @@ static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t spi_nu
REG_GET_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA);
}
/**
* Set MSPI Flash din mode
*
@@ -378,8 +376,8 @@ static inline void mspi_timing_ll_set_flash_din_mode(uint8_t spi_num, uint8_t di
{
(void)spi_num;
uint32_t reg_val = (REG_READ(SPI_MEM_C_DIN_MODE_REG) & (~(SPI_MEM_C_DIN0_MODE_M | SPI_MEM_C_DIN1_MODE_M | SPI_MEM_C_DIN2_MODE_M | SPI_MEM_C_DIN3_MODE_M | SPI_MEM_C_DIN4_MODE_M | SPI_MEM_C_DIN5_MODE_M | SPI_MEM_C_DIN6_MODE_M | SPI_MEM_C_DIN7_MODE_M | SPI_MEM_C_DINS_MODE_M)))
| (din_mode << SPI_MEM_C_DIN0_MODE_S) | (din_mode << SPI_MEM_C_DIN1_MODE_S) | (din_mode << SPI_MEM_C_DIN2_MODE_S) | (din_mode << SPI_MEM_C_DIN3_MODE_S)
| (din_mode << SPI_MEM_C_DIN4_MODE_S) | (din_mode << SPI_MEM_C_DIN5_MODE_S) | (din_mode << SPI_MEM_C_DIN6_MODE_S) | (din_mode << SPI_MEM_C_DIN7_MODE_S) | (din_mode << SPI_MEM_C_DINS_MODE_S);
| (din_mode << SPI_MEM_C_DIN0_MODE_S) | (din_mode << SPI_MEM_C_DIN1_MODE_S) | (din_mode << SPI_MEM_C_DIN2_MODE_S) | (din_mode << SPI_MEM_C_DIN3_MODE_S)
| (din_mode << SPI_MEM_C_DIN4_MODE_S) | (din_mode << SPI_MEM_C_DIN5_MODE_S) | (din_mode << SPI_MEM_C_DIN6_MODE_S) | (din_mode << SPI_MEM_C_DIN7_MODE_S) | (din_mode << SPI_MEM_C_DINS_MODE_S);
REG_WRITE(SPI_MEM_C_DIN_MODE_REG, reg_val);
REG_SET_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE);
}
@@ -395,8 +393,8 @@ static inline void mspi_timing_ll_set_flash_din_num(uint8_t spi_num, uint8_t din
{
(void)spi_num;
uint32_t reg_val = (REG_READ(SPI_MEM_C_DIN_NUM_REG) & (~(SPI_MEM_C_DIN0_NUM_M | SPI_MEM_C_DIN1_NUM_M | SPI_MEM_C_DIN2_NUM_M | SPI_MEM_C_DIN3_NUM_M | SPI_MEM_C_DIN4_NUM_M | SPI_MEM_C_DIN5_NUM_M | SPI_MEM_C_DIN6_NUM_M | SPI_MEM_C_DIN7_NUM_M | SPI_MEM_C_DINS_NUM_M)))
| (din_num << SPI_MEM_C_DIN0_NUM_S) | (din_num << SPI_MEM_C_DIN1_NUM_S) | (din_num << SPI_MEM_C_DIN2_NUM_S) | (din_num << SPI_MEM_C_DIN3_NUM_S)
| (din_num << SPI_MEM_C_DIN4_NUM_S) | (din_num << SPI_MEM_C_DIN5_NUM_S) | (din_num << SPI_MEM_C_DIN6_NUM_S) | (din_num << SPI_MEM_C_DIN7_NUM_S) | (din_num << SPI_MEM_C_DINS_NUM_S);
| (din_num << SPI_MEM_C_DIN0_NUM_S) | (din_num << SPI_MEM_C_DIN1_NUM_S) | (din_num << SPI_MEM_C_DIN2_NUM_S) | (din_num << SPI_MEM_C_DIN3_NUM_S)
| (din_num << SPI_MEM_C_DIN4_NUM_S) | (din_num << SPI_MEM_C_DIN5_NUM_S) | (din_num << SPI_MEM_C_DIN6_NUM_S) | (din_num << SPI_MEM_C_DIN7_NUM_S) | (din_num << SPI_MEM_C_DINS_NUM_S);
REG_WRITE(SPI_MEM_C_DIN_NUM_REG, reg_val);
REG_SET_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE);
}
@@ -571,21 +569,21 @@ static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t
}
switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK) {
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
}
}

7
components/hal/esp32p4/include/hal/psram_ctrlr_ll.h → components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h
View File

@@ -38,7 +38,6 @@ extern "C" {
#define PSRAM_CTRLR_LL_FIFO_MAX_BYTES 64
/**
* @brief Set PSRAM write cmd
*
@@ -565,7 +564,7 @@ __attribute__((always_inline))
static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t page_size)
{
(void)mspi_id;
switch(page_size) {
switch (page_size) {
case 256:
SPIMEM2.smem_ecc_ctrl.smem_page_size = 0;
break;
@@ -597,7 +596,7 @@ static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id)
uint32_t page_size = 0;
uint32_t reg_val = SPIMEM2.smem_ecc_ctrl.smem_page_size;
switch(reg_val) {
switch (reg_val) {
case 0:
page_size = 256;
break;
@@ -758,7 +757,7 @@ static inline void psram_ctrlr_ll_common_transaction(uint32_t mspi_id,
bool is_write_erase_operation)
{
esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
uint32_t cs_mask = 1<<1;
uint32_t cs_mask = 1 << 1;
psram_ctrlr_ll_common_transaction_base(mspi_id, mode, cmd, cmd_bitlen, addr, addr_bitlen, dummy_bits,
mosi_data, mosi_bitlen, miso_data, miso_bitlen, cs_mask,
is_write_erase_operation);

7
components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32p4/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -114,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) {
while (REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) {
}
}
@@ -124,7 +123,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_MEM_C_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) {
while (REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) {
}
}

1
components/hal/esp32p4/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32p4/include/hal/spi_flash_ll.h
View File

@@ -102,7 +102,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32p4/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32p4/include/hal/spimem_flash_ll.h
View File

@@ -377,7 +377,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

0
components/hal/esp32s2/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h
View File

0
components/hal/esp32s2/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32s2/include/hal/mspi_ll.h
View File

7
components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32s2/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -123,7 +122,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
while (REG_READ(AES_XTS_STATE_REG) == 0x1) {
}
}
@@ -133,7 +132,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(AES_XTS_RELEASE_REG, 1);
while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
while (REG_READ(AES_XTS_STATE_REG) != 0x3) {
}
}

3
components/hal/esp32s3/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32s2/include/hal/spi_flash_ll.h
View File

@@ -45,6 +45,7 @@ typedef union {
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len)
@@ -68,6 +69,7 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
#else
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev)
@@ -99,7 +101,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32s2/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32s2/include/hal/spimem_flash_ll.h
View File

@@ -306,7 +306,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

1
components/hal/esp32s3/include/hal/gpspi_flash_ll.h → components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h
View File

@@ -346,7 +346,6 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
dev->addr = (addr << (32 - bitlen)) | padding_ones;
}
/**
* Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
*

179
components/hal/esp32s3/include/hal/mspi_ll.h → components/esp_hal_mspi/esp32s3/include/hal/mspi_ll.h
View File

@@ -78,7 +78,8 @@ static inline void mspi_timing_ll_set_all_pin_drive(uint8_t spi_num, uint32_t va
IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG};
IO_MUX_GPIO37_REG
};
for (int i = 0; i < ARRAY_SIZE(regs); i++) {
PIN_SET_DRV(regs[i], val);
}
@@ -160,20 +161,20 @@ static inline void mspi_timing_ll_set_core_clock(uint8_t spi_num, uint32_t core_
uint32_t reg_val = 0;
switch (core_clk_mhz) {
case 80:
reg_val = 0;
break;
case 120:
reg_val = 1;
break;
case 160:
reg_val = 2;
break;
case 240:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
case 80:
reg_val = 0;
break;
case 120:
reg_val = 1;
break;
case 160:
reg_val = 2;
break;
case 240:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
@@ -208,7 +209,7 @@ static inline void mspi_timing_ll_set_psram_clock(uint8_t spi_num, uint32_t freq
if (freqdiv == 1) {
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
} else {
uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S);
WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
}
}
@@ -223,8 +224,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
}
@@ -238,8 +239,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_flash_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
}
@@ -259,21 +260,21 @@ static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t
}
switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK) {
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QIO_MODE;
case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
return MSPI_TIMING_LL_FLASH_QUAD_MODE;
case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DIO_MODE;
case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
return MSPI_TIMING_LL_FLASH_DUAL_MODE;
case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
return MSPI_TIMING_LL_FLASH_FAST_MODE;
case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
return MSPI_TIMING_LL_FLASH_SLOW_MODE;
default:
HAL_ASSERT(false);
return (mspi_timing_ll_flash_mode_t)0;
}
}
@@ -290,11 +291,11 @@ static inline void mspi_timing_ll_set_octal_flash_extra_dummy(uint8_t spi_num, u
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
@@ -322,8 +323,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_mode(uint8_t spi_num, uint8_t din_mode)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
}
@@ -337,8 +338,8 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_set_psram_din_num(uint8_t spi_num, uint8_t din_num)
{
uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
}
@@ -354,11 +355,11 @@ static inline void mspi_timing_ll_set_octal_psram_extra_dummy(uint8_t spi_num, u
if (extra_dummy > 0) {
SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
} else {
CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
}
}
@@ -385,7 +386,7 @@ __attribute__((always_inline))
static inline void mspi_timing_ll_clear_fifo(uint8_t spi_num)
{
for (int i = 0; i < 16; i++) {
REG_WRITE(SPI_MEM_W0_REG(spi_num) + i*4, 0);
REG_WRITE(SPI_MEM_W0_REG(spi_num) + i * 4, 0);
}
}
@@ -485,21 +486,21 @@ typedef union {
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_addr(uint8_t spi_num, uint32_t region, uint32_t address)
{
switch(region){
case 0:
SYSCON.flash_ace0_addr = address;
break;
case 1:
SYSCON.flash_ace1_addr = address;
break;
case 2:
SYSCON.flash_ace2_addr = address;
break;
case 3:
SYSCON.flash_ace3_addr = address;
break;
default:
HAL_ASSERT(false);
switch (region) {
case 0:
SYSCON.flash_ace0_addr = address;
break;
case 1:
SYSCON.flash_ace1_addr = address;
break;
case 2:
SYSCON.flash_ace2_addr = address;
break;
case 3:
SYSCON.flash_ace3_addr = address;
break;
default:
HAL_ASSERT(false);
}
}
@@ -514,21 +515,21 @@ static inline void mspi_ll_set_flash_protection_addr(uint8_t spi_num, uint32_t r
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_size(uint8_t spi_num, uint32_t region, uint32_t size)
{
switch(region){
case 0:
SYSCON.flash_ace0_size.flash_ace0_size = size;
break;
case 1:
SYSCON.flash_ace1_size.flash_ace1_size = size;
break;
case 2:
SYSCON.flash_ace2_size.flash_ace2_size = size;
break;
case 3:
SYSCON.flash_ace3_size.flash_ace3_size = size;
break;
default:
HAL_ASSERT(false);
switch (region) {
case 0:
SYSCON.flash_ace0_size.flash_ace0_size = size;
break;
case 1:
SYSCON.flash_ace1_size.flash_ace1_size = size;
break;
case 2:
SYSCON.flash_ace2_size.flash_ace2_size = size;
break;
case 3:
SYSCON.flash_ace3_size.flash_ace3_size = size;
break;
default:
HAL_ASSERT(false);
}
}
@@ -543,21 +544,21 @@ static inline void mspi_ll_set_flash_protection_size(uint8_t spi_num, uint32_t r
__attribute__((always_inline))
static inline void mspi_ll_set_flash_protection_access(uint8_t spi_num, uint32_t region, mspi_ll_flash_ace_ctrl_t ctrl)
{
switch(region){
case 0:
SYSCON.flash_ace0_attr.flash_ace0_attr = ctrl.val;
break;
case 1:
SYSCON.flash_ace1_attr.flash_ace1_attr = ctrl.val;
break;
case 2:
SYSCON.flash_ace2_attr.flash_ace2_attr = ctrl.val;
break;
case 3:
SYSCON.flash_ace3_attr.flash_ace3_attr = ctrl.val;
break;
default:
HAL_ASSERT(false);
switch (region) {
case 0:
SYSCON.flash_ace0_attr.flash_ace0_attr = ctrl.val;
break;
case 1:
SYSCON.flash_ace1_attr.flash_ace1_attr = ctrl.val;
break;
case 2:
SYSCON.flash_ace2_attr.flash_ace2_attr = ctrl.val;
break;
case 3:
SYSCON.flash_ace3_attr.flash_ace3_attr = ctrl.val;
break;
default:
HAL_ASSERT(false);
}
}

2
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h → components/esp_hal_mspi/esp32s3/include/hal/psram_ctrlr_ll.h
View File

@@ -111,7 +111,7 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode)
{
typeof (SPIMEM0.cache_sctrl) cache_sctrl;
typeof(SPIMEM0.cache_sctrl) cache_sctrl;
cache_sctrl.val = SPIMEM0.cache_sctrl.val;
cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);

7
components/hal/esp32s3/include/hal/spi_flash_encrypted_ll.h → components/esp_hal_mspi/esp32s3/include/hal/spi_flash_encrypted_ll.h
View File

@@ -26,8 +26,7 @@ extern "C" {
#endif
/// Choose type of chip you want to encrypt manually
typedef enum
{
typedef enum {
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
@@ -114,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
while (REG_READ(AES_XTS_STATE_REG) == 0x1) {
}
}
@@ -124,7 +123,7 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(AES_XTS_RELEASE_REG, 1);
while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
while (REG_READ(AES_XTS_STATE_REG) != 0x3) {
}
}

4
components/hal/esp32s2/include/hal/spi_flash_ll.h → components/esp_hal_mspi/esp32s3/include/hal/spi_flash_ll.h
View File

@@ -21,7 +21,6 @@
extern "C" {
#endif
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
: gpspi_flash_ll_calculate_clock_reg(clock_div))
@@ -46,7 +45,6 @@ typedef union {
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len)
@@ -70,7 +68,6 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
#else
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev)
@@ -102,7 +99,6 @@ typedef union {
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif
#ifdef __cplusplus

1
components/hal/esp32s3/include/hal/spimem_flash_ll.h → components/esp_hal_mspi/esp32s3/include/hal/spimem_flash_ll.h
View File

@@ -368,7 +368,6 @@ static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const voi
}
}
/**
* Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
* this to set the address to program.

2
components/hal/include/hal/esp_flash_err.h → components/esp_hal_mspi/include/hal/esp_flash_err.h
View File

@@ -17,7 +17,7 @@ extern "C" {
* Possible errors returned from esp flash internal functions, these error codes
* should be consistent with esp_err_t codes. But in order to make the source
* files less dependent to esp_err_t, they use the error codes defined in this
* replacable header. This header should ensure the consistency to esp_err_t.
* replaceable header. This header should ensure the consistency to esp_err_t.
*/
enum {

0
components/hal/include/hal/spi_flash_encrypt_hal.h → components/esp_hal_mspi/include/hal/spi_flash_encrypt_hal.h
View File

0
components/hal/include/hal/spi_flash_encrypt_types.h → components/esp_hal_mspi/include/hal/spi_flash_encrypt_types.h
View File

0
components/hal/include/hal/spi_flash_hal.h → components/esp_hal_mspi/include/hal/spi_flash_hal.h
View File

12
components/hal/include/hal/spi_flash_types.h → components/esp_hal_mspi/include/hal/spi_flash_types.h
View File

@@ -54,16 +54,15 @@ typedef enum {
typedef struct {
uint32_t sus_mask; ///< SUS/SUS1/SUS2 bit in flash register.
struct {
uint32_t cmd_rdsr :8; ///< Read flash status register(2) command.
uint32_t sus_cmd :8; ///< Flash suspend command.
uint32_t res_cmd :8; ///< Flash resume command.
uint32_t reserved :8; ///< Reserved, set to 0.
uint32_t cmd_rdsr : 8; ///< Read flash status register(2) command.
uint32_t sus_cmd : 8; ///< Flash suspend command.
uint32_t res_cmd : 8; ///< Flash resume command.
uint32_t reserved : 8; ///< Reserved, set to 0.
};
} spi_flash_sus_cmd_conf;
/// Structure for flash encryption operations.
typedef struct
{
typedef struct {
/**
* @brief Enable the flash encryption
*/
@@ -111,7 +110,6 @@ typedef struct {
// Implementations can wrap this structure into their own ones, and append other data here
} spi_flash_host_inst_t ;
/** Host driver configuration and context structure. */
struct spi_flash_host_driver_s {
/**

0
components/esp_hal_mspi/linux/include/hal/.gitkeep Normal file
View File

0
components/hal/spi_flash_encrypt_hal_iram.c → components/esp_hal_mspi/spi_flash_encrypt_hal_iram.c
View File

6
components/hal/spi_flash_hal.c → components/esp_hal_mspi/spi_flash_hal.c
View File

@@ -122,11 +122,10 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
} else
#endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING
{
data_out->extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ/get_flash_clock_divider(cfg));
data_out->extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ / get_flash_clock_divider(cfg));
data_out->clock_conf = (spi_flash_ll_clock_reg_t)spi_flash_cal_clock(cfg);
}
if (cfg->auto_sus_en) {
data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND;
data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
@@ -159,11 +158,10 @@ bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void
return direct_write;
}
bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
{
(void)p;
//currently the host doesn't support to read through dma, no word-aligned requirements
bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
bool direct_read = (((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
return direct_read;
}

24
components/hal/spi_flash_hal_common.inc → components/esp_hal_mspi/spi_flash_hal_common.inc
View File

@@ -105,7 +105,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
#ifndef GPSPI_BUILD
#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
// The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
spi_flash_ll_set_dummy_out(dev, (conf_required ? 1 : 0), 1);
#else
/**
* - On current chips, addr phase can support 32 bits at most.
@@ -125,20 +125,20 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
* - DIO is similar.
*/
if (conf_required) {
int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
int line_width = (io_mode == SPI_FLASH_DIO ? 2 : 4);
dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
#endif
spi_flash_ll_set_extra_address(dev, 0);
// TODO: [IDF-13582]
// Currently, REE and TEE use different sets of APIs for flash operations -
// REE uses the IDF SPI flash driver while TEE call the ROM APIs. This inconsistency
// leads to compatibility issues on ESP32-C5.
// One specific issue arises when esp_flash_read() is used in REE, which internally
// calls spi_flash_ll_wb_mode_enable(). This function enables the WB mode bit in
// the flash write operation. However, the ROM API does not support this
// feature, resulting in failures when TEE attempts to access flash after this call.
// TODO: [IDF-13582]
// Currently, REE and TEE use different sets of APIs for flash operations -
// REE uses the IDF SPI flash driver while TEE call the ROM APIs. This inconsistency
// leads to compatibility issues on ESP32-C5.
// One specific issue arises when esp_flash_read() is used in REE, which internally
// calls spi_flash_ll_wb_mode_enable(). This function enables the WB mode bit in
// the flash write operation. However, the ROM API does not support this
// feature, resulting in failures when TEE attempts to access flash after this call.
#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL && !CONFIG_SECURE_ENABLE_TEE
spi_flash_ll_wb_mode_enable(dev, true);
#endif
@@ -146,7 +146,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
#endif
#else
if (conf_required) {
gpspi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
gpspi_flash_ll_set_dummy_out(dev, (conf_required ? 1 : 0), 1);
}
#endif
@@ -155,7 +155,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
unsigned chip_version = efuse_hal_chip_revision();
if (unlikely(!ESP_CHIP_REV_ABOVE(chip_version, 1))) {
if (conf_required) {
int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
int line_width = (io_mode == SPI_FLASH_DIO ? 2 : 4);
dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
spi_flash_ll_set_extra_address(dev, 0);

0
components/hal/spi_flash_hal_gpspi.c → components/esp_hal_mspi/spi_flash_hal_gpspi.c
View File

8
components/hal/spi_flash_hal_iram.c → components/esp_hal_mspi/spi_flash_hal_iram.c
View File

@@ -29,7 +29,7 @@ void spi_flash_hal_erase_chip(spi_flash_host_inst_t *host)
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_erase_chip(dev);
#if SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
if((((spi_flash_hal_context_t*)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
if ((((spi_flash_hal_context_t *)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
host->driver->poll_cmd_done(host);
}
#else
@@ -46,7 +46,7 @@ void spi_flash_hal_erase_sector(spi_flash_host_inst_t *host, uint32_t start_addr
spi_flash_ll_erase_sector(dev);
#if SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
if((((spi_flash_hal_context_t*)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
if ((((spi_flash_hal_context_t *)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
host->driver->poll_cmd_done(host);
}
#else
@@ -62,7 +62,7 @@ void spi_flash_hal_erase_block(spi_flash_host_inst_t *host, uint32_t start_addre
spi_flash_ll_set_address(dev, start_address & ADDRESS_MASK_24BIT);
spi_flash_ll_erase_block(dev);
#if SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
if((((spi_flash_hal_context_t*)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
if ((((spi_flash_hal_context_t *)host)->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) == 0) {
host->driver->poll_cmd_done(host);
}
#else
@@ -114,7 +114,7 @@ uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
#endif
// Not clear if this is necessary, or only necessary if
// chip->spi == SPI1. But probably doesn't hurt...
if ((void*) dev == spi_flash_ll_get_hw(SPI1_HOST)) {
if ((void *) dev == spi_flash_ll_get_hw(SPI1_HOST)) {
#if SOC_IS(ESP32)
status &= spi_flash_ll_host_idle(&SPI0);
#endif

2
components/esp_hw_support/CMakeLists.txt
View File

@@ -78,7 +78,7 @@ if(NOT non_os_build)
esp_timer
esp_pm)
list(APPEND priv_requires esp_mm)
list(APPEND priv_requires esp_mm esp_hal_mspi)
if(CONFIG_IDF_TARGET_ESP32 OR CONFIG_IDF_TARGET_ESP32S2)
list(APPEND srcs "rtc_wdt.c")

2
components/esp_hw_support/test_apps/mspi/main/CMakeLists.txt
View File

@@ -7,5 +7,5 @@ set(srcs
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_timer spi_flash esp_partition
PRIV_REQUIRES unity esp_timer spi_flash esp_partition esp_hal_mspi
WHOLE_ARCHIVE)

1
components/esp_pm/pm_impl.c
View File

@@ -28,7 +28,6 @@
#include "hal/clk_tree_ll.h"
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
#include "hal/mspi_ll.h"
#include "driver/gpio.h"

2
components/esp_psram/CMakeLists.txt
View File

@@ -10,7 +10,7 @@ if(CONFIG_SOC_SPIRAM_XIP_SUPPORTED)
list(APPEND includes xip_impl/include)
endif()
set(priv_requires heap spi_flash esp_mm)
set(priv_requires heap spi_flash esp_mm esp_hal_mspi)
if(${target} STREQUAL "esp32")
list(APPEND priv_requires bootloader_support esp_driver_spi esp_driver_gpio)
endif()

1
components/esp_psram/test_apps/.build-test-rules.yml
View File

@@ -10,3 +10,4 @@ components/esp_psram/test_apps/psram:
- esp_driver_gpio
- esp_driver_spi
- spi_flash
- esp_hal_mspi

2
components/esp_system/CMakeLists.txt
View File

@@ -72,7 +72,7 @@ else()
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS include
PRIV_REQUIRES spi_flash esp_timer esp_mm
PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_mspi
# [refactor-todo] requirements due to init code,
# should be removable once using component init functions
# link-time registration is used.

17
components/hal/CMakeLists.txt
View File

@@ -58,22 +58,9 @@ if(esp_tee_build)
"hmac_hal.c"
"ds_hal.c"
"ecc_hal.c")
if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
list(APPEND srcs "spi_flash_hal.c")
endif()
elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "color_hal.c")
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
if(CONFIG_SOC_SPI_FLASH_SUPPORTED)
list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c")
endif()
if(CONFIG_SOC_FLASH_ENC_SUPPORTED)
list(APPEND srcs "spi_flash_encrypt_hal_iram.c")
endif()
endif()
if(CONFIG_SOC_CLK_TREE_SUPPORTED)
list(APPEND srcs "${target}/clk_tree_hal.c")
endif()
@@ -263,10 +250,6 @@ elseif(NOT BOOTLOADER_BUILD)
endif()
endif()
if(CONFIG_SOC_GPSPI_SUPPORTED AND NOT CONFIG_IDF_TARGET_ESP32)
list(APPEND srcs "spi_flash_hal_gpspi.c")
endif()
if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
list(APPEND srcs "sdio_slave_hal.c")
endif()

3
components/spi_flash/CMakeLists.txt
View File

@@ -6,6 +6,7 @@ if(${target} STREQUAL "linux")
"linux/cache_utils.c"
"linux/flash_mmap.c"
INCLUDE_DIRS include
REQUIRES esp_hal_mspi
PRIV_INCLUDE_DIRS include/spi_flash)
return()
endif()
@@ -60,7 +61,7 @@ else()
endif()
idf_component_register(SRCS "${srcs}"
REQUIRES hal
REQUIRES hal esp_hal_mspi
PRIV_REQUIRES "${priv_requires}"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS include/spi_flash

2
components/spi_flash/linker.lf
View File

@@ -74,7 +74,7 @@ entries:
spi_flash_hpm_enable (noflash)
[mapping:spi_flash_hal]
archive: libhal.a
archive: libesp_hal_mspi.a
entries:
if SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM = y:
spi_flash_hal_iram (noflash)

6
components/spi_flash/test_apps/.build-test-rules.yml
View File

@@ -14,6 +14,7 @@ components/spi_flash/test_apps/esp_flash:
- esp_driver_gpio
- esp_driver_spi
- esptool_py # Some flash related kconfigs are listed here.
- esp_hal_mspi
components/spi_flash/test_apps/esp_flash_stress:
disable:
@@ -23,6 +24,7 @@ components/spi_flash/test_apps/esp_flash_stress:
depends_components:
- esp_mm
- spi_flash
- esp_hal_mspi
components/spi_flash/test_apps/flash_encryption:
disable:
@@ -37,11 +39,13 @@ components/spi_flash/test_apps/flash_encryption:
depends_components:
- esp_mm
- spi_flash
- esp_hal_mspi
components/spi_flash/test_apps/flash_mmap:
depends_components:
- esp_mm
- spi_flash
- esp_hal_mspi
enable:
- if: CONFIG_NAME == "release" and IDF_TARGET != "linux"
- if: CONFIG_NAME == "rom_impl" and ESP_ROM_HAS_SPI_FLASH == 1
@@ -64,6 +68,7 @@ components/spi_flash/test_apps/flash_suspend:
depends_components:
- spi_flash
- esp_driver_gptimer
- esp_hal_mspi
components/spi_flash/test_apps/mspi_test:
disable:
@@ -78,3 +83,4 @@ components/spi_flash/test_apps/mspi_test:
- esp_driver_gpio
- esp_driver_spi
- esptool_py # Some flash related kconfigs are listed here.
- esp_hal_mspi

4
docs/doxygen/Doxyfile
View File

@@ -163,6 +163,8 @@ INPUT = \
$(PROJECT_PATH)/components/esp_event/include/esp_event.h \
$(PROJECT_PATH)/components/esp_hal_timg/include/hal/timer_types.h \
$(PROJECT_PATH)/components/esp_hal_i2c/include/hal/i2c_types.h \
$(PROJECT_PATH)/components/esp_hal_mspi/include/hal/esp_flash_err.h \
$(PROJECT_PATH)/components/esp_hal_mspi/include/hal/spi_flash_types.h \
$(PROJECT_PATH)/components/esp_http_client/include/esp_http_client.h \
$(PROJECT_PATH)/components/esp_http_server/include/esp_http_server.h \
$(PROJECT_PATH)/components/esp_https_ota/include/esp_https_ota.h \
@@ -250,7 +252,6 @@ INPUT = \
$(PROJECT_PATH)/components/hal/include/hal/adc_types.h \
$(PROJECT_PATH)/components/hal/include/hal/color_types.h \
$(PROJECT_PATH)/components/hal/include/hal/dac_types.h \
$(PROJECT_PATH)/components/hal/include/hal/esp_flash_err.h \
$(PROJECT_PATH)/components/hal/include/hal/gpio_types.h \
$(PROJECT_PATH)/components/hal/include/hal/i2s_types.h \
$(PROJECT_PATH)/components/hal/include/hal/lcd_types.h \
@@ -262,7 +263,6 @@ INPUT = \
$(PROJECT_PATH)/components/hal/include/hal/rtc_io_types.h \
$(PROJECT_PATH)/components/hal/include/hal/sdio_slave_types.h \
$(PROJECT_PATH)/components/hal/include/hal/sdm_types.h \
$(PROJECT_PATH)/components/hal/include/hal/spi_flash_types.h \
$(PROJECT_PATH)/components/hal/include/hal/spi_types.h \
$(PROJECT_PATH)/components/hal/include/hal/temperature_sensor_types.h \
$(PROJECT_PATH)/components/hal/include/hal/twai_types.h \

2
docs/en/api-reference/peripherals/spi_flash/index.rst
View File

@@ -184,7 +184,7 @@ The ``esp_flash_t`` structure holds chip data as well as three important parts o
Host Driver
^^^^^^^^^^^
The host driver relies on an interface (``spi_flash_host_driver_t``) defined in the ``spi_flash_types.h`` (in the ``hal/include/hal`` folder). This interface provides some common functions to communicate with the chip.
The host driver relies on an interface (``spi_flash_host_driver_t``) defined in the ``spi_flash_types.h`` (in the ``esp_hal_mspi/include/hal`` folder). This interface provides some common functions to communicate with the chip.
In other files of the SPI HAL, some of these functions are implemented with existing {IDF_TARGET_NAME} memory-spi functionalities. However, due to the speed limitations of {IDF_TARGET_NAME}, the HAL layer cannot provide high-speed implementations to some reading commands (so the support for it was dropped). The files (``memspi_host_driver.h`` and ``.c``) implement the high-speed version of these commands with the ``common_command`` function provided in the HAL, and wrap these functions as ``spi_flash_host_driver_t`` for upper layer to use.

2
docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
View File

@@ -184,7 +184,7 @@ SPI flash 实现
主机驱动
^^^^^^^^^^^^^^^
主机驱动依赖 ``hal/include/hal`` 文件夹下 ``spi_flash_types.h`` 定义的 ``spi_flash_host_driver_t`` 接口。该接口提供了一些常用的函数，用于与芯片通信。
主机驱动依赖 ``esp_hal_mspi/include/hal`` 文件夹下 ``spi_flash_types.h`` 定义的 ``spi_flash_host_driver_t`` 接口。该接口提供了一些常用的函数，用于与芯片通信。
在 SPI HAL 文件中，有些函数是基于现有的 {IDF_TARGET_NAME} memory-spi 来实现的。但是，由于 {IDF_TARGET_NAME} 的速度限制，HAL 层无法提供某些读命令的高速实现（所以这些命令根本没有在 HAL 的文件中被实现）。``memspi_host_driver.h`` 和 ``.c`` 文件使用 HAL 提供的 ``common_command`` 函数实现上述读命令的高速版本，并将所有它实现的以及 HAL 函数封装为 ``spi_flash_host_driver_t`` 供更上层调用。