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docs(i2s): update i2s cap overview

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This commit is contained in:
laokaiyao
2024-11-13 16:34:57 +08:00
parent 1a685b7e1c
commit 3ea47a6cf3
3 changed files with 13 additions and 2 deletions
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9
components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
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@ -182,8 +182,17 @@ static void test_i2s_tdm_slave(uint32_t sample_rate, i2s_data_bit_width_t bit_wi
}; };
#if SOC_I2S_SUPPORTS_APLL #if SOC_I2S_SUPPORTS_APLL
i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL; i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
/* APLL clock source can only reach upto 125MHz, and the max BCLK among these cases is 6.144 MHz
The BCLK can only be 10 using APLL clock source, see the reason below
Formula: MAX_BCLK = 48K * 32 * 4 = 6.144 MHz. MAX_BCLK_DIV <= (125 /2) / MAX_BCLK */
i2s_tdm_config.clk_cfg.bclk_div = 10; i2s_tdm_config.clk_cfg.bclk_div = 10;
#else #else
/* The greater the bclk division is, the greater mclk frequency will be, and the less data latency the slave will have
As the sample rate of the test cases are high, we need a greater BCLK division to reduce the slave data latency,
Otherwise the large data latency will cause the data shifted when receiving on the master side.
However, due to the MCLK limitation(i.e., less or equal than half of the source clock),
the max bclk division is depended on the source clock, sample rate and the bclk ticks in one frame
Formula: MAX_BCLK = 48K * 32 * 4 = 6.144 MHz. MAX_BCLK_DIV <= (160 /2) / MAX_BCLK */
i2s_tdm_config.clk_cfg.bclk_div = 12; i2s_tdm_config.clk_cfg.bclk_div = 12;
#endif #endif
TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config)); TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config));

3
docs/en/api-reference/peripherals/i2s.rst
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@ -125,7 +125,8 @@ ESP32-C6 I2S 0 I2S 0 none I2S 0 none none
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none none ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none none
ESP32-H2 I2S 0 I2S 0 none I2S 0 none none ESP32-H2 I2S 0 I2S 0 none I2S 0 none none
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 none none ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 none none
ESP32-C5 I2S 0 I2S 0 none I2S 0 none none ESP32-C5 I2S 0 I2S 0 I2S 0 I2S 0 none none
ESP32-C61 I2S 0 I2S 0 I2S 0 I2S 0 none none
========= ======== ======== ======== ======== ======== ========== ========= ======== ======== ======== ======== ======== ==========
Standard Mode Standard Mode

3
docs/zh_CN/api-reference/peripherals/i2s.rst
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@ -125,7 +125,8 @@ ESP32-C6 I2S 0 I2S 0 无 I2S 0 无 无
ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 无 无 ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 无 无
ESP32-H2 I2S 0 I2S 0 无 I2S 0 无 无 ESP32-H2 I2S 0 I2S 0 无 I2S 0 无 无
ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 无 无 ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 无 无
ESP32-C5 I2S 0 I2S 0 无 I2S 0 无 无 ESP32-C5 I2S 0 I2S 0 I2S 0 I2S 0 无 无
ESP32-C61 I2S 0 I2S 0 I2S 0 I2S 0 无 无
========= ======== ======== ======== ======== ======== ========== ========= ======== ======== ======== ======== ======== ==========
标准模式 标准模式