diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index 2edcf6661b..c28befda31 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -92,6 +92,40 @@ static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, ~cfg.fe_pd); } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = 0, + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .rom_mem_pd_en = 0, + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .lslp_meminf_pd = 1, + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, + }; + + if ((sleep_flags) & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; + out_config->dbg_atten_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_NODROP : RTC_CNTL_DBG_ATTEN_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_NODROP; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { // set shortest possible sleep time limit diff --git a/components/esp_hw_support/port/esp32c3/rtc_pm.c b/components/esp_hw_support/port/esp32c3/rtc_pm.c index 58f2719418..1be846c097 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_pm.c +++ b/components/esp_hw_support/port/esp32c3/rtc_pm.c @@ -53,9 +53,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par switch (sleep_mode) { case PM_LIGHT_SLEEP: cfg.wifi_pd_en = 1; - cfg.dig_dbias_wak = 4; cfg.dig_dbias_slp = 0; - cfg.rtc_dbias_wak = 0; cfg.rtc_dbias_slp = 0; rtc_sleep_init(cfg); break; diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index 24f83baf32..b985152ef8 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -62,6 +62,114 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) } } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0, + .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + assert(sleep_flags & RTC_SLEEP_PD_XTAL); + bool eco2_workaround = false; + #if CONFIG_ESP32C3_REV_MIN_FULL < 3 + if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) { + eco2_workaround = true; /* workaround for deep sleep issue in high temp on ECO2 and below */ + } + #endif + if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * dbg_att_slp need to set to 0: rtc voltage is about 0.83v + * support all features: + * - 8MD256 as RTC slow clock src + * - RTC memory under high temperature + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + out_config->rtc_dbias_slp = 0; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + /* + * Default mode + * rtc voltage in sleep need stable and not less than 0.7v + * support features: + * - RTC memory under high temperature + * - RTC IO as input + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7; + } else { + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power): + * not support features: + * - RTC IO as input + * - RTC memory under high temperature + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = 0; /* not used */ + } + } else { + out_config->rtc_regulator_fpu = 1; + // rtc & digital voltage from high to low + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { + /* + * digital voltage need to be >= 1.1v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){ + /* + * dbg_att_slp need to set to 0: digital voltage is about 0.67v & rtc vol is about 0.83v + * Support features: + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = 0; + out_config->rtc_dbias_slp = 0; + } else { + /* + * digital voltage not less than 0.6v. + * not support features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6; + } + } + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } else { + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -90,24 +198,19 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + if (cfg.deep_slp) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; -#if CONFIG_ESP32C3_REV_MIN_FULL < 3 - if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) { - atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ - } -#endif - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -115,12 +218,10 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); @@ -133,9 +234,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); diff --git a/components/esp_hw_support/port/esp32s2/rtc_pm.c b/components/esp_hw_support/port/esp32s2/rtc_pm.c index 2f63dc8beb..cfa5df0994 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_pm.c +++ b/components/esp_hw_support/port/esp32s2/rtc_pm.c @@ -53,9 +53,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par switch (sleep_mode) { case PM_LIGHT_SLEEP: cfg.wifi_pd_en = 1; - cfg.dig_dbias_wak = 4; cfg.dig_dbias_slp = 0; - cfg.rtc_dbias_wak = 0; cfg.rtc_dbias_slp = 0; rtc_sleep_init(cfg); break; diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index f99dd1331f..3e27a73197 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -52,6 +52,124 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + assert(sleep_flags & RTC_SLEEP_PD_XTAL); + out_config->dig_dbias_slp = 0; //not used + //rtc voltage from high to low + if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * rtc voltage in sleep mode >= 0.9v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * Support all features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - 8MD256 as RTC slow clock src + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + /* + * rtc voltage in sleep mode >= 0.7v (default mode) + * Support features: + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7; + } else { + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power) + * Support features: + * - ULP + * - Touch sensor + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = 0; + } + } else { + out_config->rtc_regulator_fpu = 1; + // rtc & digital voltage from high to low + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) { + /* + * digital voltage need to be >= 1.1v + * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0 + * rtc voltage need to near digital voltage to keep system stable + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0) + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { + /* + * rtc voltage need to be >= 0.9v + * digital voltage need to near rtc voltage to make system stable and low current + * Support features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9; + } else { + /* + * digital voltage not less than 0.75v. + * rtc voltage need to near digital voltage to keep system stable + * Support features: + * - ULP + * - Touch sensor + */ + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75; + out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75; + } + } + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } else { + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)? + RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -97,27 +215,29 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } + assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + if (cfg.deep_slp) { - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); } else { - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { @@ -128,11 +248,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */ diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index 1f1de73d8f..cfa52baf96 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -60,6 +60,54 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) } } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0, + .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -105,14 +153,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + if (cfg.deep_slp) { CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -120,18 +174,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); } /* enable VDDSDIO control by state machine */ REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); } diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index 07913385f8..a6325cbe54 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -180,6 +180,10 @@ static bool s_light_sleep_wakeup = false; static portMUX_TYPE spinlock_rtc_deep_sleep = portMUX_INITIALIZER_UNLOCKED; static const char *TAG = "sleep"; +static RTC_FAST_ATTR bool s_adc_tsen_enabled = false; +//in this mode, 2uA is saved, but RTC memory can't use at high temperature, and RTCIO can't be used as INPUT. +static bool s_ultra_low_enabled = false; + static bool s_periph_use_8m_flag = false; @@ -639,8 +643,21 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) #endif } + //Append some flags in addition to power domains + uint32_t sleep_flags = pd_flags; + if (s_adc_tsen_enabled) { + sleep_flags |= RTC_SLEEP_USE_ADC_TESEN_MONITOR; + } + if (!s_ultra_low_enabled) { + sleep_flags |= RTC_SLEEP_NO_ULTRA_LOW; + } + if (rtc_dig_8m_enabled()) { + sleep_flags |= RTC_SLEEP_DIG_USE_8M; + } + // Enter sleep - rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); + rtc_sleep_config_t config; + rtc_sleep_get_default_config(sleep_flags, &config); rtc_sleep_init(config); rtc_sleep_low_init(s_config.rtc_clk_cal_period); @@ -1518,3 +1535,13 @@ void esp_deep_sleep_disable_rom_logging(void) { esp_rom_disable_logging(); } + +void esp_sleep_enable_adc_tsens_monitor(bool enable) +{ + s_adc_tsen_enabled = enable; +} + +void rtc_sleep_enable_ultra_low(bool enable) +{ + s_ultra_low_enabled = enable; +} diff --git a/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt b/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt new file mode 100644 index 0000000000..a5579444f2 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt @@ -0,0 +1,7 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.5) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(rtc_power_modes) diff --git a/components/esp_system/test_apps/rtc_power_modes/README.md b/components/esp_system/test_apps/rtc_power_modes/README.md new file mode 100644 index 0000000000..5c923a3eee --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/README.md @@ -0,0 +1,19 @@ +| Supported Targets | ESP32-S3 | +| ----------------- | -------- | + +# RTC power test + +This test app is to enter 7 different sub power modes we have, so that the power consumption under different power modes can be measured. + +Currently there are 6 sub power modes, 3 for deepsleep and 3 for lightsleep. Show as below (priority from high to low). + +## Deepsleep +1. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mode, call `rtc_sleep_enable_adc_tesn_monitor`. +2. Default mode. +3. Ultra low power mode. To enable this mode, call `rtc_sleep_enable_ultra_low`. Note if mode 1 has higher priority than this. + +## Lightsleep +1. Mode for using 40 MHz XTAL in lightsleep. To enable this mode, call `esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)`. +2. Mode for using 8M clock by digital system (peripherals). To enable this mode, initialize LEDC with 8M clock source. +3. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mdoe, call `rtc_sleep_enable_adc_tesn_monitor`. +4. Default mode. diff --git a/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt b/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt new file mode 100644 index 0000000000..201f4fcddb --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "test_rtc_power.c" + PRIV_REQUIRES unity) diff --git a/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c b/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c new file mode 100644 index 0000000000..1d34b63e44 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "unity_test_utils.h" + +#define LEAKS (400) + + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + unity_utils_evaluate_leaks_direct(LEAKS); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c b/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c new file mode 100644 index 0000000000..16d9ff09c2 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_sleep.h" +#include "unity.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/uart.h" +#include "soc/soc_caps.h" +#include "driver/ledc.h" +#include "soc/rtc.h" + +static const char TAG[] = "rtc_power"; + +static void test_deepsleep(void) +{ + esp_sleep_enable_timer_wakeup(2000000); + ESP_LOGI(TAG, "Entering deep sleep"); + esp_deep_sleep_start(); +} + +TEST_CASE("Power Test: Deepsleep (with ADC/TSEN in monitor)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_adc_tesn_monitor(bool); + rtc_sleep_enable_adc_tesn_monitor(true); + test_deepsleep(); +} + +TEST_CASE("Power Test: Deepsleep (default)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + test_deepsleep(); +} + +TEST_CASE("Power Test: Deepsleep (ultra-low power)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_ultra_low(bool); + rtc_sleep_enable_ultra_low(true); + test_deepsleep(); +} + +static void test_lightsleep(void) +{ + esp_sleep_enable_timer_wakeup(2000000); + + while (true) { + printf("Entering light sleep\n"); + /* To make sure the complete line is printed before entering sleep mode, + * need to wait until UART TX FIFO is empty: + */ + uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM); + + /* Enter sleep mode */ + esp_light_sleep_start(); + + /* Determine wake up reason */ + const char* wakeup_reason; + switch (esp_sleep_get_wakeup_cause()) { + case ESP_SLEEP_WAKEUP_TIMER: + wakeup_reason = "timer"; + break; + default: + wakeup_reason = "other"; + break; + } + printf("Returned from light sleep, reason: %s\n", wakeup_reason); + + vTaskDelay(1000/portTICK_PERIOD_MS); + } +} + +TEST_CASE("Power Test: Lightsleep (XTAL 40M)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (8M by digital)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + ledc_timer_config_t config = { + .speed_mode = LEDC_LOW_SPEED_MODE, + .duty_resolution = LEDC_TIMER_12_BIT, + .timer_num = 0, + .freq_hz = 2 * 1000, + .clk_cfg = LEDC_USE_RTC8M_CLK, + }; + ledc_timer_config(&config); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (with ADC/TSEN in monitor)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_adc_tesn_monitor(bool); + rtc_sleep_enable_adc_tesn_monitor(true); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (default)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + test_lightsleep(); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults b/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults new file mode 100644 index 0000000000..b308cb2ddd --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index bf8bfa11e6..3a5ad9de5e 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -517,43 +517,6 @@ typedef struct rtc_sleep_config_s { uint32_t dbg_atten_slp : 2; //!< voltage parameter } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .rom_mem_pd_en = 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_0V90, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_0V90, \ - .lslp_meminf_pd = 1, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .dbg_atten_slp = !is_dslp(sleep_flags) ? RTC_CNTL_DBG_ATTEN_NODROP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_NODROP \ - : RTC_CNTL_DBG_ATTEN_DEFAULT, \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -563,6 +526,21 @@ typedef struct rtc_sleep_config_s { #define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL #define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /* Various delays to be programmed into power control state machines */ #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000) #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index c6e0a0ff70..cf6fe21a43 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -269,6 +269,8 @@ /*-------------------------- Power Management CAPS ---------------------------*/ #define SOC_PM_SUPPORT_EXT_WAKEUP (1) +#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) + /* ---------------------------- Compatibility ------------------------------- */ #define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED #define CAN_BRP_MIN SOC_TWAI_BRP_MIN diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 9a0c95a210..b52c248439 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -62,7 +62,6 @@ extern "C" { /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. */ -#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias #define RTC_CNTL_DBIAS_0V90 13 //digital voltage #define RTC_CNTL_DBIAS_0V95 16 #define RTC_CNTL_DBIAS_1V00 18 @@ -111,14 +110,27 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 25 + +/* +use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5 /* The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value @@ -651,52 +663,18 @@ typedef struct { uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -710,6 +688,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 053ddeac2f..1503f34892 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -123,13 +123,30 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 + +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 +#define RTC_CNTL_BIASSLP_MONITOR_ON 0 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_ON 0 + +/* +use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 RTC_CNTL_DBIAS_1V25 + +/* +use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT +*/ +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9 5 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9 4 +#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75 0 +#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75 1 #define APLL_SDM_STOP_VAL_1 0x09 #define APLL_SDM_STOP_VAL_2_REV0 0x69 @@ -674,51 +691,20 @@ typedef struct { uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DIG_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DIG_DBIAS_1V10 \ - : !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DIG_DBIAS_1V10 \ - : RTC_CNTL_DIG_DBIAS_0V90, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_1V00 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_1V00, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -729,6 +715,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(8) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 6bed59e117..ffdcd96a50 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -316,9 +316,9 @@ #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) /*-------------------------- Power Management CAPS ---------------------------*/ #define SOC_PM_SUPPORT_EXT_WAKEUP (1) - #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) #define SOC_PM_SUPPORT_WIFI_PD (1) /* ---------------------------- Compatibility ------------------------------- */ diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 593a58613f..52647edf98 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -645,37 +645,17 @@ typedef struct { uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -686,6 +666,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index a8aa73f9ec..735dd98cbf 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -151,14 +151,13 @@ /*-------------------------- Power Management CAPS ---------------------------*/ #define SOC_PM_SUPPORT_EXT_WAKEUP (1) - #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - +#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) /* Has a centralized DMA, which is shared with all peripherals */ #define SOC_AES_GDMA (1) + #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_256 (1) diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index abda314691..7a779aac82 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -72,7 +72,6 @@ build_stage2() { CONFIG_STR=$(get_config_str sdkconfig.ci.*=) search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} - search_cmake esp32s3 ${CONFIG_STR} search_cmake esp32c3 ${CONFIG_STR} CONFIG_STR=$(get_config_str sdkconfig.ci.*= sdkconfig.ci2.*=) @@ -84,7 +83,6 @@ build_stage2() { search_make esp32 ${CONFIG_STR} search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} - search_cmake esp32s3 ${CONFIG_STR} search_cmake esp32c3 ${CONFIG_STR} # Override EXTRA_CFLAGS and EXTRA_CXXFLAGS in the environment @@ -97,7 +95,6 @@ build_stage1() { CONFIG_STR=$(get_config_str sdkconfig.ci2.*=) search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} - search_cmake esp32s3 ${CONFIG_STR} search_cmake esp32c3 ${CONFIG_STR} build