diff --git a/components/hal/esp32p4/include/hal/usb_utmi_ll.h b/components/hal/esp32p4/include/hal/usb_utmi_ll.h
index f58d72f9f5..e8a21547c0 100644
--- a/components/hal/esp32p4/include/hal/usb_utmi_ll.h
+++ b/components/hal/esp32p4/include/hal/usb_utmi_ll.h
@@ -16,12 +16,27 @@
 extern "C" {
 #endif
 
+/* ---------------------------- USB PHY Control  ---------------------------- */
+
+/**
+ * @brief Configure Low-Speed mode
+ *
+ * @param[in] hw       Beginning address of the peripheral registers
+ * @param[in] parallel Parallel or serial LS mode
+ * @return FORCE_INLINE_ATTR
+ */
+FORCE_INLINE_ATTR void usb_utmi_ll_configure_ls(usb_utmi_dev_t *hw, bool parallel)
+{
+    hw->fc_06.ls_par_en = parallel;
+    hw->fc_06.ls_kpalv_en = 1;
+}
+
 /* ----------------------------- RCC Functions  ----------------------------- */
 
 /**
  * @brief Enable the bus clock for the USB UTMI PHY and USB_DWC_HS controller
  *
- * @param clk_en True to enable, false to disable
+ * @param[in] clk_en True to enable, false to disable
  */
 FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
 {
@@ -39,8 +54,11 @@ FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
  */
 FORCE_INLINE_ATTR void usb_utmi_ll_reset_register(void)
 {
+    //@todo call this function somewhere
     // Reset the USB_UTMI and USB_DWC_HS
     LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20 = 1;
+    LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20_phy = 1;
+    LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20_phy = 0;
     LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20 = 0;
 }
 
diff --git a/components/soc/esp32p4/include/soc/usb_utmi_struct.h b/components/soc/esp32p4/include/soc/usb_utmi_struct.h
index fa2c9f9c92..29c8ff745d 100644
--- a/components/soc/esp32p4/include/soc/usb_utmi_struct.h
+++ b/components/soc/esp32p4/include/soc/usb_utmi_struct.h
@@ -12,6 +12,11 @@
 extern "C" {
 #endif
 
+/**
+ * Following register description is taken from
+ * U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
+ */
+
 typedef union {
     struct {
         /** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
@@ -93,38 +98,130 @@ typedef union {
           * PLL adjustment signal
           */
         uint32_t adj_pll:4;
-        /** adj_osc : R/W; bitpos: [4]; default: 2'b00
-          * PLL adjustment signal
+        /** adj_osc : R/W; bitpos: [4]; default: 3'b000
+          * TX Clock phase adjust signal
           */
-        uint32_t adj_osc:2;
-        uint32_t reserved_6:26;
+        uint32_t adj_txclk_phase:3;
+        uint32_t reserved_7:25;
     };
     uint32_t val;
 } usb_utmi_fc_03_reg_t;
 
 typedef union {
     struct {
-        /** reserved_out5 : R/W; bitpos: [0]; default: 8'b0
-          * RESERVED_OUT5
+        /** test_sel : R/W; bitpos: [0]; default: 8'b0
+          * The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
+          * In our implementation output of this register is left floating and DTO is driven from Probe module.
+          * Thus writing to this register has no effect and is renamed to 'reserved'
           */
-        uint32_t reserved_out5:8;
+        uint32_t reserved:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
 } usb_utmi_fc_04_reg_t;
 
+typedef union {
+    struct {
+        /** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
+          * RXGAP fix enable
+          */
+        uint32_t rxgap_fix_en:1;
+        /** counter_sel : R/W; bitpos: [1]; default: 1'b0
+          * SIE_input sample enable
+          */
+        uint32_t counter_sel:1;
+        /** clk_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK60_30 source select
+          */
+        uint32_t clk_sel:1;
+        /** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
+          * PHY MODE select
+          */
+        uint32_t phy_mode_sel:1;
+        /** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
+          * UNI_BIDI signal
+          */
+        uint32_t uni_bidi_i:1;
+        /** short_5v : R/W; bitpos: [5]; default: 1'b0
+          * SHORT_5V signal
+          */
+        uint32_t short_5v:1;
+        /** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
+          * SHORT_5V_ENABLE signal
+          */
+        uint32_t short_5v_enable:1;
+        /** usable_en : R/W; bitpos: [7]; default: 1'b1
+          * compare_begin delay time select
+          */
+        uint32_t usable_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} usb_utmi_fc_05_reg_t;
+
+typedef union {
+    struct {
+        /** ls_par_en : R/W; bitpos: [0]; default: 1'b0
+          * LS mode with parallel enable
+          */
+        uint32_t ls_par_en:1;
+        /** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
+          * FS EOP detect enable
+          */
+        uint32_t det_fseop_en:1;
+        /** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
+          * Dis_preamble enable
+          */
+        uint32_t pre_hphy_lsie:1;
+        /** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
+          * LS mode keep alive enable
+          */
+        uint32_t ls_kpalv_en:1;
+        /** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
+          * PHY High-SPeed bus turn-around time select
+          */
+        uint32_t hs_tx2rx_dly_cnt_sel:3;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_utmi_fc_06_reg_t;
+
+typedef union {
+    struct {
+        /** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
+          * 3 ms counter select
+          * 00: 392us (Default)
+          * 01: 682us
+          * 10: 1.36ms
+          * 11: 2.72ms
+          */
+        uint32_t cnt_num:2;
+        /** clk480_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK_480 output time select
+          * 0: CLK_480 is valid after a delay time when PLL is locked
+          * 1: CLK_480 is valid immediately after PLL is locked
+          */
+        uint32_t clk480_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_utmi_fc_07_reg_t;
+
 typedef struct usb_utmi_dev_t {
     volatile usb_utmi_fc_00_reg_t fc_00;
     volatile usb_utmi_fc_01_reg_t fc_01;
     volatile usb_utmi_fc_02_reg_t fc_02;
     volatile usb_utmi_fc_03_reg_t fc_03;
-    usb_utmi_fc_04_reg_t fc_04;
+    volatile usb_utmi_fc_04_reg_t fc_04;
+    volatile usb_utmi_fc_05_reg_t fc_05;
+    volatile usb_utmi_fc_06_reg_t fc_06;
+    volatile usb_utmi_fc_07_reg_t fc_07;
 } usb_utmi_dev_t;
 
 extern usb_utmi_dev_t USB_UTMI;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(usb_utmi_dev_t) == 0x14, "Invalid size of usb_utmi_dev_t structure");
+_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/usb/usb_phy_p4.c b/components/usb/usb_phy_p4.c
index a541fafe4c..1d9ef406b5 100644
--- a/components/usb/usb_phy_p4.c
+++ b/components/usb/usb_phy_p4.c
@@ -4,13 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// This is only a dummy USB PHY file for successful linking of ESP32-P4 target
-// The internal HS PHY is enabled by default, therefore it needs no configuration
-
 // TODO: Refactor during the IDF-9198
 #include "sdkconfig.h"
 #include "soc/usb_dwc_cfg.h"
 #include "hal/usb_wrap_hal.h"
+#include "hal/usb_utmi_ll.h"
 // TODO: Remove this file when proper support of P4 PHYs is implemented IDF-7323
 #include "esp_private/usb_phy.h"
 
@@ -25,6 +23,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
     For correct detection of the device detaching, internal signal should be set to 1 by the software.
     */
     usb_wrap_ll_enable_precise_detection();
+    usb_utmi_ll_configure_ls(&USB_UTMI, true);
 #endif // CONFIG_IDF_TARGET_ESP32P4
 #endif // (OTG_HSPHY_INTERFACE != 0)
     return ESP_OK;