From 3fb3600ee083ab3611de5dd894bc8c8b4d0be195 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 11 Nov 2022 17:45:03 +0800 Subject: [PATCH] psram: remove CS/CLK pin settings in kconfig on ESP32S2/S3 --- components/esp32s2/Kconfig | 22 ++++++------------- components/esp32s2/sdkconfig.rename | 5 +++++ components/esp32s3/Kconfig | 22 ++++++------------- components/esp32s3/sdkconfig.rename | 5 +++++ .../port/esp32s2/spiram_psram.c | 4 ++-- .../port/esp32s3/opiram_psram.c | 2 +- .../port/esp32s3/spiram_psram.c | 4 ++-- 7 files changed, 29 insertions(+), 35 deletions(-) create mode 100644 components/esp32s2/sdkconfig.rename create mode 100644 components/esp32s3/sdkconfig.rename diff --git a/components/esp32s2/Kconfig b/components/esp32s2/Kconfig index f0e809908c..dbbdf9c4b9 100644 --- a/components/esp32s2/Kconfig +++ b/components/esp32s2/Kconfig @@ -143,22 +143,14 @@ menu "ESP32S2-specific" default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 0 - menu "PSRAM clock and cs IO for ESP32S2" - depends on ESP32S2_SPIRAM_SUPPORT - config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. + config SPIRAM_CLK_IO + int + default 30 + + config SPIRAM_CS_IO + int + default 26 - config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - endmenu config SPIRAM_FETCH_INSTRUCTIONS bool "Cache fetch instructions from SPI RAM" default n diff --git a/components/esp32s2/sdkconfig.rename b/components/esp32s2/sdkconfig.rename new file mode 100644 index 0000000000..3c7ba13acf --- /dev/null +++ b/components/esp32s2/sdkconfig.rename @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO +CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index a381a8b4b9..d4a4d0631c 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -213,22 +213,14 @@ menu "ESP32S3-Specific" default 33554432 if SPIRAM_TYPE_ESPPSRAM256 default 0 - menu "PSRAM Clock and CS IO for ESP32S3" - depends on ESP32S3_SPIRAM_SUPPORT - config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. + config SPIRAM_CLK_IO + int + default 30 + + config SPIRAM_CS_IO + int + default 26 - config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - endmenu config SPIRAM_FETCH_INSTRUCTIONS bool "Cache fetch instructions from SPI RAM" default n diff --git a/components/esp32s3/sdkconfig.rename b/components/esp32s3/sdkconfig.rename new file mode 100644 index 0000000000..3c7ba13acf --- /dev/null +++ b/components/esp32s3/sdkconfig.rename @@ -0,0 +1,5 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO +CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO diff --git a/components/esp_hw_support/port/esp32s2/spiram_psram.c b/components/esp_hw_support/port/esp32s2/spiram_psram.c index bb40c9f781..7e0ffce9f0 100644 --- a/components/esp_hw_support/port/esp32s2/spiram_psram.c +++ b/components/esp_hw_support/port/esp32s2/spiram_psram.c @@ -86,8 +86,8 @@ static const char* TAG = "psram"; #define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 -#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM +#define PSRAM_CS_IO SPI_CS1_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM diff --git a/components/esp_hw_support/port/esp32s3/opiram_psram.c b/components/esp_hw_support/port/esp32s3/opiram_psram.c index 1d188b8f9e..0f40a3d7dd 100644 --- a/components/esp_hw_support/port/esp32s3/opiram_psram.c +++ b/components/esp_hw_support/port/esp32s3/opiram_psram.c @@ -38,7 +38,7 @@ #define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) -#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO +#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM #define OCT_PSRAM_CS_SETUP_TIME 3 #define OCT_PSRAM_CS_HOLD_TIME 3 diff --git a/components/esp_hw_support/port/esp32s3/spiram_psram.c b/components/esp_hw_support/port/esp32s3/spiram_psram.c index 6c243bf2ac..be4900661d 100644 --- a/components/esp_hw_support/port/esp32s3/spiram_psram.c +++ b/components/esp_hw_support/port/esp32s3/spiram_psram.c @@ -90,8 +90,8 @@ static const char* TAG = "psram"; #define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 -#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM +#define PSRAM_CS_IO SPI_CS1_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM