From f5ca47c0fcfda3c0855d88f54d7b882529f6553a Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 7 Jan 2021 17:34:59 +0800 Subject: [PATCH 1/3] mcpwm: rename macros related to soc capbility --- components/driver/include/driver/mcpwm.h | 2 +- components/driver/mcpwm.c | 39 ++++++++++--------- components/hal/include/hal/mcpwm_hal.h | 10 ++--- components/hal/mcpwm_hal.c | 20 +++++----- components/soc/esp32/include/soc/soc_caps.h | 16 +++++--- components/soc/esp32s3/include/soc/soc_caps.h | 13 +++++++ 6 files changed, 59 insertions(+), 41 deletions(-) diff --git a/components/driver/include/driver/mcpwm.h b/components/driver/include/driver/mcpwm.h index fce8a815ea..f4ec17a2a9 100644 --- a/components/driver/include/driver/mcpwm.h +++ b/components/driver/include/driver/mcpwm.h @@ -86,7 +86,7 @@ typedef enum { MCPWM_UNIT_MAX, /*!= SOC_MCPWM_TIMER_NUM, "This driver assumes the timer num equals to the operator num."); -_Static_assert(SOC_MCPWM_COMPARATOR_NUM >= SOC_MCPWM_GENERATOR_NUM, "This driver assumes the generator num equals to the generator num."); -_Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator num equals to 2."); +_Static_assert(SOC_MCPWM_OPERATORS_PER_GROUP >= SOC_MCPWM_TIMERS_PER_GROUP, "This driver assumes the timer num equals to the operator num."); +_Static_assert(SOC_MCPWM_COMPARATORS_PER_OPERATOR >= SOC_MCPWM_GENERATORS_PER_OPERATOR, "This driver assumes the generator num equals to the generator num."); +_Static_assert(SOC_MCPWM_GENERATORS_PER_OPERATOR == 2, "This driver assumes the generator num equals to 2."); #define MCPWM_TIMER_ID_CHECK(mcpwm_num, timer_num) do {\ - MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); \ - MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMER_NUM, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \ + MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); \ + MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMERS_PER_GROUP, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \ } while(0) #define MCPWM_TIMER_CHECK(mcpwm_num, timer_num) do{\ @@ -82,7 +83,7 @@ _Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator } while(0) -static mcpwm_context_t context[SOC_MCPWM_PERIPH_NUM] = { +static mcpwm_context_t context[SOC_MCPWM_GROUPS] = { CONTEXT_INITIALIZER(), CONTEXT_INITIALIZER(), }; @@ -105,7 +106,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, return ESP_OK; } - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num); @@ -138,7 +139,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_gpio_init(mcpwm_num, MCPWM0A, mcpwm_pin->mcpwm0a_out_num); //MCPWM0A mcpwm_gpio_init(mcpwm_num, MCPWM0B, mcpwm_pin->mcpwm0b_out_num); //MCPWM0B mcpwm_gpio_init(mcpwm_num, MCPWM1A, mcpwm_pin->mcpwm1a_out_num); //MCPWM1A @@ -274,7 +275,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw //update the comparer to keep the same duty rate mcpwm_hal_operator_update_basic(hal, op); - for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { + for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) { hal->op[op].gen[gen] = (mcpwm_hal_generator_config_t) { .comparator = gen, //the driver currently always use the comparator A for PWMxA output, and comparator B for PWMxB output .duty_type = mcpwm_conf->duty_mode, @@ -447,7 +448,7 @@ esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, //the driver currently always use the timer x for operator x const int op = timer_num; MCPWM_TIMER_CHECK(mcpwm_num, timer_num); - MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DB_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DT_ERROR, ESP_ERR_INVALID_ARG); mcpwm_hal_context_t *hal = &context[mcpwm_num].hal; mcpwm_hal_deadzone_conf_t deadzone = { .red = red, @@ -477,7 +478,7 @@ esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_critical_enter(mcpwm_num); mcpwm_hal_fault_init(&context[mcpwm_num].hal, fault_sig, intput_level); @@ -487,7 +488,7 @@ esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t int esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_critical_enter(mcpwm_num); mcpwm_hal_fault_disable(&context[mcpwm_num].hal, fault_sig); @@ -533,7 +534,7 @@ esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge, uint32_t num_of_pulse) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_hal_init_config_t init_config = { .host_id = mcpwm_num, }; @@ -555,7 +556,7 @@ esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t ca esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_critical_enter(mcpwm_num); mcpwm_hal_capture_disable(&context[mcpwm_num].hal, cap_sig); @@ -565,7 +566,7 @@ esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t c uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); uint32_t captured_value; mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, &captured_value, NULL); @@ -574,7 +575,7 @@ uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_si uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) { - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); mcpwm_capture_on_edge_t edge; mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, NULL, &edge); return (edge == MCPWM_NEG_EDGE ? 2 : 1); @@ -609,7 +610,7 @@ esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num) esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle) { esp_err_t ret; - MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); + MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG); ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle); return ret; diff --git a/components/hal/include/hal/mcpwm_hal.h b/components/hal/include/hal/mcpwm_hal.h index 1d45b9dafa..cfe0ba3d25 100644 --- a/components/hal/include/hal/mcpwm_hal.h +++ b/components/hal/include/hal/mcpwm_hal.h @@ -87,8 +87,8 @@ typedef struct { /// Configuration of each operator typedef struct { - mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATOR_NUM]; ///< Configuration of the generators - float duty[SOC_MCPWM_COMPARATOR_NUM]; ///< Duty rate for each comparator, 10 means 10%. + mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Configuration of the generators + float duty[SOC_MCPWM_COMPARATORS_PER_OPERATOR]; ///< Duty rate for each comparator, 10 means 10%. int timer; ///< The timer this operator is using } mcpwm_hal_operator_config_t; @@ -102,8 +102,8 @@ typedef struct { typedef struct { mcpwm_dev_t *dev; ///< Beginning address of the MCPWM peripheral registers. Call `mcpwm_hal_init` to initialize it. uint32_t prescale; ///< Prescale from the 160M clock to MCPWM main clock. - mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMER_NUM]; ///< Configuration of the timers - mcpwm_hal_operator_config_t op[SOC_MCPWM_OP_NUM]; ///< Configuration of the operators + mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMERS_PER_GROUP]; ///< Configuration of the timers + mcpwm_hal_operator_config_t op[SOC_MCPWM_OPERATORS_PER_GROUP]; ///< Configuration of the operators } mcpwm_hal_context_t; /// Configuration of the carrier @@ -125,7 +125,7 @@ typedef struct { typedef struct { uint32_t cbc_enabled_mask; ///< Whether the cycle-by-cycle fault handling is enabled on each fault signal. BIT(n) stands for signal n. uint32_t ost_enabled_mask; ///< Whether the oneshot fault handling is enabled on each on each fault signal. BIT(n) stands for signal n. - mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATOR_NUM]; ///< Action to perform on each generator when any one of the fault signal triggers. + mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Action to perform on each generator when any one of the fault signal triggers. } mcpwm_hal_fault_conf_t; /// Configuration of the synchronization of each clock diff --git a/components/hal/mcpwm_hal.c b/components/hal/mcpwm_hal.c index a68d228554..fc555909ff 100644 --- a/components/hal/mcpwm_hal.c +++ b/components/hal/mcpwm_hal.c @@ -43,11 +43,11 @@ void mcpwm_hal_timer_update_basic(mcpwm_hal_context_t *hal, int timer) mcpwm_ll_timer_set_prescale(hal->dev, timer, hal->timer[timer].timer_prescale); uint32_t period = MCPWM_BASE_CLK / (hal->timer[timer].freq * - (hal->prescale +1) * (hal->timer[timer].timer_prescale + 1)); + (hal->prescale + 1) * (hal->timer[timer].timer_prescale + 1)); mcpwm_ll_timer_set_period(hal->dev, timer, period); //write back the actual value to the context hal->timer[timer].freq = MCPWM_BASE_CLK / (period * - (hal->prescale +1) * (hal->timer[timer].timer_prescale + 1)); + (hal->prescale + 1) * (hal->timer[timer].timer_prescale + 1)); mcpwm_ll_timer_set_count_mode(hal->dev, timer, hal->timer[timer].count_mode); } @@ -70,10 +70,10 @@ void mcpwm_hal_operator_update_basic(mcpwm_hal_context_t *hal, int op) { mcpwm_hal_operator_config_t *op_conf = &hal->op[op]; mcpwm_ll_operator_select_timer(hal->dev, op, op_conf->timer); - for (int cmp = 0; cmp < SOC_MCPWM_COMPARATOR_NUM; cmp++) { + for (int cmp = 0; cmp < SOC_MCPWM_COMPARATORS_PER_OPERATOR; cmp++) { mcpwm_hal_operator_update_comparator(hal, op, cmp); } - for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { + for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) { mcpwm_hal_operator_update_generator(hal, op, gen); } } @@ -88,7 +88,7 @@ void mcpwm_hal_operator_update_comparator(mcpwm_hal_context_t *hal, int op, int void mcpwm_hal_operator_update_generator(mcpwm_hal_context_t *hal, int op, int gen_num) { - mcpwm_hal_generator_config_t* gen_config = &(hal->op[op].gen[gen_num]); + mcpwm_hal_generator_config_t *gen_config = &(hal->op[op].gen[gen_num]); if (gen_config->duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) { mcpwm_ll_gen_set_zero_action(hal->dev, op, gen_num, MCPWM_ACTION_FORCE_HIGH); mcpwm_ll_gen_set_period_action(hal->dev, op, gen_num, MCPWM_ACTION_FORCE_HIGH); @@ -166,21 +166,21 @@ void mcpwm_hal_fault_init(mcpwm_hal_context_t *hal, int fault_sig, bool level) void mcpwm_hal_operator_update_fault(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_fault_conf_t *fault_conf) { - for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) { + for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) { bool enabled = (fault_conf->cbc_enabled_mask & BIT(fault_sig)) ? true : false; mcpwm_ll_fault_cbc_enable_signal(hal->dev, op, fault_sig, enabled); } - for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) { + for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) { bool enabled = (fault_conf->ost_enabled_mask & BIT(fault_sig)) ? true : false; mcpwm_ll_fault_oneshot_enable_signal(hal->dev, op, fault_sig, enabled); } if (fault_conf->cbc_enabled_mask) { - for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { + for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) { mcpwm_ll_fault_set_cyc_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]); } } if (fault_conf->ost_enabled_mask) { - for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { + for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) { mcpwm_ll_fault_set_oneshot_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]); } } @@ -193,7 +193,7 @@ void mcpwm_hal_fault_oneshot_clear(mcpwm_hal_context_t *hal, int op) void mcpwm_hal_fault_disable(mcpwm_hal_context_t *hal, int fault_sig) { - for (int op = 0; op < SOC_MCPWM_OP_NUM; op++) { + for (int op = 0; op < SOC_MCPWM_OPERATORS_PER_GROUP; op++) { if (mcpwm_ll_fault_oneshot_signal_enabled(hal->dev, op, fault_sig)) { mcpwm_ll_fault_clear_ost(hal->dev, op); } diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 51ecd22ce3..00829c6011 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -150,12 +150,16 @@ #define SOC_LEDC_TIMER_BIT_WIDE_NUM (20) /*-------------------------- MCPWM CAPS --------------------------------------*/ -#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number -#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has -#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has -#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has -#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has -#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has +#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has +#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz /*-------------------------- MPU CAPS ----------------------------------------*/ //TODO: correct the caller and remove unsupported lines diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index f6ceceb8b7..ba9a73d1e4 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -10,6 +10,7 @@ #define SOC_TWAI_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_I80_LCD_SUPPORTED 1 +#define SOC_MCPWM_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_CPU_CORES_NUM 2 #define SOC_CACHE_SUPPORT_WRAP 1 @@ -52,6 +53,18 @@ /*-------------------------- LEDC CAPS ---------------------------------------*/ #include "ledc_caps.h" +/*-------------------------- MCPWM CAPS --------------------------------------*/ +#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has +#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz + /*-------------------------- MPU CAPS ----------------------------------------*/ #include "mpu_caps.h" From 3b66958b330484364a8fe375757545067f027fd3 Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 25 Feb 2021 18:55:30 +0800 Subject: [PATCH 2/3] mcpwm: added peripheral signal description list --- components/soc/esp32/CMakeLists.txt | 1 + components/soc/esp32/mcpwm_periph.c | 160 ++++++++++++++++++++++ components/soc/esp32s3/CMakeLists.txt | 1 + components/soc/esp32s3/mcpwm_periph.c | 160 ++++++++++++++++++++++ components/soc/include/soc/mcpwm_periph.h | 34 +++++ 5 files changed, 356 insertions(+) create mode 100644 components/soc/esp32/mcpwm_periph.c create mode 100644 components/soc/esp32s3/mcpwm_periph.c diff --git a/components/soc/esp32/CMakeLists.txt b/components/soc/esp32/CMakeLists.txt index 3814ba716f..438cddd69a 100644 --- a/components/soc/esp32/CMakeLists.txt +++ b/components/soc/esp32/CMakeLists.txt @@ -6,6 +6,7 @@ set(srcs "i2s_periph.c" "interrupts.c" "ledc_periph.c" + "mcpwm_periph.c" "pcnt_periph.c" "rmt_periph.c" "rtc_io_periph.c" diff --git a/components/soc/esp32/mcpwm_periph.c b/components/soc/esp32/mcpwm_periph.c new file mode 100644 index 0000000000..0a30191ff1 --- /dev/null +++ b/components/soc/esp32/mcpwm_periph.c @@ -0,0 +1,160 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc.h" +#include "soc/mcpwm_periph.h" +#include "soc/gpio_sig_map.h" + +const mcpwm_signal_conn_t mcpwm_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_PWM0_MODULE, + .irq_id = ETS_PWM0_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT0A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT0B_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT1A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT1B_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT2A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT2B_IDX + } + } + } + }, + .detectors = { + [0] = { + .fault_sig = PWM0_F0_IN_IDX + }, + [1] = { + .fault_sig = PWM0_F1_IN_IDX + }, + [2] = { + .fault_sig = PWM0_F2_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM0_CAP0_IN_IDX + }, + [1] = { + .cap_sig = PWM0_CAP1_IN_IDX + }, + [2] = { + .cap_sig = PWM0_CAP2_IN_IDX + } + }, + .ext_syncers = { + [0] = { + .sync_sig = PWM0_SYNC0_IN_IDX + }, + [1] = { + .sync_sig = PWM0_SYNC1_IN_IDX + }, + [2] = { + .sync_sig = PWM0_SYNC2_IN_IDX + } + } + }, + [1] = { + .module = PERIPH_PWM1_MODULE, + .irq_id = ETS_PWM1_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT0A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT0B_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT1A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT1B_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT2A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT2B_IDX + } + } + } + }, + .detectors = { + [0] = { + .fault_sig = PWM1_F0_IN_IDX + }, + [1] = { + .fault_sig = PWM1_F1_IN_IDX + }, + [2] = { + .fault_sig = PWM1_F2_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM1_CAP0_IN_IDX + }, + [1] = { + .cap_sig = PWM1_CAP1_IN_IDX + }, + [2] = { + .cap_sig = PWM1_CAP2_IN_IDX + } + }, + .ext_syncers = { + [0] = { + .sync_sig = PWM1_SYNC0_IN_IDX + }, + [1] = { + .sync_sig = PWM1_SYNC1_IN_IDX + }, + [2] = { + .sync_sig = PWM1_SYNC2_IN_IDX + } + } + } + } +}; diff --git a/components/soc/esp32s3/CMakeLists.txt b/components/soc/esp32s3/CMakeLists.txt index 61312030dd..8016bf6ed8 100644 --- a/components/soc/esp32s3/CMakeLists.txt +++ b/components/soc/esp32s3/CMakeLists.txt @@ -9,6 +9,7 @@ set(srcs "interrupts.c" "lcd_periph.c" "ledc_periph.c" + "mcpwm_periph.c" "pcnt_periph.c" "rmt_periph.c" "rtc_io_periph.c" diff --git a/components/soc/esp32s3/mcpwm_periph.c b/components/soc/esp32s3/mcpwm_periph.c new file mode 100644 index 0000000000..0a30191ff1 --- /dev/null +++ b/components/soc/esp32s3/mcpwm_periph.c @@ -0,0 +1,160 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc.h" +#include "soc/mcpwm_periph.h" +#include "soc/gpio_sig_map.h" + +const mcpwm_signal_conn_t mcpwm_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_PWM0_MODULE, + .irq_id = ETS_PWM0_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT0A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT0B_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT1A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT1B_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM0_OUT2A_IDX + }, + [1] = { + .pwm_sig = PWM0_OUT2B_IDX + } + } + } + }, + .detectors = { + [0] = { + .fault_sig = PWM0_F0_IN_IDX + }, + [1] = { + .fault_sig = PWM0_F1_IN_IDX + }, + [2] = { + .fault_sig = PWM0_F2_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM0_CAP0_IN_IDX + }, + [1] = { + .cap_sig = PWM0_CAP1_IN_IDX + }, + [2] = { + .cap_sig = PWM0_CAP2_IN_IDX + } + }, + .ext_syncers = { + [0] = { + .sync_sig = PWM0_SYNC0_IN_IDX + }, + [1] = { + .sync_sig = PWM0_SYNC1_IN_IDX + }, + [2] = { + .sync_sig = PWM0_SYNC2_IN_IDX + } + } + }, + [1] = { + .module = PERIPH_PWM1_MODULE, + .irq_id = ETS_PWM1_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT0A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT0B_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT1A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT1B_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM1_OUT2A_IDX + }, + [1] = { + .pwm_sig = PWM1_OUT2B_IDX + } + } + } + }, + .detectors = { + [0] = { + .fault_sig = PWM1_F0_IN_IDX + }, + [1] = { + .fault_sig = PWM1_F1_IN_IDX + }, + [2] = { + .fault_sig = PWM1_F2_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM1_CAP0_IN_IDX + }, + [1] = { + .cap_sig = PWM1_CAP1_IN_IDX + }, + [2] = { + .cap_sig = PWM1_CAP2_IN_IDX + } + }, + .ext_syncers = { + [0] = { + .sync_sig = PWM1_SYNC0_IN_IDX + }, + [1] = { + .sync_sig = PWM1_SYNC1_IN_IDX + }, + [2] = { + .sync_sig = PWM1_SYNC2_IN_IDX + } + } + } + } +}; diff --git a/components/soc/include/soc/mcpwm_periph.h b/components/soc/include/soc/mcpwm_periph.h index d7223da45d..ae5809c91e 100644 --- a/components/soc/include/soc/mcpwm_periph.h +++ b/components/soc/include/soc/mcpwm_periph.h @@ -13,5 +13,39 @@ // limitations under the License. #pragma once + +#include "soc/soc_caps.h" #include "soc/mcpwm_reg.h" #include "soc/mcpwm_struct.h" +#include "soc/periph_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + struct { + const periph_module_t module; // Peripheral module + const int irq_id; + struct { + struct { + const uint32_t pwm_sig; + } generators[SOC_MCPWM_GENERATORS_PER_OPERATOR]; + } operators[SOC_MCPWM_OPERATORS_PER_GROUP]; + struct { + const uint32_t fault_sig; + } detectors[SOC_MCPWM_FAULT_DETECTORS_PER_GROUP]; + struct { + const uint32_t cap_sig; + } captures[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER]; + struct { + const uint32_t sync_sig; + } ext_syncers[SOC_MCPWM_EXT_SYNCERS_PER_GROUP]; + } groups[SOC_MCPWM_GROUPS]; +} mcpwm_signal_conn_t; + +extern const mcpwm_signal_conn_t mcpwm_periph_signals; + +#ifdef __cplusplus +} +#endif From ff65363ada755391568fe724eeab8edb538a914a Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 25 Feb 2021 19:08:22 +0800 Subject: [PATCH 3/3] mcpwm: configure gpio using by lookup table --- components/driver/mcpwm.c | 52 +++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/components/driver/mcpwm.c b/components/driver/mcpwm.c index 98a19a405a..6cab15d37e 100644 --- a/components/driver/mcpwm.c +++ b/components/driver/mcpwm.c @@ -101,38 +101,33 @@ static inline void mcpwm_critical_exit(mcpwm_unit_t mcpwm_num) esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num) { - if (gpio_num == MCPWM_PIN_IGNORE) { - //IGNORE + if (gpio_num < 0) { // ignore on minus gpio number return ESP_OK; } MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); - periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num); + // we enabled both input and output mode for GPIO used here, which can help to simulate trigger source especially in test code PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); - bool mcpwm_gpio_sig = (io_signal <= MCPWM2B); - if (mcpwm_num == MCPWM_UNIT_0) { - if (mcpwm_gpio_sig) { - MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); - gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(gpio_num, PWM0_OUT0A_IDX + io_signal, 0, 0); - } else { - gpio_set_direction(gpio_num, GPIO_MODE_INPUT); - esp_rom_gpio_connect_in_signal(gpio_num, PWM0_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0); - } - } else { //MCPWM_UNIT_1 - if (mcpwm_gpio_sig) { - MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); - gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(gpio_num, PWM1_OUT0A_IDX + io_signal, 0, 0); - } else if (io_signal >= MCPWM_SYNC_0 && io_signal <= MCPWM_FAULT_2) { - gpio_set_direction(gpio_num, GPIO_MODE_INPUT); - esp_rom_gpio_connect_in_signal(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0); - } else { - gpio_set_direction(gpio_num, GPIO_MODE_INPUT); - esp_rom_gpio_connect_in_signal(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_2, 0); - } + if (io_signal <= MCPWM2B) { // Generator output signal + MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); + gpio_set_direction(gpio_num, GPIO_MODE_INPUT_OUTPUT); + int operator_id = io_signal / 2; + int generator_id = io_signal % 2; + esp_rom_gpio_connect_out_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].operators[operator_id].generators[generator_id].pwm_sig, 0, 0); + } else if (io_signal <= MCPWM_SYNC_2) { // External sync input signal + gpio_set_direction(gpio_num, GPIO_MODE_INPUT_OUTPUT); + int ext_sync_id = io_signal - MCPWM_SYNC_0; + esp_rom_gpio_connect_in_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].ext_syncers[ext_sync_id].sync_sig, 0); + } else if (io_signal <= MCPWM_FAULT_2) { // Fault input signal + gpio_set_direction(gpio_num, GPIO_MODE_INPUT_OUTPUT); + int fault_id = io_signal - MCPWM_FAULT_0; + esp_rom_gpio_connect_in_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].detectors[fault_id].fault_sig, 0); + } else if (io_signal >= MCPWM_CAP_0 && io_signal <= MCPWM_CAP_2) { // Capture input signal + gpio_set_direction(gpio_num, GPIO_MODE_INPUT_OUTPUT); + int capture_id = io_signal - MCPWM_CAP_0; + esp_rom_gpio_connect_in_signal(gpio_num, mcpwm_periph_signals.groups[mcpwm_num].captures[capture_id].cap_sig, 0); } return ESP_OK; } @@ -251,7 +246,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw //the driver currently always use the timer x for operator x const int op = timer_num; MCPWM_TIMER_ID_CHECK(mcpwm_num, op); - periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num); + periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module); mcpwm_hal_context_t *hal = &context[mcpwm_num].hal; mcpwm_hal_init_config_t init_config = { @@ -535,6 +530,8 @@ esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t ca uint32_t num_of_pulse) { MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); + // enable MCPWM module incase user don't use `mcpwm_init` at all + periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module); mcpwm_hal_init_config_t init_config = { .host_id = mcpwm_num, }; @@ -561,6 +558,7 @@ esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t c mcpwm_critical_enter(mcpwm_num); mcpwm_hal_capture_disable(&context[mcpwm_num].hal, cap_sig); mcpwm_critical_exit(mcpwm_num); + periph_module_disable(mcpwm_periph_signals.groups[mcpwm_num].module); return ESP_OK; } @@ -612,6 +610,6 @@ esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *a esp_err_t ret; MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG); - ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle); + ret = esp_intr_alloc(mcpwm_periph_signals.groups[mcpwm_num].irq_id, intr_alloc_flags, fn, arg, handle); return ret; }