diff --git a/components/esp_driver_sd_intf/CMakeLists.txt b/components/esp_driver_sd_intf/CMakeLists.txt new file mode 100644 index 0000000000..4966109cc2 --- /dev/null +++ b/components/esp_driver_sd_intf/CMakeLists.txt @@ -0,0 +1,13 @@ +idf_build_get_property(target IDF_TARGET) + +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs "sd_host.c") + +set(public_include "include") + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + PRIV_REQUIRES sdmmc) diff --git a/components/esp_driver_sd_intf/README.md b/components/esp_driver_sd_intf/README.md new file mode 100644 index 0000000000..fc004be98b --- /dev/null +++ b/components/esp_driver_sd_intf/README.md @@ -0,0 +1,3 @@ +# SD Host Driver Interface Layer + +This component provides the SD Host driver APIs. diff --git a/components/esp_driver_sd_intf/include/driver/sd_host.h b/components/esp_driver_sd_intf/include/driver/sd_host.h new file mode 100644 index 0000000000..69480addef --- /dev/null +++ b/components/esp_driver_sd_intf/include/driver/sd_host.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +* +* SPDX-License-Identifier: Apache-2.0 +*/ + +#pragma once + +#include "esp_err.h" +#include "soc/gpio_num.h" +#include "driver/sd_types.h" +#include "sd_protocol_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configure SD Host slot + * + * @param[in] slot SD Host slot handle + * @param[in] config SD Host slot configuration + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config); + +/** + * @brief Do a transaction for the slot + * + * @param[in] slot SD Host slot handle + * @param[in] cmdinfo SD command info, see `sdmmc_command_t` + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo); + +/** + * @brief Register SD event callbacks + * + * @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in + * the `cbs` structure to NULL. + * + * @param[in] slot SD Host slot handle + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be delivered to the callback functions directly + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ +esp_err_t sd_host_slot_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data); + +/** + * @brief Remove an SD Host slot + * + * @param[in] slot SD Host slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_STATE: Invalid state, slot is not available + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_remove_slot(sd_host_slot_handle_t slot); + +/** + * @brief Set an SD Host slot clock always on + * + * @param[in] slot SD Host slot handle + * @param[in] always_on Always on or not + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on); + +/** + * @brief Enable an SD Host slot IO interrupt + * + * @param[in] slot SD Host slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_enable_io_int(sd_host_slot_handle_t slot); + +/** + * @brief Wait for IO interrupt event + * + * @param[in] slot SD Host slot handle + * @param[in] timeout_ticks Timeout ticks + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_TIMEOUT: Timeout + */ +esp_err_t sd_host_slot_wait_io_int(sd_host_slot_handle_t slot, TickType_t timeout_ticks); + +/** + * @brief Get slot info + * + * @param[in] slot SD Host slot handle + * @param[out] info SD slot info + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info); + +/** + * @brief Delete an SD Host controller + * + * @param[in] ctlr SD Host controller handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Invalid state, there's still registered slot(s) + */ +esp_err_t sd_host_del_controller(sd_host_ctlr_handle_t ctlr); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sd_intf/include/driver/sd_types.h b/components/esp_driver_sd_intf/include/driver/sd_types.h new file mode 100644 index 0000000000..bf8417fca1 --- /dev/null +++ b/components/esp_driver_sd_intf/include/driver/sd_types.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_err.h" +#include "hal/sd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief SD Host controller handle + */ +typedef struct sd_host_driver_t *sd_host_ctlr_handle_t; + +/** + * @brief SD Host slot handle + */ +typedef struct sd_slot_driver_t *sd_host_slot_handle_t; + +/** + * @brief SD Host slot configuration + */ +typedef struct { + struct { + int freq_hz; ///< Frequency in Hz + bool override; ///< If set to true, frequency will be set to freq_hz; If set to false, frequency is unchanged. By default it's false + } freq; ///< Frequency settings + struct { + bool override; ///< If set to true, width will be set to width configured in `sd_host_sdmmc_slot_io_cfg_t`; If set to false, width is unchanged. By default it's false + } width; ///< Bus width settings + struct { + sd_sampling_mode_t mode; ///< Sampling mode, see `sd_sampling_mode_t` + bool override; ///< If set to true, sampling mode will be set to sampling_mode; If set to false, sampling mode is unchanged. By default it's false + } sampling_mode; ///< Sampling mode settings + struct { + sdmmc_delay_phase_t delayphase; ///< Delay phase, see `sdmmc_delay_phase_t` + bool override; ///< If set to true, delay phase will be set to delay_phase; If set to false, delay phase is unchanged. By default it's false + } delay_phase; ///< Delay phase settings + struct { + sdmmc_delay_line_t delayline; ///< Delay line, see `sdmmc_delay_line_t` + bool override; ///< If set to true, delay line will be set to delay_line; If set to false, delay line is unchanged. By default it's false + } delay_line; ///< Delay line settings +} sd_host_slot_cfg_t; + +/** + * @brief Slot info + */ +typedef struct { + int freq_hz; ///< Frequency in Hz + uint8_t width; ///< Bus width + sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t` + sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t` +} sd_host_slot_info_t; + +/*--------------------------------------------- + Event Callbacks +----------------------------------------------*/ +/** + * @brief SD event data structure + */ +typedef struct { + //leave empty for future-proof +} sd_host_evt_data_t; + +/** + * @brief Prototype of SD event callback + * + * @param[in] slot Slot handle + * @param[in] edata SD event data + * @param[in] user_data User registered context, registered when in `esp_isp_register_event_callbacks()` + * + * @return Whether a high priority task is woken up by this function + */ +typedef bool (*sd_host_callback_t)(sd_host_slot_handle_t slot, const sd_host_evt_data_t *edata, void *user_data); + +/** + * @brief SD event callbacks + */ +typedef struct { + sd_host_callback_t on_trans_done; ///< Event callback, invoked when one transaction done + sd_host_callback_t on_io_interrupt; ///< Event callback, invoked when IO interrupts +} sd_host_evt_cbs_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sd_intf/include/esp_private/sd_driver_interface.h b/components/esp_driver_sd_intf/include/esp_private/sd_driver_interface.h new file mode 100644 index 0000000000..9fa1fb6119 --- /dev/null +++ b/components/esp_driver_sd_intf/include/esp_private/sd_driver_interface.h @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_err.h" +#include "driver/sd_types.h" +#include "sd_protocol_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct sd_host_driver_t sd_host_driver_t; /*!< Type of SD driver host context */ +typedef struct sd_slot_driver_t sd_slot_driver_t; /*!< Type of SD driver slot context */ + +/** + * @brief SD driver host driver context + */ +struct sd_host_driver_t { + /** + * @brief Delete an SD Host controller + * + * @param[in] ctlr_ctx SD driver host controller context + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Invalid state, there's still registered slot(s) + */ + esp_err_t (*del_ctlr)(sd_host_driver_t *ctlr_ctx); +}; + +/** + * @brief SD driver API definition + */ +struct sd_slot_driver_t { + /** + * @brief Configure SD Host slot + * + * @param[in] slot_drv SD Host slot driver handle + * @param[in] config SD Host slot configuration + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ + esp_err_t (*configure)(sd_slot_driver_t *slot_drv, const sd_host_slot_cfg_t *config); + + /** + * @brief Do a transaction for the slot + * + * @param[in] slot_drv SD Host slot driver handle + * @param[in] cmdinfo SD command info, see `sdmmc_command_t` + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ + esp_err_t (*do_transaction)(sd_slot_driver_t *slot_drv, sdmmc_command_t *cmdinfo); + + /** + * @brief Register SD event callbacks + * + * @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in + * the `cbs` structure to NULL. + * + * @param[in] slot_drv SD Host slot driver handle + * @param[in] cbs Group of callback functions + * @param[in] user_data User data, which will be delivered to the callback functions directly + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment + */ + esp_err_t (*register_cbs)(sd_slot_driver_t *slot_drv, const sd_host_evt_cbs_t *cbs, void *user_data); + + /** + * @brief Remove an SD Host slot + * + * @param[in] slot_drv SD Host slot driver handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_STATE: Invalid state, slot is not available + * - ESP_ERR_INVALID_ARG: Invalid argument + */ + esp_err_t (*remove_slot)(sd_slot_driver_t *slot_drv); + + /** + * @brief Set an SD Host slot clock always on + * + * @param[in] slot_drv SD Host slot driver handle + * @param[in] always_on Always on or not + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ + esp_err_t (*set_cclk_always_on)(sd_slot_driver_t *slot_drv, bool always_on); + + /** + * @brief Enable an SD Host slot IO interrupt + * + * @param[in] slot_drv SD Host slot driver handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ + esp_err_t (*enable_io_int)(sd_slot_driver_t *slot_drv); + + /** + * @brief Wait for IO interrupt event + * + * @param[in] slot SD Host slot handle + * @param[in] timeout_ticks Timeout ticks + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_TIMEOUT: Timeout + */ + esp_err_t (*wait_io_int)(sd_slot_driver_t *slot_drv, TickType_t timeout_ticks); + + /** + * @brief Get slot info + * + * @param[in] slot SD Host slot handle + * @param[out] info SD slot info + */ + esp_err_t (*get_info)(sd_slot_driver_t *slot_drv, sd_host_slot_info_t *info); +}; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sd_intf/sd_host.c b/components/esp_driver_sd_intf/sd_host.c new file mode 100644 index 0000000000..096956ee08 --- /dev/null +++ b/components/esp_driver_sd_intf/sd_host.c @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_types.h" +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp_check.h" +#include "driver/sd_host.h" +#include "esp_private/sd_driver_interface.h" + +static const char *TAG = "SD_HOST"; + +#define SD_HOST_ARG_CHECK(arg) do { \ + if (unlikely(!(arg))) { \ + ESP_LOGE(TAG, "invalid argument: null pointer"); \ + return ESP_ERR_INVALID_ARG; \ + } \ +} while(0) + +#define SD_HOST_FUNC_CHECK(arg) do { \ + if (unlikely(!(arg))) { \ + ESP_LOGE(TAG, "controller driver function not supported"); \ + return ESP_ERR_NOT_SUPPORTED; \ + } \ +} while(0) + +esp_err_t sd_host_slot_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config) +{ + SD_HOST_ARG_CHECK(slot && config); + SD_HOST_FUNC_CHECK(slot->configure); + + return slot->configure(slot, config); +} + +esp_err_t sd_host_slot_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->do_transaction); + + return slot->do_transaction(slot, cmdinfo); +} + +esp_err_t sd_host_slot_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->register_cbs); + + return slot->register_cbs(slot, cbs, user_data); +} + +esp_err_t sd_host_remove_slot(sd_host_slot_handle_t slot) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->remove_slot); + + return slot->remove_slot(slot); +} + +esp_err_t sd_host_del_controller(sd_host_ctlr_handle_t ctlr) +{ + SD_HOST_ARG_CHECK(ctlr); + SD_HOST_FUNC_CHECK(ctlr->del_ctlr); + + return ctlr->del_ctlr(ctlr); +} + +esp_err_t sd_host_slot_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->set_cclk_always_on); + + return slot->set_cclk_always_on(slot, always_on); +} + +esp_err_t sd_host_slot_enable_io_int(sd_host_slot_handle_t slot) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->enable_io_int); + + return slot->enable_io_int(slot); +} + +esp_err_t sd_host_slot_wait_io_int(sd_host_slot_handle_t slot, TickType_t timeout_ticks) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->wait_io_int); + + return slot->wait_io_int(slot, timeout_ticks); +} + +esp_err_t sd_host_slot_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info) +{ + SD_HOST_ARG_CHECK(slot); + SD_HOST_FUNC_CHECK(slot->get_info); + + return slot->get_info(slot, info); +} diff --git a/components/esp_driver_sdmmc/CMakeLists.txt b/components/esp_driver_sdmmc/CMakeLists.txt index fd94c42b34..e581a97a6b 100644 --- a/components/esp_driver_sdmmc/CMakeLists.txt +++ b/components/esp_driver_sdmmc/CMakeLists.txt @@ -8,13 +8,15 @@ set(public_include "include") if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) list(APPEND srcs "src/sdmmc_transaction.c" "src/sdmmc_host.c") + "src/sd_host_sdmmc.c" + "src/sd_trans_sdmmc.c") endif() if(${target} STREQUAL "linux") set(requires "") set(priv_requires esp_timer) else() - set(requires sdmmc esp_driver_gpio) + set(requires esp_driver_sd_intf sdmmc esp_driver_gpio) set(priv_requires esp_timer esp_pm esp_mm) endif() diff --git a/components/esp_driver_sdmmc/Kconfig b/components/esp_driver_sdmmc/Kconfig new file mode 100644 index 0000000000..06b3f2833c --- /dev/null +++ b/components/esp_driver_sdmmc/Kconfig @@ -0,0 +1,12 @@ +menu "ESP-Driver: SD Host SDMMC Controller Configurations" + + depends on SOC_SDMMC_HOST_SUPPORTED + + config SD_HOST_SDMMC_ISR_CACHE_SAFE + bool "SD Host ISR Cache-Safe" + default n + help + Ensure the SD Host SDMMC driver ISR is Cache-Safe. When enabled, + the ISR handler will be available when the cache is disabled. + +endmenu # SD Host Controller Configurations diff --git a/components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h b/components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h new file mode 100644 index 0000000000..c6db874fe4 --- /dev/null +++ b/components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +* +* SPDX-License-Identifier: Apache-2.0 +*/ + +#pragma once + +#include "esp_err.h" +#include "soc/gpio_num.h" +#include "driver/sd_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SD_HOST_SLOT_WIDTH_DEFAULT 0 ///< use the maximum possible width for the slot + +/** + * @brief SD Host SDMMC controller configuration + */ +typedef struct { + uint32_t event_queue_items; ///< Event queue items. If 0, fallback to default queue item number (4) + uint32_t dma_desc_num; ///< Number of DMA descriptor, fallback to default dma descriptor number (4) +} sd_host_sdmmc_cfg_t; + +/** + * @brief SD Host slot IO configuration + */ +typedef struct { + sd_bus_width_t width; ///< Slot bus width + gpio_num_t clk_io; ///< Clock + gpio_num_t cmd_io; ///< Command + gpio_num_t cd_io; ///< Card detect + gpio_num_t wp_io; ///< Write protect + gpio_num_t d0_io; ///< Data0 + gpio_num_t d1_io; ///< Data1 + gpio_num_t d2_io; ///< Data2 + gpio_num_t d3_io; ///< Data3 + gpio_num_t d4_io; ///< Data4 + gpio_num_t d5_io; ///< Data5 + gpio_num_t d6_io; ///< Data6 + gpio_num_t d7_io; ///< Data7 +} sd_host_sdmmc_slot_io_cfg_t; + +/** + * @brief SD Host slot init configuration + */ +typedef struct { + int slot_id; ///< Slot ID + sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t` + sd_host_sdmmc_slot_io_cfg_t io_config; ///< IO configuration + + struct { + uint32_t internal_pullup: 1; ///< Enable internal pullup or not + uint32_t wp_active_high: 1; ///< WP signal is active high or not + } slot_flags; ///< Slot flags +} sd_host_slot_sdmmc_init_cfg_t; + +/** + * @brief Create an SDMMC Host controller + * + * @param[in] config SDMMC Host controller configuration + * @param[out] ret_handle Returned SDMMC Host controller handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_NO_MEM: Out of memory + * - ESP_ERR_NOT_FOUND: Controller not found + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_create_sdmmc_controller(const sd_host_sdmmc_cfg_t *config, sd_host_ctlr_handle_t *ret_handle); + +/** + * @brief Add an SD slot to the SDMMC Host controller + * + * @param[in] ctlr SD Host controller handle + * @param[in] config SD Host slot init configuration + * @param[out] ret_handle Returned SD Host slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_STATE: Invalid state, slot is not available + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: Out of memory + */ +esp_err_t sd_host_sdmmc_controller_add_slot(sd_host_ctlr_handle_t ctlr, const sd_host_slot_sdmmc_init_cfg_t *config, sd_host_slot_handle_t *ret_handle); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sdmmc/include/esp_private/sd_host_private.h b/components/esp_driver_sdmmc/include/esp_private/sd_host_private.h new file mode 100644 index 0000000000..29e9518675 --- /dev/null +++ b/components/esp_driver_sdmmc/include/esp_private/sd_host_private.h @@ -0,0 +1,389 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include +#include "esp_log.h" +#include "esp_intr_alloc.h" +#include "esp_check.h" +#include "esp_pm.h" +#include "esp_cache.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "driver/sd_host_sdmmc.h" +#include "esp_private/sd_driver_interface.h" +#include "sd_protocol_defs.h" +#include "soc/soc_caps.h" +#if SOC_SDMMC_HOST_SUPPORTED +#include "hal/sdmmc_hal.h" +#include "hal/sd_types.h" +#include "hal/sdmmc_ll.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if SOC_SDMMC_HOST_SUPPORTED +#if CONFIG_SD_HOST_SDMMC_ISR_CACHE_SAFE +#define SD_HOST_SDMMC_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) +#else +#define SD_HOST_SDMMC_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT +#endif + +#if !SOC_RCC_IS_INDEPENDENT +// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section +#define SD_HOST_SDMMC_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define SD_HOST_SDMMC_RCC_ATOMIC() +#endif + +#if SOC_PERIPH_CLK_CTRL_SHARED +// Clock source and related clock settings are mixing with other peripherals, so we need to use a critical section +#define SD_HOST_SDMMC_CLK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define SD_HOST_SDMMC_CLK_SRC_ATOMIC() +#endif + +#define SD_HOST_SDMMC_CLOCK_UPDATE_CMD_TIMEOUT_US (1000 * 1000) +#define SD_HOST_SDMMC_START_CMD_TIMEOUT_US (1000 * 1000) +#define SD_HOST_SDMMC_RESET_TIMEOUT_US (5000 * 1000) + +/* Number of DMA descriptors used for transfer. + * Increasing this value above 4 doesn't improve performance for the usual case + * of SD memory cards (most data transfers are multiples of 512 bytes). + */ +#define SD_HOST_SDMMC_DMA_DESC_CNT 4 + +#define GPIO_NUM_CHECK(_gpio_num) \ +if (!GPIO_IS_VALID_GPIO(_gpio_num)) { \ + esp_err_t _err = ESP_ERR_INVALID_ARG; \ + ESP_LOGE(TAG, "%s: Invalid GPIO number %d, returned 0x%x", __func__, _gpio_num, _err); \ + return _err; \ +} + +/** + * @brief SD Host SDMMC FSM + */ +typedef enum { + SD_HOST_FSM_INIT = 1, + SD_HOST_FSM_ENABLED, + SD_HOST_FSM_STARTED, +} sd_host_sdmmc_fsm_t; + +/** + * @brief SD Host SDMMC event type + */ +typedef struct { + uint32_t sdmmc_status; ///< masked SDMMC interrupt status + uint32_t dma_status; ///< masked DMA interrupt status +} sd_host_sdmmc_event_t; + +/** + * @brief SD Host SDMMC slot state + */ +typedef enum sd_host_sdmmc_slot_state_t { + SD_HOST_SLOT_STATE_INIT, ///< Slot is only initialised + SD_HOST_SLOT_STATE_READY, ///< Slot is ready +} sd_host_sdmmc_slot_state_t; + +/** + * @brief SD Host SDMMC transaction state + */ +typedef struct { + uint8_t* ptr; + size_t size_remaining; + size_t next_desc; + size_t desc_remaining; +} sd_host_sdmmc_trans_state_t; + +typedef struct sd_host_sdmmc_slot_t sd_host_sdmmc_slot_t; +typedef struct sd_host_sdmmc_ctlr_t sd_host_sdmmc_ctlr_t; + +/** + * @brief SD Host SDMMC slot context + */ +struct sd_host_sdmmc_slot_t { + sd_slot_driver_t drv; + int slot_id; + sd_mode_t sd_mode; + sd_host_sdmmc_slot_io_cfg_t io_config; + bool use_gpio_matrix; + + struct { + int width; + sd_host_sdmmc_slot_state_t width_state; + } width; + struct { + int freq_hz; + sd_host_sdmmc_slot_state_t freq_state; + int real_freq_hz; + } freq; + struct { + sd_sampling_mode_t mode; + sd_host_sdmmc_slot_state_t sampling_mode_state; + } sampling_mode; + struct { + sdmmc_delay_phase_t delayphase; + sd_host_sdmmc_slot_state_t delay_phase_state; + } delay_phase; + struct { + sdmmc_delay_line_t delayline; + sd_host_sdmmc_slot_state_t delay_line_state; + } delay_line; + + bool cclk_always_on; + soc_periph_sdmmc_clk_src_t clk_src; + + sd_host_sdmmc_ctlr_t *ctlr; + sd_host_evt_cbs_t cbs; + void *user_data; +}; + +/** + * @brief SD Host context + */ +struct sd_host_sdmmc_ctlr_t { + sd_host_driver_t drv; //host driver + int host_id; //host id + sd_host_sdmmc_slot_t *slot[SOC_SDMMC_NUM_SLOTS]; //slot + int registered_slot_nums; //registered slot nums + sdmmc_hal_context_t hal; //hal context + + sdmmc_desc_t *dma_desc; //pointer to dma descriptors + int dma_desc_num; //number of DMA descriptor + sd_host_sdmmc_trans_state_t cur_transfer; //current dma trans + int cur_slot_id; //current slot id + bool is_app_cmd; //this flag is set if the next command is an APP command + + portMUX_TYPE spinlock; //spinlock + SemaphoreHandle_t io_intr_sem; //io interrupt semaphore + SemaphoreHandle_t mutex; //mutex + QueueHandle_t event_queue; //event queue + + intr_handle_t intr_handle; //interrupt handle + sd_host_evt_cbs_t cbs; //user callbacks + void *cbs_user_data; //callback userdata + esp_pm_lock_handle_t pm_lock; //power management lock +}; + +/*--------------------------------------------------------------- + Internal APIs (not used by other components) +---------------------------------------------------------------*/ +/*--------------------------------------------------------------- + IO Control +---------------------------------------------------------------*/ +/** + * @brief Do a transaction for the slot + * + * @param[in] slot SD Host slot handle + * @param[in] cmdinfo SD command info, see `sdmmc_command_t` + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t sd_host_slot_sdmmc_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo); + +/*--------------------------------------------------------------- + HW Commands +---------------------------------------------------------------*/ +/** + * @brief HW command for the slot + * + * @param[in] slot SD Host Slot handle + * @param[in] cmd SD HW command + * @param[in] arg SD command argument + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_NOT_FOUND: Command not found + */ +esp_err_t sd_host_slot_start_command(sd_host_sdmmc_slot_t *slot, sdmmc_hw_cmd_t cmd, uint32_t arg); + +/*--------------------------------------------------------------- + Configuration APIs +---------------------------------------------------------------*/ +/** + * @brief Set clock for the slot + * + * @param[in] slot SD Host Slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_NOT_FOUND: Command not found + */ +esp_err_t sd_host_slot_set_card_clk(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Set bus width for the slot + * + * @param[in] slot SD Host Slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_slot_set_bus_width(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Set sampling mode for the slot + * + * @param[in] slot SD Host Slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_slot_set_bus_sampling_mode(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Set delay phase for the slot + * + * @param[in] slot SD Host Slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_set_delay_phase(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Set delay line for the slot + * + * @param[in] slot SD Host Slot handle + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_set_delay_line(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Set clock always on for the slot + * + * @param[in] slot SD Host Slot handle + * @param[in] always_on always on or not + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_NOT_FOUND: Command not found + */ +esp_err_t sd_host_slot_set_cclk_always_on_internal(sd_host_sdmmc_slot_t *slot, bool always_on); + +/** + * @brief Enable clock and cmd11 mode + * + * @param[in] slot SD Host Slot handle + * @param[in] enable enable or not + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + * - ESP_ERR_NOT_FOUND: Command not found + */ +void sd_host_slot_enable_clk_cmd11(sd_host_sdmmc_slot_t *slot, bool enable); + +/*--------------------------------------------------------------- + DMA APIs +---------------------------------------------------------------*/ +/** + * @brief Get free descriptor numbers + * + * @param[in] slot SD Host Slot handle + * + * @return + * Number of free descriptors + */ +size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Fill descriptor + * + * @param[in] slot SD Host Slot handle + * @param[in] num_desc Number of descriptors to fill + */ +void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc); + +/** + * @brief Stop DMA + * + * @param[in] slot SD Host Slot handle + */ +void sd_host_dma_stop(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Resume DMA + * + * @param[in] slot SD Host Slot handle + */ +void sd_host_dma_resume(sd_host_sdmmc_slot_t *slot); + +/** + * @brief Stop DMA + * + * @param[in] slot SD Host Slot handle + * @param[in] data_ptr Pointer to data + * @param[in] data_size Size of data + * @param[in] block_size Block size + */ +void sd_host_dma_prepare(sd_host_sdmmc_slot_t *slot, void* data_ptr, size_t data_size, size_t block_size); + +/*--------------------------------------------------------------- + Info APIs +---------------------------------------------------------------*/ +/** + * @brief Check SD buffer alignment + * + * @param[in] slot SD Host slot handle + * @param[in] buf Buffer pointer + * @param[in] size Buffer size + * + * @return + * - True: alignment requirement is satisfied + * - False: alignment requirement is not satisfied + */ +bool sd_host_check_buffer_alignment(sd_host_sdmmc_slot_t *slot, const void *buf, size_t size); + +/** + * @brief Get SD Host slot real frequency + * + * @param[in] slot SD Host Slot handle + * @param[out] real_freq_khz Real frequency in Hz + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_slot_get_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz); + +/** + * @brief Get SD Host slot real calculated frequency + * + * @note This is used to for protocol layer to get frequency + * SD Host driver will only make all registers valid when a real + * transaction is done (in `sd_host_slot_do_transaction`). Whereas protocol + * layer is querying real frequency in quite early stage + * + * @param[in] slot SD Host Slot handle + * @param[out] real_freq_khz Real frequency in Hz + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments + */ +esp_err_t sd_host_slot_get_calc_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz); +#endif //#if SOC_SDMMC_HOST_SUPPORTED + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_sdmmc/src/sd_host_sdmmc.c b/components/esp_driver_sdmmc/src/sd_host_sdmmc.c new file mode 100644 index 0000000000..35dcb6817c --- /dev/null +++ b/components/esp_driver_sdmmc/src/sd_host_sdmmc.c @@ -0,0 +1,1335 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "esp_log.h" +#include "esp_intr_alloc.h" +#include "esp_check.h" +#include "esp_clk_tree.h" +#include "esp_timer.h" +#include "esp_memory_utils.h" +#include "soc/chip_revision.h" +#include "soc/sdmmc_periph.h" +#include "soc/soc_caps.h" +#include "hal/efuse_hal.h" +#include "hal/sd_types.h" +#include "hal/sdmmc_hal.h" +#include "hal/sdmmc_ll.h" +#include "driver/sd_host.h" +#include "driver/sd_host_sdmmc.h" +#include "esp_private/sd_driver_interface.h" +#include "esp_private/esp_clk_tree_common.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_cache_private.h" +#include "esp_private/gpio.h" +#include "esp_private/sd_host_private.h" + +typedef struct sd_platform_t { + _lock_t mutex; + sd_host_sdmmc_ctlr_t *controllers[SDMMC_LL_HOST_CTLR_NUMS]; +} sd_platform_t; + +static const char *TAG = "SD_HOST"; +static sd_platform_t s_platform; + +//Controller Allocation +static esp_err_t sd_host_claim_controller(sd_host_sdmmc_ctlr_t *controller); +static esp_err_t sd_host_declaim_controller(sd_host_sdmmc_ctlr_t *controller); +//ISR Handler +static void sd_host_isr(void *arg); +//HW Commands +static esp_err_t sd_host_slot_clock_update_command(sd_host_sdmmc_slot_t *slot, bool is_cmd11); +//Control +static esp_err_t sd_host_reset(sd_host_sdmmc_ctlr_t *ctlr); +//Clock +static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk_src_t src, int div); +static int sd_host_calc_freq(soc_periph_sdmmc_clk_src_t src, const int host_div, const int card_div); +static void sd_host_slot_get_clk_dividers(sd_host_sdmmc_slot_t *slot, uint32_t freq_khz, int *host_div, int *card_div, soc_periph_sdmmc_clk_src_t *src); +//IO +static void configure_pin(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name, bool use_gpio_matrix); +static esp_err_t sdmmc_slot_io_config(sd_host_sdmmc_slot_t *slot, const sd_host_slot_sdmmc_init_cfg_t *slot_init_config); +//Public APIs +static esp_err_t sd_host_slot_sdmmc_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config); +static esp_err_t sd_host_slot_sdmmc_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data); +static esp_err_t sd_host_controller_remove_sdmmc_slot(sd_host_slot_handle_t slot); +static esp_err_t sd_host_del_sdmmc_controller(sd_host_ctlr_handle_t ctlr); +static esp_err_t sd_host_slot_sdmmc_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on); +static esp_err_t sd_host_slot_sdmmc_io_int_enable(sd_host_slot_handle_t slot); +static esp_err_t sd_host_slot_sdmmc_io_int_wait(sd_host_slot_handle_t slot, TickType_t timeout_ticks); +static esp_err_t sd_host_slot_sdmmc_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info); + +/*--------------------------------------------------------------- + Public APIs +---------------------------------------------------------------*/ +esp_err_t sd_host_create_sdmmc_controller(const sd_host_sdmmc_cfg_t *config, sd_host_ctlr_handle_t *ret_handle) +{ + esp_err_t ret = ESP_FAIL; + ESP_RETURN_ON_FALSE(config && ret_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + sd_host_sdmmc_ctlr_t *ctlr = heap_caps_calloc(1, sizeof(sd_host_sdmmc_ctlr_t), SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(ctlr, ESP_ERR_NO_MEM, TAG, "no mem for sd host controller context"); + + ret = sd_host_claim_controller(ctlr); + if (ret != ESP_OK) { + //claim fail, clean and return directly + free(ctlr); + ESP_RETURN_ON_ERROR(ret, TAG, "no available sd host controller"); + } + + size_t alignment = 0; + size_t cache_alignment_bytes = 0; + ret = esp_cache_get_alignment(0, &cache_alignment_bytes); + assert(ret == ESP_OK); + if (cache_alignment_bytes != 0) { + alignment = cache_alignment_bytes; + } else { + alignment = 4; + } + + ESP_LOGD(TAG, "size: %d, alignment: %d", sizeof(sdmmc_desc_t), alignment); + ctlr->dma_desc_num = config->dma_desc_num ? config->dma_desc_num : SD_HOST_SDMMC_DMA_DESC_CNT; + ctlr->dma_desc = heap_caps_aligned_calloc(alignment, 1, sizeof(sdmmc_desc_t) * ctlr->dma_desc_num, SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_LOGD(TAG, "ctlr->dma_desc addr: %p", ctlr->dma_desc); + ESP_RETURN_ON_FALSE(ctlr->dma_desc, ESP_ERR_NO_MEM, TAG, "no mem for dma descriptors"); + + ctlr->io_intr_sem = xSemaphoreCreateBinaryWithCaps(SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(ctlr->io_intr_sem, ESP_ERR_NO_MEM, err, TAG, "no mem for io interrupt semaphore"); + + ctlr->mutex = xSemaphoreCreateMutexWithCaps(SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(ctlr->mutex, ESP_ERR_NO_MEM, err, TAG, "no mem for mutex"); + + ctlr->event_queue = xQueueCreateWithCaps(config->event_queue_items ? config->event_queue_items : 4, sizeof(sd_host_sdmmc_event_t), SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(ctlr->event_queue, ESP_ERR_NO_MEM, err, TAG, "no mem for mutex"); + + //use `ETS_SDIO_HOST_INTR_SOURCE` for now, replace with `sdmmc_periph.c` then. IDF-12585 + ESP_GOTO_ON_ERROR(esp_intr_alloc(ETS_SDIO_HOST_INTR_SOURCE, 0, &sd_host_isr, ctlr, &ctlr->intr_handle), err, TAG, "failed to install interrupt service"); + +#if CONFIG_PM_ENABLE + ESP_GOTO_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "sdmmc", &ctlr->pm_lock), err, TAG, "failed to create pm lock"); +#endif //CONFIG_PM_ENABLE + + sdmmc_hal_init(&ctlr->hal); + sd_host_set_clk_div(ctlr, SDMMC_CLK_SRC_DEFAULT, 2); + + // Reset + esp_err_t err = sd_host_reset(ctlr); + if (err != ESP_OK) { + ESP_LOGE(TAG, "%s: sd_host_reset returned 0x%x", __func__, err); + return err; + } + + ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, sdmmc_ll_get_version_id(ctlr->hal.dev), sdmmc_ll_get_hw_config_info(ctlr->hal.dev)); + + sdmmc_ll_clear_interrupt(ctlr->hal.dev, 0xffffffff); + sdmmc_ll_enable_interrupt(ctlr->hal.dev, 0xffffffff, false); + sdmmc_ll_enable_global_interrupt(ctlr->hal.dev, false); + sdmmc_ll_enable_interrupt(ctlr->hal.dev, SDMMC_LL_EVENT_DEFAULT, true); + sdmmc_ll_enable_global_interrupt(ctlr->hal.dev, true); + sdmmc_ll_init_dma(ctlr->hal.dev); + + ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + ctlr->drv.del_ctlr = sd_host_del_sdmmc_controller; + *ret_handle = &ctlr->drv; + + return ESP_OK; + +err: + sd_host_del_sdmmc_controller(&ctlr->drv); + + return ret; +} + +esp_err_t sd_host_sdmmc_controller_add_slot(sd_host_ctlr_handle_t ctlr, const sd_host_slot_sdmmc_init_cfg_t *config, sd_host_slot_handle_t *ret_handle) +{ + esp_err_t ret = ESP_FAIL; + sd_host_sdmmc_ctlr_t *ctlr_ctx = __containerof(ctlr, sd_host_sdmmc_ctlr_t, drv); + ESP_RETURN_ON_FALSE(ctlr && config && ret_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(config->slot_id >= 0 && config->slot_id < SOC_SDMMC_NUM_SLOTS, ESP_ERR_INVALID_ARG, TAG, "invalid slot id"); + + sd_host_sdmmc_slot_t *slot = heap_caps_calloc(1, sizeof(sd_host_sdmmc_slot_t), SD_HOST_SDMMC_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(slot, ESP_ERR_NO_MEM, TAG, "no mem for sd host slot context"); + + bool slot_available = false; + portENTER_CRITICAL(&ctlr_ctx->spinlock); + if (!ctlr_ctx->slot[config->slot_id]) { + slot_available = true; + ctlr_ctx->slot[config->slot_id] = slot; + } + portEXIT_CRITICAL(&ctlr_ctx->spinlock); + ESP_GOTO_ON_FALSE(slot_available, ESP_ERR_INVALID_STATE, err, TAG, "slot is not available"); + + portENTER_CRITICAL(&ctlr_ctx->spinlock); + slot->slot_id = config->slot_id; + slot->sd_mode = config->sd_mode; + slot->freq.freq_hz = 400 * 1000; + slot->freq.freq_state = SD_HOST_SLOT_STATE_INIT; + slot->ctlr = ctlr_ctx; + ctlr_ctx->registered_slot_nums = ctlr_ctx->registered_slot_nums + 1; + + slot->drv.configure = sd_host_slot_sdmmc_configure; + slot->drv.do_transaction = sd_host_slot_sdmmc_do_transaction; + slot->drv.register_cbs = sd_host_slot_sdmmc_register_event_callbacks; + slot->drv.remove_slot = sd_host_controller_remove_sdmmc_slot; + slot->drv.set_cclk_always_on = sd_host_slot_sdmmc_set_cclk_always_on; + slot->drv.enable_io_int = sd_host_slot_sdmmc_io_int_enable; + slot->drv.wait_io_int = sd_host_slot_sdmmc_io_int_wait; + slot->drv.get_info = sd_host_slot_sdmmc_get_info; + portEXIT_CRITICAL(&ctlr_ctx->spinlock); + + ESP_GOTO_ON_ERROR(sdmmc_slot_io_config(slot, config), err, TAG, "failed to config slot io"); + + *ret_handle = &slot->drv; + + return ESP_OK; + +err: + free(slot); + + return ret; +} + +/*--------------------------------------------------------------- + Public API Impls +---------------------------------------------------------------*/ +static esp_err_t sd_host_slot_sdmmc_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config) +{ + ESP_RETURN_ON_FALSE(slot && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); +#if SDMMC_LL_DELAY_PHASE_SUPPORTED + ESP_RETURN_ON_FALSE(config->delay_phase.delayphase < SOC_SDMMC_DELAY_PHASE_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid delay phase"); +#else + //DIG-217 + ESP_LOGW(TAG, "esp32 doesn't support input phase delay, fallback to 0 delay"); +#endif + +#if SOC_SDMMC_UHS_I_SUPPORTED + ESP_RETURN_ON_FALSE(config->delay_line.delayline < SOC_SDMMC_DELAY_PHASE_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid delay line"); +#else + ESP_LOGW(TAG, "input line delay not supported, fallback to 0 delay"); +#endif + +#if CONFIG_IDF_TARGET_ESP32P4 + if (config->freq.freq_hz == SDMMC_FREQ_SDR104 * 1000) { + unsigned chip_version = efuse_hal_chip_revision(); + ESP_LOGD(TAG, "chip_version: %d", chip_version); + if (!ESP_CHIP_REV_ABOVE(chip_version, 200)) { + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "UHS-I SDR104 is not supported on ESP32P4 chips prior than v2.0"); + } + } +#endif + + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + portENTER_CRITICAL(&slot_ctx->ctlr->spinlock); + if (config->freq.override) { + slot_ctx->freq.freq_hz = config->freq.freq_hz; + slot_ctx->freq.freq_state = SD_HOST_SLOT_STATE_READY; + } + if (config->width.override) { + slot_ctx->width.width_state = SD_HOST_SLOT_STATE_READY; + } + if (config->sampling_mode.override) { + slot_ctx->sampling_mode.mode = config->sampling_mode.mode; + slot_ctx->sampling_mode.sampling_mode_state = SD_HOST_SLOT_STATE_READY; + } + if (config->delay_phase.override) { +#if SDMMC_LL_DELAY_PHASE_SUPPORTED + slot_ctx->delay_phase.delayphase = config->delay_phase.delayphase; +#else + slot_ctx->delay_phase.delayphase = SDMMC_DELAY_PHASE_0; +#endif + slot_ctx->delay_phase.delay_phase_state = SD_HOST_SLOT_STATE_READY; + } + if (config->delay_line.override) { +#if SOC_SDMMC_UHS_I_SUPPORTED + slot_ctx->delay_line.delayline = config->delay_line.delayline; +#else + slot_ctx->delay_line.delayline = SDMMC_DELAY_LINE_0; +#endif + slot_ctx->delay_line.delay_line_state = SD_HOST_SLOT_STATE_READY; + } + portEXIT_CRITICAL(&slot_ctx->ctlr->spinlock); + + return ESP_OK; +} + +static esp_err_t sd_host_slot_sdmmc_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data) +{ + ESP_RETURN_ON_FALSE(slot && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + +#if CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE + if (cbs->on_trans_done) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_trans_done), ESP_ERR_INVALID_ARG, TAG, "on_trans_done callback not in IRAM"); + } + if (cbs->on_io_interrupt) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_io_interrupt), ESP_ERR_INVALID_ARG, TAG, "on_io_interrupt callback not in IRAM"); + } +#endif + + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + slot_ctx->cbs.on_trans_done = cbs->on_trans_done; + slot_ctx->cbs.on_io_interrupt = cbs->on_io_interrupt; + slot_ctx->user_data = user_data; + + return ESP_OK; +} + +esp_err_t sd_host_slot_set_cclk_always_on_internal(sd_host_sdmmc_slot_t *slot, bool always_on) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + // During initialization this is not protected by a mutex + if (always_on) { + sdmmc_ll_enable_card_clock_low_power(slot->ctlr->hal.dev, slot->slot_id, false); + } else { + sdmmc_ll_enable_card_clock_low_power(slot->ctlr->hal.dev, slot->slot_id, true); + } + sd_host_slot_clock_update_command(slot, false); + + return ESP_OK; +} + +static esp_err_t sd_host_slot_sdmmc_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on) +{ + esp_err_t ret = ESP_FAIL; + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + + xSemaphoreTake(slot_ctx->ctlr->mutex, portMAX_DELAY); + ret = sd_host_slot_set_cclk_always_on_internal(slot_ctx, always_on); + xSemaphoreGive(slot_ctx->ctlr->mutex); + + ESP_RETURN_ON_ERROR(ret, TAG, "failed to set cclk always on"); + + return ESP_OK; +} + +static esp_err_t sd_host_controller_remove_sdmmc_slot(sd_host_slot_handle_t slot) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + sd_host_sdmmc_ctlr_t *ctlr = slot_ctx->ctlr; + + bool slot_registered = false; + portENTER_CRITICAL(&ctlr->spinlock); + if (ctlr->slot[slot_ctx->slot_id]) { + slot_registered = true; + ctlr->slot[slot_ctx->slot_id] = NULL; + ctlr->registered_slot_nums -= 1; + } + portEXIT_CRITICAL(&ctlr->spinlock); + ESP_RETURN_ON_FALSE(slot_registered, ESP_ERR_INVALID_STATE, TAG, "slot is not registered"); + + if (slot_ctx->io_config.clk_io != GPIO_NUM_NC) { + gpio_output_disable(slot_ctx->io_config.clk_io); + } + if (slot_ctx->io_config.cmd_io != GPIO_NUM_NC) { + gpio_output_disable(slot_ctx->io_config.cmd_io); + } + if (slot_ctx->io_config.cd_io != GPIO_NUM_NC) { + gpio_output_disable(slot_ctx->io_config.cd_io); + } + if (slot_ctx->io_config.wp_io != GPIO_NUM_NC) { + gpio_output_disable(slot_ctx->io_config.wp_io); + } + if (slot_ctx->io_config.width >= 1) { + gpio_output_disable(slot_ctx->io_config.d0_io); + } + if (slot_ctx->io_config.width >= 4) { + gpio_output_disable(slot_ctx->io_config.d1_io); + gpio_output_disable(slot_ctx->io_config.d2_io); + gpio_output_disable(slot_ctx->io_config.d3_io); + } + if (slot_ctx->io_config.width == 8) { + gpio_output_disable(slot_ctx->io_config.d4_io); + gpio_output_disable(slot_ctx->io_config.d5_io); + gpio_output_disable(slot_ctx->io_config.d6_io); + gpio_output_disable(slot_ctx->io_config.d7_io); + } + + free(slot); + + return ESP_OK; +} + +static esp_err_t sd_host_del_sdmmc_controller(sd_host_ctlr_handle_t ctlr) +{ + sd_host_sdmmc_ctlr_t *ctlr_ctx = __containerof(ctlr, sd_host_sdmmc_ctlr_t, drv); + ESP_RETURN_ON_FALSE(ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(ctlr_ctx->registered_slot_nums == 0, ESP_ERR_INVALID_STATE, TAG, "host controller with slot registered"); + + ESP_RETURN_ON_ERROR(sd_host_declaim_controller(ctlr_ctx), TAG, "controller isn't in use"); + ESP_RETURN_ON_ERROR(esp_intr_free(ctlr_ctx->intr_handle), TAG, "failed to delete interrupt service"); + + if (ctlr_ctx->event_queue) { + vQueueDeleteWithCaps(ctlr_ctx->event_queue); + } + if (ctlr_ctx->mutex) { + vSemaphoreDeleteWithCaps(ctlr_ctx->mutex); + } + if (ctlr_ctx->io_intr_sem) { + vSemaphoreDeleteWithCaps(ctlr_ctx->io_intr_sem); + } + if (ctlr_ctx->pm_lock) { + esp_pm_lock_delete(ctlr_ctx->pm_lock); + } + + free(ctlr_ctx->dma_desc); + ctlr_ctx->dma_desc = NULL; + free(ctlr_ctx); + ctlr_ctx = NULL; + + return ESP_OK; +} + +static esp_err_t sd_host_slot_sdmmc_io_int_enable(sd_host_slot_handle_t slot) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + configure_pin(slot_ctx->io_config.d1_io, sdmmc_slot_gpio_sig[slot_ctx->slot_id].d1, GPIO_MODE_INPUT_OUTPUT, "d1", slot_ctx->use_gpio_matrix); + return ESP_OK; +} + +static esp_err_t sd_host_slot_sdmmc_io_int_wait(sd_host_slot_handle_t slot, TickType_t timeout_ticks) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + esp_err_t ret = ESP_FAIL; + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + + /* SDIO interrupts are negedge sensitive ones: the status bit is only set + * when first interrupt triggered. + * + * If D1 GPIO is low when entering this function, we know that interrupt + * (in SDIO sense) has occurred and we don't need to use SDMMC peripheral + * interrupt. + */ + + /* Disable SDIO interrupt */ + if (slot_ctx->slot_id == 0) { + sdmmc_ll_enable_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT0, false); + sdmmc_ll_clear_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT0); + } else { + sdmmc_ll_enable_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT1, false); + sdmmc_ll_clear_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT1); + } + + if (gpio_get_level(slot_ctx->io_config.d1_io) == 0) { + return ESP_OK; + } + /* Otherwise, need to wait for an interrupt. Since D1 was high, + * SDMMC peripheral interrupt is guaranteed to trigger on negedge. + */ + xSemaphoreTake(slot_ctx->ctlr->io_intr_sem, 0); + + /* Re-enable SDIO interrupt */ + if (slot_ctx->slot_id == 0) { + sdmmc_ll_enable_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT0, true); + } else { + sdmmc_ll_enable_interrupt(slot_ctx->ctlr->hal.dev, SDMMC_INTMASK_IO_SLOT1, true); + } + + if (xSemaphoreTake(slot_ctx->ctlr->io_intr_sem, timeout_ticks) == pdTRUE) { + ret = ESP_OK; + } else { + ret = ESP_ERR_TIMEOUT; + } + + return ret; +} + +static esp_err_t sd_host_slot_sdmmc_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info) +{ + ESP_RETURN_ON_FALSE(slot && info, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + portENTER_CRITICAL(&slot_ctx->ctlr->spinlock); + info->freq_hz = slot_ctx->freq.real_freq_hz; + info->width = slot_ctx->width.width; + info->sd_mode = slot_ctx->sd_mode; + info->sampling_mode = slot_ctx->sampling_mode.mode; + portEXIT_CRITICAL(&slot_ctx->ctlr->spinlock); + + return ESP_OK; +} + +/*--------------------------------------------------------------- + Internal APIs +---------------------------------------------------------------*/ +bool sd_host_check_buffer_alignment(sd_host_sdmmc_slot_t *slot, const void *buf, size_t size) +{ + //for future-proof + (void)slot; + if (!buf || !size) { + return false; + } + + esp_err_t ret = ESP_FAIL; + int cache_flags = 0; + size_t cache_alignment_bytes = 0; + if (esp_ptr_external_ram(buf)) { + cache_flags |= MALLOC_CAP_SPIRAM; + } + ret = esp_cache_get_alignment(cache_flags, &cache_alignment_bytes); + assert(ret == ESP_OK); + + bool is_aligned = false; + size_t alignment = 0; + + if (cache_alignment_bytes != 0) { + alignment = cache_alignment_bytes; + } else { + alignment = SDMMC_DMA_ALIGNMENT; + } + + is_aligned = ((intptr_t)buf % alignment == 0) && (size % alignment == 0); + + return is_aligned; +} + +esp_err_t sd_host_slot_set_card_clk(sd_host_sdmmc_slot_t *slot) +{ + // Disable clock first + sdmmc_ll_enable_card_clock(slot->ctlr->hal.dev, slot->slot_id, false); + esp_err_t ret = sd_host_slot_clock_update_command(slot, false); + ESP_RETURN_ON_ERROR(ret, TAG, "%s: sd_host_slot_clock_update_command returned 0x%x, failed to disable clk, ", __func__, ret); + + int freq_khz = 0; + if (slot->freq.freq_state == SD_HOST_SLOT_STATE_READY) { + freq_khz = slot->freq.freq_hz / 1000; + } else { + freq_khz = 400; + } + ESP_LOGD(TAG, "freq: %d khz, state: %d", freq_khz, slot->freq.freq_state); + + soc_periph_sdmmc_clk_src_t clk_src = 0; + int host_div = 0; /* clock divider of the host (SDMMC.clock) */ + int card_div = 0; /* 1/2 of card clock divider (SDMMC.clkdiv) */ + sd_host_slot_get_clk_dividers(slot, freq_khz, &host_div, &card_div, &clk_src); + + int real_freq_khz = sd_host_calc_freq(clk_src, host_div, card_div); + slot->freq.real_freq_hz = real_freq_khz * 1000; + ESP_LOGD(TAG, "slot_id=%d clk_src=%d host_div=%d card_div=%d freq=%dkHz (max %" PRIu32 "kHz)", slot->slot_id, clk_src, host_div, card_div, real_freq_khz, freq_khz); + + // Program card clock settings, send them to the CIU + sdmmc_ll_set_card_clock_div(slot->ctlr->hal.dev, slot->slot_id, card_div); + sd_host_set_clk_div(slot->ctlr, clk_src, host_div); + ret = sd_host_slot_clock_update_command(slot, false); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "setting clk div failed"); + ESP_LOGE(TAG, "%s: sd_host_slot_clock_update_command returned 0x%x", __func__, ret); + return ret; + } + + // Re-enable clocks + sdmmc_ll_enable_card_clock(slot->ctlr->hal.dev, slot->slot_id, true); + sdmmc_ll_enable_card_clock_low_power(slot->ctlr->hal.dev, slot->slot_id, true); + ret = sd_host_slot_clock_update_command(slot, false); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "re-enabling clk failed"); + ESP_LOGE(TAG, "%s: sd_host_slot_clock_update_command returned 0x%x", __func__, ret); + return ret; + } + + const uint32_t data_timeout_ms = 100; + uint32_t data_timeout_cycles = data_timeout_ms * freq_khz; + sdmmc_ll_set_data_timeout(slot->ctlr->hal.dev, data_timeout_cycles); + // always set response timeout to highest value, it's small enough anyway + sdmmc_ll_set_response_timeout(slot->ctlr->hal.dev, 255); + + return ESP_OK; +} + +esp_err_t sd_host_slot_get_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz) +{ + ESP_RETURN_ON_FALSE(slot && real_freq_khz, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + int host_div = 0; + int card_div = 0; + host_div = sdmmc_ll_get_clock_div(slot->ctlr->hal.dev); + card_div = sdmmc_ll_get_card_clock_div(slot->ctlr->hal.dev, slot->slot_id); + *real_freq_khz = sd_host_calc_freq(slot->clk_src, host_div, card_div); + + return ESP_OK; +} + +esp_err_t sd_host_slot_get_calc_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz) +{ + ESP_RETURN_ON_FALSE(slot && real_freq_khz, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + soc_periph_sdmmc_clk_src_t clk_src = 0; + int host_div = 0; + int card_div = 0; + sd_host_slot_get_clk_dividers(slot, slot->freq.freq_hz / 1000, &host_div, &card_div, &clk_src); + *real_freq_khz = sd_host_calc_freq(slot->clk_src, host_div, card_div); + + return ESP_OK; +} + +esp_err_t sd_host_slot_set_bus_width(sd_host_sdmmc_slot_t *slot) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + int width = slot->width.width_state == SD_HOST_SLOT_STATE_READY ? slot->width.width : 1; + ESP_LOGD(TAG, "width: %d, state: %d", width, slot->width.width_state); + sd_host_sdmmc_slot_io_cfg_t *slot_gpio = &slot->io_config; + + if (width == 1) { + sdmmc_ll_set_card_width(slot->ctlr->hal.dev, slot->slot_id, SD_BUS_WIDTH_1_BIT); + } else if (width == 4) { + sdmmc_ll_set_card_width(slot->ctlr->hal.dev, slot->slot_id, SD_BUS_WIDTH_4_BIT); + // D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set + configure_pin(slot_gpio->d3_io, sdmmc_slot_gpio_sig[slot->slot_id].d3, GPIO_MODE_INPUT_OUTPUT, "d3", slot->use_gpio_matrix); + } else if (width == 8) { + sdmmc_ll_set_card_width(slot->ctlr->hal.dev, slot->slot_id, SD_BUS_WIDTH_8_BIT); + // D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set + configure_pin(slot_gpio->d3_io, sdmmc_slot_gpio_sig[slot->slot_id].d3, GPIO_MODE_INPUT_OUTPUT, "d3", slot->use_gpio_matrix); + } else { + return ESP_ERR_INVALID_ARG; + } + + ESP_LOGD(TAG, "slot_id=%d width=%d", slot->slot_id, width); + return ESP_OK; +} + +esp_err_t sd_host_slot_set_bus_sampling_mode(sd_host_sdmmc_slot_t *slot) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + if (slot->sampling_mode.sampling_mode_state == SD_HOST_SLOT_STATE_READY) { + ESP_RETURN_ON_FALSE((slot->width.width != 8), ESP_ERR_NOT_SUPPORTED, TAG, "DDR mode with 8-bit bus width is not supported yet"); + } + + bool ddr = false; + if (slot->sampling_mode.sampling_mode_state == SD_HOST_SLOT_STATE_READY) { + if (slot->sampling_mode.mode == SD_SAMPLING_MODE_DDR) { + ddr = true; + } + } + + sdmmc_ll_enable_ddr_mode(slot->ctlr->hal.dev, slot->slot_id, ddr); + ESP_LOGD(TAG, "slot_id=%d ddr=%d", slot->slot_id, ddr ? 1 : 0); + + return ESP_OK; +} + +esp_err_t sd_host_set_delay_phase(sd_host_sdmmc_slot_t *slot) +{ +#if SDMMC_LL_DELAY_PHASE_SUPPORTED + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + sdmmc_delay_phase_t delay_phase = SDMMC_DELAY_PHASE_0; + if (slot->delay_phase.delay_phase_state == SD_HOST_SLOT_STATE_READY) { + delay_phase = slot->delay_phase.delayphase; + } + + uint32_t clk_src_freq_hz = 0; + ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(slot->clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz), + TAG, "get source clock frequency failed"); + + //Now we're in high speed. Note ESP SDMMC Host HW only supports integer divider. + int delay_phase_num = 0; + sdmmc_ll_delay_phase_t phase = SDMMC_LL_DELAY_PHASE_0; + sdmmc_ll_speed_mode_t speed_mode = (slot->freq.freq_hz / 1000) == SDMMC_FREQ_SDR104 ? SDMMC_LL_SPEED_MODE_HS : SDMMC_LL_SPEED_MODE_LS; + switch (delay_phase) { + case SDMMC_DELAY_PHASE_1: + phase = SDMMC_LL_DELAY_PHASE_1; + delay_phase_num = 1; + break; + case SDMMC_DELAY_PHASE_2: + phase = SDMMC_LL_DELAY_PHASE_2; + delay_phase_num = 2; + break; + case SDMMC_DELAY_PHASE_3: + phase = SDMMC_LL_DELAY_PHASE_3; + delay_phase_num = 3; + break; +#if SOC_SDMMC_DELAY_PHASE_NUM > 4 + case SDMMC_DELAY_PHASE_4: + phase = SDMMC_LL_DELAY_PHASE_4; + delay_phase_num = 4; + break; + case SDMMC_DELAY_PHASE_5: + phase = SDMMC_LL_DELAY_PHASE_5; + delay_phase_num = 5; + break; + case SDMMC_DELAY_PHASE_6: + phase = SDMMC_LL_DELAY_PHASE_6; + delay_phase_num = 6; + break; + case SDMMC_DELAY_PHASE_7: + phase = SDMMC_LL_DELAY_PHASE_7; + delay_phase_num = 7; + break; +#endif + default: + phase = SDMMC_LL_DELAY_PHASE_0; + delay_phase_num = 0; + break; + } + SD_HOST_SDMMC_CLK_SRC_ATOMIC() { + sdmmc_ll_set_din_delay_phase(slot->ctlr->hal.dev, phase, speed_mode); + sdmmc_ll_set_dout_delay_phase(slot->ctlr->hal.dev, phase, speed_mode); + } + + int src_clk_period_ps = (1 * 1000 * 1000) / (clk_src_freq_hz / (1 * 1000 * 1000)); + int delay_phase_total_num = (slot->freq.freq_hz / 1000) == SDMMC_FREQ_SDR104 ? SOC_SDMMC_DELAY_PHASE_NUM : SDMMC_LL_DELAY_MAX_NUMS_LS; + ESP_LOGD(TAG, "slot->freq.freq_hz: %d, delay_phase_total_num: %d", slot->freq.freq_hz, delay_phase_total_num); + int phase_diff_ps = src_clk_period_ps * sdmmc_ll_get_clock_div(slot->ctlr->hal.dev) / delay_phase_total_num; + ESP_LOGD(TAG, "difference between delay phases is %d ps", phase_diff_ps); + ESP_LOGD(TAG, "host sampling edge is delayed by %d ps", phase_diff_ps * delay_phase_num); + + return ESP_OK; +#else + //DIG-217 + ESP_LOGD(TAG, "esp32 doesn't support phase delay, fallback to 0 delay"); + return ESP_OK; +#endif +} + +esp_err_t sd_host_set_delay_line(sd_host_sdmmc_slot_t *slot) +{ +#if SOC_SDMMC_UHS_I_SUPPORTED + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + if ((slot->freq.freq_hz / 1000) == SDMMC_FREQ_SDR104) { + sdmmc_delay_line_t delay_line = SDMMC_DELAY_LINE_0; + if (slot->delay_line.delay_line_state == SD_HOST_SLOT_STATE_READY) { + delay_line = slot->delay_line.delayline; + } + + sdmmc_ll_delay_line_t line = SDMMC_LL_DELAY_LINE_0; + switch (delay_line) { + case SDMMC_DELAY_LINE_1: + line = SDMMC_LL_DELAY_LINE_1; + break; + case SDMMC_DELAY_LINE_2: + line = SDMMC_LL_DELAY_LINE_2; + break; + case SDMMC_DELAY_LINE_3: + line = SDMMC_LL_DELAY_LINE_3; + break; + case SDMMC_DELAY_LINE_4: + line = SDMMC_LL_DELAY_LINE_4; + break; + case SDMMC_DELAY_LINE_5: + line = SDMMC_LL_DELAY_LINE_5; + break; + case SDMMC_DELAY_LINE_6: + line = SDMMC_LL_DELAY_LINE_6; + break; + case SDMMC_DELAY_LINE_7: + line = SDMMC_LL_DELAY_LINE_7; + break; + default: + line = SDMMC_LL_DELAY_LINE_0; + break; + } + sdmmc_ll_set_din_delay_line(slot->ctlr->hal.dev, line, SDMMC_LL_SPEED_MODE_HS); + sdmmc_ll_set_dout_delay_line(slot->ctlr->hal.dev, line, SDMMC_LL_SPEED_MODE_HS); + } + + return ESP_OK; +#else + ESP_LOGD(TAG, "delay line not supported, fallback to 0 delay line"); + return ESP_OK; +#endif +} + +void sd_host_slot_enable_clk_cmd11(sd_host_sdmmc_slot_t *slot, bool enable) +{ + sdmmc_ll_enable_card_clock(slot->ctlr->hal.dev, slot->slot_id, enable); + sd_host_slot_clock_update_command(slot, true); + sdmmc_ll_enable_1v8_mode(slot->ctlr->hal.dev, slot->slot_id, enable); +} + +/*--------------------------------------------------------------- + Static: Controller Allocation +---------------------------------------------------------------*/ +static esp_err_t sd_host_claim_controller(sd_host_sdmmc_ctlr_t *controller) +{ + assert(controller); + + _lock_acquire(&s_platform.mutex); + bool found = false; + for (int i = 0; i < SDMMC_LL_HOST_CTLR_NUMS; i ++) { + found = !s_platform.controllers[i]; + if (found) { + s_platform.controllers[i] = controller; + controller->host_id = i; + SD_HOST_SDMMC_RCC_ATOMIC() { + sdmmc_ll_enable_bus_clock(i, true); + sdmmc_ll_reset_register(i); + } + break; + } + } + _lock_release(&s_platform.mutex); + + if (!found) { + return ESP_ERR_NOT_FOUND; + } + return ESP_OK; +} + +static esp_err_t sd_host_declaim_controller(sd_host_sdmmc_ctlr_t *controller) +{ + assert(controller); + + _lock_acquire(&s_platform.mutex); + s_platform.controllers[controller->host_id] = NULL; + SD_HOST_SDMMC_RCC_ATOMIC() { + sdmmc_ll_enable_bus_clock(0, false); + } + _lock_release(&s_platform.mutex); + + return ESP_OK; +} + +/*--------------------------------------------------------------- + Static: ISR Handler +---------------------------------------------------------------*/ +static void sd_host_isr(void *arg) +{ + sd_host_sdmmc_ctlr_t *ctlr = (sd_host_sdmmc_ctlr_t *)arg; + sd_host_sdmmc_slot_t *slot = ctlr->slot[ctlr->cur_slot_id]; + + sd_host_sdmmc_event_t event = {}; + bool need_yield = false; + int higher_priority_task_awoken = pdFALSE; + + uint32_t pending = sdmmc_ll_get_intr_status(ctlr->hal.dev) & SDMMC_LL_SD_EVENT_MASK; + sdmmc_ll_clear_interrupt(ctlr->hal.dev, pending); + event.sdmmc_status = pending; + + uint32_t dma_pending = sdmmc_ll_get_idsts_interrupt_raw(ctlr->hal.dev); + sdmmc_ll_clear_idsts_interrupt(ctlr->hal.dev, dma_pending); + + if (dma_pending & SDMMC_LL_EVENT_DMA_NI) { + // refill DMA descriptors + size_t free_desc = sd_host_get_free_descriptors_count(slot); + if (free_desc > 0) { + sd_host_fill_dma_descriptors(slot, free_desc); + sd_host_dma_resume(slot); + } + //NI, logic OR of TI and RI. This is a sticky bit and must be cleared each time TI or RI is cleared. + dma_pending &= ~(SDMMC_LL_EVENT_DMA_NI | SDMMC_LL_EVENT_DMA_TI | SDMMC_LL_EVENT_DMA_RI); + } + event.dma_status = dma_pending & SDMMC_LL_EVENT_DMA_MASK; + + if (pending != 0 || dma_pending != 0) { + xQueueSendFromISR(ctlr->event_queue, &event, &higher_priority_task_awoken); + if (slot->cbs.on_trans_done) { + sd_host_evt_data_t edata = {}; + if (slot->cbs.on_trans_done(&slot->drv, &edata, slot->user_data)) { + need_yield |= true; + } + } + } + + uint32_t sdio_pending = (sdmmc_ll_get_intr_status(ctlr->hal.dev) & (SDMMC_INTMASK_IO_SLOT1 | SDMMC_INTMASK_IO_SLOT0)); + if (sdio_pending) { + // disable the interrupt (no need to clear here, this is done in sdmmc_host_io_int_wait) + sdmmc_ll_enable_interrupt(ctlr->hal.dev, sdio_pending, false); + xSemaphoreGiveFromISR(ctlr->io_intr_sem, &higher_priority_task_awoken); + if (slot->cbs.on_io_interrupt) { + sd_host_evt_data_t edata = {}; + if (slot->cbs.on_io_interrupt(&slot->drv, &edata, slot->user_data)) { + need_yield |= true; + } + } + } + + need_yield |= higher_priority_task_awoken == pdTRUE; + if (need_yield) { + portYIELD_FROM_ISR(); + } +} + +/*--------------------------------------------------------------- + HW Commands +---------------------------------------------------------------*/ +esp_err_t sd_host_slot_start_command(sd_host_sdmmc_slot_t *slot, sdmmc_hw_cmd_t cmd, uint32_t arg) +{ + ESP_RETURN_ON_FALSE(slot, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + // if this isn't a clock update command, check the card detect status + if (!sdmmc_ll_is_card_detected(slot->ctlr->hal.dev, slot->slot_id) && !cmd.update_clk_reg) { + return ESP_ERR_NOT_FOUND; + } + if (cmd.data_expected && cmd.rw && sdmmc_ll_is_card_write_protected(slot->ctlr->hal.dev, slot->slot_id)) { + return ESP_ERR_INVALID_STATE; + } + /* Outputs should be synchronized to cclk_out */ + cmd.use_hold_reg = 1; + + int64_t yield_delay_us = 100 * 1000; // initially 100ms + int64_t t0 = esp_timer_get_time(); + int64_t t1 = 0; + bool skip_wait = (cmd.volt_switch && cmd.update_clk_reg); + if (!skip_wait) { + while (!(sdmmc_ll_is_command_taken(slot->ctlr->hal.dev))) { + t1 = esp_timer_get_time(); + if (t1 - t0 > SD_HOST_SDMMC_START_CMD_TIMEOUT_US) { + return ESP_ERR_TIMEOUT; + } + if (t1 - t0 > yield_delay_us) { + yield_delay_us *= 2; + vTaskDelay(1); + } + } + } + sdmmc_ll_set_command_arg(slot->ctlr->hal.dev, arg); + cmd.card_num = slot->slot_id; + cmd.start_command = 1; + sdmmc_ll_set_command(slot->ctlr->hal.dev, cmd); + + while (!(sdmmc_ll_is_command_taken(slot->ctlr->hal.dev))) { + t1 = esp_timer_get_time(); + if (t1 - t0 > SD_HOST_SDMMC_START_CMD_TIMEOUT_US) { + return ESP_ERR_TIMEOUT; + } + if (t1 - t0 > yield_delay_us) { + yield_delay_us *= 2; + vTaskDelay(1); + } + } + return ESP_OK; +} + +static esp_err_t sd_host_slot_clock_update_command(sd_host_sdmmc_slot_t *slot, bool is_cmd11) +{ + assert(slot); + + // Clock update command (not a real command; just updates CIU registers) + sdmmc_hw_cmd_t cmd_val = { + .card_num = slot->slot_id, + .update_clk_reg = 1, + .wait_complete = 1 + }; + if (is_cmd11) { + cmd_val.volt_switch = 1; + } + ESP_RETURN_ON_ERROR(sd_host_slot_start_command(slot, cmd_val, 0), TAG, "sd_host_start_command returned 0x%x", err_rc_); + + return ESP_OK; +} + +/*--------------------------------------------------------------- + Static: Controls +---------------------------------------------------------------*/ +static void s_module_reset(sd_host_sdmmc_ctlr_t *ctlr) +{ + // reset module + sdmmc_ll_reset_controller(ctlr->hal.dev); + sdmmc_ll_reset_dma(ctlr->hal.dev); + sdmmc_ll_reset_fifo(ctlr->hal.dev); +} + +static bool s_is_module_reset_done(sd_host_sdmmc_ctlr_t *ctlr) +{ + bool is_done = sdmmc_ll_is_controller_reset_done(ctlr->hal.dev) && sdmmc_ll_is_dma_reset_done(ctlr->hal.dev) && sdmmc_ll_is_fifo_reset_done(ctlr->hal.dev); + return is_done; +} + +static esp_err_t sd_host_reset(sd_host_sdmmc_ctlr_t *ctlr) +{ + s_module_reset(ctlr); + + // Wait for the reset bits to be cleared by hardware + int64_t yield_delay_us = 100 * 1000; // initially 100ms + int64_t t0 = esp_timer_get_time(); + int64_t t1 = 0; + while (!s_is_module_reset_done(ctlr)) { + t1 = esp_timer_get_time(); + if (t1 - t0 > SD_HOST_SDMMC_RESET_TIMEOUT_US) { + return ESP_ERR_TIMEOUT; + } + if (t1 - t0 > yield_delay_us) { + yield_delay_us *= 2; + vTaskDelay(1); + } + } + + return ESP_OK; +} + +/*--------------------------------------------------------------- + Static: Clock +---------------------------------------------------------------*/ +/* We have two clock divider stages: + * - one is the clock generator which drives SDMMC peripheral, + * it can be configured using SDMMC.clock register. It can generate + * frequencies 160MHz/(N + 1), where 0 < N < 16, I.e. from 10 to 80 MHz. + * - 4 clock dividers inside SDMMC peripheral, which can divide clock + * from the first stage by 2 * M, where 0 < M < 255 + * (they can also be bypassed). + * + * For cards which aren't UHS-1 or UHS-2 cards, which we don't support, + * maximum bus frequency in high speed (HS) mode is 50 MHz. + * Note: for non-UHS-1 cards, HS mode is optional. + * Default speed (DS) mode is mandatory, it works up to 25 MHz. + * Whether the card supports HS or not can be determined using TRAN_SPEED + * field of card's CSD register. + * + * 50 MHz can not be obtained exactly, closest we can get is 53 MHz. + * + * The first stage divider is set to the highest possible value for the given + * frequency, and the the second stage dividers are used if division factor + * is >16. + * + * Of the second stage dividers, div0 is used for card 0, and div1 is used + * for card 1. + */ +static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk_src_t src, int div) +{ + esp_clk_tree_enable_src((soc_module_clk_t)src, true); + SD_HOST_SDMMC_CLK_SRC_ATOMIC() { + sdmmc_ll_set_clock_div(ctlr->hal.dev, div); + sdmmc_ll_select_clk_source(ctlr->hal.dev, src); + sdmmc_ll_init_phase_delay(ctlr->hal.dev); +#if SOC_CLK_SDIO_PLL_SUPPORTED + if (src == SDMMC_CLK_SRC_SDIO_200M) { + sdmmc_ll_enable_sdio_pll(ctlr->hal.dev, true); + } +#endif + } + + // Wait for the clock to propagate + esp_rom_delay_us(10); +} + +static void sd_host_slot_get_clk_dividers(sd_host_sdmmc_slot_t *slot, uint32_t freq_khz, int *host_div, int *card_div, soc_periph_sdmmc_clk_src_t *src) +{ + uint32_t clk_src_freq_hz = 0; + soc_periph_sdmmc_clk_src_t clk_src = 0; +#if SOC_SDMMC_UHS_I_SUPPORTED + if (freq_khz > SDMMC_FREQ_HIGHSPEED) { + clk_src = SDMMC_CLK_SRC_SDIO_200M; + } else +#endif + { + clk_src = SDMMC_CLK_SRC_DEFAULT; + } + slot->clk_src = clk_src; + + esp_err_t ret = esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + assert(ret == ESP_OK); + ESP_LOGD(TAG, "clk_src_freq_hz: %"PRId32" hz", clk_src_freq_hz); + +#if SDMMC_LL_MAX_FREQ_KHZ_FPGA + if (freq_khz >= SDMMC_LL_MAX_FREQ_KHZ_FPGA) { + ESP_LOGW(TAG, "working on FPGA, fallback to use the %d KHz", SDMMC_LL_MAX_FREQ_KHZ_FPGA); + freq_khz = SDMMC_LL_MAX_FREQ_KHZ_FPGA; + } +#endif + + // Calculate new dividers +#if SOC_SDMMC_UHS_I_SUPPORTED + if (freq_khz == SDMMC_FREQ_SDR104) { + *host_div = 1; // 200 MHz / 1 = 200 MHz + *card_div = 0; + } else if (freq_khz == SDMMC_FREQ_SDR50) { + *host_div = 2; // 200 MHz / 2 = 100 MHz + *card_div = 0; + } else +#endif + if (freq_khz >= SDMMC_FREQ_HIGHSPEED) { + *host_div = 4; // 160 MHz / 4 = 40 MHz + *card_div = 0; + } else if (freq_khz == SDMMC_FREQ_DEFAULT) { + *host_div = 8; // 160 MHz / 8 = 20 MHz + *card_div = 0; + } else if (freq_khz == SDMMC_FREQ_PROBING) { + *host_div = 10; // 160 MHz / 10 / (20 * 2) = 400 kHz + *card_div = 20; + } else { + /* + * for custom frequencies use maximum range of host divider (1-16), find the closest <= div. combination + * if exceeded, combine with the card divider to keep reasonable precision (applies mainly to low frequencies) + * effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme) + */ + *host_div = (clk_src_freq_hz) / (freq_khz * 1000); + if (*host_div > 15) { + *host_div = 2; + *card_div = (clk_src_freq_hz / 2) / (2 * freq_khz * 1000); + if (((clk_src_freq_hz / 2) % (2 * freq_khz * 1000)) > 0) { + (*card_div)++; + } + } else if ((clk_src_freq_hz % (freq_khz * 1000)) > 0) { + (*host_div)++; + } + } + + *src = clk_src; +} + +static int sd_host_calc_freq(soc_periph_sdmmc_clk_src_t src, const int host_div, const int card_div) +{ + uint32_t clk_src_freq_hz = 0; + esp_err_t ret = esp_clk_tree_src_get_freq_hz(src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + assert(ret == ESP_OK); + + return clk_src_freq_hz / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000; +} + +/*--------------------------------------------------------------- + Static: IO +---------------------------------------------------------------*/ +static void configure_pin_iomux(uint8_t gpio_num) +{ + assert(gpio_num != (uint8_t) GPIO_NUM_NC); + gpio_pulldown_dis(gpio_num); + gpio_input_enable(gpio_num); + gpio_iomux_output(gpio_num, SDMMC_LL_IOMUX_FUNC); +#if !CONFIG_IDF_TARGET_ESP32 + /** + * On ESP32, the default pin drive value (2) works + */ + gpio_set_drive_capability(gpio_num, 3); +#endif +} + +static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name) +{ + assert(gpio_num != (uint8_t) GPIO_NUM_NC); + ESP_LOGD(TAG, "using GPIO%d as %s pin", gpio_num, name); + //todo: IDF-11125 + gpio_reset_pin(gpio_num); + gpio_set_direction(gpio_num, mode); + gpio_pulldown_dis(gpio_num); + if (mode == GPIO_MODE_INPUT || mode == GPIO_MODE_INPUT_OUTPUT) { + esp_rom_gpio_connect_in_signal(gpio_num, gpio_matrix_sig, false); + } + if (mode == GPIO_MODE_OUTPUT || mode == GPIO_MODE_INPUT_OUTPUT) { + esp_rom_gpio_connect_out_signal(gpio_num, gpio_matrix_sig, false, false); + } +} + +static void configure_pin(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name, bool use_gpio_matrix) +{ + if (use_gpio_matrix) { + configure_pin_gpio_matrix(gpio_num, gpio_matrix_sig, mode, name); + } else { + configure_pin_iomux(gpio_num); + } +} + +//True: pins are all not set; False: one or more pins are set +static bool s_check_pin_not_set(const sd_host_sdmmc_slot_io_cfg_t *io_config) +{ +#if SOC_SDMMC_USE_GPIO_MATRIX + bool pin_not_set = !io_config->clk_io && !io_config->cmd_io && !io_config->d0_io && !io_config->d1_io && !io_config->d2_io && + !io_config->d3_io && !io_config->d4_io && !io_config->d5_io && !io_config->d6_io && !io_config->d7_io; + return pin_not_set; +#else + return true; +#endif +} + +static esp_err_t sdmmc_host_pullup_en_internal(sd_host_sdmmc_slot_t *slot) +{ + if (slot->width.width > sdmmc_slot_info[slot->slot_id].width) { + //in esp32 we only support 8 bit in slot 0, note this is occupied by the flash by default + return ESP_ERR_INVALID_ARG; + } + // according to the spec, the host controls the clk, we don't to pull it up here + gpio_pullup_en(slot->io_config.cmd_io); + gpio_pullup_en(slot->io_config.d0_io); + if (slot->width.width >= 4) { + gpio_pullup_en(slot->io_config.d1_io); + gpio_pullup_en(slot->io_config.d2_io); + gpio_pullup_en(slot->io_config.d3_io); + } + if (slot->width.width == 8) { + gpio_pullup_en(slot->io_config.d4_io); + gpio_pullup_en(slot->io_config.d5_io); + gpio_pullup_en(slot->io_config.d6_io); + gpio_pullup_en(slot->io_config.d7_io); + } + return ESP_OK; +} + +static esp_err_t sdmmc_slot_io_config(sd_host_sdmmc_slot_t *slot, const sd_host_slot_sdmmc_init_cfg_t *slot_init_config) +{ + bool gpio_wp_polarity = slot_init_config->slot_flags.wp_active_high; + sd_bus_width_t slot_width = slot_init_config->io_config.width; + int slot_id = slot_init_config->slot_id; + + const sdmmc_slot_info_t *slot_info = &sdmmc_slot_info[slot_id]; + ESP_RETURN_ON_FALSE(slot_width <= slot_info->width, ESP_ERR_INVALID_ARG, TAG, "wrong slot width"); + if (slot_width == SD_HOST_SLOT_WIDTH_DEFAULT) { + slot_width = slot_info->width; + } + + const sd_host_sdmmc_slot_io_cfg_t *io_config = &slot_init_config->io_config; + sd_host_sdmmc_slot_io_cfg_t *slot_gpio = &slot->io_config; + + slot->io_config.clk_io = GPIO_NUM_NC; + slot->io_config.cmd_io = GPIO_NUM_NC; + slot->io_config.cd_io = GPIO_NUM_NC; + slot->io_config.wp_io = GPIO_NUM_NC; + slot->io_config.d0_io = GPIO_NUM_NC; + slot->io_config.d1_io = GPIO_NUM_NC; + slot->io_config.d2_io = GPIO_NUM_NC; + slot->io_config.d3_io = GPIO_NUM_NC; + slot->io_config.d4_io = GPIO_NUM_NC; + slot->io_config.d5_io = GPIO_NUM_NC; + slot->io_config.d6_io = GPIO_NUM_NC; + slot->io_config.d7_io = GPIO_NUM_NC; + slot->width.width = slot_width; + slot->width.width_state = SD_HOST_SLOT_STATE_INIT; + slot_gpio->cd_io = io_config->cd_io; + slot_gpio->wp_io = io_config->wp_io; + + bool pin_not_set = s_check_pin_not_set(io_config); + //SD driver behaviour is: all pins not defined == using iomux + bool use_gpio_matrix = !pin_not_set; + + if (slot_id == 0) { +#if !SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(0) + if (use_gpio_matrix && + SDMMC_SLOT0_IOMUX_PIN_NUM_CLK == io_config->clk_io && + SDMMC_SLOT0_IOMUX_PIN_NUM_CMD == io_config->cmd_io && + SDMMC_SLOT0_IOMUX_PIN_NUM_D0 == io_config->d0_io && + SDMMC_SLOT0_IOMUX_PIN_NUM_D1 == io_config->d1_io && + SDMMC_SLOT0_IOMUX_PIN_NUM_D2 == io_config->d2_io && + SDMMC_SLOT0_IOMUX_PIN_NUM_D3 == io_config->d3_io) { + use_gpio_matrix = false; + } else { + ESP_RETURN_ON_FALSE(!use_gpio_matrix, ESP_ERR_INVALID_ARG, TAG, "doesn't support routing from GPIO matrix, driver uses dedicated IOs"); + } +#endif + } else { +#if !SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(1) + ESP_RETURN_ON_FALSE(!use_gpio_matrix, ESP_ERR_INVALID_ARG, TAG, "doesn't support routing from GPIO matrix, driver uses dedicated IOs"); +#endif + } + slot->use_gpio_matrix = use_gpio_matrix; + +#if SOC_SDMMC_USE_GPIO_MATRIX + if (use_gpio_matrix) { + /* Save pin configuration for this slot */ + slot_gpio->clk_io = io_config->clk_io; + slot_gpio->cmd_io = io_config->cmd_io; + slot_gpio->d0_io = io_config->d0_io; + /* Save d1 even in 1-line mode, it might be needed for SDIO INT line */ + slot_gpio->d1_io = io_config->d1_io; + if (slot_width >= 4) { + slot_gpio->d2_io = io_config->d2_io; + } + /* Save d3 even for 1-line mode, as it needs to be set high */ + slot_gpio->d3_io = io_config->d3_io; + if (slot_width >= 8) { + slot_gpio->d4_io = io_config->d4_io; + slot_gpio->d5_io = io_config->d5_io; + slot_gpio->d6_io = io_config->d6_io; + slot_gpio->d7_io = io_config->d7_io; + } + } else +#endif //#if SOC_SDMMC_USE_GPIO_MATRIX + { + /* init pin configuration for this slot */ + slot_gpio->clk_io = sdmmc_slot_gpio_num[slot_id].clk; + slot_gpio->cmd_io = sdmmc_slot_gpio_num[slot_id].cmd; + slot_gpio->d0_io = sdmmc_slot_gpio_num[slot_id].d0; + slot_gpio->d1_io = sdmmc_slot_gpio_num[slot_id].d1; + slot_gpio->d2_io = sdmmc_slot_gpio_num[slot_id].d2; + slot_gpio->d3_io = sdmmc_slot_gpio_num[slot_id].d3; + slot_gpio->d4_io = sdmmc_slot_gpio_num[slot_id].d4; + slot_gpio->d5_io = sdmmc_slot_gpio_num[slot_id].d5; + slot_gpio->d6_io = sdmmc_slot_gpio_num[slot_id].d6; + slot_gpio->d7_io = sdmmc_slot_gpio_num[slot_id].d7; + } + + bool pullup = slot_init_config->slot_flags.internal_pullup; + if (pullup) { + sdmmc_host_pullup_en_internal(slot); + } + + if (slot_width >= 1) { + GPIO_NUM_CHECK(slot_gpio->clk_io); + GPIO_NUM_CHECK(slot_gpio->cmd_io); + GPIO_NUM_CHECK(slot_gpio->d0_io); + } + if (slot_width >= 4) { + GPIO_NUM_CHECK(slot_gpio->d1_io); + GPIO_NUM_CHECK(slot_gpio->d2_io); + GPIO_NUM_CHECK(slot_gpio->d3_io); + } + if (slot_width == 8) { + GPIO_NUM_CHECK(slot_gpio->d4_io); + GPIO_NUM_CHECK(slot_gpio->d5_io); + GPIO_NUM_CHECK(slot_gpio->d6_io); + GPIO_NUM_CHECK(slot_gpio->d7_io); + } + + configure_pin(slot_gpio->clk_io, sdmmc_slot_gpio_sig[slot_id].clk, GPIO_MODE_OUTPUT, "clk", use_gpio_matrix); + configure_pin(slot_gpio->cmd_io, sdmmc_slot_gpio_sig[slot_id].cmd, GPIO_MODE_INPUT_OUTPUT, "cmd", use_gpio_matrix); + configure_pin(slot_gpio->d0_io, sdmmc_slot_gpio_sig[slot_id].d0, GPIO_MODE_INPUT_OUTPUT, "d0", use_gpio_matrix); + + if (slot_width >= 4) { + configure_pin(slot_gpio->d1_io, sdmmc_slot_gpio_sig[slot_id].d1, GPIO_MODE_INPUT_OUTPUT, "d1", use_gpio_matrix); + configure_pin(slot_gpio->d2_io, sdmmc_slot_gpio_sig[slot_id].d2, GPIO_MODE_INPUT_OUTPUT, "d2", use_gpio_matrix); + if (slot->sd_mode == SD_MODE_UHS1) { + configure_pin(slot_gpio->d3_io, sdmmc_slot_gpio_sig[slot_id].d3, GPIO_MODE_INPUT_OUTPUT, "d3", use_gpio_matrix); + } else { + // Force D3 high to make slave enter SD mode. + // Connect to peripheral after width configuration. + if (slot_gpio->d3_io > GPIO_NUM_NC) { + gpio_config_t gpio_conf = { + .pin_bit_mask = BIT64(slot_gpio->d3_io), + .mode = GPIO_MODE_OUTPUT, + .pull_up_en = 0, + .pull_down_en = 0, + .intr_type = GPIO_INTR_DISABLE, + }; + gpio_config(&gpio_conf); + gpio_set_level(slot_gpio->d3_io, 1); + } + } + } + if (slot_width == 8) { + configure_pin(slot_gpio->d4_io, sdmmc_slot_gpio_sig[slot_id].d4, GPIO_MODE_INPUT_OUTPUT, "d4", use_gpio_matrix); + configure_pin(slot_gpio->d5_io, sdmmc_slot_gpio_sig[slot_id].d5, GPIO_MODE_INPUT_OUTPUT, "d5", use_gpio_matrix); + configure_pin(slot_gpio->d6_io, sdmmc_slot_gpio_sig[slot_id].d6, GPIO_MODE_INPUT_OUTPUT, "d6", use_gpio_matrix); + configure_pin(slot_gpio->d7_io, sdmmc_slot_gpio_sig[slot_id].d7, GPIO_MODE_INPUT_OUTPUT, "d7", use_gpio_matrix); + } + + // SDIO slave interrupt is edge sensitive to ~(int_n | card_int | card_detect) + // set this and card_detect to high to enable sdio interrupt + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, slot_info->card_int, false); + + // Set up Card Detect input + int matrix_in_cd = 0; + if (io_config->cd_io != GPIO_NUM_NC) { + ESP_LOGD(TAG, "using GPIO%d as CD pin", io_config->cd_io); + esp_rom_gpio_pad_select_gpio(io_config->cd_io); + gpio_set_direction(io_config->cd_io, GPIO_MODE_INPUT); + matrix_in_cd = io_config->cd_io; + } else { + // if not set, default to CD low (card present) + matrix_in_cd = GPIO_MATRIX_CONST_ZERO_INPUT; + } + esp_rom_gpio_connect_in_signal(matrix_in_cd, slot_info->card_detect, false); + + // Set up Write Protect input + int matrix_in_wp; + if (io_config->wp_io != GPIO_NUM_NC) { + ESP_LOGD(TAG, "using GPIO%d as WP pin", io_config->wp_io); + esp_rom_gpio_pad_select_gpio(io_config->wp_io); + gpio_set_direction(io_config->wp_io, GPIO_MODE_INPUT); + matrix_in_wp = io_config->wp_io; + } else { + // if not set, default to WP high (not write protected) + matrix_in_wp = GPIO_MATRIX_CONST_ONE_INPUT; + } + // As hardware expects an active-high signal, + // if WP signal is active low, then invert it in GPIO matrix, + // else keep it in its default state + esp_rom_gpio_connect_in_signal(matrix_in_wp, slot_info->write_protect, (gpio_wp_polarity ? false : true)); + + return ESP_OK; +} diff --git a/components/esp_driver_sdmmc/src/sd_trans_sdmmc.c b/components/esp_driver_sdmmc/src/sd_trans_sdmmc.c new file mode 100644 index 0000000000..0874bfb688 --- /dev/null +++ b/components/esp_driver_sdmmc/src/sd_trans_sdmmc.c @@ -0,0 +1,588 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +* +* SPDX-License-Identifier: Apache-2.0 +*/ + +#include +#include +#include +#include +#include +#include "esp_log.h" +#include "esp_intr_alloc.h" +#include "esp_check.h" +#include "soc/soc_caps.h" +#include "driver/sd_host.h" +#include "esp_private/sd_host_private.h" + +typedef enum { + SDMMC_IDLE, + SDMMC_SENDING_CMD, + SDMMC_SENDING_DATA, + SDMMC_BUSY, + SDMMC_SENDING_VOLTAGE_SWITCH, + SDMMC_WAITING_VOLTAGE_SWITCH, +} sdmmc_req_state_t; + +static const char *TAG = "SD_TRANS"; + +const uint32_t SD_DATA_ERR_MASK = + SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC | + SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE | + SDMMC_INTMASK_EBE; + +const uint32_t SD_DMA_DONE_MASK = + SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI | + SDMMC_IDMAC_INTMASK_NI; + +const uint32_t SD_CMD_ERR_MASK = + SDMMC_INTMASK_RTO | + SDMMC_INTMASK_RCRC | + SDMMC_INTMASK_RESP_ERR; + +/*--------------------------------------------------------------- + Voltage +---------------------------------------------------------------*/ +static void handle_voltage_switch_stage1(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd) +{ + ESP_LOGV(TAG, "%s: enabling clock", __func__); + sd_host_slot_set_cclk_always_on_internal(slot, true); +} + +static void handle_voltage_switch_stage2(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd) +{ + ESP_LOGV(TAG, "%s: disabling clock", __func__); + sd_host_slot_enable_clk_cmd11(slot, false); + usleep(100); + ESP_LOGV(TAG, "%s: switching voltage", __func__); + esp_err_t err = cmd->volt_switch_cb(cmd->volt_switch_cb_arg, 1800); + if (err != ESP_OK) { + ESP_LOGE(TAG, "failed to switch voltage (0x%x)", err); + cmd->error = err; + } + ESP_LOGV(TAG, "%s: waiting 10ms", __func__); + usleep(10000); + ESP_LOGV(TAG, "%s: enabling clock", __func__); + sd_host_slot_enable_clk_cmd11(slot, true); +} + +static void handle_voltage_switch_stage3(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd) +{ + ESP_LOGV(TAG, "%s: voltage switch complete, clock back to low-power mode", __func__); + sd_host_slot_set_cclk_always_on_internal(slot, false); +} + +/*--------------------------------------------------------------- + DMA +---------------------------------------------------------------*/ +size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot) +{ + const size_t next = slot->ctlr->cur_transfer.next_desc; + size_t count = 0; + /* Starting with the current DMA descriptor, count the number of + * descriptors which have 'owned_by_idmac' set to 0. These are the + * descriptors already processed by the DMA engine. + */ + int dma_desc_num = slot->ctlr->dma_desc_num; + for (size_t i = 0; i < dma_desc_num; ++i) { + sdmmc_desc_t *desc = slot->ctlr->dma_desc + ((next + i) % dma_desc_num); +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_M2C); + assert(ret == ESP_OK); +#endif + if (desc->owned_by_idmac) { + break; + } + ++count; + if (desc->next_desc_ptr == NULL) { + /* final descriptor in the chain */ + break; + } + } + return count; +} + +void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc) +{ + sd_host_sdmmc_trans_state_t *cur_trans = &slot->ctlr->cur_transfer; + for (size_t i = 0; i < num_desc; ++i) { + if (cur_trans->size_remaining == 0) { + return; + } + const size_t next = cur_trans->next_desc; + sdmmc_desc_t *desc = slot->ctlr->dma_desc + next; + assert(!desc->owned_by_idmac); + size_t size_to_fill = + (cur_trans->size_remaining < SDMMC_DMA_MAX_BUF_LEN) ? + cur_trans->size_remaining : SDMMC_DMA_MAX_BUF_LEN; + bool last = size_to_fill == cur_trans->size_remaining; + desc->last_descriptor = last; + desc->second_address_chained = 1; + desc->owned_by_idmac = 1; + desc->buffer1_ptr = cur_trans->ptr; + desc->next_desc_ptr = (last) ? NULL : slot->ctlr->dma_desc + ((next + 1) % num_desc); + assert(size_to_fill < 4 || size_to_fill % 4 == 0); + desc->buffer1_size = (size_to_fill + 3) & (~3); + + cur_trans->size_remaining -= size_to_fill; + cur_trans->ptr += size_to_fill; + cur_trans->next_desc = (cur_trans->next_desc + 1) % num_desc; + ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d", + num_desc, next, cur_trans->size_remaining, + cur_trans->next_desc, desc->last_descriptor, desc->buffer1_size); +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M); + assert(ret == ESP_OK); +#endif + } +} + +void sd_host_dma_stop(sd_host_sdmmc_slot_t *slot) +{ + sdmmc_ll_stop_dma(slot->ctlr->hal.dev); +} + +void sd_host_dma_resume(sd_host_sdmmc_slot_t *slot) +{ + sdmmc_ll_poll_demand(slot->ctlr->hal.dev); +} + +void sd_host_dma_prepare(sd_host_sdmmc_slot_t *slot, void *data_ptr, size_t data_size, size_t block_size) +{ + // this clears "owned by IDMAC" bits + memset(slot->ctlr->dma_desc, 0, sizeof(sdmmc_desc_t) * slot->ctlr->dma_desc_num); + // initialize first descriptor + sdmmc_desc_t *desc = slot->ctlr->dma_desc; + desc->first_descriptor = 1; + // save transfer info + slot->ctlr->cur_transfer.ptr = data_ptr; + slot->ctlr->cur_transfer.size_remaining = data_size; + slot->ctlr->cur_transfer.next_desc = 0; + slot->ctlr->cur_transfer.desc_remaining = (data_size + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN; + // prepare descriptors + sd_host_fill_dma_descriptors(slot, slot->ctlr->dma_desc_num); + + // Set size of data and DMA descriptor pointer + sdmmc_ll_set_data_transfer_len(slot->ctlr->hal.dev, data_size); + sdmmc_ll_set_block_size(slot->ctlr->hal.dev, block_size); + sdmmc_ll_set_desc_addr(slot->ctlr->hal.dev, (uint32_t)desc); + // Enable everything needed to use DMA + sdmmc_ll_enable_dma(slot->ctlr->hal.dev, true); + sd_host_dma_resume(slot); +} + +/*--------------------------------------------------------------- + CMD +---------------------------------------------------------------*/ +static bool cmd_needs_auto_stop(const sdmmc_command_t *cmd) +{ + /* SDMMC host needs an "auto stop" flag for the following commands: */ + return cmd->datalen > 0 && + (cmd->opcode == MMC_WRITE_BLOCK_MULTIPLE || + cmd->opcode == MMC_READ_BLOCK_MULTIPLE || + cmd->opcode == MMC_WRITE_DAT_UNTIL_STOP || + cmd->opcode == MMC_READ_DAT_UNTIL_STOP); +} + +static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t *cmd) +{ + sdmmc_hw_cmd_t res = { 0 }; + + res.cmd_index = cmd->opcode; + if (cmd->opcode == MMC_STOP_TRANSMISSION) { + res.stop_abort_cmd = 1; + } else if (cmd->opcode == MMC_GO_IDLE_STATE) { + res.send_init = 1; + } else if (cmd->opcode == SD_SWITCH_VOLTAGE) { + res.volt_switch = 1; + } else { + res.wait_complete = 1; + } + if (cmd->opcode == MMC_GO_IDLE_STATE) { + res.send_init = 1; + } + + if (cmd->flags & SCF_RSP_PRESENT) { + res.response_expect = 1; + if (cmd->flags & SCF_RSP_136) { + res.response_long = 1; + } + } + if (cmd->flags & SCF_RSP_CRC) { + res.check_response_crc = 1; + } + if (cmd->data) { + res.data_expected = 1; + if ((cmd->flags & SCF_CMD_READ) == 0) { + res.rw = 1; + } + assert(cmd->datalen % cmd->blklen == 0); + res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0; + } + ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__, + res.cmd_index, res.response_expect, res.check_response_crc, + res.send_auto_stop); + return res; +} + +static inline bool mask_check_and_clear(uint32_t *state, uint32_t mask) +{ + bool ret = ((*state) & mask) != 0; + *state &= ~mask; + return ret; +} + +static void process_command_response(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd) +{ + if (cmd->flags & SCF_RSP_PRESENT) { + if (cmd->flags & SCF_RSP_136) { + /* Destination is 4-byte aligned, can memcopy from peripheral registers */ + memcpy(cmd->response, (uint32_t*) SDMMC.resp, 4 * sizeof(uint32_t)); + } else { + cmd->response[0] = SDMMC.resp[0]; + cmd->response[1] = 0; + cmd->response[2] = 0; + cmd->response[3] = 0; + } + } + esp_err_t err = ESP_OK; + if (status & SDMMC_INTMASK_RTO) { + // response timeout is only possible when response is expected + assert(cmd->flags & SCF_RSP_PRESENT); + err = ESP_ERR_TIMEOUT; + } else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) { + err = ESP_ERR_INVALID_CRC; + } else if (status & SDMMC_INTMASK_RESP_ERR) { + err = ESP_ERR_INVALID_RESPONSE; + } + if (err != ESP_OK) { + cmd->error = err; + if (cmd->data) { + sd_host_dma_stop(slot); + } + ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, err, status); + } +} + +/*--------------------------------------------------------------- + Events +---------------------------------------------------------------*/ +static esp_err_t sd_host_wait_for_event(sd_host_sdmmc_slot_t *slot, int tick_count, sd_host_sdmmc_event_t *out_event) +{ + assert(out_event); + assert(slot->ctlr->event_queue); + + int ret = xQueueReceive(slot->ctlr->event_queue, out_event, tick_count); + if (ret == pdFALSE) { + return ESP_ERR_TIMEOUT; + } + return ESP_OK; +} + +static esp_err_t sd_host_handle_idle_state_events(sd_host_sdmmc_slot_t *slot) +{ + /* Handle any events which have happened in between transfers. + * Under current assumptions (no SDIO support) only card detect events + * can happen in the idle state. + */ + sd_host_sdmmc_event_t evt; + while (sd_host_wait_for_event(slot, 0, &evt) == ESP_OK) { + if (evt.sdmmc_status & SDMMC_INTMASK_CD) { + ESP_LOGV(TAG, "card detect event"); + evt.sdmmc_status &= ~SDMMC_INTMASK_CD; + } + if (evt.sdmmc_status != 0 || evt.dma_status != 0) { + ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32, + evt.sdmmc_status, evt.dma_status); + } + + } + return ESP_OK; +} + +static void process_data_status(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd) +{ + if (status & SD_DATA_ERR_MASK) { + if (status & SDMMC_INTMASK_DTO) { + cmd->error = ESP_ERR_TIMEOUT; + } else if (status & SDMMC_INTMASK_DCRC) { + cmd->error = ESP_ERR_INVALID_CRC; + } else if ((status & SDMMC_INTMASK_EBE) && + (cmd->flags & SCF_CMD_READ) == 0) { + cmd->error = ESP_ERR_TIMEOUT; + } else { + cmd->error = ESP_FAIL; + } + SDMMC.ctrl.fifo_reset = 1; + } + if (cmd->error != 0) { + if (cmd->data) { + sd_host_dma_stop(slot); + } + ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, cmd->error, status); + } + +} + +static esp_err_t process_events(sd_host_sdmmc_slot_t *slot, sd_host_sdmmc_event_t evt, sdmmc_command_t *cmd, + sdmmc_req_state_t *pstate, sd_host_sdmmc_event_t *unhandled_events) +{ + const char* const s_state_names[] __attribute__((unused)) = { + "IDLE", + "SENDING_CMD", + "SENDIND_DATA", + "BUSY", + "SENDING_VOLTAGE_SWITCH", + "WAITING_VOLTAGE_SWITCH", + }; + sd_host_sdmmc_event_t orig_evt = evt; + ESP_LOGV(TAG, "%s: slot_id=%d state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, slot->slot_id, + s_state_names[*pstate], evt.sdmmc_status, evt.dma_status); + sdmmc_req_state_t next_state = *pstate; + sdmmc_req_state_t state = (sdmmc_req_state_t) -1; + while (next_state != state) { + state = next_state; + switch (state) { + case SDMMC_IDLE: + break; + + case SDMMC_SENDING_CMD: + if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) { + process_command_response(slot, orig_evt.sdmmc_status, cmd); + // In addition to the error interrupt, CMD_DONE will also be + // reported. It may occur immediately (in the same sd_host_sdmmc_event_t) or + // be delayed until the next interrupt. + } + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) { + process_command_response(slot, orig_evt.sdmmc_status, cmd); + if (cmd->error != ESP_OK) { + next_state = SDMMC_IDLE; + break; + } + + if (cmd->data == NULL) { + next_state = SDMMC_IDLE; + } else { + next_state = SDMMC_SENDING_DATA; + } + } + break; + + case SDMMC_SENDING_VOLTAGE_SWITCH: + if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) { + process_command_response(slot, orig_evt.sdmmc_status, cmd); + next_state = SDMMC_IDLE; + } + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) { + handle_voltage_switch_stage2(slot, cmd); + if (cmd->error != ESP_OK) { + next_state = SDMMC_IDLE; + } else { + next_state = SDMMC_WAITING_VOLTAGE_SWITCH; + } + } + break; + + case SDMMC_WAITING_VOLTAGE_SWITCH: + if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) { + process_command_response(slot, orig_evt.sdmmc_status, cmd); + next_state = SDMMC_IDLE; + } + if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) { + handle_voltage_switch_stage3(slot, cmd); + next_state = SDMMC_IDLE; + } + break; + + case SDMMC_SENDING_DATA: + if (mask_check_and_clear(&evt.sdmmc_status, SD_DATA_ERR_MASK)) { + process_data_status(slot, orig_evt.sdmmc_status, cmd); + sd_host_dma_stop(slot); + } + if (mask_check_and_clear(&evt.dma_status, SD_DMA_DONE_MASK)) { + next_state = SDMMC_BUSY; + } + if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) { + // On start bit error, DATA_DONE interrupt will not be generated + next_state = SDMMC_IDLE; + break; + } + break; + + case SDMMC_BUSY: + if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) { + break; + } + process_data_status(slot, orig_evt.sdmmc_status, cmd); + next_state = SDMMC_IDLE; + break; + } + ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]); + } + *pstate = state; + *unhandled_events = evt; + return ESP_OK; +} + +static esp_err_t handle_event(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd, sdmmc_req_state_t *state, + sd_host_sdmmc_event_t *unhandled_events) +{ + sd_host_sdmmc_event_t event; + esp_err_t err = sd_host_wait_for_event(slot, cmd->timeout_ms / portTICK_PERIOD_MS, &event); + if (err != ESP_OK) { + ESP_LOGE(TAG, "sd_host_wait_for_event returned 0x%x", err); + if (err == ESP_ERR_TIMEOUT) { + sd_host_dma_stop(slot); + } + return err; + } + ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32, + slot->slot_id, event.sdmmc_status, event.dma_status, + unhandled_events->sdmmc_status, unhandled_events->dma_status); + event.sdmmc_status |= unhandled_events->sdmmc_status; + event.dma_status |= unhandled_events->dma_status; + process_events(slot, event, cmd, state, unhandled_events); + ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d events unhandled: %08"PRIx32" %08"PRIx32, slot->slot_id, unhandled_events->sdmmc_status, unhandled_events->dma_status); + return ESP_OK; +} + +static bool sd_host_card_busy(sd_host_sdmmc_slot_t *slot) +{ + return sdmmc_ll_is_card_data_busy(slot->ctlr->hal.dev); +} + +static bool wait_for_busy_cleared(sd_host_sdmmc_slot_t *slot, uint32_t timeout_ms) +{ + if (timeout_ms == 0) { + return !sd_host_card_busy(slot); + } + + /* It would have been nice to do this without polling, however the peripheral + * can only generate Busy Clear Interrupt for data write commands, and waiting + * for busy clear is mostly needed for other commands such as MMC_SWITCH. + */ + uint32_t timeout_ticks = (timeout_ms + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS; + while (timeout_ticks-- > 0) { + if (!sd_host_card_busy(slot)) { + return true; + } + vTaskDelay(1); + } + return false; +} + +/*--------------------------------------------------------------- + Public API Impl +---------------------------------------------------------------*/ +esp_err_t sd_host_slot_sdmmc_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo) +{ + esp_err_t ret = ESP_FAIL; + ESP_RETURN_ON_FALSE(slot && cmdinfo, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv); + + xSemaphoreTake(slot_ctx->ctlr->mutex, portMAX_DELAY); + if (slot_ctx->ctlr->pm_lock) { + ESP_GOTO_ON_ERROR(esp_pm_lock_acquire(slot_ctx->ctlr->pm_lock), out, TAG, "acquire pm_lock failed"); + } + slot_ctx->ctlr->cur_slot_id = slot_ctx->slot_id; + + // By default, set probing frequency (400kHz) and 1-bit bus + if (slot_ctx->freq.freq_state != SD_HOST_SLOT_STATE_READY) { + ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk"); + } else { + int real_freq_khz = 0; + ret = sd_host_slot_get_real_freq(slot_ctx, &real_freq_khz); + assert(ret == ESP_OK); + if (real_freq_khz != (slot_ctx->freq.freq_hz / 1000)) { + ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk"); + } + } + ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_width(slot_ctx), out, TAG, "failed to set width"); + ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_sampling_mode(slot_ctx), out, TAG, "failed to set sampling mode"); + ESP_GOTO_ON_ERROR(sd_host_set_delay_phase(slot_ctx), out, TAG, "failed to set delay phase"); + ESP_GOTO_ON_ERROR(sd_host_set_delay_line(slot_ctx), out, TAG, "failed to set delay line"); + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + // cache sync related + size_t cache_sync_len = 0; +#endif + + // dispose of any events which happened asynchronously + sd_host_handle_idle_state_events(slot_ctx); + + // special handling for voltage switch command + if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) { + handle_voltage_switch_stage1(slot_ctx, cmdinfo); + } + + // convert cmdinfo to hardware register value + sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo); + if (cmdinfo->data) { + // Length should be either <4 or >=4 and =0 (mod 4). + if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) { + ESP_LOGE(TAG, "%s: invalid size: total=%d", + __func__, cmdinfo->datalen); + ret = ESP_ERR_INVALID_SIZE; + goto out; + } + + bool is_aligned = sd_host_check_buffer_alignment(slot_ctx, cmdinfo->data, cmdinfo->buflen); + if (!is_aligned) { + ESP_LOGE(TAG, "%s: buffer %p can not be used for DMA", __func__, cmdinfo->data); + ret = ESP_ERR_INVALID_ARG; + goto out; + } + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + cache_sync_len = cmdinfo->buflen; + ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M); + if (ret != ESP_OK) { + goto out; + } +#endif + // write transfer info into hardware + sd_host_dma_prepare(slot_ctx, cmdinfo->data, cmdinfo->datalen, cmdinfo->blklen); + } + // write command into hardware, this also sends the command to the card + ret = sd_host_slot_start_command(slot_ctx, hw_cmd, cmdinfo->arg); + if (ret != ESP_OK) { + goto out; + } + // process events until transfer is complete + cmdinfo->error = ESP_OK; + sdmmc_req_state_t state = SDMMC_SENDING_CMD; + if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) { + state = SDMMC_SENDING_VOLTAGE_SWITCH; + } + sd_host_sdmmc_event_t unhandled_events = {}; + while (state != SDMMC_IDLE) { + ret = handle_event(slot_ctx, cmdinfo, &state, &unhandled_events); + if (ret != ESP_OK) { + break; + } + } + if (ret == ESP_OK && (cmdinfo->flags & SCF_WAIT_BUSY)) { + if (!wait_for_busy_cleared(slot_ctx, cmdinfo->timeout_ms)) { + ret = ESP_ERR_TIMEOUT; + } + } + slot_ctx->ctlr->is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == MMC_APP_CMD); + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + if (cmdinfo->data) { + ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C); + if (ret != ESP_OK) { + goto out; + } + } +#endif + +out: + if (slot_ctx->ctlr->pm_lock) { + ESP_RETURN_ON_ERROR(esp_pm_lock_release(slot_ctx->ctlr->pm_lock), TAG, "release pm_lock failed"); + } + xSemaphoreGive(slot_ctx->ctlr->mutex); + + return ret; +} diff --git a/components/hal/esp32/include/hal/sdmmc_ll.h b/components/hal/esp32/include/hal/sdmmc_ll.h index a509637723..225d4d8a67 100644 --- a/components/hal/esp32/include/hal/sdmmc_ll.h +++ b/components/hal/esp32/include/hal/sdmmc_ll.h @@ -84,9 +84,8 @@ extern "C" { * SDMMC capabilities */ #define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 0 - - -#define SDMMC_LL_IOMUX_FUNC 3 +#define SDMMC_LL_IOMUX_FUNC 3 +#define SDMMC_LL_HOST_CTLR_NUMS 1U typedef enum { SDMMC_LL_DELAY_PHASE_0, @@ -102,11 +101,12 @@ typedef enum { /** * @brief Enable the bus clock for SDMMC module * - * @param hw hardware instance address - * @param en enable / disable + * @param group_id Group ID + * @param en enable / disable */ -static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) +static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en) { + (void)group_id; if (en) { DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_SDIO_HOST_EN); } else { @@ -121,10 +121,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) /** * @brief Reset the SDMMC module * - * @param hw hardware instance address + * @param group_id Group ID */ -static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw) +static inline void sdmmc_ll_reset_register(int group_id) { + (void)group_id; DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST); } @@ -256,10 +257,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo uint32_t card_div = 0; if (slot == 0) { - HAL_ASSERT(hw->clksrc.card0 == 0); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div0); } else if (slot == 1) { - HAL_ASSERT(hw->clksrc.card1 == 1); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div1); } else { HAL_ASSERT(false); diff --git a/components/hal/esp32p4/include/hal/sdmmc_ll.h b/components/hal/esp32p4/include/hal/sdmmc_ll.h index 2710b0d778..573dc17a53 100644 --- a/components/hal/esp32p4/include/hal/sdmmc_ll.h +++ b/components/hal/esp32p4/include/hal/sdmmc_ll.h @@ -104,11 +104,12 @@ typedef enum { /** * @brief Enable the bus clock for SDMMC module * - * @param hw hardware instance address - * @param en enable / disable + * @param group_id Group ID + * @param en enable / disable */ -static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) +static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en) { + (void)group_id; HP_SYS_CLKRST.soc_clk_ctrl1.reg_sdmmc_sys_clk_en = en; } @@ -119,10 +120,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) /** * @brief Reset the SDMMC module * - * @param hw hardware instance address + * @param group_id Group ID */ -static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw) +static inline void sdmmc_ll_reset_register(int group_id) { + (void)group_id; LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 1; LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 0; } @@ -348,10 +350,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo uint32_t card_div = 0; if (slot == 0) { - HAL_ASSERT(hw->clksrc.card0 == 0); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, clk_divider0); } else if (slot == 1) { - HAL_ASSERT(hw->clksrc.card1 == 1); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, clk_divider1); } else { HAL_ASSERT(false); diff --git a/components/hal/esp32s3/include/hal/sdmmc_ll.h b/components/hal/esp32s3/include/hal/sdmmc_ll.h index d5d450fa26..dc67f7437e 100644 --- a/components/hal/esp32s3/include/hal/sdmmc_ll.h +++ b/components/hal/esp32s3/include/hal/sdmmc_ll.h @@ -101,11 +101,12 @@ typedef enum { /** * @brief Enable the bus clock for SDMMC module * - * @param hw hardware instance address - * @param en enable / disable + * @param group_id Group ID + * @param en enable / disable */ -static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) +static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en) { + (void)group_id; SYSTEM.perip_clk_en1.sdio_host_clk_en = en; } @@ -116,10 +117,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en) /** * @brief Reset the SDMMC module * - * @param hw hardware instance address + * @param group_id Group ID */ -static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw) +static inline void sdmmc_ll_reset_register(int group_id) { + (void)group_id; SYSTEM.perip_rst_en1.sdio_host_rst = 1; SYSTEM.perip_rst_en1.sdio_host_rst = 0; } @@ -292,10 +294,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo uint32_t card_div = 0; if (slot == 0) { - HAL_ASSERT(hw->clksrc.card0 == 0); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div0); } else if (slot == 1) { - HAL_ASSERT(hw->clksrc.card1 == 1); card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div1); } else { HAL_ASSERT(false); diff --git a/components/hal/include/hal/sd_types.h b/components/hal/include/hal/sd_types.h index bdc2a6fa85..4b26ab1519 100644 --- a/components/hal/include/hal/sd_types.h +++ b/components/hal/include/hal/sd_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,34 @@ extern "C" { * @brief SD bus width */ typedef enum { - SD_BUS_WIDTH_1_BIT, ///< 1 bit - SD_BUS_WIDTH_4_BIT, ///< 4 bit - SD_BUS_WIDTH_8_BIT, ///< 8 bit + SD_BUS_WIDTH_1_BIT = 1, ///< 1 bit + SD_BUS_WIDTH_4_BIT = 4, ///< 4 bit + SD_BUS_WIDTH_8_BIT = 8, ///< 8 bit } sd_bus_width_t; + /** + * @brief SD mode + */ + typedef enum { + SD_MODE_NORMAL, ///< Normal SD mode + SD_MODE_UHS1, ///< UHS-I SD mode +} sd_mode_t; + + /** + * @brief SD sampling mode + */ + typedef enum { + SD_SAMPLING_MODE_SDR, ///< Single data rate mode + SD_SAMPLING_MODE_DDR, ///< Double data rate mode +} sd_sampling_mode_t; +#if SOC_SDMMC_DATA_WIDTH_MAX +#define SDMMC_DATA_SIG_NUM SOC_SDMMC_DATA_WIDTH_MAX ///< Number of data signals +#else +#define SDMMC_DATA_SIG_NUM 0 ///< Number of data signals +#endif + +#define SDMMC_DMA_ALIGNMENT 4 + #ifdef __cplusplus } #endif diff --git a/components/sdmmc/include/sd_protocol_types.h b/components/sdmmc/include/sd_protocol_types.h index 66a5bfe499..473f88d432 100644 --- a/components/sdmmc/include/sd_protocol_types.h +++ b/components/sdmmc/include/sd_protocol_types.h @@ -29,6 +29,7 @@ #include "freertos/FreeRTOS.h" #include "sd_pwr_ctrl.h" #include "esp_dma_utils.h" +#include "hal/sd_types.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 7517216c38..df9a0f1f25 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -943,6 +943,10 @@ config SOC_SDMMC_NUM_SLOTS int default 2 +config SOC_SDMMC_DATA_WIDTH_MAX + int + default 8 + config SOC_WIFI_WAPI_SUPPORT bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 199b940414..0cac7c2bf5 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -442,8 +442,9 @@ /* On ESP32, clock/cmd/data pins use IO MUX. * Card detect, write protect, interrupt use GPIO Matrix on all chips. */ -#define SOC_SDMMC_USE_IOMUX 1 -#define SOC_SDMMC_NUM_SLOTS 2 +#define SOC_SDMMC_USE_IOMUX 1 +#define SOC_SDMMC_NUM_SLOTS 2 +#define SOC_SDMMC_DATA_WIDTH_MAX 8 /*-------------------------- WI-FI HARDWARE CAPS -------------------------------*/ #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 3f20a61b83..1144f28235 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1415,9 +1415,13 @@ config SOC_SDMMC_NUM_SLOTS int default 2 +config SOC_SDMMC_DATA_WIDTH_MAX + int + default 8 + config SOC_SDMMC_DELAY_PHASE_NUM int - default 4 + default 8 config SOC_SDMMC_IO_POWER_EXTERNAL bool diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 3d54409089..4bbcdd900c 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -511,8 +511,9 @@ #define SOC_SDMMC_USE_IOMUX 1 #define SOC_SDMMC_USE_GPIO_MATRIX 1 #define SOC_SDMMC_NUM_SLOTS 2 +#define SOC_SDMMC_DATA_WIDTH_MAX 8 /* Supported host clock delay phase number */ -#define SOC_SDMMC_DELAY_PHASE_NUM 4 +#define SOC_SDMMC_DELAY_PHASE_NUM 8 #define SOC_SDMMC_IO_POWER_EXTERNAL 1 ///< SDMMC IO power controlled by external power supply #define SOC_SDMMC_PSRAM_DMA_CAPABLE 1 ///< SDMMC peripheral can do DMA transfer to/from PSRAM #define SOC_SDMMC_UHS_I_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 45f2afeaf5..6f3479aea9 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -1463,6 +1463,10 @@ config SOC_SDMMC_NUM_SLOTS int default 2 +config SOC_SDMMC_DATA_WIDTH_MAX + int + default 8 + config SOC_SDMMC_SUPPORT_XTAL_CLOCK bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 7f761a3a86..3280410efe 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -574,6 +574,7 @@ */ #define SOC_SDMMC_USE_GPIO_MATRIX 1 #define SOC_SDMMC_NUM_SLOTS 2 +#define SOC_SDMMC_DATA_WIDTH_MAX 8 /* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */ #define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1 /* Supported host clock delay phase number */ diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index 87d1877ae1..a4c2e99aaf 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -134,9 +134,12 @@ INPUT = \ $(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_types.h \ $(PROJECT_PATH)/components/esp_driver_sdio/include/driver/sdio_slave.h \ $(PROJECT_PATH)/components/esp_driver_sdm/include/driver/sdm.h \ - $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h \ - $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_host.h \ - $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_types.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_default_configs.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_host.h \ + $(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_types.h \ + $(PROJECT_PATH)/components/esp_driver_sd_intf/include/driver/sd_host.h \ + $(PROJECT_PATH)/components/esp_driver_sd_intf/include/driver/sd_types.h \ $(PROJECT_PATH)/components/esp_driver_sdspi/include/driver/sdspi_host.h \ $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_common.h \ $(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_master.h \