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system: update edma reset in system_api_esp32c3/s3.c

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This commit is contained in:
Armando
2021-01-22 20:23:54 +08:00
committed by bot
parent f5f0461264
commit 402ccacc10
2 changed files with 5 additions and 6 deletions
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6
components/esp32c3/system_api_esp32c3.c
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@@ -100,16 +100,12 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset timer/spi/uart // Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SPI3_DMA_RST | SYSTEM_SPI2_DMA_RST); SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
// Reset dma // Reset dma
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
// Set CPU back to XTAL source, no PLL, same as hard reset // Set CPU back to XTAL source, no PLL, same as hard reset
#if !CONFIG_IDF_ENV_FPGA #if !CONFIG_IDF_ENV_FPGA
rtc_clk_cpu_freq_set_xtal(); rtc_clk_cpu_freq_set_xtal();

5
components/esp32s3/system_api_esp32s3.c
View File

@@ -98,13 +98,16 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset timer/spi/uart // Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SPI3_DMA_RST | SYSTEM_SPI2_DMA_RST); SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
// Reset dma // Reset dma
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
// Set CPU back to XTAL source, no PLL, same as hard reset // Set CPU back to XTAL source, no PLL, same as hard reset
#if !CONFIG_IDF_ENV_FPGA #if !CONFIG_IDF_ENV_FPGA
rtc_clk_cpu_freq_set_xtal(); rtc_clk_cpu_freq_set_xtal();