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Merge branch 'feature/support_esp32c5_mp_target' into 'master'

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feat(esp32c5mp): add soc files (stage 2/8, part 1/2)

See merge request espressif/esp-idf!29369
This commit is contained in:
Kevin (Lao Kaiyao)
2024-03-06 14:19:40 +08:00
parent efc3f9fa88 a56b575535
commit 413c53d39a
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components/soc/esp32c5/mp/ld/.gitkeep → components/soc/esp32c5/mp/gpio_periph.c
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components/soc/esp32c5/mp/include/soc/aes_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* AES key data register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* AES key data register 0
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_2_REG register
* AES key data register 0
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_3_REG register
* AES key data register 0
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_4_REG register
* AES key data register 0
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_5_REG register
* AES key data register 0
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_6_REG register
* AES key data register 0
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_7_REG register
* AES key data register 0
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_TEXT_IN_0_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_2_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_3_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_OUT_0_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_2_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_3_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_MODE_REG register
* Defines key length and encryption / decryption
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.\\
* 0: AES-128 encryption\\
* 1: AES-192 encryption\\
* 2: AES-256 encryption\\
* 3: Reserved\\
* 4: AES-128 decryption\\
* 5: AES-192 decryption\\
* 6: AES-256 decryption\\
* 7: Reserved\\
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_ENDIAN_REG register
* AES Endian configure register
*/
#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
#define AES_ENDIAN 0x0000003FU
#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
#define AES_ENDIAN_V 0x0000003FU
#define AES_ENDIAN_S 0
/** AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation. \\
* 0: No effect\\
* 1: Start\\
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator. \\
* In Typical AES working mode:\\
* 0: IDLE\\
* 1: WORK\\
* 2: No effect\\
* 3: No effect\\
* In DMA-AES working mode:\\
* 0: IDLE\\
* 1: WORK\\
* 2: DONE\\
* 3: No effect\\
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* Selects the working mode of the AES accelerator
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator. \\
* 0: Typical AES\\
* 1: DMA-AES\\
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* Defines the block cipher mode
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode. \\
* 0: ECB (Electronic Code Block)\\
* 1: CBC (Cipher Block Chaining)\\
* 2: OFB (Output FeedBack)\\
* 3: CTR (Counter)\\
* 4: CFB8 (8-bit Cipher FeedBack)\\
* 5: CFB128 (128-bit Cipher FeedBack)\\
* 6: GCM\\
* 7: Reserved\\
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section <a
* href=sec:aes-block-number">link</a>. "
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation. \\
* 0: INC<SUB>32</SUB>\\
* 1: INC<SUB>128</SUB>\\
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_AAD_BLOCK_NUM_REG register
* Additional Authential Data block number register
*/
#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_S 0
/** AES_REMAINDER_BIT_NUM_REG register
* AES remainder bit number register
*/
#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
#define AES_REMAINDER_BIT_NUM 0x0000007FU
#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
#define AES_REMAINDER_BIT_NUM_V 0x0000007FU
#define AES_REMAINDER_BIT_NUM_S 0
/** AES_CONTINUE_REG register
* AES continue register
*/
#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
#define AES_CONTINUE (BIT(0))
#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
#define AES_CONTINUE_V 0x00000001U
#define AES_CONTINUE_S 0
/** AES_INT_CLEAR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt. \\
* 0: No effect \\
* 1: Clear \\
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.\\
* 0: Disable\\
* 1: Enable \\
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x0FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x0FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation. \\
* 0: No effect\\
* 1: Exit\\
* Only valid for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
/** AES_RX_RESET_REG register
* AES-DMA reset rx-fifo register
*/
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
#define AES_RX_RESET (BIT(0))
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
#define AES_RX_RESET_V 0x00000001U
#define AES_RX_RESET_S 0
/** AES_TX_RESET_REG register
* AES-DMA reset tx-fifo register
*/
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
#define AES_TX_RESET (BIT(0))
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
#define AES_TX_RESET_V 0x00000001U
#define AES_TX_RESET_S 0
/** AES_PSEUDO_REG register
* AES PSEUDO function configure register
*/
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
#define AES_PSEUDO_EN (BIT(0))
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
#define AES_PSEUDO_EN_V 0x00000001U
#define AES_PSEUDO_EN_S 0
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
#define AES_PSEUDO_BASE 0x0000000FU
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
#define AES_PSEUDO_BASE_V 0x0000000FU
#define AES_PSEUDO_BASE_S 1
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
#define AES_PSEUDO_INC 0x00000003U
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
#define AES_PSEUDO_INC_V 0x00000003U
#define AES_PSEUDO_INC_S 5
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
#define AES_PSEUDO_RNG_CNT 0x00000007U
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
#define AES_PSEUDO_RNG_CNT_S 7
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
* AES key data register 0
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Registers */
/** Type of text_in_n register
* Source text data register 0
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_n_reg_t;
/** Group: TEXT_OUT Registers */
/** Type of text_out_n register
* Result text data register 0
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_n_reg_t;
/** Group: Control / Configuration Registers */
/** Type of mode register
* Defines key length and encryption / decryption
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.\\
* 0: AES-128 encryption\\
* 1: AES-192 encryption\\
* 2: AES-256 encryption\\
* 3: Reserved\\
* 4: AES-128 decryption\\
* 5: AES-192 decryption\\
* 6: AES-256 decryption\\
* 7: Reserved\\
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of trigger register
* Operation start controlling register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation. \\
* 0: No effect\\
* 1: Start\\
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of dma_enable register
* Selects the working mode of the AES accelerator
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator. \\
* 0: Typical AES\\
* 1: DMA-AES\\
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of block_mode register
* Defines the block cipher mode
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode. \\
* 0: ECB (Electronic Code Block)\\
* 1: CBC (Cipher Block Chaining)\\
* 2: OFB (Output FeedBack)\\
* 3: CTR (Counter)\\
* 4: CFB8 (8-bit Cipher FeedBack)\\
* 5: CFB128 (128-bit Cipher FeedBack)\\
* 6: GCM\\
* 7: Reserved\\
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* Block number configuration register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section <a
* href=sec:aes-block-number">link</a>. "
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation. \\
* 0: INC<SUB>32</SUB>\\
* 1: INC<SUB>128</SUB>\\
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of dma_exit register
* Operation exit controlling register
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation. \\
* 0: No effect\\
* 1: Exit\\
* Only valid for DMA-AES operation.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Type of rx_reset register
* AES-DMA reset rx-fifo register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
uint32_t rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_rx_reset_reg_t;
/** Type of tx_reset register
* AES-DMA reset tx-fifo register
*/
typedef union {
struct {
/** tx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
uint32_t tx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_tx_reset_reg_t;
/** Group: Configuration register */
/** Type of endian register
* AES Endian configure register
*/
typedef union {
struct {
/** endian : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
uint32_t endian:6;
uint32_t reserved_6:26;
};
uint32_t val;
} aes_endian_reg_t;
/** Type of aad_block_num register
* Additional Authential Data block number register
*/
typedef union {
struct {
/** aad_block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
uint32_t aad_block_num:32;
};
uint32_t val;
} aes_aad_block_num_reg_t;
/** Type of remainder_bit_num register
* AES remainder bit number register
*/
typedef union {
struct {
/** remainder_bit_num : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
uint32_t remainder_bit_num:7;
uint32_t reserved_7:25;
};
uint32_t val;
} aes_remainder_bit_num_reg_t;
/** Type of pseudo register
* AES PSEUDO function configure register
*/
typedef union {
struct {
/** pseudo_en : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
uint32_t pseudo_en:1;
/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
uint32_t pseudo_base:4;
/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
uint32_t pseudo_inc:2;
/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
uint32_t pseudo_rng_cnt:3;
uint32_t reserved_10:22;
};
uint32_t val;
} aes_pseudo_reg_t;
/** Group: Status Register */
/** Type of state register
* Operation status register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator. \\
* In Typical AES working mode:\\
* 0: IDLE\\
* 1: WORK\\
* 2: No effect\\
* 3: No effect\\
* In DMA-AES working mode:\\
* 0: IDLE\\
* 1: WORK\\
* 2: DONE\\
* 3: No effect\\
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Group: memory type */
/** Group: Control/Status register */
/** Type of continue register
* AES continue register
*/
typedef union {
struct {
/** continue : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
uint32_t continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_continue_reg_t;
/** Group: Interrupt Registers */
/** Type of int_clear register
* DMA-AES interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt. \\
* 0: No effect \\
* 1: Clear \\
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* DMA-AES interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.\\
* 0: Disable\\
* 1: Enable \\
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_n_reg_t key_n[8];
volatile aes_text_in_n_reg_t text_in_n[4];
volatile aes_text_out_n_reg_t text_out_n[4];
volatile aes_mode_reg_t mode;
volatile aes_endian_reg_t endian;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
volatile aes_aad_block_num_reg_t aad_block_num;
volatile aes_remainder_bit_num_reg_t remainder_bit_num;
volatile aes_continue_reg_t continue;
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
uint32_t reserved_0bc;
volatile aes_rx_reset_reg_t rx_reset;
volatile aes_tx_reset_reg_t tx_reset;
uint32_t reserved_0c8[2];
volatile aes_pseudo_reg_t pseudo;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_FSM_WAIT_REG register
* digital saradc configure register
*/
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_BASE + 0xc)
/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S)
#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_S 0
/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S)
#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_S 8
/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S)
#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_S 16
/** APB_SARADC_SAR1_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_BASE + 0x10)
/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S)
#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_S 0
/** APB_SARADC_SAR2_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_BASE + 0x14)
/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S)
#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_S 0
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c)
/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S)
#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_S 0
/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S)
#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_S 12
/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
#define APB_SARADC_TSENS_CLK_INV (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S)
#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U
#define APB_SARADC_TSENS_CLK_INV_S 14
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/apb_saradc_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_fsm_wait register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
uint32_t saradc_saradc_xpd_wait:8;
/** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
uint32_t saradc_saradc_rstb_wait:8;
/** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
uint32_t saradc_saradc_standby_wait:8;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_fsm_wait_reg_t;
/** Type of saradc_sar1_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
uint32_t saradc_saradc_sar1_status:32;
};
uint32_t val;
} apb_saradc_sar1_status_reg_t;
/** Type of saradc_sar2_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
uint32_t saradc_saradc_sar2_status:32;
};
uint32_t val;
} apb_saradc_sar2_status_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
uint32_t saradc_tsens_xpd_wait:12;
/** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
uint32_t saradc_tsens_xpd_force:2;
/** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
uint32_t saradc_tsens_clk_inv:1;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/assist_debug_reg.h Normal file
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@@ -0,0 +1,824 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether to monitor read operations in region 0 by the Data bus. \\
* 0: Not monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Configures whether to monitor write operations in region 0 by the Data bus.\\
* 0: Not monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Configures whether to monitor read operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Configures whether to monitor write operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Configures whether to monitor SP exceeding the lower bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Configures whether to monitor SP exceeding the upper bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enbale
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* The raw interrupt status of read operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* The raw interrupt status of write operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* The raw interrupt status of read operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* The raw interrupt status of write operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* The raw interrupt status of read operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* The raw interrupt status of write operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* The raw interrupt status of read operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* The raw interrupt status of write operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* The raw interrupt status of SP exceeding the lower bound address of SP monitored
* region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* The raw interrupt status of SP exceeding the upper bound address of SP monitored
* region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enbale
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clear register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Data bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
* monitored region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
* monitored region.
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Data bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* Configures lower boundary address of region 0 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* Configures upper boundary address of region 0 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 0.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* Configures lower boundary address of region 1 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* Configures upper boundary address of region 1 monitored on Peripheral bus
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 1.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* Region monitoring HP CPU PC status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value when an interrupt is triggered during region monitoring.
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* Region monitoring HP CPU SP status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* Represents the SP value when an interrupt is triggered during region monitoring.
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* Configures stack monitoring lower boundary address
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of SP.
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* Configures stack monitoring upper boundary address
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the upper bound address of SP.
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* Stack monitoring HP CPU PC status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value during stack monitoring.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* HP CPU PC logging enable register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable PC logging.\\
* 0: Disable\\
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Configures whether to enable HP CPU debugging.\\
* 0: Disable\\
* 1: HP CPU outputs PC\\
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* PC logging register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* Represents the PC value at HP CPU reset.
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* PC logging register
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* Represents SP.
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register2
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register3
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* exception monitor status register4
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* exception monitor status register5
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
* exception monitor status register6
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
* exception monitor status register7
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* Represents the PC of the last command before the HP CPU enters exception.
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
* 1: In debugging mode\\
* 0: Not in debugging mode\\
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* Represents the status of the RISC-V CPU (HP CPU) debug module.\\
* 1: Active status\\
* Other: Inactive status\\
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register8
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register9
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* Register clock control
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to enable the register clock gating. \\
* 0: Disable\\
* 1: Enable\\
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* Version control register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: monitor configuration registers */
/** Type of core_0_montr_ena register
* core0 monitor enable configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
* Configures whether to monitor read operations in region 0 by the Data bus. \\
* 0: Not monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_dram0_0_rd_ena:1;
/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
* Configures whether to monitor write operations in region 0 by the Data bus.\\
* 0: Not monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_dram0_0_wr_ena:1;
/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
* Configures whether to monitor read operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_dram0_1_rd_ena:1;
/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
* Configures whether to monitor write operations in region 1 by the Data bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_dram0_1_wr_ena:1;
/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
* Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_pif_0_rd_ena:1;
/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
* Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_pif_0_wr_ena:1;
/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
* Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_pif_1_rd_ena:1;
/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
* Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_area_pif_1_wr_ena:1;
/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
* Configures whether to monitor SP exceeding the lower bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_sp_spill_min_ena:1;
/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
* Configures whether to monitor SP exceeding the upper bound address of SP monitored
* region.\\
* 0: Not Monitor\\
* 1: Monitor\\
*/
uint32_t core_0_sp_spill_max_ena:1;
/** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
uint32_t core_0_iram0_exception_monitor_ena:1;
/** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enbale
*/
uint32_t core_0_dram0_exception_monitor_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_montr_ena_reg_t;
/** Type of core_0_area_dram0_0_min register
* Configures lower boundary address of region 0 monitored on Data bus
*/
typedef union {
struct {
/** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 0.
*/
uint32_t core_0_area_dram0_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_min_reg_t;
/** Type of core_0_area_dram0_0_max register
* Configures upper boundary address of region 0 monitored on Data bus
*/
typedef union {
struct {
/** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 0.
*/
uint32_t core_0_area_dram0_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_max_reg_t;
/** Type of core_0_area_dram0_1_min register
* Configures lower boundary address of region 1 monitored on Data bus
*/
typedef union {
struct {
/** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Data bus region 1.
*/
uint32_t core_0_area_dram0_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_min_reg_t;
/** Type of core_0_area_dram0_1_max register
* Configures upper boundary address of region 1 monitored on Data bus
*/
typedef union {
struct {
/** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Data bus region 1.
*/
uint32_t core_0_area_dram0_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_max_reg_t;
/** Type of core_0_area_pif_0_min register
* Configures lower boundary address of region 0 monitored on Peripheral bus
*/
typedef union {
struct {
/** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 0.
*/
uint32_t core_0_area_pif_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_min_reg_t;
/** Type of core_0_area_pif_0_max register
* Configures upper boundary address of region 0 monitored on Peripheral bus
*/
typedef union {
struct {
/** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 0.
*/
uint32_t core_0_area_pif_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_max_reg_t;
/** Type of core_0_area_pif_1_min register
* Configures lower boundary address of region 1 monitored on Peripheral bus
*/
typedef union {
struct {
/** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the lower bound address of Peripheral bus region 1.
*/
uint32_t core_0_area_pif_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_min_reg_t;
/** Type of core_0_area_pif_1_max register
* Configures upper boundary address of region 1 monitored on Peripheral bus
*/
typedef union {
struct {
/** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of Peripheral bus region 1.
*/
uint32_t core_0_area_pif_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_max_reg_t;
/** Type of core_0_area_pc register
* Region monitoring HP CPU PC status register
*/
typedef union {
struct {
/** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
* Represents the PC value when an interrupt is triggered during region monitoring.
*/
uint32_t core_0_area_pc:32;
};
uint32_t val;
} assist_debug_core_0_area_pc_reg_t;
/** Type of core_0_area_sp register
* Region monitoring HP CPU SP status register
*/
typedef union {
struct {
/** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
* Represents the SP value when an interrupt is triggered during region monitoring.
*/
uint32_t core_0_area_sp:32;
};
uint32_t val;
} assist_debug_core_0_area_sp_reg_t;
/** Type of core_0_sp_min register
* Configures stack monitoring lower boundary address
*/
typedef union {
struct {
/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of SP.
*/
uint32_t core_0_sp_min:32;
};
uint32_t val;
} assist_debug_core_0_sp_min_reg_t;
/** Type of core_0_sp_max register
* Configures stack monitoring upper boundary address
*/
typedef union {
struct {
/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the upper bound address of SP.
*/
uint32_t core_0_sp_max:32;
};
uint32_t val;
} assist_debug_core_0_sp_max_reg_t;
/** Type of core_0_sp_pc register
* Stack monitoring HP CPU PC status register
*/
typedef union {
struct {
/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
* Represents the PC value during stack monitoring.
*/
uint32_t core_0_sp_pc:32;
};
uint32_t val;
} assist_debug_core_0_sp_pc_reg_t;
/** Group: interrupt configuration register */
/** Type of core_0_intr_raw register
* core0 monitor interrupt status register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
* The raw interrupt status of read operations in region 0 by Data bus.
*/
uint32_t core_0_area_dram0_0_rd_raw:1;
/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
* The raw interrupt status of write operations in region 0 by Data bus.
*/
uint32_t core_0_area_dram0_0_wr_raw:1;
/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
* The raw interrupt status of read operations in region 1 by Data bus.
*/
uint32_t core_0_area_dram0_1_rd_raw:1;
/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
* The raw interrupt status of write operations in region 1 by Data bus.
*/
uint32_t core_0_area_dram0_1_wr_raw:1;
/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
* The raw interrupt status of read operations in region 0 by Peripheral bus.
*/
uint32_t core_0_area_pif_0_rd_raw:1;
/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
* The raw interrupt status of write operations in region 0 by Peripheral bus.
*/
uint32_t core_0_area_pif_0_wr_raw:1;
/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
* The raw interrupt status of read operations in region 1 by Peripheral bus.
*/
uint32_t core_0_area_pif_1_rd_raw:1;
/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
* The raw interrupt status of write operations in region 1 by Peripheral bus.
*/
uint32_t core_0_area_pif_1_wr_raw:1;
/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
* The raw interrupt status of SP exceeding the lower bound address of SP monitored
* region.
*/
uint32_t core_0_sp_spill_min_raw:1;
/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
* The raw interrupt status of SP exceeding the upper bound address of SP monitored
* region.
*/
uint32_t core_0_sp_spill_max_raw:1;
/** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
uint32_t core_0_iram0_exception_monitor_raw:1;
/** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
uint32_t core_0_dram0_exception_monitor_raw:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_raw_reg_t;
/** Type of core_0_intr_ena register
* core0 monitor interrupt enable register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_rd_intr_ena:1;
/** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_wr_intr_ena:1;
/** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_rd_intr_ena:1;
/** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_wr_intr_ena:1;
/** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
uint32_t core_0_area_pif_0_rd_intr_ena:1;
/** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
uint32_t core_0_area_pif_0_wr_intr_ena:1;
/** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
uint32_t core_0_area_pif_1_rd_intr_ena:1;
/** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
uint32_t core_0_area_pif_1_wr_intr_ena:1;
/** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_min_intr_ena:1;
/** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_max_intr_ena:1;
/** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
uint32_t core_0_iram0_exception_monitor_intr_ena:1;
/** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enbale
*/
uint32_t core_0_dram0_exception_monitor_intr_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_ena_reg_t;
/** Type of core_0_intr_clr register
* core0 monitor interrupt clear register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
*/
uint32_t core_0_area_dram0_0_rd_clr:1;
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Data bus.
*/
uint32_t core_0_area_dram0_0_wr_clr:1;
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Data bus.
*/
uint32_t core_0_area_dram0_1_rd_clr:1;
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Data bus.
*/
uint32_t core_0_area_dram0_1_wr_clr:1;
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
* Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
*/
uint32_t core_0_area_pif_0_rd_clr:1;
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
* Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
*/
uint32_t core_0_area_pif_0_wr_clr:1;
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
* Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
*/
uint32_t core_0_area_pif_1_rd_clr:1;
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
* Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
*/
uint32_t core_0_area_pif_1_wr_clr:1;
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
* monitored region.
*/
uint32_t core_0_sp_spill_min_clr:1;
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
* Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
* monitored region.
*/
uint32_t core_0_sp_spill_max_clr:1;
/** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
uint32_t core_0_iram0_exception_monitor_clr:1;
/** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
uint32_t core_0_dram0_exception_monitor_clr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_clr_reg_t;
/** Group: pc reording configuration register */
/** Type of core_0_rcd_en register
* HP CPU PC logging enable register
*/
typedef union {
struct {
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
* Configures whether to enable PC logging.\\
* 0: Disable\\
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
*/
uint32_t core_0_rcd_recorden:1;
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
* Configures whether to enable HP CPU debugging.\\
* 0: Disable\\
* 1: HP CPU outputs PC\\
*/
uint32_t core_0_rcd_pdebugen:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_rcd_en_reg_t;
/** Group: pc reording status register */
/** Type of core_0_rcd_pdebugpc register
* PC logging register
*/
typedef union {
struct {
/** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
* Represents the PC value at HP CPU reset.
*/
uint32_t core_0_rcd_pdebugpc:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugpc_reg_t;
/** Type of core_0_rcd_pdebugsp register
* PC logging register
*/
typedef union {
struct {
/** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
* Represents SP.
*/
uint32_t core_0_rcd_pdebugsp:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugsp_reg_t;
/** Group: exception monitor regsiter */
/** Type of core_0_iram0_exception_monitor_0 register
* exception monitor status register0
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
uint32_t core_0_iram0_recording_addr_0:30;
/** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
uint32_t core_0_iram0_recording_wr_0:1;
/** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
uint32_t core_0_iram0_recording_loadstore_0:1;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
/** Type of core_0_iram0_exception_monitor_1 register
* exception monitor status register1
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
uint32_t core_0_iram0_recording_addr_1:30;
/** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
uint32_t core_0_iram0_recording_wr_1:1;
/** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
uint32_t core_0_iram0_recording_loadstore_1:1;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_0 register
* exception monitor status register2
*/
typedef union {
struct {
/** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
uint32_t core_0_dram0_recording_wr_0:1;
/** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
uint32_t core_0_dram0_recording_byteen_0:4;
uint32_t reserved_5:27;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
/** Type of core_0_dram0_exception_monitor_1 register
* exception monitor status register3
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
uint32_t core_0_dram0_recording_addr_0:30;
uint32_t reserved_30:2;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_2 register
* exception monitor status register4
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
uint32_t core_0_dram0_recording_pc_0:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
/** Type of core_0_dram0_exception_monitor_3 register
* exception monitor status register5
*/
typedef union {
struct {
/** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
uint32_t core_0_dram0_recording_wr_1:1;
/** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
uint32_t core_0_dram0_recording_byteen_1:4;
uint32_t reserved_5:27;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
/** Type of core_0_dram0_exception_monitor_4 register
* exception monitor status register6
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
uint32_t core_0_dram0_recording_addr_1:30;
uint32_t reserved_30:2;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
/** Type of core_0_dram0_exception_monitor_5 register
* exception monitor status register7
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
uint32_t core_0_dram0_recording_pc_1:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_0 register
* exception monitor status register8
*/
typedef union {
struct {
/** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
uint32_t core_x_iram0_dram0_limit_cycle_0:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_1 register
* exception monitor status register9
*/
typedef union {
struct {
/** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
uint32_t core_x_iram0_dram0_limit_cycle_1:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
/** Group: cpu status registers */
/** Type of core_0_lastpc_before_exception register
* cpu status register
*/
typedef union {
struct {
/** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
* Represents the PC of the last command before the HP CPU enters exception.
*/
uint32_t core_0_lastpc_before_exc:32;
};
uint32_t val;
} assist_debug_core_0_lastpc_before_exception_reg_t;
/** Type of core_0_debug_mode register
* cpu status register
*/
typedef union {
struct {
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
* 1: In debugging mode\\
* 0: Not in debugging mode\\
*/
uint32_t core_0_debug_mode:1;
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
* Represents the status of the RISC-V CPU (HP CPU) debug module.\\
* 1: Active status\\
* Other: Inactive status\\
*/
uint32_t core_0_debug_module_active:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_debug_mode_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* Register clock control
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to enable the register clock gating. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_clock_gate_reg_t;
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} assist_debug_date_reg_t;
typedef struct {
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
uint32_t reserved_078[34];
volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
volatile assist_debug_clock_gate_reg_t clock_gate;
uint32_t reserved_10c[188];
volatile assist_debug_date_reg_t date;
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/bitscrambler_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BITSCRAMBLER_TX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_S 0
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_S 3
/** BITSCRAMBLER_TX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_S 0
/** BITSCRAMBLER_RX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_S 0
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_S 3
/** BITSCRAMBLER_RX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_S 0
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_S 0
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_S 11
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_S 0
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_S 0
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_S 11
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_S 0
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
/** BITSCRAMBLER_TX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
#define BITSCRAMBLER_TX_ENA (BIT(0))
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
#define BITSCRAMBLER_TX_ENA_S 0
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_PAUSE_S 1
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_HALT (BIT(2))
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_S 2
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_MODE_S 3
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_COND_MODE_S 4
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_MODE_S 6
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_RST_S 8
/** BITSCRAMBLER_RX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
#define BITSCRAMBLER_RX_ENA (BIT(0))
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
#define BITSCRAMBLER_RX_ENA_S 0
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_PAUSE_S 1
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_HALT (BIT(2))
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_S 2
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_MODE_S 3
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_COND_MODE_S 4
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_MODE_S 6
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_RST_S 8
/** BITSCRAMBLER_TX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_IDLE_S 0
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_TX_IN_RUN_S 1
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_TX_IN_WAIT_S 2
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 1;
* represents the bitscrambler tx fifo in empty state
*/
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_RX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_IDLE_S 0
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_RX_IN_RUN_S 1
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_RX_IN_WAIT_S 2
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_SYS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
#define BITSCRAMBLER_LOOP_MODE_S 0
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define BITSCRAMBLER_CLK_EN (BIT(31))
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
#define BITSCRAMBLER_CLK_EN_S 31
/** BITSCRAMBLER_VERSION_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36766257;
* Reserved
*/
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 1;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
uint32_t reserved_5:11;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
uint32_t reserved_5:11;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36766257;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
typedef struct {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
volatile bitscrambler_tx_state_reg_t tx_state;
volatile bitscrambler_rx_state_reg_t rx_state;
uint32_t reserved_038[48];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* Activates the DS module
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.\\
* 0: Invalid\\
* 1: Activate the DS peripheral\\
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* Ends DS operation
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation. \\
* 0: Invalid\\
* 1: End DS operation\\
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* Status of the DS module
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.\\
* 0: The DS module is idle\\
* 1: The DS module is busy\\
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.\\
* 0: HMAC is not called\\
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)\\
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* Queries DS check result
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.\\
* 0: The MD check passes\\
* 1: The MD check fails\\
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.\\
* 0: The padding check passes\\
* 1: The padding check fails\\
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_KEY_SOURCE_REG register
* DS configure key source register
*/
#define DS_KEY_SOURCE_REG (DR_REG_DS_BASE + 0xe18)
/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
* digital signature key source bit. \\
* 1'b0: key is from hmac.\\
* 1'b1: key is from key manager. \\
*/
#define DS_KEY_SOURCE (BIT(0))
#define DS_KEY_SOURCE_M (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
#define DS_KEY_SOURCE_V 0x00000001U
#define DS_KEY_SOURCE_S 0
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 539166977;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* Activates the DS module
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.\\
* 0: Invalid\\
* 1: Activate the DS peripheral\\
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* Ends DS operation
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation. \\
* 0: Invalid\\
* 1: End DS operation\\
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* Status of the DS module
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.\\
* 0: The DS module is idle\\
* 1: The DS module is busy\\
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.\\
* 0: HMAC is not called\\
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)\\
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* Queries DS check result
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.\\
* 0: The MD check passes\\
* 1: The MD check fails\\
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.\\
* 0: The padding check passes\\
* 1: The padding check fails\\
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: Configuration registers */
/** Type of key_source register
* DS configure key source register
*/
typedef union {
struct {
/** key_source : R/W; bitpos: [0]; default: 0;
* digital signature key source bit. \\
* 1'b0: key is from hmac.\\
* 1'b1: key is from key manager. \\
*/
uint32_t key_source:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_key_source_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539166977;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
volatile ds_key_source_reg_t key_source;
uint32_t reserved_e1c;
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC raw interrupt status register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC masked interrupt status register
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configuration register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done. \\
* 0: No effect\\
* 1: Start calculation of ECC Accelerator\\
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator. \\
* 0: No effect\\
* 1: Reset\\
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator. \\
* 0: P-192\\
* 1: P-256\\
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11. \\
* 0: n(order of curve)\\
* 1: p(mod base of curve)\\
*/
#define ECC_MULT_MOD_BASE (BIT(3))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 3
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.\\
* 0: Point Multi mode\\
* 1: Reserved\\
* 2: Point Verif mode\\
* 3: Point Verif + Multi mode\\
* 4: Jacobian Point Multi mode\\
* 5: Reserved\\
* 6: Jacobian Point Verif mode\\
* 7: Point Verif + Jacobian Point Multi mode\\
* 8: Mod Add mode\\
* 9. Mod Sub mode\\
* 10: Mod Multi mode\\
* 11: Mod Div mode\\
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 4
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.\\
* 0: no secure function enabled.\\
* 1: enable constant-time calculation in all point multiplication modes.\\
*/
#define ECC_MULT_SECURITY_MODE (BIT(8))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 8
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate. \\
* 0: No effect\\
* 1: Force on\\
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate. \\
* 0: No effect\\
* 1: Force on\\
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37752928;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_QX_MEM_SIZE_BYTES 32
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
#define ECC_MULT_QY_MEM_SIZE_BYTES 32
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1a0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC raw interrupt status register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC masked interrupt status register
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configuration register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done. \\
* 0: No effect\\
* 1: Start calculation of ECC Accelerator\\
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* Configures the key length mode bit of ECC Accelerator. \\
* 0: P-192\\
* 1: P-256\\
*/
uint32_t key_length:1;
/** mod_base : R/W; bitpos: [3]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11. \\
* 0: n(order of curve)\\
* 1: p(mod base of curve)\\
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [7:4]; default: 0;
* Configures the work mode of ECC Accelerator.\\
* 0: Point Multi mode\\
* 1: Reserved\\
* 2: Point Verif mode\\
* 3: Point Verif + Multi mode\\
* 4: Jacobian Point Multi mode\\
* 5: Reserved\\
* 6: Jacobian Point Verif mode\\
* 7: Point Verif + Jacobian Point Multi mode\\
* 8: Mod Add mode\\
* 9. Mod Sub mode\\
* 10: Mod Multi mode\\
* 11: Mod Div mode\\
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [8]; default: 0;
* Configures the security mode of ECC Accelerator.\\
* 0: no secure function enabled.\\
* 1: enable constant-time calculation in all point multiplication modes.\\
*/
uint32_t security_mode:1;
uint32_t reserved_9:20;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate. \\
* 0: No effect\\
* 1: Force on\\
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate. \\
* 0: No effect\\
* 1: Force on\\
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37752928;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[8];
volatile uint32_t px[8];
volatile uint32_t py[8];
volatile uint32_t qx[8];
volatile uint32_t qy[8];
volatile uint32_t qz[8];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x1c0, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
#define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
#define ECDSA_K_VALUE_WARNING (BIT(1))
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
#define ECDSA_K_VALUE_WARNING_S 1
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340)
#define ECDSA_R_MEM_SIZE_BYTES 32
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360)
#define ECDSA_S_MEM_SIZE_BYTES 32
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380)
#define ECDSA_Z_MEM_SIZE_BYTES 32
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0)
#define ECDSA_QAX_MEM_SIZE_BYTES 32
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0)
#define ECDSA_QAY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
uint32_t ecc_curve:1;
/** software_set_k : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
/** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
uint32_t deterministic_loop:16;
uint32_t reserved_22:10;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
/** k_value_warning : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
uint32_t k_value_warning:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
uint32_t sha_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36725040;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[8];
uint32_t reserved_2a0[40];
volatile uint32_t r[8];
volatile uint32_t s[8];
volatile uint32_t z[8];
volatile uint32_t qax[8];
volatile uint32_t qay[8];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX 4
#define LEDC_LS_SIG_OUT5_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define CPU_TESTBUS0_IDX 19
#define CPU_TESTBUS1_IDX 20
#define CPU_TESTBUS2_IDX 21
#define CPU_TESTBUS3_IDX 22
#define CPU_TESTBUS4_IDX 23
#define CPU_TESTBUS5_IDX 24
#define CPU_TESTBUS6_IDX 25
#define CPU_TESTBUS7_IDX 26
#define CPU_GPIO_IN0_IDX 27
#define CPU_GPIO_OUT0_IDX 27
#define CPU_GPIO_IN1_IDX 28
#define CPU_GPIO_OUT1_IDX 28
#define CPU_GPIO_IN2_IDX 29
#define CPU_GPIO_OUT2_IDX 29
#define CPU_GPIO_IN3_IDX 30
#define CPU_GPIO_OUT3_IDX 30
#define CPU_GPIO_IN4_IDX 31
#define CPU_GPIO_OUT4_IDX 31
#define CPU_GPIO_IN5_IDX 32
#define CPU_GPIO_OUT5_IDX 32
#define CPU_GPIO_IN6_IDX 33
#define CPU_GPIO_OUT6_IDX 33
#define CPU_GPIO_IN7_IDX 34
#define CPU_GPIO_OUT7_IDX 34
#define USB_JTAG_TDO_IDX 35
#define USB_JTAG_TRST_IDX 35
#define USB_JTAG_SRST_IDX 36
#define USB_JTAG_TCK_IDX 37
#define USB_JTAG_TMS_IDX 38
#define USB_JTAG_TDI_IDX 39
#define CPU_USB_JTAG_TDO_IDX 40
#define USB_EXTPHY_VP_IDX 41
#define USB_EXTPHY_OEN_IDX 41
#define USB_EXTPHY_VM_IDX 42
#define USB_EXTPHY_SPEED_IDX 42
#define USB_EXTPHY_RCV_IDX 43
#define USB_EXTPHY_VPO_IDX 43
#define USB_EXTPHY_VMO_IDX 44
#define USB_EXTPHY_SUSPND_IDX 45
#define I2CEXT0_SCL_IN_IDX 46
#define I2CEXT0_SCL_OUT_IDX 46
#define I2CEXT0_SDA_IN_IDX 47
#define I2CEXT0_SDA_OUT_IDX 47
#define PARL_RX_DATA0_IDX 48
#define PARL_TX_DATA0_IDX 48
#define PARL_RX_DATA1_IDX 49
#define PARL_TX_DATA1_IDX 49
#define PARL_RX_DATA2_IDX 50
#define PARL_TX_DATA2_IDX 50
#define PARL_RX_DATA3_IDX 51
#define PARL_TX_DATA3_IDX 51
#define PARL_RX_DATA4_IDX 52
#define PARL_TX_DATA4_IDX 52
#define PARL_RX_DATA5_IDX 53
#define PARL_TX_DATA5_IDX 53
#define PARL_RX_DATA6_IDX 54
#define PARL_TX_DATA6_IDX 54
#define PARL_RX_DATA7_IDX 55
#define PARL_TX_DATA7_IDX 55
#define FSPICLK_IN_IDX 56
#define FSPICLK_OUT_IDX 56
#define FSPIQ_IN_IDX 57
#define FSPIQ_OUT_IDX 57
#define FSPID_IN_IDX 58
#define FSPID_OUT_IDX 58
#define FSPIHD_IN_IDX 59
#define FSPIHD_OUT_IDX 59
#define FSPIWP_IN_IDX 60
#define FSPIWP_OUT_IDX 60
#define FSPICS0_IN_IDX 61
#define FSPICS0_OUT_IDX 61
#define PARL_RX_CLK_IN_IDX 62
#define PARL_RX_CLK_OUT_IDX 62
#define PARL_TX_CLK_IN_IDX 63
#define PARL_TX_CLK_OUT_IDX 63
#define RMT_SIG_IN0_IDX 64
#define RMT_SIG_OUT0_IDX 64
#define RMT_SIG_IN1_IDX 65
#define RMT_SIG_OUT1_IDX 65
#define TWAI0_RX_IDX 66
#define TWAI0_TX_IDX 66
#define TWAI0_BUS_OFF_ON_IDX 67
#define TWAI0_CLKOUT_IDX 68
#define TWAI0_STANDBY_IDX 69
#define TWAI1_RX_IDX 70
#define TWAI1_TX_IDX 70
#define TWAI1_BUS_OFF_ON_IDX 71
#define TWAI1_CLKOUT_IDX 72
#define TWAI1_STANDBY_IDX 73
#define EXTERN_PRIORITY_I_IDX 74
#define EXTERN_PRIORITY_O_IDX 74
#define EXTERN_ACTIVE_I_IDX 75
#define EXTERN_ACTIVE_O_IDX 75
#define PCNT_RST_IN0_IDX 76
#define GPIO_SD0_OUT_IDX 76
#define PCNT_RST_IN1_IDX 77
#define GPIO_SD1_OUT_IDX 77
#define PCNT_RST_IN2_IDX 78
#define GPIO_SD2_OUT_IDX 78
#define PCNT_RST_IN3_IDX 79
#define GPIO_SD3_OUT_IDX 79
#define PWM0_SYNC0_IN_IDX 80
#define PWM0_OUT0A_IDX 80
#define PWM0_SYNC1_IN_IDX 81
#define PWM0_OUT0B_IDX 81
#define PWM0_SYNC2_IN_IDX 82
#define PWM0_OUT1A_IDX 82
#define PWM0_F0_IN_IDX 83
#define PWM0_OUT1B_IDX 83
#define PWM0_F1_IN_IDX 84
#define PWM0_OUT2A_IDX 84
#define PWM0_F2_IN_IDX 85
#define PWM0_OUT2B_IDX 85
#define PWM0_CAP0_IN_IDX 86
#define PWM0_CAP1_IN_IDX 87
#define PWM0_CAP2_IN_IDX 88
#define GPIO_EVENT_MATRIX_IN0_IDX 89
#define GPIO_TASK_MATRIX_OUT0_IDX 89
#define GPIO_EVENT_MATRIX_IN1_IDX 90
#define GPIO_TASK_MATRIX_OUT1_IDX 90
#define GPIO_EVENT_MATRIX_IN2_IDX 91
#define GPIO_TASK_MATRIX_OUT2_IDX 91
#define GPIO_EVENT_MATRIX_IN3_IDX 92
#define GPIO_TASK_MATRIX_OUT3_IDX 92
#define CLK_OUT_OUT1_IDX 93
#define CLK_OUT_OUT2_IDX 94
#define CLK_OUT_OUT3_IDX 95
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define PCNT_SIG_CH0_IN0_IDX 101
#define FSPICS1_OUT_IDX 101
#define PCNT_SIG_CH1_IN0_IDX 102
#define FSPICS2_OUT_IDX 102
#define PCNT_CTRL_CH0_IN0_IDX 103
#define FSPICS3_OUT_IDX 103
#define PCNT_CTRL_CH1_IN0_IDX 104
#define FSPICS4_OUT_IDX 104
#define PCNT_SIG_CH0_IN1_IDX 105
#define FSPICS5_OUT_IDX 105
#define PCNT_SIG_CH1_IN1_IDX 106
#define MODEM_DIAG0_IDX 106
#define PCNT_CTRL_CH0_IN1_IDX 107
#define MODEM_DIAG1_IDX 107
#define PCNT_CTRL_CH1_IN1_IDX 108
#define MODEM_DIAG2_IDX 108
#define PCNT_SIG_CH0_IN2_IDX 109
#define MODEM_DIAG3_IDX 109
#define PCNT_SIG_CH1_IN2_IDX 110
#define MODEM_DIAG4_IDX 110
#define PCNT_CTRL_CH0_IN2_IDX 111
#define MODEM_DIAG5_IDX 111
#define PCNT_CTRL_CH1_IN2_IDX 112
#define MODEM_DIAG6_IDX 112
#define PCNT_SIG_CH0_IN3_IDX 113
#define MODEM_DIAG7_IDX 113
#define PCNT_SIG_CH1_IN3_IDX 114
#define MODEM_DIAG8_IDX 114
#define PCNT_CTRL_CH0_IN3_IDX 115
#define MODEM_DIAG9_IDX 115
#define PCNT_CTRL_CH1_IN3_IDX 116
#define MODEM_DIAG10_IDX 116
#define MODEM_DIAG11_IDX 117
#define MODEM_DIAG12_IDX 118
#define MODEM_DIAG13_IDX 119
#define MODEM_DIAG14_IDX 120
#define MODEM_DIAG15_IDX 121
#define MODEM_DIAG16_IDX 122
#define MODEM_DIAG17_IDX 123
#define MODEM_DIAG18_IDX 124
#define MODEM_DIAG19_IDX 125
#define MODEM_DIAG20_IDX 126
#define MODEM_DIAG21_IDX 127
#define MODEM_DIAG22_IDX 128
#define MODEM_DIAG23_IDX 129
#define MODEM_DIAG24_IDX 130
#define MODEM_DIAG25_IDX 131
#define MODEM_DIAG26_IDX 132
#define MODEM_DIAG27_IDX 133
#define MODEM_DIAG28_IDX 134
#define MODEM_DIAG29_IDX 135
#define MODEM_DIAG30_IDX 136
#define MODEM_DIAG31_IDX 137
#define ANT_SEL0_IDX 138
#define ANT_SEL1_IDX 139
#define ANT_SEL2_IDX 140
#define ANT_SEL3_IDX 141
#define ANT_SEL4_IDX 142
#define ANT_SEL5_IDX 143
#define ANT_SEL6_IDX 144
#define ANT_SEL7_IDX 145
#define ANT_SEL8_IDX 146
#define ANT_SEL9_IDX 147
#define ANT_SEL10_IDX 148
#define ANT_SEL11_IDX 149
#define ANT_SEL12_IDX 150
#define ANT_SEL13_IDX 151
#define ANT_SEL14_IDX 152
#define ANT_SEL15_IDX 153
#define SIG_GPIO_OUT_IDX 256
// version date 2311280

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* HMAC start control register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
* \\0: Disable HMAC
* \\1: Enable HMAC
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* HMAC parameter configuration register
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table <a
* href=tab:hmac-key-purpose">link</a>. "
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* HMAC parameters configuration register
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* HMAC configuration completion register
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
* \\0: No effect
* \\1: Finish configuration
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* HMAC message control register
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* HMAC message continue register
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
* \\0: No unprocessed message block
* \\1: There are still some message blocks to be processed.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* HMAC message end register
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
* \\0: No effect
* \\1: Start hardware padding
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* HMAC result reading finish register
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
* \\0: Not exit
* \\1: Exit upstream mode and clear calculation results.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate JTAG result register
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
* \\0: Not clear
* \\1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate digital signature result register
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
* \\0: Not clear
* \\1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Stores matching results between keys generated by users and corresponding purposes
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
* \\0: Match
* \\1: Error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy state of HMAC module
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
* \\0: Idle
* \\1: HMAC is still working on the calculation
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Software padding register
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
* \\0: Not applied by software
* \\1: Applied by software
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* One block message register
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
* \\0: Disable
* \\1: Enable
* \\
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Re-enable JTAG register 1
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Version control register
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Status Registers */
/** Type of set_start register
* HMAC start control register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
* \\0: Disable HMAC
* \\1: Enable HMAC
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_finish register
* HMAC configuration completion register
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
* \\0: No effect
* \\1: Finish configuration
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* HMAC message control register
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* HMAC message continue register
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
* \\0: No unprocessed message block
* \\1: There are still some message blocks to be processed.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* HMAC message end register
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
* \\0: No effect
* \\1: Start hardware padding
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* HMAC result reading finish register
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
* \\0: Not exit
* \\1: Exit upstream mode and clear calculation results.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate JTAG result register
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
* \\0: Not clear
* \\1: Clear calculation results
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate digital signature result register
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
* \\0: Not clear
* \\1: Clear calculation results
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of query_error register
* Stores matching results between keys generated by users and corresponding purposes
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
* \\0: Match
* \\1: Error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy state of HMAC module
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
* \\0: Idle
* \\1: HMAC is still working on the calculation
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Type of set_message_pad register
* Software padding register
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
* \\0: Not applied by software
* \\1: Applied by software
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* One block message register
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Group: Configuration Registers */
/** Type of set_para_purpose register
* HMAC parameter configuration register
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table <a
* href=tab:hmac-key-purpose">link</a>. "
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* HMAC parameters configuration register
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of wr_jtag register
* Re-enable JTAG register 1
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Memory Type */
/** Group: Configuration Register */
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
* \\0: Disable
* \\1: Enable
* \\
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [15:0]; default: 1;
* Configure bit $n (0-15) to enable region $n.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t region_filter_en:16;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:32;
};
uint32_t val;
} hp_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} hp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} hp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
/** m4_func_en : R/W; bitpos: [4]; default: 1;
* PMS M4 function enable
*/
uint32_t m4_func_en:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} hp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} hp_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:16;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} hp_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:16;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} hp_apm_m3_exception_info1_reg_t;
/** Group: M4 status register */
/** Type of m4_status register
* M4 status register
*/
typedef union {
struct {
/** m4_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m4_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_apm_m4_status_reg_t;
/** Group: M4 status clear register */
/** Type of m4_status_clr register
* M4 status clear register
*/
typedef union {
struct {
/** m4_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m4_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_m4_status_clr_reg_t;
/** Group: M4 exception_info0 register */
/** Type of m4_exception_info0 register
* M4 exception_info0 register
*/
typedef union {
struct {
/** m4_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m4_exception_region:16;
/** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m4_exception_mode:2;
/** m4_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m4_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} hp_apm_m4_exception_info0_reg_t;
/** Group: M4 exception_info1 register */
/** Type of m4_exception_info1 register
* M4 exception_info1 register
*/
typedef union {
struct {
/** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m4_exception_addr:32;
};
uint32_t val;
} hp_apm_m4_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m3_apm_int_en:1;
/** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
* Configures to enable APM M4 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m4_apm_int_en:1;
uint32_t reserved_5:27;
};
uint32_t val;
} hp_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36773904;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_apm_date_reg_t;
typedef struct {
volatile hp_apm_region_filter_en_reg_t region_filter_en;
volatile hp_apm_regionn_addr_start_reg_t region0_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region0_addr_end;
volatile hp_apm_regionn_attr_reg_t region0_attr;
volatile hp_apm_regionn_addr_start_reg_t region1_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region1_addr_end;
volatile hp_apm_regionn_attr_reg_t region1_attr;
volatile hp_apm_regionn_addr_start_reg_t region2_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region2_addr_end;
volatile hp_apm_regionn_attr_reg_t region2_attr;
volatile hp_apm_regionn_addr_start_reg_t region3_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region3_addr_end;
volatile hp_apm_regionn_attr_reg_t region3_attr;
volatile hp_apm_regionn_addr_start_reg_t region4_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region4_addr_end;
volatile hp_apm_regionn_attr_reg_t region4_attr;
volatile hp_apm_regionn_addr_start_reg_t region5_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region5_addr_end;
volatile hp_apm_regionn_attr_reg_t region5_attr;
volatile hp_apm_regionn_addr_start_reg_t region6_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region6_addr_end;
volatile hp_apm_regionn_attr_reg_t region6_attr;
volatile hp_apm_regionn_addr_start_reg_t region7_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region7_addr_end;
volatile hp_apm_regionn_attr_reg_t region7_attr;
volatile hp_apm_regionn_addr_start_reg_t region8_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region8_addr_end;
volatile hp_apm_regionn_attr_reg_t region8_attr;
volatile hp_apm_regionn_addr_start_reg_t region9_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region9_addr_end;
volatile hp_apm_regionn_attr_reg_t region9_attr;
volatile hp_apm_regionn_addr_start_reg_t region10_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region10_addr_end;
volatile hp_apm_regionn_attr_reg_t region10_attr;
volatile hp_apm_regionn_addr_start_reg_t region11_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region11_addr_end;
volatile hp_apm_regionn_attr_reg_t region11_attr;
volatile hp_apm_regionn_addr_start_reg_t region12_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region12_addr_end;
volatile hp_apm_regionn_attr_reg_t region12_attr;
volatile hp_apm_regionn_addr_start_reg_t region13_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region13_addr_end;
volatile hp_apm_regionn_attr_reg_t region13_attr;
volatile hp_apm_regionn_addr_start_reg_t region14_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region14_addr_end;
volatile hp_apm_regionn_attr_reg_t region14_attr;
volatile hp_apm_regionn_addr_start_reg_t region15_addr_start;
volatile hp_apm_regionn_addr_end_reg_t region15_addr_end;
volatile hp_apm_regionn_attr_reg_t region15_attr;
volatile hp_apm_func_ctrl_reg_t func_ctrl;
volatile hp_apm_m0_status_reg_t m0_status;
volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile hp_apm_m1_status_reg_t m1_status;
volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile hp_apm_m2_status_reg_t m2_status;
volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile hp_apm_m3_status_reg_t m3_status;
volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
volatile hp_apm_m4_status_reg_t m4_status;
volatile hp_apm_m4_status_clr_reg_t m4_status_clr;
volatile hp_apm_m4_exception_info0_reg_t m4_exception_info0;
volatile hp_apm_m4_exception_info1_reg_t m4_exception_info1;
volatile hp_apm_int_en_reg_t int_en;
uint32_t reserved_11c[439];
volatile hp_apm_clock_gate_reg_t clock_gate;
volatile hp_apm_date_reg_t date;
} hp_apm_dev_t;
extern hp_apm_dev_t HP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

515
components/soc/esp32c5/mp/include/soc/hp_system_reg.h Normal file
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@@ -0,0 +1,515 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* External device encryption/decryption configuration register
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYSTEM_CACHE_USAGE (BIT(0))
#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U
#define HP_SYSTEM_CACHE_USAGE_S 0
/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
#define HP_SYSTEM_SRAM_USAGE 0x0000000FU
#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
#define HP_SYSTEM_SRAM_USAGE_V 0x0000000FU
#define HP_SYSTEM_SRAM_USAGE_S 8
/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
#define HP_SYSTEM_MAC_DUMP_ALLOC (BIT(16))
#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x00000001U
#define HP_SYSTEM_MAC_DUMP_ALLOC_S 16
/** HP_SYSTEM_SEC_DPA_CONF_REG register
* HP anti-DPA security configuration register
*/
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
*/
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
*/
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U
#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2
/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0))
#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYSTEM_DIS_SDIO_PROB_S 0
/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
* ROM-Table lock register
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYSTEM_ROM_TABLE_LOCK_S 0
/** HP_SYSTEM_ROM_TABLE_REG register
* ROM-Table register
*/
#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c)
/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_S 0
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
* Core Debug RunStall configurion register
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.\\
* 0: Disable\\
* 1: Enable\\
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S 0
/** HP_SYSTEM_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
#define HP_SYSTEM_CORE_RUNSTALLED (BIT(1))
#define HP_SYSTEM_CORE_RUNSTALLED_M (HP_SYSTEM_CORE_RUNSTALLED_V << HP_SYSTEM_CORE_RUNSTALLED_S)
#define HP_SYSTEM_CORE_RUNSTALLED_V 0x00000001U
#define HP_SYSTEM_CORE_RUNSTALLED_S 1
/** HP_SYSTEM_MEM_TEST_CONF_REG register
* MEM_TEST configuration register
*/
#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
#define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U
#define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
#define HP_SYSTEM_HP_MEM_WPULSE_V 0x00000007U
#define HP_SYSTEM_HP_MEM_WPULSE_S 0
/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
#define HP_SYSTEM_HP_MEM_WA 0x00000007U
#define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
#define HP_SYSTEM_HP_MEM_WA_V 0x00000007U
#define HP_SYSTEM_HP_MEM_WA_S 3
/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
#define HP_SYSTEM_HP_MEM_RA 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
#define HP_SYSTEM_HP_MEM_RA_V 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_S 6
/** HP_SYSTEM_SPROM_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x70)
/** HP_SYSTEM_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_M (HP_SYSTEM_SPROM_MEM_AUX_CTRL_V << HP_SYSTEM_SPROM_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SPRAM_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x74)
/** HP_SYSTEM_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_M (HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V << HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SPRF_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x78)
/** HP_SYSTEM_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SPRF_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_SDPRF_CTRL_REG register
* reserved
*/
#define HP_SYSTEM_SDPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x7c)
/** HP_SYSTEM_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S)
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0
/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
* reserved
*/
#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYSTEM_BASE + 0x80)
/** HP_SYSTEM_BITSCRAMBLER_RX_SEL : R/W; bitpos: [3:0]; default: 0;
* select peri that will be connected to bitscrambler,dir : receive data from bs
*/
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_M (HP_SYSTEM_BITSCRAMBLER_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_RX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_V 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_RX_SEL_S 0
/** HP_SYSTEM_BITSCRAMBLER_TX_SEL : R/W; bitpos: [7:4]; default: 0;
* select peri that will be connected to bitscrambler,dir : transfer data to peri
*/
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_M (HP_SYSTEM_BITSCRAMBLER_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_TX_SEL_S)
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_V 0x0000000FU
#define HP_SYSTEM_BITSCRAMBLER_TX_SEL_S 4
/** HP_SYSTEM_RND_ECO_REG register
* redcy eco register.
*/
#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_ENA (BIT(0))
#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
#define HP_SYSTEM_REDCY_ENA_V 0x00000001U
#define HP_SYSTEM_REDCY_ENA_S 0
/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_RESULT (BIT(1))
#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U
#define HP_SYSTEM_REDCY_RESULT_S 1
/** HP_SYSTEM_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_S 0
/** HP_SYSTEM_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_S 0
/** HP_SYSTEM_DEBUG_REG register
* HP-SYSTEM debug register
*/
#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x3f4)
/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
* Reserved
*/
#define HP_SYSTEM_FPGA_DEBUG (BIT(0))
#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S)
#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U
#define HP_SYSTEM_FPGA_DEBUG_S 0
/** HP_SYSTEM_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
*/
#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
#define HP_SYSTEM_CLK_EN (BIT(0))
#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
#define HP_SYSTEM_CLK_EN_V 0x00000001U
#define HP_SYSTEM_CLK_EN_S 0
/** HP_SYSTEM_DATE_REG register
* Date control and version control register
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36774016;
* Version control register.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU
#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
#define HP_SYSTEM_DATE_V 0x0FFFFFFFU
#define HP_SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif

559
components/soc/esp32c5/mp/include/soc/hp_system_struct.h Normal file
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@@ -0,0 +1,559 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
* External device encryption/decryption configuration register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable MSPI XTS auto decryption in download boot
* mode.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable MSPI XTS manual encryption in download boot
* mode. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_system_external_device_encrypt_decrypt_control_reg_t;
/** Type of sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
/** sram_usage : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
uint32_t sram_usage:4;
uint32_t reserved_12:4;
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
uint32_t mac_dump_alloc:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_system_sram_usage_conf_reg_t;
/** Type of sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to enable anti-DPA attack. Valid only when
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
* 0: Disable\\
* 1-3: Enable. The larger the number, the higher the security level, which represents
* the ability to resist DPA attacks, with increased computational overhead of the
* hardware crypto-accelerators at the same time. \\
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
* eFuse) to control DPA level. \\
* 0: Select EFUSE_SEC_DPA_LEVEL\\
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_sec_dpa_conf_reg_t;
/** Type of sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t dis_sdio_prob:1;
/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_sdio_ctrl_reg_t;
/** Type of rom_table_lock register
* ROM-Table lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
* 0: Unlock \\
* 1: Lock \\
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rom_table_lock_reg_t;
/** Type of rom_table register
* ROM-Table register
*/
typedef union {
struct {
/** rom_table : R/W; bitpos: [31:0]; default: 0;
* Software ROM-Table register, whose content can be modified only when
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
*/
uint32_t rom_table:32;
};
uint32_t val;
} hp_system_rom_table_reg_t;
/** Type of core_debug_runstall_conf register
* Core Debug RunStall configurion register
*/
typedef union {
struct {
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable debug RunStall functionality between HP CPU and
* LP CPU.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t core_debug_runstall_enable:1;
/** core_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
uint32_t core_runstalled:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_core_debug_runstall_conf_reg_t;
/** Type of mem_test_conf register
* MEM_TEST configuration register
*/
typedef union {
struct {
/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
uint32_t hp_mem_wpulse:3;
/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
uint32_t hp_mem_wa:3;
/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
uint32_t hp_mem_ra:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_system_mem_test_conf_reg_t;
/** Type of sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
uint32_t sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprom_ctrl_reg_t;
/** Type of spram_ctrl register
* reserved
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sprf_ctrl_reg_t;
/** Type of sdprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_system_sdprf_ctrl_reg_t;
/** Type of bitscrambler_peri_sel register
* reserved
*/
typedef union {
struct {
/** bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0;
* select peri that will be connected to bitscrambler,dir : receive data from bs
*/
uint32_t bitscrambler_rx_sel:4;
/** bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0;
* select peri that will be connected to bitscrambler,dir : transfer data to peri
*/
uint32_t bitscrambler_tx_sel:4;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_system_bitscrambler_peri_sel_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_clock_gate_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing CPU peripheral
* register in the number of clock cycles of the clock domain.
*/
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Write 1 to clear timeout interrupt.
*/
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing CPU peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_cpu_peri_timeout_conf_reg_t;
/** Type of cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_cpu_peri_timeout_addr_reg_t;
/** Type of cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_cpu_peri_timeout_uid_reg_t;
/** Type of hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Configures the timeout threshold for bus access for accessing HP peripheral
* register, corresponding to the number of clock cycles of the clock domain.
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Configures whether or not to clear timeout interrupt.\\
* 0: No effect\\
* 1: Clear timeout interrupt\\
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Configures whether or not to enable timeout protection for accessing HP peripheral
* registers.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_hp_peri_timeout_conf_reg_t;
/** Type of hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address information of abnormal access.
*/
uint32_t hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_hp_peri_timeout_addr_reg_t;
/** Type of hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
* register will be cleared after the interrupt is cleared.
*/
uint32_t hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_hp_peri_timeout_uid_reg_t;
/** Type of modem_peri_timeout_conf register
* MODEM_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_modem_peri_timeout_conf_reg_t;
/** Type of modem_peri_timeout_addr register
* MODEM_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t modem_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_modem_peri_timeout_addr_reg_t;
/** Type of modem_peri_timeout_uid register
* MODEM_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_modem_peri_timeout_uid_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} hp_system_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} hp_system_rnd_eco_high_reg_t;
/** Group: Debug Register */
/** Type of debug register
* HP-SYSTEM debug register
*/
typedef union {
struct {
/** fpga_debug : R/W; bitpos: [0]; default: 1;
* Reserved
*/
uint32_t fpga_debug:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_debug_reg_t;
/** Group: Version Register */
/** Type of date register
* Date control and version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774016;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_system_date_reg_t;
typedef struct {
volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
uint32_t reserved_034;
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
volatile hp_system_rom_table_reg_t rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
volatile hp_system_mem_test_conf_reg_t mem_test_conf;
uint32_t reserved_048[10];
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
uint32_t reserved_084[215];
volatile hp_system_rnd_eco_reg_t rnd_eco;
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
uint32_t reserved_3ec[2];
volatile hp_system_debug_reg_t debug;
volatile hp_system_clock_gate_reg_t clock_gate;
volatile hp_system_date_reg_t date;
} hp_system_dev_t;
extern hp_system_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/huk_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
uint32_t reserved_5:27;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
extern huk_dev_t HUK;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_INTR_EXT_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/
ETS_TWAI0_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/
ETS_TWAI1_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_APB_ADC_INTR_SOURCE = 62, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GPSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_0 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_1 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_2 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* CPU_INTR_FROM_CPU_0 mapping register
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_3 mapping register.
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* Version control register
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
* Version control register.
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
/** INTPRI_RND_ECO_REG register
* redcy eco register.
*/
#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_ENA (BIT(0))
#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
#define INTPRI_REDCY_ENA_V 0x00000001U
#define INTPRI_REDCY_ENA_S 0
/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_RESULT (BIT(1))
#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
#define INTPRI_REDCY_RESULT_V 0x00000001U
#define INTPRI_REDCY_RESULT_S 1
/** INTPRI_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_LOW 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_S 0
/** INTPRI_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_HIGH 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_n register
* CPU_INTR_FROM_CPU_0 mapping register
*/
typedef union {
struct {
/** cpu_intr_from_cpu_n : R/W; bitpos: [0]; default: 0;
* CPU_INTR_FROM_CPU_n mapping register.
*/
uint32_t cpu_intr_from_cpu_n:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_n_reg_t;
/** Group: Version Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36712784;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} intpri_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} intpri_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} intpri_rnd_eco_high_reg_t;
typedef struct {
uint32_t reserved_000[36];
volatile intpri_cpu_intr_from_cpu_n_reg_t cpu_intr_from_cpu_n[4];
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
uint32_t reserved_0a8;
volatile intpri_rnd_eco_reg_t rnd_eco;
volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
uint32_t reserved_0b4[210];
volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpio register
* IO MUX configuration register for gpio
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of gpio in sleep mode.
* 0: Disable\\
* 1: Enable\\
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for gpio.\\
* 0: Not enter\\
* 1: Enter\\
*/
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of gpio in sleep mode.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of gpio during sleep mode. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of gpio during sleep mode.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of gpio during sleep mode. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of gpio.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of gpio.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of gpio.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of gpio. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal. \\
* 0: Select Function 0\\
* 1: Select Function 1\\
* ......\\
*/
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t filter_en:1;
/** hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_HYS_SEL is set to 1.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for gpio. \\
* 0: Choose the output enable signal of eFuse\\
* 1: Choose the output enable signal of IO_MUX_HYS_EN\\
*/
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpio_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 36770416;
* Version control register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
typedef struct {
volatile io_mux_gpio_reg_t gpio[29];
uint32_t reserved_074[98];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_REG_CG_FORCE_ON_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 5
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 10
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_S 11
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_S 12
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: flash_256_1_key. 3:
* flash_256_2_key. 4: flash_128_key. 6: hmac_key. 7: ds_key. 8: psram_256_1_key. 9:
* psram_256_2_key. 10: psram_128_key. Others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_VLD_S 0
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_FLASH_VLD (BIT(1))
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
#define KEYMNG_KEY_FLASH_VLD_S 1
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [2]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_HMAC_VLD (BIT(2))
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
#define KEYMNG_KEY_HMAC_VLD_S 2
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [3]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_DS_VLD (BIT(3))
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
#define KEYMNG_KEY_DS_VLD_S 3
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [4]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_PSRAM_VLD (BIT(4))
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
#define KEYMNG_KEY_PSRAM_VLD_S 4
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36774224;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t reg_cg_force_on:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:5;
/** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** flash_key_len : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t flash_key_len:1;
/** psram_key_len : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t psram_key_len:1;
uint32_t reserved_13:19;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:5;
/** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
uint32_t flash_key_len_lock:1;
/** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
uint32_t psram_key_len_lock:1;
uint32_t reserved_9:23;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: flash_256_1_key. 3:
* flash_256_2_key. 4: flash_128_key. 6: hmac_key. 7: ds_key. 8: psram_256_1_key. 9:
* psram_256_2_key. 10: psram_128_key. Others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_ecdsa_vld:1;
/** key_flash_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_flash_vld:1;
/** key_hmac_vld : RO; bitpos: [2]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_hmac_vld:1;
/** key_ds_vld : RO; bitpos: [3]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ds_vld:1;
/** key_psram_vld : RO; bitpos: [4]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_psram_vld:1;
uint32_t reserved_5:27;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774224;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
extern keymng_dev_t KEYMNG;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* Configure brownout mode0
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* Configure brownout mode1
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_CK_GLITCH_CNTL_REG register
* Configure power glitch
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
*/
#define LP_ANA_PWR_GLITCH_RESET_ENA 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_M (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
#define LP_ANA_PWR_GLITCH_RESET_ENA_V 0x0000000FU
#define LP_ANA_PWR_GLITCH_RESET_ENA_S 27
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_FIB_ENABLE_REG register
* configure FIB REG
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
*/
#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_S 0
/** LP_ANA_INT_RAW_REG register
* interrpt raw register
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* interrpt status register
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* interrpt enable register
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* interrpt clear register
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* lp interrupt raw register
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* lp interrupt status register
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* lp interrupt enable register
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* lp interrupt clear register
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* version register
*/
#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 36774528;
* version register
*/
#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 0
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
#define LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* Configure brownout mode0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* enable suspend spi when brownout interrupt or not
* 1:enable
* 0:disable
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* enable power down RF when brownout interrupt or not
* 1:enable
* 0:disable
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* set the undervoltage hold time for triggering brownout interrupt
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* set the undervoltage hold time for triggering brownout reset
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* clear brownout count or not
* 1: clear
* 0: no operation
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* enable brownout interrupt or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* select brownout reset level
* 1: system reset
* 0: chip reset
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout reset or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* Configure brownout mode1
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* enable brownout mode1 reset or not
* 1: enable
* 0: disable
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* Configure power glitch
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** pwr_glitch_reset_ena : R/W; bitpos: [30:27]; default: 0;
* enable powerglitch or not
*/
uint32_t pwr_glitch_reset_ena:4;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* configure FIB REG
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* configure analog fib by software
*/
uint32_t ana_fib_ena:32;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* interrpt raw register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 interrupt raw register
*/
uint32_t bod_mode0_int_raw:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* interrpt status register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 interrupt status register
*/
uint32_t bod_mode0_int_st:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* interrpt enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 interrupt enable register
*/
uint32_t bod_mode0_int_ena:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* interrpt clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 interrupt clear register
*/
uint32_t bod_mode0_int_clr:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* lp interrupt raw register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt raw register
*/
uint32_t bod_mode0_lp_int_raw:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* lp interrupt status register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt status register
*/
uint32_t bod_mode0_lp_int_st:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* lp interrupt enable register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt enable register
*/
uint32_t bod_mode0_lp_int_ena:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* lp interrupt clear register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* brownout mode0 lp interrupt clear register
*/
uint32_t bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of date register
* version register
*/
typedef union {
struct {
/** lp_ana_date : R/W; bitpos: [30:0]; default: 36774528;
* version register
*/
uint32_t lp_ana_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;
volatile lp_ana_int_ena_reg_t int_ena;
volatile lp_ana_int_clr_reg_t int_clr;
volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
volatile lp_ana_lp_int_st_reg_t lp_int_st;
volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_030[243];
volatile lp_ana_date_reg_t date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* store the software massege0 in always-on field
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* store the software massege0 in always-on field
*/
#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* store the software massege1 in always-on field
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* store the software massege1 in always-on field
*/
#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* store the software massege2 in always-on field
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* store the software massege2 in always-on field
*/
#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* store the software massege3 in always-on field
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* store the software massege3 in always-on field
*/
#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* store the software massege4 in always-on field
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* store the software massege4 in always-on field
*/
#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* store the software massege5 in always-on field
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* store the software massege5 in always-on field
*/
#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* store the software massege6 in always-on field
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* store the software massege6 in always-on field
*/
#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* store the software massege7 in always-on field
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* store the software massege7 in always-on field
*/
#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* store the software massege8 in always-on field
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* store the software massege8 in always-on field
*/
#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* store the software massege9 in always-on field
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* store the software massege9 in always-on field
*/
#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* select the lp io controlled by hp iomux or lp iomux
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
* select the lp io 0~7 controlled by hp iomux or lp iomux
* 1: controlled by lp iomux
* 0: controlled by hp iomux
*/
#define LP_AON_GPIO_MUX_SEL 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* configure all io hold
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_GPIO_HOLD1_REG register
* reserved
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_S 0
/** LP_AON_SYS_CFG_REG register
* configure system register
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT_STATUS : RO; bitpos: [29]; default: 0;
* get force download mode status
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS (BIT(29))
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_M (LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V << LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_STATUS_S 29
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
* enable chip entry download mode or not
* 1: enable
* 0: no operation
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
* 0: no operation
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE0_CFG_REG register
* configure core reset register
*/
#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* enable cpu entry stall status
* 0x86: entry stall status
* Others : no operation
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
* enable core reset by software
* 1: reset
* 0: no operation
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(28))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* reserved
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29
/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
* configure core boot address
* 1: ROM
* 0: lp memory
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30
/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
* disable bypass core dreset
* 1: enable bypass
* 0: disable bypass
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U
#define LP_AON_CPU_CORE0_DRESET_MASK_S 31
/** LP_AON_IO_MUX_REG register
* configure hp iomux reset bypass
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* bypass hp iomux reset from hp system reset event
* 1: bypass
* 0: no operation
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* configure alwayson external io wakeup
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
* get external wakeup status bitmap
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
* clear external wakeup status
* 1: clear
* 0: no operation
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
* enable io0~7 bit map use to external wakeup
* 1: enable
* 0: disable
*/
#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_S 15
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
* select external wakeup io level
* 1: io high level wakeup
* 0: io low level wakeup
*/
#define LP_AON_EXT_WAKEUP_LV 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_S 23
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* enable external filter or not
* 1: enable
* 0: disable
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* configure usb reset bypass
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* bypass usb reset from hp system reset event
* 1: bypass
* 0: no operation
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* Select lp memory bus
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* get current lp memory bus fsm status
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* get current lp memory bus mode
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* enable reg_fast_mem_sel configure
* 1: enable
* 0: no operation
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* select lp memory bus is high speed mode or low speed mode
* 1: high speed from hp system ahb
* 0: low speed from lp system
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_SDIO_ACTIVE_REG register
* configure sdio act dnum
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* reserved
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* configure etm wakeup register
*/
#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* clear etm wakeup latch
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* latch etmwakeup event
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1
/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
* disable lp core
* 1:disable
* 0:no operation
*/
#define LP_AON_LPCORE_DISABLE (BIT(31))
#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
#define LP_AON_LPCORE_DISABLE_V 0x00000001U
#define LP_AON_LPCORE_DISABLE_S 31
/** LP_AON_SAR_CCT_REG register
* configure sar cct
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* configure sar cct
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_S 29
/** LP_AON_MODEM_BUS_REG register
* configure modem sync bridge
*/
#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58)
/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0;
* enable modem sync bridge or not
* 1: enable
* 0: disable
*/
#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31))
#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S)
#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U
#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31
/** LP_AON_SPRAM_CTRL_REG register
* configure lp memory power status
*/
#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60)
/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* configure lp memory power status
*/
#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S)
#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0
/** LP_AON_SPRF_CTRL_REG register
* configure memory in lp system power status
*/
#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64)
/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* configure memory in lp system power status
*/
#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S)
#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_S 0
/** LP_AON_DEBUG_SEL0_REG register
* reserved
*/
#define LP_AON_DEBUG_SEL0_REG (DR_REG_LP_AON_BASE + 0x68)
/** LP_AON_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
#define LP_AON_LP_DEBUG_SEL0 0x0000007FU
#define LP_AON_LP_DEBUG_SEL0_M (LP_AON_LP_DEBUG_SEL0_V << LP_AON_LP_DEBUG_SEL0_S)
#define LP_AON_LP_DEBUG_SEL0_V 0x0000007FU
#define LP_AON_LP_DEBUG_SEL0_S 0
/** LP_AON_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
#define LP_AON_LP_DEBUG_SEL1 0x0000007FU
#define LP_AON_LP_DEBUG_SEL1_M (LP_AON_LP_DEBUG_SEL1_V << LP_AON_LP_DEBUG_SEL1_S)
#define LP_AON_LP_DEBUG_SEL1_V 0x0000007FU
#define LP_AON_LP_DEBUG_SEL1_S 7
/** LP_AON_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
#define LP_AON_LP_DEBUG_SEL2 0x0000007FU
#define LP_AON_LP_DEBUG_SEL2_M (LP_AON_LP_DEBUG_SEL2_V << LP_AON_LP_DEBUG_SEL2_S)
#define LP_AON_LP_DEBUG_SEL2_V 0x0000007FU
#define LP_AON_LP_DEBUG_SEL2_S 14
/** LP_AON_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
#define LP_AON_LP_DEBUG_SEL3 0x0000007FU
#define LP_AON_LP_DEBUG_SEL3_M (LP_AON_LP_DEBUG_SEL3_V << LP_AON_LP_DEBUG_SEL3_S)
#define LP_AON_LP_DEBUG_SEL3_V 0x0000007FU
#define LP_AON_LP_DEBUG_SEL3_S 21
/** LP_AON_DEBUG_SEL1_REG register
* need des
*/
#define LP_AON_DEBUG_SEL1_REG (DR_REG_LP_AON_BASE + 0x6c)
/** LP_AON_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
#define LP_AON_LP_DEBUG_SEL4 0x0000007FU
#define LP_AON_LP_DEBUG_SEL4_M (LP_AON_LP_DEBUG_SEL4_V << LP_AON_LP_DEBUG_SEL4_S)
#define LP_AON_LP_DEBUG_SEL4_V 0x0000007FU
#define LP_AON_LP_DEBUG_SEL4_S 0
/** LP_AON_BACKUP_DMA_CFG0_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70)
/** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
* Set this field to configure max value of burst in signle transfer.
*/
#define LP_AON_BURST_LIMIT_AON 0x0000001FU
#define LP_AON_BURST_LIMIT_AON_M (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S)
#define LP_AON_BURST_LIMIT_AON_V 0x0000001FU
#define LP_AON_BURST_LIMIT_AON_S 0
/** LP_AON_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
* Set this field to configure read registers' interval time in reading mode.
*/
#define LP_AON_READ_INTERVAL_AON 0x0000007FU
#define LP_AON_READ_INTERVAL_AON_M (LP_AON_READ_INTERVAL_AON_V << LP_AON_READ_INTERVAL_AON_S)
#define LP_AON_READ_INTERVAL_AON_V 0x0000007FU
#define LP_AON_READ_INTERVAL_AON_S 5
/** LP_AON_BRANCH_LINK_LENGTH_AON : R/W; bitpos: [15:12]; default: 0;
* Set this field to configure link address.
*/
#define LP_AON_BRANCH_LINK_LENGTH_AON 0x0000000FU
#define LP_AON_BRANCH_LINK_LENGTH_AON_M (LP_AON_BRANCH_LINK_LENGTH_AON_V << LP_AON_BRANCH_LINK_LENGTH_AON_S)
#define LP_AON_BRANCH_LINK_LENGTH_AON_V 0x0000000FU
#define LP_AON_BRANCH_LINK_LENGTH_AON_S 12
/** LP_AON_BACKUP_DMA_CFG1_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG1_REG (DR_REG_LP_AON_BASE + 0x74)
/** LP_AON_LINK_WAIT_TOUT_THRES_AON : R/W; bitpos: [9:0]; default: 100;
* Set this field to configure the number of consecutive links of link list.
*/
#define LP_AON_LINK_WAIT_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_M (LP_AON_LINK_WAIT_TOUT_THRES_AON_V << LP_AON_LINK_WAIT_TOUT_THRES_AON_S)
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_S 0
/** LP_AON_LINK_WORK_TOUT_THRES_AON : R/W; bitpos: [19:10]; default: 100;
* Set this field to configure maximum waiting time in waiting mode.
*/
#define LP_AON_LINK_WORK_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_WORK_TOUT_THRES_AON_M (LP_AON_LINK_WORK_TOUT_THRES_AON_V << LP_AON_LINK_WORK_TOUT_THRES_AON_S)
#define LP_AON_LINK_WORK_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_WORK_TOUT_THRES_AON_S 10
/** LP_AON_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [29:20]; default: 100;
* Set this field to configure maximum waiting time in backup mode.
*/
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_M (LP_AON_LINK_BACKUP_TOUT_THRES_AON_V << LP_AON_LINK_BACKUP_TOUT_THRES_AON_S)
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20
/** LP_AON_AON_BYPASS : R/W; bitpos: [31]; default: 0;
* reserved
*/
#define LP_AON_AON_BYPASS (BIT(31))
#define LP_AON_AON_BYPASS_M (LP_AON_AON_BYPASS_V << LP_AON_AON_BYPASS_S)
#define LP_AON_AON_BYPASS_V 0x00000001U
#define LP_AON_AON_BYPASS_S 31
/** LP_AON_BACKUP_DMA_CFG2_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG2_REG (DR_REG_LP_AON_BASE + 0x78)
/** LP_AON_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
* Set this field to configure link address.
*/
#define LP_AON_LINK_ADDR_AON 0xFFFFFFFFU
#define LP_AON_LINK_ADDR_AON_M (LP_AON_LINK_ADDR_AON_V << LP_AON_LINK_ADDR_AON_S)
#define LP_AON_LINK_ADDR_AON_V 0xFFFFFFFFU
#define LP_AON_LINK_ADDR_AON_S 0
/** LP_AON_MEM_CTRL_REG register
* configure rmemory power in lp system register
*/
#define LP_AON_MEM_CTRL_REG (DR_REG_LP_AON_BASE + 0x7c)
/** LP_AON_LP_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
* force off lp memory
*/
#define LP_AON_LP_MEM_FORCE_PD (BIT(0))
#define LP_AON_LP_MEM_FORCE_PD_M (LP_AON_LP_MEM_FORCE_PD_V << LP_AON_LP_MEM_FORCE_PD_S)
#define LP_AON_LP_MEM_FORCE_PD_V 0x00000001U
#define LP_AON_LP_MEM_FORCE_PD_S 0
/** LP_AON_LP_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
* force on lp memory
*/
#define LP_AON_LP_MEM_FORCE_PU (BIT(1))
#define LP_AON_LP_MEM_FORCE_PU_M (LP_AON_LP_MEM_FORCE_PU_V << LP_AON_LP_MEM_FORCE_PU_S)
#define LP_AON_LP_MEM_FORCE_PU_V 0x00000001U
#define LP_AON_LP_MEM_FORCE_PU_S 1
/** LP_AON_HUK_MEM_FORCE_PD : R/W; bitpos: [2]; default: 1;
* force off huk memory
*/
#define LP_AON_HUK_MEM_FORCE_PD (BIT(2))
#define LP_AON_HUK_MEM_FORCE_PD_M (LP_AON_HUK_MEM_FORCE_PD_V << LP_AON_HUK_MEM_FORCE_PD_S)
#define LP_AON_HUK_MEM_FORCE_PD_V 0x00000001U
#define LP_AON_HUK_MEM_FORCE_PD_S 2
/** LP_AON_HUK_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0;
* force on huk memory
*/
#define LP_AON_HUK_MEM_FORCE_PU (BIT(3))
#define LP_AON_HUK_MEM_FORCE_PU_M (LP_AON_HUK_MEM_FORCE_PU_V << LP_AON_HUK_MEM_FORCE_PU_S)
#define LP_AON_HUK_MEM_FORCE_PU_V 0x00000001U
#define LP_AON_HUK_MEM_FORCE_PU_S 3
/** LP_AON_DATE_REG register
* reserved
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36774512;
* version register
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* version register
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store0 register
* store the software massege0 in always-on field
*/
typedef union {
struct {
/** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
* store the software massege0 in always-on field
*/
uint32_t lp_aon_store0:32;
};
uint32_t val;
} lp_aon_store0_reg_t;
/** Type of store1 register
* store the software massege1 in always-on field
*/
typedef union {
struct {
/** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
* store the software massege1 in always-on field
*/
uint32_t lp_aon_store1:32;
};
uint32_t val;
} lp_aon_store1_reg_t;
/** Type of store2 register
* store the software massege2 in always-on field
*/
typedef union {
struct {
/** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
* store the software massege2 in always-on field
*/
uint32_t lp_aon_store2:32;
};
uint32_t val;
} lp_aon_store2_reg_t;
/** Type of store3 register
* store the software massege3 in always-on field
*/
typedef union {
struct {
/** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
* store the software massege3 in always-on field
*/
uint32_t lp_aon_store3:32;
};
uint32_t val;
} lp_aon_store3_reg_t;
/** Type of store4 register
* store the software massege4 in always-on field
*/
typedef union {
struct {
/** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
* store the software massege4 in always-on field
*/
uint32_t lp_aon_store4:32;
};
uint32_t val;
} lp_aon_store4_reg_t;
/** Type of store5 register
* store the software massege5 in always-on field
*/
typedef union {
struct {
/** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
* store the software massege5 in always-on field
*/
uint32_t lp_aon_store5:32;
};
uint32_t val;
} lp_aon_store5_reg_t;
/** Type of store6 register
* store the software massege6 in always-on field
*/
typedef union {
struct {
/** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
* store the software massege6 in always-on field
*/
uint32_t lp_aon_store6:32;
};
uint32_t val;
} lp_aon_store6_reg_t;
/** Type of store7 register
* store the software massege7 in always-on field
*/
typedef union {
struct {
/** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
* store the software massege7 in always-on field
*/
uint32_t lp_aon_store7:32;
};
uint32_t val;
} lp_aon_store7_reg_t;
/** Type of store8 register
* store the software massege8 in always-on field
*/
typedef union {
struct {
/** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
* store the software massege8 in always-on field
*/
uint32_t lp_aon_store8:32;
};
uint32_t val;
} lp_aon_store8_reg_t;
/** Type of store9 register
* store the software massege9 in always-on field
*/
typedef union {
struct {
/** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
* store the software massege9 in always-on field
*/
uint32_t lp_aon_store9:32;
};
uint32_t val;
} lp_aon_store9_reg_t;
/** Type of gpio_mux register
* select the lp io controlled by hp iomux or lp iomux
*/
typedef union {
struct {
/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
* select the lp io 0~7 controlled by hp iomux or lp iomux
* 1: controlled by lp iomux
* 0: controlled by hp iomux
*/
uint32_t gpio_mux_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of gpio_hold0 register
* configure all io hold
*/
typedef union {
struct {
/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of gpio_hold1 register
* reserved
*/
typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t gpio_hold1:32;
};
uint32_t val;
} lp_aon_gpio_hold1_reg_t;
/** Type of sys_cfg register
* configure system register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** force_download_boot_status : RO; bitpos: [29]; default: 0;
* get force download mode status
*/
uint32_t force_download_boot_status:1;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
* enable chip entry download mode or not
* 1: enable
* 0: no operation
*/
uint32_t force_download_boot:1;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
* 0: no operation
*/
uint32_t hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of cpucore0_cfg register
* configure core reset register
*/
typedef union {
struct {
/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* enable cpu entry stall status
* 0x86: entry stall status
* Others : no operation
*/
uint32_t cpu_core0_sw_stall:8;
uint32_t reserved_8:20;
/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
* enable core reset by software
* 1: reset
* 0: no operation
*/
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* reserved
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* configure core boot address
* 1: ROM
* 0: lp memory
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* disable bypass core dreset
* 1: enable bypass
* 0: disable bypass
*/
uint32_t cpu_core0_dreset_mask:1;
};
uint32_t val;
} lp_aon_cpucore0_cfg_reg_t;
/** Type of io_mux register
* configure hp iomux reset bypass
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* bypass hp iomux reset from hp system reset event
* 1: bypass
* 0: no operation
*/
uint32_t io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of ext_wakeup_cntl register
* configure alwayson external io wakeup
*/
typedef union {
struct {
/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
* get external wakeup status bitmap
*/
uint32_t ext_wakeup_status:8;
uint32_t reserved_8:6;
/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
* clear external wakeup status
* 1: clear
* 0: no operation
*/
uint32_t ext_wakeup_status_clr:1;
/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
* enable io0~7 bit map use to external wakeup
* 1: enable
* 0: disable
*/
uint32_t ext_wakeup_sel:8;
/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
* select external wakeup io level
* 1: io high level wakeup
* 0: io low level wakeup
*/
uint32_t ext_wakeup_lv:8;
/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* enable external filter or not
* 1: enable
* 0: disable
*/
uint32_t ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of usb register
* configure usb reset bypass
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
* bypass usb reset from hp system reset event
* 1: bypass
* 0: no operation
*/
uint32_t usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
* Select lp memory bus
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* get current lp memory bus fsm status
*/
uint32_t fast_mem_mux_fsm_idle:1;
/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* get current lp memory bus mode
*/
uint32_t fast_mem_mux_sel_status:1;
/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* enable reg_fast_mem_sel configure
* 1: enable
* 0: no operation
*/
uint32_t fast_mem_mux_sel_update:1;
/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* select lp memory bus is high speed mode or low speed mode
* 1: high speed from hp system ahb
* 0: low speed from lp system
*/
uint32_t fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of sdio_active register
* configure sdio act dnum
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* reserved
*/
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* configure etm wakeup register
*/
typedef union {
struct {
/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* clear etm wakeup latch
*/
uint32_t lpcore_etm_wakeup_flag_clr:1;
/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* latch etmwakeup event
*/
uint32_t lpcore_etm_wakeup_flag:1;
uint32_t reserved_2:29;
/** lpcore_disable : R/W; bitpos: [31]; default: 0;
* disable lp core
* 1:disable
* 0:no operation
*/
uint32_t lpcore_disable:1;
};
uint32_t val;
} lp_aon_lpcore_reg_t;
/** Type of sar_cct register
* configure sar cct
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* configure sar cct
*/
uint32_t sar2_pwdet_cct:3;
};
uint32_t val;
} lp_aon_sar_cct_reg_t;
/** Type of modem_bus register
* configure modem sync bridge
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0;
* enable modem sync bridge or not
* 1: enable
* 0: disable
*/
uint32_t modem_sync_bridge_en:1;
};
uint32_t val;
} lp_aon_modem_bus_reg_t;
/** Type of debug_sel0 register
* reserved
*/
typedef union {
struct {
/** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel0:7;
/** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t lp_debug_sel1:7;
/** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t lp_debug_sel2:7;
/** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t lp_debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_aon_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_aon_debug_sel1_reg_t;
/** Type of backup_dma_cfg0 register
* configure regdma always on register
*/
typedef union {
struct {
/** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
* Set this field to configure max value of burst in signle transfer.
*/
uint32_t burst_limit_aon:5;
/** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
* Set this field to configure read registers' interval time in reading mode.
*/
uint32_t read_interval_aon:7;
/** branch_link_length_aon : R/W; bitpos: [15:12]; default: 0;
* Set this field to configure link address.
*/
uint32_t branch_link_length_aon:4;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_aon_backup_dma_cfg0_reg_t;
/** Type of backup_dma_cfg1 register
* configure regdma always on register
*/
typedef union {
struct {
/** link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100;
* Set this field to configure the number of consecutive links of link list.
*/
uint32_t link_wait_tout_thres_aon:10;
/** link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100;
* Set this field to configure maximum waiting time in waiting mode.
*/
uint32_t link_work_tout_thres_aon:10;
/** link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100;
* Set this field to configure maximum waiting time in backup mode.
*/
uint32_t link_backup_tout_thres_aon:10;
uint32_t reserved_30:1;
/** aon_bypass : R/W; bitpos: [31]; default: 0;
* reserved
*/
uint32_t aon_bypass:1;
};
uint32_t val;
} lp_aon_backup_dma_cfg1_reg_t;
/** Type of backup_dma_cfg2 register
* configure regdma always on register
*/
typedef union {
struct {
/** link_addr_aon : R/W; bitpos: [31:0]; default: 0;
* Set this field to configure link address.
*/
uint32_t link_addr_aon:32;
};
uint32_t val;
} lp_aon_backup_dma_cfg2_reg_t;
/** Type of mem_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** lp_mem_force_pd : R/W; bitpos: [0]; default: 0;
* force off lp memory
*/
uint32_t lp_mem_force_pd:1;
/** lp_mem_force_pu : R/W; bitpos: [1]; default: 1;
* force on lp memory
*/
uint32_t lp_mem_force_pu:1;
/** huk_mem_force_pd : R/W; bitpos: [2]; default: 1;
* force off huk memory
*/
uint32_t huk_mem_force_pd:1;
/** huk_mem_force_pu : R/W; bitpos: [3]; default: 0;
* force on huk memory
*/
uint32_t huk_mem_force_pu:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_aon_mem_ctrl_reg_t;
/** Type of date register
* reserved
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36774512;
* version register
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* version register
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
/** Group: Configuration Register */
/** Type of spram_ctrl register
* configure lp memory power status
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* configure lp memory power status
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* configure memory in lp system power status
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* configure memory in lp system power status
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_sprf_ctrl_reg_t;
typedef struct {
volatile lp_aon_store0_reg_t store0;
volatile lp_aon_store1_reg_t store1;
volatile lp_aon_store2_reg_t store2;
volatile lp_aon_store3_reg_t store3;
volatile lp_aon_store4_reg_t store4;
volatile lp_aon_store5_reg_t store5;
volatile lp_aon_store6_reg_t store6;
volatile lp_aon_store7_reg_t store7;
volatile lp_aon_store8_reg_t store8;
volatile lp_aon_store9_reg_t store9;
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
volatile lp_aon_modem_bus_reg_t modem_bus;
uint32_t reserved_05c;
volatile lp_aon_spram_ctrl_reg_t spram_ctrl;
volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl;
volatile lp_aon_debug_sel0_reg_t debug_sel0;
volatile lp_aon_debug_sel1_reg_t debug_sel1;
volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0;
volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1;
volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2;
volatile lp_aon_mem_ctrl_reg_t mem_ctrl;
uint32_t reserved_080[223];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n(0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 0
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_S 0
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 0
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 0.
*/
#define LP_APM0_REGION0_R0_X (BIT(0))
#define LP_APM0_REGION0_R0_X_M (LP_APM0_REGION0_R0_X_V << LP_APM0_REGION0_R0_X_S)
#define LP_APM0_REGION0_R0_X_V 0x00000001U
#define LP_APM0_REGION0_R0_X_S 0
/** LP_APM0_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 0.
*/
#define LP_APM0_REGION0_R0_W (BIT(1))
#define LP_APM0_REGION0_R0_W_M (LP_APM0_REGION0_R0_W_V << LP_APM0_REGION0_R0_W_S)
#define LP_APM0_REGION0_R0_W_V 0x00000001U
#define LP_APM0_REGION0_R0_W_S 1
/** LP_APM0_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 0.
*/
#define LP_APM0_REGION0_R0_R (BIT(2))
#define LP_APM0_REGION0_R0_R_M (LP_APM0_REGION0_R0_R_V << LP_APM0_REGION0_R0_R_S)
#define LP_APM0_REGION0_R0_R_V 0x00000001U
#define LP_APM0_REGION0_R0_R_S 2
/** LP_APM0_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 0.
*/
#define LP_APM0_REGION0_R1_X (BIT(4))
#define LP_APM0_REGION0_R1_X_M (LP_APM0_REGION0_R1_X_V << LP_APM0_REGION0_R1_X_S)
#define LP_APM0_REGION0_R1_X_V 0x00000001U
#define LP_APM0_REGION0_R1_X_S 4
/** LP_APM0_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 0.
*/
#define LP_APM0_REGION0_R1_W (BIT(5))
#define LP_APM0_REGION0_R1_W_M (LP_APM0_REGION0_R1_W_V << LP_APM0_REGION0_R1_W_S)
#define LP_APM0_REGION0_R1_W_V 0x00000001U
#define LP_APM0_REGION0_R1_W_S 5
/** LP_APM0_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 0.
*/
#define LP_APM0_REGION0_R1_R (BIT(6))
#define LP_APM0_REGION0_R1_R_M (LP_APM0_REGION0_R1_R_V << LP_APM0_REGION0_R1_R_S)
#define LP_APM0_REGION0_R1_R_V 0x00000001U
#define LP_APM0_REGION0_R1_R_S 6
/** LP_APM0_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 0.
*/
#define LP_APM0_REGION0_R2_X (BIT(8))
#define LP_APM0_REGION0_R2_X_M (LP_APM0_REGION0_R2_X_V << LP_APM0_REGION0_R2_X_S)
#define LP_APM0_REGION0_R2_X_V 0x00000001U
#define LP_APM0_REGION0_R2_X_S 8
/** LP_APM0_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 0.
*/
#define LP_APM0_REGION0_R2_W (BIT(9))
#define LP_APM0_REGION0_R2_W_M (LP_APM0_REGION0_R2_W_V << LP_APM0_REGION0_R2_W_S)
#define LP_APM0_REGION0_R2_W_V 0x00000001U
#define LP_APM0_REGION0_R2_W_S 9
/** LP_APM0_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 0.
*/
#define LP_APM0_REGION0_R2_R (BIT(10))
#define LP_APM0_REGION0_R2_R_M (LP_APM0_REGION0_R2_R_V << LP_APM0_REGION0_R2_R_S)
#define LP_APM0_REGION0_R2_R_V 0x00000001U
#define LP_APM0_REGION0_R2_R_S 10
/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION0_LOCK (BIT(11))
#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S)
#define LP_APM0_REGION0_LOCK_V 0x00000001U
#define LP_APM0_REGION0_LOCK_S 11
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 1
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_S 0
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 1
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 1.
*/
#define LP_APM0_REGION1_R0_X (BIT(0))
#define LP_APM0_REGION1_R0_X_M (LP_APM0_REGION1_R0_X_V << LP_APM0_REGION1_R0_X_S)
#define LP_APM0_REGION1_R0_X_V 0x00000001U
#define LP_APM0_REGION1_R0_X_S 0
/** LP_APM0_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 1.
*/
#define LP_APM0_REGION1_R0_W (BIT(1))
#define LP_APM0_REGION1_R0_W_M (LP_APM0_REGION1_R0_W_V << LP_APM0_REGION1_R0_W_S)
#define LP_APM0_REGION1_R0_W_V 0x00000001U
#define LP_APM0_REGION1_R0_W_S 1
/** LP_APM0_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 1.
*/
#define LP_APM0_REGION1_R0_R (BIT(2))
#define LP_APM0_REGION1_R0_R_M (LP_APM0_REGION1_R0_R_V << LP_APM0_REGION1_R0_R_S)
#define LP_APM0_REGION1_R0_R_V 0x00000001U
#define LP_APM0_REGION1_R0_R_S 2
/** LP_APM0_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 1.
*/
#define LP_APM0_REGION1_R1_X (BIT(4))
#define LP_APM0_REGION1_R1_X_M (LP_APM0_REGION1_R1_X_V << LP_APM0_REGION1_R1_X_S)
#define LP_APM0_REGION1_R1_X_V 0x00000001U
#define LP_APM0_REGION1_R1_X_S 4
/** LP_APM0_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 1.
*/
#define LP_APM0_REGION1_R1_W (BIT(5))
#define LP_APM0_REGION1_R1_W_M (LP_APM0_REGION1_R1_W_V << LP_APM0_REGION1_R1_W_S)
#define LP_APM0_REGION1_R1_W_V 0x00000001U
#define LP_APM0_REGION1_R1_W_S 5
/** LP_APM0_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 1.
*/
#define LP_APM0_REGION1_R1_R (BIT(6))
#define LP_APM0_REGION1_R1_R_M (LP_APM0_REGION1_R1_R_V << LP_APM0_REGION1_R1_R_S)
#define LP_APM0_REGION1_R1_R_V 0x00000001U
#define LP_APM0_REGION1_R1_R_S 6
/** LP_APM0_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 1.
*/
#define LP_APM0_REGION1_R2_X (BIT(8))
#define LP_APM0_REGION1_R2_X_M (LP_APM0_REGION1_R2_X_V << LP_APM0_REGION1_R2_X_S)
#define LP_APM0_REGION1_R2_X_V 0x00000001U
#define LP_APM0_REGION1_R2_X_S 8
/** LP_APM0_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 1.
*/
#define LP_APM0_REGION1_R2_W (BIT(9))
#define LP_APM0_REGION1_R2_W_M (LP_APM0_REGION1_R2_W_V << LP_APM0_REGION1_R2_W_S)
#define LP_APM0_REGION1_R2_W_V 0x00000001U
#define LP_APM0_REGION1_R2_W_S 9
/** LP_APM0_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 1.
*/
#define LP_APM0_REGION1_R2_R (BIT(10))
#define LP_APM0_REGION1_R2_R_M (LP_APM0_REGION1_R2_R_V << LP_APM0_REGION1_R2_R_S)
#define LP_APM0_REGION1_R2_R_V 0x00000001U
#define LP_APM0_REGION1_R2_R_S 10
/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION1_LOCK (BIT(11))
#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S)
#define LP_APM0_REGION1_LOCK_V 0x00000001U
#define LP_APM0_REGION1_LOCK_S 11
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 2
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_S 0
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 2
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 2.
*/
#define LP_APM0_REGION2_R0_X (BIT(0))
#define LP_APM0_REGION2_R0_X_M (LP_APM0_REGION2_R0_X_V << LP_APM0_REGION2_R0_X_S)
#define LP_APM0_REGION2_R0_X_V 0x00000001U
#define LP_APM0_REGION2_R0_X_S 0
/** LP_APM0_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 2.
*/
#define LP_APM0_REGION2_R0_W (BIT(1))
#define LP_APM0_REGION2_R0_W_M (LP_APM0_REGION2_R0_W_V << LP_APM0_REGION2_R0_W_S)
#define LP_APM0_REGION2_R0_W_V 0x00000001U
#define LP_APM0_REGION2_R0_W_S 1
/** LP_APM0_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 2.
*/
#define LP_APM0_REGION2_R0_R (BIT(2))
#define LP_APM0_REGION2_R0_R_M (LP_APM0_REGION2_R0_R_V << LP_APM0_REGION2_R0_R_S)
#define LP_APM0_REGION2_R0_R_V 0x00000001U
#define LP_APM0_REGION2_R0_R_S 2
/** LP_APM0_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 2.
*/
#define LP_APM0_REGION2_R1_X (BIT(4))
#define LP_APM0_REGION2_R1_X_M (LP_APM0_REGION2_R1_X_V << LP_APM0_REGION2_R1_X_S)
#define LP_APM0_REGION2_R1_X_V 0x00000001U
#define LP_APM0_REGION2_R1_X_S 4
/** LP_APM0_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 2.
*/
#define LP_APM0_REGION2_R1_W (BIT(5))
#define LP_APM0_REGION2_R1_W_M (LP_APM0_REGION2_R1_W_V << LP_APM0_REGION2_R1_W_S)
#define LP_APM0_REGION2_R1_W_V 0x00000001U
#define LP_APM0_REGION2_R1_W_S 5
/** LP_APM0_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 2.
*/
#define LP_APM0_REGION2_R1_R (BIT(6))
#define LP_APM0_REGION2_R1_R_M (LP_APM0_REGION2_R1_R_V << LP_APM0_REGION2_R1_R_S)
#define LP_APM0_REGION2_R1_R_V 0x00000001U
#define LP_APM0_REGION2_R1_R_S 6
/** LP_APM0_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 2.
*/
#define LP_APM0_REGION2_R2_X (BIT(8))
#define LP_APM0_REGION2_R2_X_M (LP_APM0_REGION2_R2_X_V << LP_APM0_REGION2_R2_X_S)
#define LP_APM0_REGION2_R2_X_V 0x00000001U
#define LP_APM0_REGION2_R2_X_S 8
/** LP_APM0_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 2.
*/
#define LP_APM0_REGION2_R2_W (BIT(9))
#define LP_APM0_REGION2_R2_W_M (LP_APM0_REGION2_R2_W_V << LP_APM0_REGION2_R2_W_S)
#define LP_APM0_REGION2_R2_W_V 0x00000001U
#define LP_APM0_REGION2_R2_W_S 9
/** LP_APM0_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 2.
*/
#define LP_APM0_REGION2_R2_R (BIT(10))
#define LP_APM0_REGION2_R2_R_M (LP_APM0_REGION2_R2_R_V << LP_APM0_REGION2_R2_R_S)
#define LP_APM0_REGION2_R2_R_V 0x00000001U
#define LP_APM0_REGION2_R2_R_S 10
/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION2_LOCK (BIT(11))
#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S)
#define LP_APM0_REGION2_LOCK_V 0x00000001U
#define LP_APM0_REGION2_LOCK_S 11
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 3
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_S 0
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 3
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 3.
*/
#define LP_APM0_REGION3_R0_X (BIT(0))
#define LP_APM0_REGION3_R0_X_M (LP_APM0_REGION3_R0_X_V << LP_APM0_REGION3_R0_X_S)
#define LP_APM0_REGION3_R0_X_V 0x00000001U
#define LP_APM0_REGION3_R0_X_S 0
/** LP_APM0_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 3.
*/
#define LP_APM0_REGION3_R0_W (BIT(1))
#define LP_APM0_REGION3_R0_W_M (LP_APM0_REGION3_R0_W_V << LP_APM0_REGION3_R0_W_S)
#define LP_APM0_REGION3_R0_W_V 0x00000001U
#define LP_APM0_REGION3_R0_W_S 1
/** LP_APM0_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 3.
*/
#define LP_APM0_REGION3_R0_R (BIT(2))
#define LP_APM0_REGION3_R0_R_M (LP_APM0_REGION3_R0_R_V << LP_APM0_REGION3_R0_R_S)
#define LP_APM0_REGION3_R0_R_V 0x00000001U
#define LP_APM0_REGION3_R0_R_S 2
/** LP_APM0_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 3.
*/
#define LP_APM0_REGION3_R1_X (BIT(4))
#define LP_APM0_REGION3_R1_X_M (LP_APM0_REGION3_R1_X_V << LP_APM0_REGION3_R1_X_S)
#define LP_APM0_REGION3_R1_X_V 0x00000001U
#define LP_APM0_REGION3_R1_X_S 4
/** LP_APM0_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 3.
*/
#define LP_APM0_REGION3_R1_W (BIT(5))
#define LP_APM0_REGION3_R1_W_M (LP_APM0_REGION3_R1_W_V << LP_APM0_REGION3_R1_W_S)
#define LP_APM0_REGION3_R1_W_V 0x00000001U
#define LP_APM0_REGION3_R1_W_S 5
/** LP_APM0_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 3.
*/
#define LP_APM0_REGION3_R1_R (BIT(6))
#define LP_APM0_REGION3_R1_R_M (LP_APM0_REGION3_R1_R_V << LP_APM0_REGION3_R1_R_S)
#define LP_APM0_REGION3_R1_R_V 0x00000001U
#define LP_APM0_REGION3_R1_R_S 6
/** LP_APM0_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 3.
*/
#define LP_APM0_REGION3_R2_X (BIT(8))
#define LP_APM0_REGION3_R2_X_M (LP_APM0_REGION3_R2_X_V << LP_APM0_REGION3_R2_X_S)
#define LP_APM0_REGION3_R2_X_V 0x00000001U
#define LP_APM0_REGION3_R2_X_S 8
/** LP_APM0_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 3.
*/
#define LP_APM0_REGION3_R2_W (BIT(9))
#define LP_APM0_REGION3_R2_W_M (LP_APM0_REGION3_R2_W_V << LP_APM0_REGION3_R2_W_S)
#define LP_APM0_REGION3_R2_W_V 0x00000001U
#define LP_APM0_REGION3_R2_W_S 9
/** LP_APM0_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 3.
*/
#define LP_APM0_REGION3_R2_R (BIT(10))
#define LP_APM0_REGION3_R2_R_M (LP_APM0_REGION3_R2_R_V << LP_APM0_REGION3_R2_R_S)
#define LP_APM0_REGION3_R2_R_V 0x00000001U
#define LP_APM0_REGION3_R2_R_S 10
/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION3_LOCK (BIT(11))
#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S)
#define LP_APM0_REGION3_LOCK_V 0x00000001U
#define LP_APM0_REGION3_LOCK_S 11
/** LP_APM0_FUNC_CTRL_REG register
* APM function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM0_M0_FUNC_EN (BIT(0))
#define LP_APM0_M0_FUNC_EN_M (LP_APM0_M0_FUNC_EN_V << LP_APM0_M0_FUNC_EN_S)
#define LP_APM0_M0_FUNC_EN_V 0x00000001U
#define LP_APM0_M0_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status
*/
#define LP_APM0_M0_EXCEPTION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_EXCEPTION_STATUS_CLR_M (LP_APM0_M0_EXCEPTION_STATUS_CLR_V << LP_APM0_M0_EXCEPTION_STATUS_CLR_S)
#define LP_APM0_M0_EXCEPTION_STATUS_CLR_V 0x00000001U
#define LP_APM0_M0_EXCEPTION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Represents exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Represents exception id information
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.\\
* 0: disable \\
* 1: enable \\
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
#define LP_APM0_M0_APM_INT_EN_V 0x00000001U
#define LP_APM0_M0_APM_INT_EN_S 0
/** LP_APM0_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
#define LP_APM0_CLK_EN_V 0x00000001U
#define LP_APM0_CLK_EN_S 0
/** LP_APM0_DATE_REG register
* Version control register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)
#define LP_APM0_DATE_V 0x0FFFFFFFU
#define LP_APM0_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n(0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n
*/
uint32_t regionn_addr_start:32;
};
uint32_t val;
} lp_apm0_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} lp_apm0_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_regionn_attr_reg_t;
/** Group: APM function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Represents exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures APM M0 interrupt enable.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_int_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm0_date_reg_t;
typedef struct {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_regionn_addr_start_reg_t region0_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region0_addr_end;
volatile lp_apm0_regionn_attr_reg_t region0_attr;
volatile lp_apm0_regionn_addr_start_reg_t region1_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region1_addr_end;
volatile lp_apm0_regionn_attr_reg_t region1_attr;
volatile lp_apm0_regionn_addr_start_reg_t region2_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region2_addr_end;
volatile lp_apm0_regionn_attr_reg_t region2_attr;
volatile lp_apm0_regionn_addr_start_reg_t region3_addr_start;
volatile lp_apm0_regionn_addr_end_reg_t region3_addr_end;
volatile lp_apm0_regionn_attr_reg_t region3_attr;
uint32_t reserved_034[36];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm0_int_en_reg_t int_en;
volatile lp_apm0_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n (0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 0.
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 0.
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 0.
*/
#define LP_APM_REGION0_R0_X (BIT(0))
#define LP_APM_REGION0_R0_X_M (LP_APM_REGION0_R0_X_V << LP_APM_REGION0_R0_X_S)
#define LP_APM_REGION0_R0_X_V 0x00000001U
#define LP_APM_REGION0_R0_X_S 0
/** LP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 0.
*/
#define LP_APM_REGION0_R0_W (BIT(1))
#define LP_APM_REGION0_R0_W_M (LP_APM_REGION0_R0_W_V << LP_APM_REGION0_R0_W_S)
#define LP_APM_REGION0_R0_W_V 0x00000001U
#define LP_APM_REGION0_R0_W_S 1
/** LP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 0.
*/
#define LP_APM_REGION0_R0_R (BIT(2))
#define LP_APM_REGION0_R0_R_M (LP_APM_REGION0_R0_R_V << LP_APM_REGION0_R0_R_S)
#define LP_APM_REGION0_R0_R_V 0x00000001U
#define LP_APM_REGION0_R0_R_S 2
/** LP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 0.
*/
#define LP_APM_REGION0_R1_X (BIT(4))
#define LP_APM_REGION0_R1_X_M (LP_APM_REGION0_R1_X_V << LP_APM_REGION0_R1_X_S)
#define LP_APM_REGION0_R1_X_V 0x00000001U
#define LP_APM_REGION0_R1_X_S 4
/** LP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 0.
*/
#define LP_APM_REGION0_R1_W (BIT(5))
#define LP_APM_REGION0_R1_W_M (LP_APM_REGION0_R1_W_V << LP_APM_REGION0_R1_W_S)
#define LP_APM_REGION0_R1_W_V 0x00000001U
#define LP_APM_REGION0_R1_W_S 5
/** LP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 0.
*/
#define LP_APM_REGION0_R1_R (BIT(6))
#define LP_APM_REGION0_R1_R_M (LP_APM_REGION0_R1_R_V << LP_APM_REGION0_R1_R_S)
#define LP_APM_REGION0_R1_R_V 0x00000001U
#define LP_APM_REGION0_R1_R_S 6
/** LP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 0.
*/
#define LP_APM_REGION0_R2_X (BIT(8))
#define LP_APM_REGION0_R2_X_M (LP_APM_REGION0_R2_X_V << LP_APM_REGION0_R2_X_S)
#define LP_APM_REGION0_R2_X_V 0x00000001U
#define LP_APM_REGION0_R2_X_S 8
/** LP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 0.
*/
#define LP_APM_REGION0_R2_W (BIT(9))
#define LP_APM_REGION0_R2_W_M (LP_APM_REGION0_R2_W_V << LP_APM_REGION0_R2_W_S)
#define LP_APM_REGION0_R2_W_V 0x00000001U
#define LP_APM_REGION0_R2_W_S 9
/** LP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 0.
*/
#define LP_APM_REGION0_R2_R (BIT(10))
#define LP_APM_REGION0_R2_R_M (LP_APM_REGION0_R2_R_V << LP_APM_REGION0_R2_R_S)
#define LP_APM_REGION0_R2_R_V 0x00000001U
#define LP_APM_REGION0_R2_R_S 10
/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION0_LOCK (BIT(11))
#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S)
#define LP_APM_REGION0_LOCK_V 0x00000001U
#define LP_APM_REGION0_LOCK_S 11
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 1.
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 1.
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 1.
*/
#define LP_APM_REGION1_R0_X (BIT(0))
#define LP_APM_REGION1_R0_X_M (LP_APM_REGION1_R0_X_V << LP_APM_REGION1_R0_X_S)
#define LP_APM_REGION1_R0_X_V 0x00000001U
#define LP_APM_REGION1_R0_X_S 0
/** LP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 1.
*/
#define LP_APM_REGION1_R0_W (BIT(1))
#define LP_APM_REGION1_R0_W_M (LP_APM_REGION1_R0_W_V << LP_APM_REGION1_R0_W_S)
#define LP_APM_REGION1_R0_W_V 0x00000001U
#define LP_APM_REGION1_R0_W_S 1
/** LP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 1.
*/
#define LP_APM_REGION1_R0_R (BIT(2))
#define LP_APM_REGION1_R0_R_M (LP_APM_REGION1_R0_R_V << LP_APM_REGION1_R0_R_S)
#define LP_APM_REGION1_R0_R_V 0x00000001U
#define LP_APM_REGION1_R0_R_S 2
/** LP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 1.
*/
#define LP_APM_REGION1_R1_X (BIT(4))
#define LP_APM_REGION1_R1_X_M (LP_APM_REGION1_R1_X_V << LP_APM_REGION1_R1_X_S)
#define LP_APM_REGION1_R1_X_V 0x00000001U
#define LP_APM_REGION1_R1_X_S 4
/** LP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 1.
*/
#define LP_APM_REGION1_R1_W (BIT(5))
#define LP_APM_REGION1_R1_W_M (LP_APM_REGION1_R1_W_V << LP_APM_REGION1_R1_W_S)
#define LP_APM_REGION1_R1_W_V 0x00000001U
#define LP_APM_REGION1_R1_W_S 5
/** LP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 1.
*/
#define LP_APM_REGION1_R1_R (BIT(6))
#define LP_APM_REGION1_R1_R_M (LP_APM_REGION1_R1_R_V << LP_APM_REGION1_R1_R_S)
#define LP_APM_REGION1_R1_R_V 0x00000001U
#define LP_APM_REGION1_R1_R_S 6
/** LP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 1.
*/
#define LP_APM_REGION1_R2_X (BIT(8))
#define LP_APM_REGION1_R2_X_M (LP_APM_REGION1_R2_X_V << LP_APM_REGION1_R2_X_S)
#define LP_APM_REGION1_R2_X_V 0x00000001U
#define LP_APM_REGION1_R2_X_S 8
/** LP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 1.
*/
#define LP_APM_REGION1_R2_W (BIT(9))
#define LP_APM_REGION1_R2_W_M (LP_APM_REGION1_R2_W_V << LP_APM_REGION1_R2_W_S)
#define LP_APM_REGION1_R2_W_V 0x00000001U
#define LP_APM_REGION1_R2_W_S 9
/** LP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 1.
*/
#define LP_APM_REGION1_R2_R (BIT(10))
#define LP_APM_REGION1_R2_R_M (LP_APM_REGION1_R2_R_V << LP_APM_REGION1_R2_R_S)
#define LP_APM_REGION1_R2_R_V 0x00000001U
#define LP_APM_REGION1_R2_R_S 10
/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION1_LOCK (BIT(11))
#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S)
#define LP_APM_REGION1_LOCK_V 0x00000001U
#define LP_APM_REGION1_LOCK_S 11
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 2.
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 2.
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 2.
*/
#define LP_APM_REGION2_R0_X (BIT(0))
#define LP_APM_REGION2_R0_X_M (LP_APM_REGION2_R0_X_V << LP_APM_REGION2_R0_X_S)
#define LP_APM_REGION2_R0_X_V 0x00000001U
#define LP_APM_REGION2_R0_X_S 0
/** LP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 2.
*/
#define LP_APM_REGION2_R0_W (BIT(1))
#define LP_APM_REGION2_R0_W_M (LP_APM_REGION2_R0_W_V << LP_APM_REGION2_R0_W_S)
#define LP_APM_REGION2_R0_W_V 0x00000001U
#define LP_APM_REGION2_R0_W_S 1
/** LP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 2.
*/
#define LP_APM_REGION2_R0_R (BIT(2))
#define LP_APM_REGION2_R0_R_M (LP_APM_REGION2_R0_R_V << LP_APM_REGION2_R0_R_S)
#define LP_APM_REGION2_R0_R_V 0x00000001U
#define LP_APM_REGION2_R0_R_S 2
/** LP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 2.
*/
#define LP_APM_REGION2_R1_X (BIT(4))
#define LP_APM_REGION2_R1_X_M (LP_APM_REGION2_R1_X_V << LP_APM_REGION2_R1_X_S)
#define LP_APM_REGION2_R1_X_V 0x00000001U
#define LP_APM_REGION2_R1_X_S 4
/** LP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 2.
*/
#define LP_APM_REGION2_R1_W (BIT(5))
#define LP_APM_REGION2_R1_W_M (LP_APM_REGION2_R1_W_V << LP_APM_REGION2_R1_W_S)
#define LP_APM_REGION2_R1_W_V 0x00000001U
#define LP_APM_REGION2_R1_W_S 5
/** LP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 2.
*/
#define LP_APM_REGION2_R1_R (BIT(6))
#define LP_APM_REGION2_R1_R_M (LP_APM_REGION2_R1_R_V << LP_APM_REGION2_R1_R_S)
#define LP_APM_REGION2_R1_R_V 0x00000001U
#define LP_APM_REGION2_R1_R_S 6
/** LP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 2.
*/
#define LP_APM_REGION2_R2_X (BIT(8))
#define LP_APM_REGION2_R2_X_M (LP_APM_REGION2_R2_X_V << LP_APM_REGION2_R2_X_S)
#define LP_APM_REGION2_R2_X_V 0x00000001U
#define LP_APM_REGION2_R2_X_S 8
/** LP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 2.
*/
#define LP_APM_REGION2_R2_W (BIT(9))
#define LP_APM_REGION2_R2_W_M (LP_APM_REGION2_R2_W_V << LP_APM_REGION2_R2_W_S)
#define LP_APM_REGION2_R2_W_V 0x00000001U
#define LP_APM_REGION2_R2_W_S 9
/** LP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 2.
*/
#define LP_APM_REGION2_R2_R (BIT(10))
#define LP_APM_REGION2_R2_R_M (LP_APM_REGION2_R2_R_V << LP_APM_REGION2_R2_R_S)
#define LP_APM_REGION2_R2_R_V 0x00000001U
#define LP_APM_REGION2_R2_R_S 10
/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION2_LOCK (BIT(11))
#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S)
#define LP_APM_REGION2_LOCK_V 0x00000001U
#define LP_APM_REGION2_LOCK_S 11
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region 3.
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region 3.
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region 3.
*/
#define LP_APM_REGION3_R0_X (BIT(0))
#define LP_APM_REGION3_R0_X_M (LP_APM_REGION3_R0_X_V << LP_APM_REGION3_R0_X_S)
#define LP_APM_REGION3_R0_X_V 0x00000001U
#define LP_APM_REGION3_R0_X_S 0
/** LP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region 3.
*/
#define LP_APM_REGION3_R0_W (BIT(1))
#define LP_APM_REGION3_R0_W_M (LP_APM_REGION3_R0_W_V << LP_APM_REGION3_R0_W_S)
#define LP_APM_REGION3_R0_W_V 0x00000001U
#define LP_APM_REGION3_R0_W_S 1
/** LP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region 3.
*/
#define LP_APM_REGION3_R0_R (BIT(2))
#define LP_APM_REGION3_R0_R_M (LP_APM_REGION3_R0_R_V << LP_APM_REGION3_R0_R_S)
#define LP_APM_REGION3_R0_R_V 0x00000001U
#define LP_APM_REGION3_R0_R_S 2
/** LP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region 3.
*/
#define LP_APM_REGION3_R1_X (BIT(4))
#define LP_APM_REGION3_R1_X_M (LP_APM_REGION3_R1_X_V << LP_APM_REGION3_R1_X_S)
#define LP_APM_REGION3_R1_X_V 0x00000001U
#define LP_APM_REGION3_R1_X_S 4
/** LP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region 3.
*/
#define LP_APM_REGION3_R1_W (BIT(5))
#define LP_APM_REGION3_R1_W_M (LP_APM_REGION3_R1_W_V << LP_APM_REGION3_R1_W_S)
#define LP_APM_REGION3_R1_W_V 0x00000001U
#define LP_APM_REGION3_R1_W_S 5
/** LP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region 3.
*/
#define LP_APM_REGION3_R1_R (BIT(6))
#define LP_APM_REGION3_R1_R_M (LP_APM_REGION3_R1_R_V << LP_APM_REGION3_R1_R_S)
#define LP_APM_REGION3_R1_R_V 0x00000001U
#define LP_APM_REGION3_R1_R_S 6
/** LP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region 3.
*/
#define LP_APM_REGION3_R2_X (BIT(8))
#define LP_APM_REGION3_R2_X_M (LP_APM_REGION3_R2_X_V << LP_APM_REGION3_R2_X_S)
#define LP_APM_REGION3_R2_X_V 0x00000001U
#define LP_APM_REGION3_R2_X_S 8
/** LP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region 3.
*/
#define LP_APM_REGION3_R2_W (BIT(9))
#define LP_APM_REGION3_R2_W_M (LP_APM_REGION3_R2_W_V << LP_APM_REGION3_R2_W_S)
#define LP_APM_REGION3_R2_W_V 0x00000001U
#define LP_APM_REGION3_R2_W_S 9
/** LP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region 3.
*/
#define LP_APM_REGION3_R2_R (BIT(10))
#define LP_APM_REGION3_R2_R_M (LP_APM_REGION3_R2_R_V << LP_APM_REGION3_R2_R_S)
#define LP_APM_REGION3_R2_R_V 0x00000001U
#define LP_APM_REGION3_R2_R_S 10
/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION3_LOCK (BIT(11))
#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S)
#define LP_APM_REGION3_LOCK_V 0x00000001U
#define LP_APM_REGION3_LOCK_S 11
/** LP_APM_FUNC_CTRL_REG register
* APM function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_FUNC_EN (BIT(0))
#define LP_APM_M0_FUNC_EN_M (LP_APM_M0_FUNC_EN_V << LP_APM_M0_FUNC_EN_S)
#define LP_APM_M0_FUNC_EN_V 0x00000001U
#define LP_APM_M0_FUNC_EN_S 0
/** LP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
#define LP_APM_M1_FUNC_EN (BIT(1))
#define LP_APM_M1_FUNC_EN_M (LP_APM_M1_FUNC_EN_V << LP_APM_M1_FUNC_EN_S)
#define LP_APM_M1_FUNC_EN_V 0x00000001U
#define LP_APM_M1_FUNC_EN_S 1
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
#define LP_APM_M0_EXCEPTION_STATUS_CLR (BIT(0))
#define LP_APM_M0_EXCEPTION_STATUS_CLR_M (LP_APM_M0_EXCEPTION_STATUS_CLR_V << LP_APM_M0_EXCEPTION_STATUS_CLR_S)
#define LP_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_EXCEPTION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Represents exception region.
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_M1_STATUS_REG register
* M1 status register
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_S 0
/** LP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
#define LP_APM_M1_EXCEPTION_STATUS_CLR (BIT(0))
#define LP_APM_M1_EXCEPTION_STATUS_CLR_M (LP_APM_M1_EXCEPTION_STATUS_CLR_V << LP_APM_M1_EXCEPTION_STATUS_CLR_S)
#define LP_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U
#define LP_APM_M1_EXCEPTION_STATUS_CLR_S 0
/** LP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Represents exception region.
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
#define LP_APM_M1_EXCEPTION_MODE 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_S 16
/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
#define LP_APM_M1_EXCEPTION_ID 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_S 18
/** LP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
#define LP_APM_M1_APM_INT_EN_V 0x00000001U
#define LP_APM_M1_APM_INT_EN_S 1
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version control register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664;
* Version control register.
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Configure bit $n (0-3) to enable region $n.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:32;
};
uint32_t val;
} lp_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:32;
};
uint32_t val;
} lp_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.\\
* bit0: 1 represents authority_exception \\
* bit1: 1 represents space_exception \\
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.\\
* 0: disable \\
* 1: enable \\
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_regionn_addr_start_reg_t region0_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region0_addr_end;
volatile lp_apm_regionn_attr_reg_t region0_attr;
volatile lp_apm_regionn_addr_start_reg_t region1_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region1_addr_end;
volatile lp_apm_regionn_attr_reg_t region1_attr;
volatile lp_apm_regionn_addr_start_reg_t region2_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region2_addr_end;
volatile lp_apm_regionn_attr_reg_t region2_attr;
volatile lp_apm_regionn_addr_start_reg_t region3_addr_start;
volatile lp_apm_regionn_addr_end_reg_t region3_addr_end;
volatile lp_apm_regionn_attr_reg_t region3_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_m1_status_reg_t m1_status;
volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0f0[3];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/lp_clkrst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* Configures the root clk of LP system
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* Configures the source of LP_SLOW_CLK.
* 0: RC_SLOW_CLK
* 1: XTAL32K_CLK
* 2: RC32K_CLK
* 3:OSC_SLOW_CLK
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
* configures the source of LP_FAST_CLK.
* 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
* 2: XTAL_CLK
*/
#define LP_CLKRST_FAST_CLK_SEL 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
* reserved
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 4
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* Configures the clk gate to pad
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* Configures the clock gate to pad of the LP_DYN_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* Configures the clock gate to pad of the OSC_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* Configures the clock gate to pad of the RC_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* Configures the clock gate to pad of the RC32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* Configures the clock gate to pad of the XTAL32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* Configures the clock gate to pad of the EFUSE_CTRL clock.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* Configures the clock gate to pad of the LP_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* Configures the clock gate to pad of the LP_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* Configures the clock gate to pad of the RNG clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* Configures the clock gate to pad of the LP bus clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* Configure LP root clk source gate
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* Configures the clock gate to LP_FAST_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* Configures the peri of LP system software reset
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0;
* Configures whether or not to reset HUK
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_HUK_RESET_EN (BIT(27))
#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S)
#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U
#define LP_CLKRST_HUK_RESET_EN_S 27
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* Configures whether or not to reset EFUSE_CTRL always-on part
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* Configures whether or not to reset LP_TIMER
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* Configures whether or not to reset LP_WDT and super watch dog
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not to reset analog peri, include brownout controller
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CAUSE_REG register
* Represents the reset casue
*/
#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
#define LP_CLKRST_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_RESET_REG register
* Configures CPU reset
*/
#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21))
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21
/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_S 26
/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
#define LP_CLKRST_CPU_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* Configures the RC_FAST_CLK frequency
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
* Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
* field
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_RC32K_CNTL_REG register
* Configures the RC32K_CLK frequency
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* Configures the RC32K_CLK frequency, the clock frequency will increase with this
* field
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* Configures the clk gate of LP clk to HP system
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* Configures the clk gate of XTAL32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* Configures the clk gate of RC_SLOW_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* Configures the clk gate of RC32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* Configures the clk gate of RC_FAST_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* Configures the LP_MEM clk gate force parameter
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether ot not force open the clock gate of LP MEM
* 0: Invalid. The clock gate controlled by hardware FSM
* 1: Force open clock gate of LP MEM
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_LPPERI_REG register
* Configures the LP peri clk
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1;
* Configures the source clk of HUK
* 0: 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
#define LP_CLKRST_HUK_CLK_SEL (BIT(29))
#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S)
#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U
#define LP_CLKRST_HUK_CLK_SEL_S 29
/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
* Configures the source clk of LP I2C.
* 0: LP_FAST_CLK
* 1: XTAL_D2_CLK
*/
#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30))
#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_I2C_CLK_SEL_S 30
/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
* Configures the source clk of LP UART.
* 0: LP_FAST_CLK
* 1: XTAL_D2_CLK
*/
#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31))
#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_UART_CLK_SEL_S 31
/** LP_CLKRST_XTAL32K_REG register
* Configures the XTAL32K parameter
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* Configures DRES
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* Configures DGM
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* Configures DBUF
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* Configures DAC
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* Version control register
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768;
* Version control register
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* configure register clk bypass clk gate
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/lp_clkrst_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* Configures the root clk of LP system
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* Configures the source of LP_SLOW_CLK.
* 0: RC_SLOW_CLK
* 1: XTAL32K_CLK
* 2: RC32K_CLK
* 3:OSC_SLOW_CLK
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
* configures the source of LP_FAST_CLK.
* 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
* 2: XTAL_CLK
*/
uint32_t fast_clk_sel:2;
/** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
* reserved
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* Configures the clk gate to pad
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* Configures the clock gate to pad of the LP_DYN_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* Configures the clock gate to pad of the OSC_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* Configures the clock gate to pad of the RC_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* Configures the clock gate to pad of the RC32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* Configures the clock gate to pad of the XTAL32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* Configures the clock gate to pad of the EFUSE_CTRL clock.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* Configures the clock gate to pad of the LP_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* Configures the clock gate to pad of the LP_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* Configures the clock gate to pad of the RNG clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* Configures the clock gate to pad of the LP bus clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* Configure LP root clk source gate
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* Configures the clock gate to LP_FAST_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* Configures the peri of LP system software reset
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** huk_reset_en : R/W; bitpos: [27]; default: 0;
* Configures whether or not to reset HUK
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t huk_reset_en:1;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* Configures whether or not to reset EFUSE_CTRL always-on part
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to reset LP_TIMER
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* Configures whether or not to reset LP_WDT and super watch dog
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not to reset analog peri, include brownout controller
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* Represents the reset casue
*/
typedef union {
struct {
/** reset_cause : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
uint32_t reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_cause_reg_t;
/** Type of cpu_reset register
* Configures CPU reset
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
uint32_t hpcore0_lockup_reset_en:1;
/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t rtc_wdt_cpu_reset_length:3;
/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
uint32_t rtc_wdt_cpu_reset_en:1;
/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t cpu_stall_wait:5;
/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
uint32_t cpu_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_reset_reg_t;
/** Type of fosc_cntl register
* Configures the RC_FAST_CLK frequency
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
* field
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* Configures the RC32K_CLK frequency
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* Configures the RC32K_CLK frequency, the clock frequency will increase with this
* field
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* Configures the clk gate of LP clk to HP system
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* Configures the clk gate of XTAL32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* Configures the clk gate of RC_SLOW_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* Configures the clk gate of RC32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* Configures the clk gate of RC_FAST_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* Configures the LP_MEM clk gate force parameter
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether ot not force open the clock gate of LP MEM
* 0: Invalid. The clock gate controlled by hardware FSM
* 1: Force open clock gate of LP MEM
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of lpperi register
* Configures the LP peri clk
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** huk_clk_sel : R/W; bitpos: [29]; default: 1;
* Configures the source clk of HUK
* 0: 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
uint32_t huk_clk_sel:1;
/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
* Configures the source clk of LP I2C.
* 0: LP_FAST_CLK
* 1: XTAL_D2_CLK
*/
uint32_t lp_i2c_clk_sel:1;
/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
* Configures the source clk of LP UART.
* 0: LP_FAST_CLK
* 1: XTAL_D2_CLK
*/
uint32_t lp_uart_clk_sel:1;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of xtal32k register
* Configures the XTAL32K parameter
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* Configures DRES
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* Configures DGM
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* Configures DBUF
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* Configures DAC
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 36720768;
* Version control register
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* configure register clk bypass clk gate
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_cause_reg_t reset_cause;
volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_GPIO_OUT_REG register
* LP GPIO output register
*/
#define LP_GPIO_OUT_REG (DR_REG_LP_GPIO_BASE + 0x4)
/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the output of GPIO0 ~ GPIO7.\\
* 0: Low level\\
* 1: High level\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
#define LP_GPIO_OUT_DATA_ORIG 0x000000FFU
#define LP_GPIO_OUT_DATA_ORIG_M (LP_GPIO_OUT_DATA_ORIG_V << LP_GPIO_OUT_DATA_ORIG_S)
#define LP_GPIO_OUT_DATA_ORIG_V 0x000000FFU
#define LP_GPIO_OUT_DATA_ORIG_S 0
/** LP_GPIO_OUT_W1TS_REG register
* LP GPIO output set register
*/
#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x8)
/** LP_GPIO_OUT_W1TS : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be set to 1.
* - Recommended operation: use this register to set LP_IO_OUT_REG.
*/
#define LP_GPIO_OUT_W1TS 0x000000FFU
#define LP_GPIO_OUT_W1TS_M (LP_GPIO_OUT_W1TS_V << LP_GPIO_OUT_W1TS_S)
#define LP_GPIO_OUT_W1TS_V 0x000000FFU
#define LP_GPIO_OUT_W1TS_S 0
/** LP_GPIO_OUT_W1TC_REG register
* LP GPIO output clear register
*/
#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_GPIO_BASE + 0xc)
/** LP_GPIO_OUT_W1TC : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be cleared.
* - Recommended operation: use this register to clear LP_IO_OUT_REG.
*/
#define LP_GPIO_OUT_W1TC 0x000000FFU
#define LP_GPIO_OUT_W1TC_M (LP_GPIO_OUT_W1TC_V << LP_GPIO_OUT_W1TC_S)
#define LP_GPIO_OUT_W1TC_V 0x000000FFU
#define LP_GPIO_OUT_W1TC_S 0
/** LP_GPIO_ENABLE_REG register
* LP GPIO output enable register
*/
#define LP_GPIO_ENABLE_REG (DR_REG_LP_GPIO_BASE + 0x10)
/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\
* 0: Not enable\\
* 1: Enable\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
#define LP_GPIO_ENABLE_DATA 0x000000FFU
#define LP_GPIO_ENABLE_DATA_M (LP_GPIO_ENABLE_DATA_V << LP_GPIO_ENABLE_DATA_S)
#define LP_GPIO_ENABLE_DATA_V 0x000000FFU
#define LP_GPIO_ENABLE_DATA_S 0
/** LP_GPIO_ENABLE_W1TS_REG register
* LP GPIO output enable set register
*/
#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x14)
/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be set to 1.
* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
*/
#define LP_GPIO_ENABLE_W1TS 0x000000FFU
#define LP_GPIO_ENABLE_W1TS_M (LP_GPIO_ENABLE_W1TS_V << LP_GPIO_ENABLE_W1TS_S)
#define LP_GPIO_ENABLE_W1TS_V 0x000000FFU
#define LP_GPIO_ENABLE_W1TS_S 0
/** LP_GPIO_ENABLE_W1TC_REG register
* LP GPIO output enable clear register
*/
#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x18)
/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be cleared.
* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
*/
#define LP_GPIO_ENABLE_W1TC 0x000000FFU
#define LP_GPIO_ENABLE_W1TC_M (LP_GPIO_ENABLE_W1TC_V << LP_GPIO_ENABLE_W1TC_S)
#define LP_GPIO_ENABLE_W1TC_V 0x000000FFU
#define LP_GPIO_ENABLE_W1TC_S 0
/** LP_GPIO_IN_REG register
* LP GPIO input register
*/
#define LP_GPIO_IN_REG (DR_REG_LP_GPIO_BASE + 0x1c)
/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0;
* Represents the input value of GPIO0 ~ GPIO7.\\
* 0: Low level input\\
* 1: High level input\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
#define LP_GPIO_IN_DATA_NEXT 0x000000FFU
#define LP_GPIO_IN_DATA_NEXT_M (LP_GPIO_IN_DATA_NEXT_V << LP_GPIO_IN_DATA_NEXT_S)
#define LP_GPIO_IN_DATA_NEXT_V 0x000000FFU
#define LP_GPIO_IN_DATA_NEXT_S 0
/** LP_GPIO_STATUS_REG register
* LP GPIO interrupt status register
*/
#define LP_GPIO_STATUS_REG (DR_REG_LP_GPIO_BASE + 0x20)
/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the interrupt status of GPIO0 ~ GPIO7.\\
* 0: No interrupt\\
* 1: Interrupt is triggered\\
* Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This
* register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\
*/
#define LP_GPIO_STATUS_INTERRUPT 0x000000FFU
#define LP_GPIO_STATUS_INTERRUPT_M (LP_GPIO_STATUS_INTERRUPT_V << LP_GPIO_STATUS_INTERRUPT_S)
#define LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU
#define LP_GPIO_STATUS_INTERRUPT_S 0
/** LP_GPIO_STATUS_W1TS_REG register
* LP GPIO interrupt status set register
*/
#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x24)
/** LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
* GPIO0 ~ GPIO7.\\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be set to 1.
* - Recommended operation: use this register to set LP_IO_STATUS_INT.
*/
#define LP_GPIO_STATUS_W1TS 0x000000FFU
#define LP_GPIO_STATUS_W1TS_M (LP_GPIO_STATUS_W1TS_V << LP_GPIO_STATUS_W1TS_S)
#define LP_GPIO_STATUS_W1TS_V 0x000000FFU
#define LP_GPIO_STATUS_W1TS_S 0
/** LP_GPIO_STATUS_W1TC_REG register
* LP GPIO interrupt status clear register
*/
#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x28)
/** LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
* of GPIO0 ~ GPIO7. \\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be cleared
* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
*/
#define LP_GPIO_STATUS_W1TC 0x000000FFU
#define LP_GPIO_STATUS_W1TC_M (LP_GPIO_STATUS_W1TC_V << LP_GPIO_STATUS_W1TC_S)
#define LP_GPIO_STATUS_W1TC_V 0x000000FFU
#define LP_GPIO_STATUS_W1TC_S 0
/** LP_GPIO_STATUS_NEXT_REG register
* LP GPIO interrupt source register
*/
#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_GPIO_BASE + 0x2c)
/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0;
* Represents the interrupt source status of GPIO0 ~ GPIO7.\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\
* 0: Interrupt source status is invalid.\\
* 1: Interrupt source status is valid.\\
* The interrupt here can be rising-edge triggered, falling-edge triggered, any edge
* triggered, or level triggered.\\
*/
#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x000000FFU
#define LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_STATUS_INTERRUPT_NEXT_S)
#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x000000FFU
#define LP_GPIO_STATUS_INTERRUPT_NEXT_S 0
/** LP_GPIO_PIN0_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN0_REG (DR_REG_LP_GPIO_BASE + 0x30)
/** LP_GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN0_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN0_SYNC2_BYPASS_M (LP_GPIO_PIN0_SYNC2_BYPASS_V << LP_GPIO_PIN0_SYNC2_BYPASS_S)
#define LP_GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN0_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO0.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN0_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_PIN0_PAD_DRIVER_S)
#define LP_GPIO_PIN0_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN0_PAD_DRIVER_S 2
/** LP_GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN0_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN0_SYNC1_BYPASS_M (LP_GPIO_PIN0_SYNC1_BYPASS_V << LP_GPIO_PIN0_SYNC1_BYPASS_S)
#define LP_GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN0_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO0 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN0_INT_TYPE 0x00000007U
#define LP_GPIO_PIN0_INT_TYPE_M (LP_GPIO_PIN0_INT_TYPE_V << LP_GPIO_PIN0_INT_TYPE_S)
#define LP_GPIO_PIN0_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN0_INT_TYPE_S 7
/** LP_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO0 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_PIN0_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN0_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN1_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN1_REG (DR_REG_LP_GPIO_BASE + 0x34)
/** LP_GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN1_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN1_SYNC2_BYPASS_M (LP_GPIO_PIN1_SYNC2_BYPASS_V << LP_GPIO_PIN1_SYNC2_BYPASS_S)
#define LP_GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN1_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO1.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN1_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_PIN1_PAD_DRIVER_S)
#define LP_GPIO_PIN1_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN1_PAD_DRIVER_S 2
/** LP_GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN1_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN1_SYNC1_BYPASS_M (LP_GPIO_PIN1_SYNC1_BYPASS_V << LP_GPIO_PIN1_SYNC1_BYPASS_S)
#define LP_GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN1_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN1_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO1 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN1_INT_TYPE 0x00000007U
#define LP_GPIO_PIN1_INT_TYPE_M (LP_GPIO_PIN1_INT_TYPE_V << LP_GPIO_PIN1_INT_TYPE_S)
#define LP_GPIO_PIN1_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN1_INT_TYPE_S 7
/** LP_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO1 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_PIN1_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN1_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN2_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN2_REG (DR_REG_LP_GPIO_BASE + 0x38)
/** LP_GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN2_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN2_SYNC2_BYPASS_M (LP_GPIO_PIN2_SYNC2_BYPASS_V << LP_GPIO_PIN2_SYNC2_BYPASS_S)
#define LP_GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN2_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO2.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN2_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_PIN2_PAD_DRIVER_S)
#define LP_GPIO_PIN2_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN2_PAD_DRIVER_S 2
/** LP_GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN2_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN2_SYNC1_BYPASS_M (LP_GPIO_PIN2_SYNC1_BYPASS_V << LP_GPIO_PIN2_SYNC1_BYPASS_S)
#define LP_GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN2_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN2_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO2 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN2_INT_TYPE 0x00000007U
#define LP_GPIO_PIN2_INT_TYPE_M (LP_GPIO_PIN2_INT_TYPE_V << LP_GPIO_PIN2_INT_TYPE_S)
#define LP_GPIO_PIN2_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN2_INT_TYPE_S 7
/** LP_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO2 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_PIN2_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN2_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN3_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN3_REG (DR_REG_LP_GPIO_BASE + 0x3c)
/** LP_GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN3_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN3_SYNC2_BYPASS_M (LP_GPIO_PIN3_SYNC2_BYPASS_V << LP_GPIO_PIN3_SYNC2_BYPASS_S)
#define LP_GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN3_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO3.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN3_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_PIN3_PAD_DRIVER_S)
#define LP_GPIO_PIN3_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN3_PAD_DRIVER_S 2
/** LP_GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN3_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN3_SYNC1_BYPASS_M (LP_GPIO_PIN3_SYNC1_BYPASS_V << LP_GPIO_PIN3_SYNC1_BYPASS_S)
#define LP_GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN3_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN3_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO3 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN3_INT_TYPE 0x00000007U
#define LP_GPIO_PIN3_INT_TYPE_M (LP_GPIO_PIN3_INT_TYPE_V << LP_GPIO_PIN3_INT_TYPE_S)
#define LP_GPIO_PIN3_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN3_INT_TYPE_S 7
/** LP_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO3 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_PIN3_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN3_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN4_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN4_REG (DR_REG_LP_GPIO_BASE + 0x40)
/** LP_GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN4_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN4_SYNC2_BYPASS_M (LP_GPIO_PIN4_SYNC2_BYPASS_V << LP_GPIO_PIN4_SYNC2_BYPASS_S)
#define LP_GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN4_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO4.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN4_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_PIN4_PAD_DRIVER_S)
#define LP_GPIO_PIN4_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN4_PAD_DRIVER_S 2
/** LP_GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN4_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN4_SYNC1_BYPASS_M (LP_GPIO_PIN4_SYNC1_BYPASS_V << LP_GPIO_PIN4_SYNC1_BYPASS_S)
#define LP_GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN4_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN4_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO4 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN4_INT_TYPE 0x00000007U
#define LP_GPIO_PIN4_INT_TYPE_M (LP_GPIO_PIN4_INT_TYPE_V << LP_GPIO_PIN4_INT_TYPE_S)
#define LP_GPIO_PIN4_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN4_INT_TYPE_S 7
/** LP_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO4 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_PIN4_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN4_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN5_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN5_REG (DR_REG_LP_GPIO_BASE + 0x44)
/** LP_GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN5_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN5_SYNC2_BYPASS_M (LP_GPIO_PIN5_SYNC2_BYPASS_V << LP_GPIO_PIN5_SYNC2_BYPASS_S)
#define LP_GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN5_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO5.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN5_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_PIN5_PAD_DRIVER_S)
#define LP_GPIO_PIN5_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN5_PAD_DRIVER_S 2
/** LP_GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN5_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN5_SYNC1_BYPASS_M (LP_GPIO_PIN5_SYNC1_BYPASS_V << LP_GPIO_PIN5_SYNC1_BYPASS_S)
#define LP_GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN5_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN5_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO5 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN5_INT_TYPE 0x00000007U
#define LP_GPIO_PIN5_INT_TYPE_M (LP_GPIO_PIN5_INT_TYPE_V << LP_GPIO_PIN5_INT_TYPE_S)
#define LP_GPIO_PIN5_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN5_INT_TYPE_S 7
/** LP_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO5 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_PIN5_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN5_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN6_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN6_REG (DR_REG_LP_GPIO_BASE + 0x48)
/** LP_GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN6_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN6_SYNC2_BYPASS_M (LP_GPIO_PIN6_SYNC2_BYPASS_V << LP_GPIO_PIN6_SYNC2_BYPASS_S)
#define LP_GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN6_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO6.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN6_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN6_PAD_DRIVER_M (LP_GPIO_PIN6_PAD_DRIVER_V << LP_GPIO_PIN6_PAD_DRIVER_S)
#define LP_GPIO_PIN6_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN6_PAD_DRIVER_S 2
/** LP_GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN6_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN6_SYNC1_BYPASS_M (LP_GPIO_PIN6_SYNC1_BYPASS_V << LP_GPIO_PIN6_SYNC1_BYPASS_S)
#define LP_GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN6_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN6_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO6 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN6_INT_TYPE 0x00000007U
#define LP_GPIO_PIN6_INT_TYPE_M (LP_GPIO_PIN6_INT_TYPE_V << LP_GPIO_PIN6_INT_TYPE_S)
#define LP_GPIO_PIN6_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN6_INT_TYPE_S 7
/** LP_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO6 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN6_WAKEUP_ENABLE_M (LP_GPIO_PIN6_WAKEUP_ENABLE_V << LP_GPIO_PIN6_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN6_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN7_REG register
* LP GPIO0 configuration register
*/
#define LP_GPIO_PIN7_REG (DR_REG_LP_GPIO_BASE + 0x4c)
/** LP_GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN7_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN7_SYNC2_BYPASS_M (LP_GPIO_PIN7_SYNC2_BYPASS_V << LP_GPIO_PIN7_SYNC2_BYPASS_S)
#define LP_GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN7_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIO7.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
#define LP_GPIO_PIN7_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN7_PAD_DRIVER_M (LP_GPIO_PIN7_PAD_DRIVER_V << LP_GPIO_PIN7_PAD_DRIVER_S)
#define LP_GPIO_PIN7_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN7_PAD_DRIVER_S 2
/** LP_GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define LP_GPIO_PIN7_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN7_SYNC1_BYPASS_M (LP_GPIO_PIN7_SYNC1_BYPASS_V << LP_GPIO_PIN7_SYNC1_BYPASS_S)
#define LP_GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN7_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN7_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN7_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN7_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN7_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO7 interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
#define LP_GPIO_PIN7_INT_TYPE 0x00000007U
#define LP_GPIO_PIN7_INT_TYPE_M (LP_GPIO_PIN7_INT_TYPE_V << LP_GPIO_PIN7_INT_TYPE_S)
#define LP_GPIO_PIN7_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN7_INT_TYPE_S 7
/** LP_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO7 wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
#define LP_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN7_WAKEUP_ENABLE_M (LP_GPIO_PIN7_WAKEUP_ENABLE_V << LP_GPIO_PIN7_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN7_WAKEUP_ENABLE_S 10
/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b0)
/** LP_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC0_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_FUNC0_OUT_INV_SEL_S)
#define LP_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC0_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC0_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_FUNC0_OE_INV_SEL_S)
#define LP_GPIO_FUNC0_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC0_OE_INV_SEL_S 2
/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b4)
/** LP_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC1_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_FUNC1_OUT_INV_SEL_S)
#define LP_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC1_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC1_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_FUNC1_OE_INV_SEL_S)
#define LP_GPIO_FUNC1_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC1_OE_INV_SEL_S 2
/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b8)
/** LP_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC2_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_FUNC2_OUT_INV_SEL_S)
#define LP_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC2_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC2_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_FUNC2_OE_INV_SEL_S)
#define LP_GPIO_FUNC2_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC2_OE_INV_SEL_S 2
/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2bc)
/** LP_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC3_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_FUNC3_OUT_INV_SEL_S)
#define LP_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC3_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC3_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_FUNC3_OE_INV_SEL_S)
#define LP_GPIO_FUNC3_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC3_OE_INV_SEL_S 2
/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c0)
/** LP_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC4_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_FUNC4_OUT_INV_SEL_S)
#define LP_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC4_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC4_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_FUNC4_OE_INV_SEL_S)
#define LP_GPIO_FUNC4_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC4_OE_INV_SEL_S 2
/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c4)
/** LP_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC5_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_FUNC5_OUT_INV_SEL_S)
#define LP_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC5_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC5_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_FUNC5_OE_INV_SEL_S)
#define LP_GPIO_FUNC5_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC5_OE_INV_SEL_S 2
/** LP_GPIO_FUNC6_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c8)
/** LP_GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC6_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC6_OUT_INV_SEL_M (LP_GPIO_FUNC6_OUT_INV_SEL_V << LP_GPIO_FUNC6_OUT_INV_SEL_S)
#define LP_GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC6_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC6_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC6_OE_INV_SEL_M (LP_GPIO_FUNC6_OE_INV_SEL_V << LP_GPIO_FUNC6_OE_INV_SEL_S)
#define LP_GPIO_FUNC6_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC6_OE_INV_SEL_S 2
/** LP_GPIO_FUNC7_OUT_SEL_CFG_REG register
* Configuration register for GPIO0 output
*/
#define LP_GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2cc)
/** LP_GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC7_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC7_OUT_INV_SEL_M (LP_GPIO_FUNC7_OUT_INV_SEL_V << LP_GPIO_FUNC7_OUT_INV_SEL_S)
#define LP_GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC7_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define LP_GPIO_FUNC7_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC7_OE_INV_SEL_M (LP_GPIO_FUNC7_OE_INV_SEL_V << LP_GPIO_FUNC7_OE_INV_SEL_S)
#define LP_GPIO_FUNC7_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC7_OE_INV_SEL_S 2
/** LP_GPIO_CLOCK_GATE_REG register
* GPIO clock gate register
*/
#define LP_GPIO_CLOCK_GATE_REG (DR_REG_LP_GPIO_BASE + 0x3f8)
/** LP_GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate.\\
*/
#define LP_GPIO_CLK_EN (BIT(0))
#define LP_GPIO_CLK_EN_M (LP_GPIO_CLK_EN_V << LP_GPIO_CLK_EN_S)
#define LP_GPIO_CLK_EN_V 0x00000001U
#define LP_GPIO_CLK_EN_S 0
/** LP_GPIO_DATE_REG register
* GPIO version register
*/
#define LP_GPIO_DATE_REG (DR_REG_LP_GPIO_BASE + 0x3fc)
/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 36773904;
* version register.\\
*/
#define LP_GPIO_DATE 0x0FFFFFFFU
#define LP_GPIO_DATE_M (LP_GPIO_DATE_V << LP_GPIO_DATE_S)
#define LP_GPIO_DATE_V 0x0FFFFFFFU
#define LP_GPIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of out register
* LP GPIO output register
*/
typedef union {
struct {
/** out_data_orig : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the output of GPIO0 ~ GPIO7.\\
* 0: Low level\\
* 1: High level\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
uint32_t out_data_orig:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_out_reg_t;
/** Type of out_w1ts register
* LP GPIO output set register
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be set to 1.
* - Recommended operation: use this register to set LP_IO_OUT_REG.
*/
uint32_t out_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* LP GPIO output clear register
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
* GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
* will be cleared.
* - Recommended operation: use this register to clear LP_IO_OUT_REG.
*/
uint32_t out_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_out_w1tc_reg_t;
/** Type of enable register
* LP GPIO output enable register
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\
* 0: Not enable\\
* 1: Enable\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
uint32_t enable_data:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_enable_reg_t;
/** Type of enable_w1ts register
* LP GPIO output enable set register
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be set to 1.
* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
*/
uint32_t enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* LP GPIO output enable clear register
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
* GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_ENABLE_REG will be cleared.
* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
*/
uint32_t enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_enable_w1tc_reg_t;
/** Type of in register
* LP GPIO input register
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [7:0]; default: 0;
* Represents the input value of GPIO0 ~ GPIO7.\\
* 0: Low level input\\
* 1: High level input\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
*/
uint32_t in_data_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_in_reg_t;
/** Type of status register
* LP GPIO interrupt status register
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* Configures the interrupt status of GPIO0 ~ GPIO7.\\
* 0: No interrupt\\
* 1: Interrupt is triggered\\
* Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This
* register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\
*/
uint32_t status_interrupt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_status_reg_t;
/** Type of status_w1ts register
* LP GPIO interrupt status set register
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
* GPIO0 ~ GPIO7.\\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be set to 1.
* - Recommended operation: use this register to set LP_IO_STATUS_INT.
*/
uint32_t status_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* LP GPIO interrupt status clear register
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
* of GPIO0 ~ GPIO7. \\
*
* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_IO_STATUS_INT will be cleared
* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
*/
uint32_t status_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_status_w1tc_reg_t;
/** Type of status_next register
* LP GPIO interrupt source register
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* Represents the interrupt source status of GPIO0 ~ GPIO7.\\
* bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\
* 0: Interrupt source status is invalid.\\
* 1: Interrupt source status is valid.\\
* The interrupt here can be rising-edge triggered, falling-edge triggered, any edge
* triggered, or level triggered.\\
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_gpio_status_next_reg_t;
/** Type of pinn register
* LP GPIO0 configuration register
*/
typedef union {
struct {
/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pinn_sync2_bypass:2;
/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select the pin dirve mode of GPIOn.\\
* 0: Normal output\\
* 1: Open drain output\\
*/
uint32_t pinn_pad_driver:1;
/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pinn_sync1_bypass:2;
/** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
*
* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
* GPIO will be cleared.
*/
uint32_t pinn_edge_wakeup_clr:1;
uint32_t reserved_6:1;
/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIOn interrupt type.\\
* 0: GPIO interrupt disabled \\
* 1: Rising edge trigger \\
* 2: Falling edge trigger \\
* 3: Any edge trigger \\
* 4: Low level trigger \\
* 5: High level trigger \\
*/
uint32_t pinn_int_type:3;
/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIOn wake-up function.\\
* 0: Not enable\\
* 1: Enable\\
* This function is disabled when PD_LP_PERI is powered off.\\
*/
uint32_t pinn_wakeup_enable:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_gpio_pinn_reg_t;
/** Type of funcn_out_sel_cfg register
* Configuration register for GPIO0 output
*/
typedef union {
struct {
/** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t funcn_out_inv_sel:1;
uint32_t reserved_1:1;
/** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_gpio_funcn_out_sel_cfg_reg_t;
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate.\\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_gpio_clock_gate_reg_t;
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36773904;
* version register.\\
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_gpio_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile lp_gpio_out_reg_t out;
volatile lp_gpio_out_w1ts_reg_t out_w1ts;
volatile lp_gpio_out_w1tc_reg_t out_w1tc;
volatile lp_gpio_enable_reg_t enable;
volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
volatile lp_gpio_in_reg_t in;
volatile lp_gpio_status_reg_t status;
volatile lp_gpio_status_w1ts_reg_t status_w1ts;
volatile lp_gpio_status_w1tc_reg_t status_w1tc;
volatile lp_gpio_status_next_reg_t status_next;
volatile lp_gpio_pinn_reg_t pinn[8];
uint32_t reserved_050[152];
volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[8];
uint32_t reserved_2d0[74];
volatile lp_gpio_clock_gate_reg_t clock_gate;
volatile lp_gpio_date_reg_t date;
} lp_gpio_dev_t;
extern lp_gpio_dev_t LP_GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_S 0
/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define LP_I2C_ANA_MST_I2C0_BUSY_S 25
/** LP_I2C_ANA_MST_I2C0_CONF_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_S 0
/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
* reserved
*/
#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_S 24
/** LP_I2C_ANA_MST_I2C0_DATA_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_S 0
/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8
/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
* need des
*/
#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11))
#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11
/** LP_I2C_ANA_MST_ANA_CONF1_REG register
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_S 0
/** LP_I2C_ANA_MST_NOUSE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** LP_I2C_ANA_MST_DEVICE_EN_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0
/** LP_I2C_ANA_MST_DATE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0
/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28))
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of i2c0_ctrl register
* need_des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c0_conf register
* need_des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 7;
* reserved
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c0_data register
* need_des
*/
typedef union {
struct {
/** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t i2c0_rdata:8;
/** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
uint32_t i2c0_clk_sel:3;
/** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
* need des
*/
uint32_t i2c_mst_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_data_reg_t;
/** Type of ana_conf1 register
* need_des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t ana_conf1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} lp_i2c_ana_mst_ana_conf1_reg_t;
/** Type of nouse register
* need_des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} lp_i2c_ana_mst_nouse_reg_t;
/** Type of device_en register
* need_des
*/
typedef union {
struct {
/** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
uint32_t i2c_device_en:12;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_device_en_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
uint32_t i2c_mat_date:28;
/** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t i2c_mat_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} lp_i2c_ana_mst_date_reg_t;
typedef struct {
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile lp_i2c_ana_mst_nouse_reg_t nouse;
volatile lp_i2c_ana_mst_device_en_reg_t device_en;
uint32_t reserved_018[249];
volatile lp_i2c_ana_mst_date_reg_t date;
} lp_i2c_ana_mst_dev_t;
extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Registers */
/** Type of gpion register
* LP_IO_MUX Configure Register for pad GPIO0
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn during sleep mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enable the sleep mode for GPIOn.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable the pull-down resistor of GPIOn during sleep
* mode. \\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable the pull-up resistor of GPIOn during sleep
* mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode. \\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
*/
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable the pull-down resistor of GPIOn in normal
* execution mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not to enable the pull-up resistor of GPIOn in normal
* execution mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable the input of GPIOn in normal execution mode.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn in normal execution mode.\\
* 0: ~5 mA\\
* 1: ~10 mA\\
* 2: ~20 mA\\
* 3: ~40 mA\\
*/
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select the LP IO MUX function for GPIOn in normal execution mode.\\
* 0: Select Function 0\\
* 1: Select Function 1\\
* ......\\
*/
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.\\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn. \\
* 0: Choose the output enable signal of eFuse\\
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN\\
*/
uint32_t gpion_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} lp_io_mux_gpion_reg_t;
/** Type of date register
* LP_IO_MUX Version Control Register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 35721840;
* Version control register. \\
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_mux_date_reg_t;
typedef struct {
volatile lp_io_mux_gpion_reg_t gpion[8];
uint32_t reserved_020[119];
volatile lp_io_mux_date_reg_t date;
} lp_io_mux_dev_t;
extern lp_io_mux_dev_t LP_IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(lp_io_mux_dev_t) == 0x200, "Invalid size of lp_io_mux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* TEE mode control register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* Configures M0 security level mode.\\
* 0: tee_mode \\
* 1: ree_mode0 \\
* 2: ree_mode1 \\
* 3: ree_mode2 \\
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
#define LP_TEE_M0_LOCK (BIT(2))
#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
#define LP_TEE_M0_LOCK_V 0x00000001U
#define LP_TEE_M0_LOCK_S 2
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
#define LP_TEE_CLK_EN_V 0x00000001U
#define LP_TEE_CLK_EN_S 0
/** LP_TEE_FORCE_ACC_HP_REG register
* Force access to hpmem configuration register
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* Configures whether to allow LP CPU to force access to HP_MEM regardless of
* permission management.\\
* 0: disable force access HP_MEM \\
* 1: enable force access HP_MEM \\
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_DATE_REG register
* Version control register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
*/
#define LP_TEE_DATE 0x0FFFFFFFU
#define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S)
#define LP_TEE_DATE_V 0x0FFFFFFFU
#define LP_TEE_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* TEE mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* Configures M0 security level mode.\\
* 0: tee_mode \\
* 1: ree_mode0 \\
* 2: ree_mode1 \\
* 3: ree_mode2 \\
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
uint32_t m0_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.\\
* 0: enable automatic clock gating \\
* 1: keep the clock always on \\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: Force access to hpmem configuration register */
/** Type of force_acc_hp register
* Force access to hpmem configuration register
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* Configures whether to allow LP CPU to force access to HP_MEM regardless of
* permission management.\\
* 0: disable force access HP_MEM \\
* 1: enable force access HP_MEM \\
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* Version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
uint32_t reserved_094[26];
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* RTC timer threshold low bits register0
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare0.
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* RTC timer enable register0
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare0
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare0 alarm.\\0: Disable \\1: Enable
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* RTC timer threshold low bits register1
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare1.
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* RTC timer threshold high bits register0
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare1
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare1 alarm.\\0: Disable \\1: Enable
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* RTC timer update control register
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0;
* Triggers timer by software
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 27
/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28))
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S)
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers
* up
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when CPU enters or
* exits the stall state.
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when resetting digital
* core completes
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* RTC timer buffer0 low bits register
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer0 low bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* RTC timer buffer0 high bits register
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer0 high bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* RTC timer buffer1 low bits register
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer1 low bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* RTC timer buffer1 high bits register
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer1 high bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register */
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; */
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* RTC timer interrupt raw register
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow.
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value.
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* RTC timer interrupt status register
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* RTC timer interrupt enable register
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* RTC timer interrupt clear register
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow raw interrupt..
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer raw interrupt..
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* RTC timer interrupt raw register(For ULP)
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* RTC timer interrupt status register(For ULP)
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* RTC timer interrupt enable register(For ULP)
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* RTC timer interrupt clear register(For ULP)
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow clear interrupt..
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer clear interrupt..
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* Date register
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 36769936;
* Version data
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar_low register
* RTC timer threshold low bits register0
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare0.
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar_low_reg_t;
/** Type of tar_high register
* RTC timer enable register0
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare0
*/
uint32_t main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare0 alarm.\\0: Disable \\1: Enable
*/
uint32_t main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar_high_reg_t;
/** Type of update register
* RTC timer update control register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** main_timer_update : WT; bitpos: [27]; default: 0;
* Triggers timer by software
*/
uint32_t main_timer_update:1;
/** main_timer_regdma_work : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
uint32_t main_timer_regdma_work:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers
* up
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when CPU enters or
* exits the stall state.
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when resetting digital
* core completes
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf_low register
* RTC timer buffer0 low bits register
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer0 low bits register
*/
uint32_t main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf_low_reg_t;
/** Type of main_buf_high register
* RTC timer buffer0 high bits register
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer0 high bits register
*/
uint32_t main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf_high_reg_t;
/** Type of main_overflow register */
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0; */
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of int_raw register
* RTC timer interrupt raw register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow.
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value.
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of int_st register
* RTC timer interrupt status register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of int_ena register
* RTC timer interrupt enable register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of int_clr register
* RTC timer interrupt clear register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow raw interrupt..
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer raw interrupt..
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* RTC timer interrupt raw register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* RTC timer interrupt status register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* RTC timer interrupt enable register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* RTC timer interrupt clear register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow clear interrupt..
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer clear interrupt..
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of date register
* Date register
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36769936;
* Version data
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar_low_reg_t lo;
volatile lp_timer_tar_high_reg_t hi;
} lp_timer_target_reg_t;
typedef struct {
volatile lp_timer_main_buf_low_reg_t lo;
volatile lp_timer_main_buf_high_reg_t hi;
} lp_timer_counter_reg_t;
typedef struct {
volatile lp_timer_target_reg_t target[2];
volatile lp_timer_update_reg_t update;
volatile lp_timer_counter_reg_t counter[2];
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;
volatile lp_timer_int_clr_reg_t int_clr;
volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
volatile lp_timer_lp_int_st_reg_t lp_int_st;
volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_WDT_CONFIG0_REG register
* Configure the RWDT operation.
*/
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20;
* need_des
*/
#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU
#define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S)
#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0x000000FFU
#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0
/** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0;
* need_des
*/
#define LP_WDT_WDT_CHIP_RESET_EN (BIT(8))
#define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S)
#define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_CHIP_RESET_EN_S 8
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable
* \\1:Disable
*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
* Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable
*/
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable
* \\1:Enable
*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
#define LP_WDT_WDT_STG3 0x00000007U
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
#define LP_WDT_WDT_STG3_V 0x00000007U
#define LP_WDT_WDT_STG3_S 19
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
#define LP_WDT_WDT_STG2 0x00000007U
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
#define LP_WDT_WDT_STG2_V 0x00000007U
#define LP_WDT_WDT_STG2_S 22
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
#define LP_WDT_WDT_STG1 0x00000007U
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
#define LP_WDT_WDT_STG1_V 0x00000007U
#define LP_WDT_WDT_STG1_S 25
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
#define LP_WDT_WDT_STG0 0x00000007U
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
#define LP_WDT_WDT_STG0_V 0x00000007U
#define LP_WDT_WDT_STG0_S 28
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.\\0:Disable \\1:Enable
*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
#define LP_WDT_WDT_EN_V 0x00000001U
#define LP_WDT_WDT_EN_S 31
/** LP_WDT_CONFIG1_REG register
* Configure the RWDT timeout of stage0
*/
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_S 0
/** LP_WDT_CONFIG2_REG register
* Configure the RWDT timeout of stage1
*/
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_S 0
/** LP_WDT_CONFIG3_REG register
* Configure the RWDT timeout of stage2
*/
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_S 0
/** LP_WDT_CONFIG4_REG register
* Configure the RWDT timeout of stage3
*/
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_S 0
/** LP_WDT_FEED_REG register
* Configure the feed function of RWDT
*/
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT
*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
#define LP_WDT_RTC_WDT_FEED_V 0x00000001U
#define LP_WDT_RTC_WDT_FEED_S 31
/** LP_WDT_WPROTECT_REG register
* Configure the lock function of SWD
*/
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_S 0
/** LP_WDT_SWD_CONFIG_REG register
* Configure the SWD operation
*/
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes
*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
#define LP_WDT_SWD_RESET_FLAG_S 0
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable
* \\1: Enable
*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag
*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit. \\ Measurement unit:
* LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD
*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
#define LP_WDT_SWD_DISABLE_V 0x00000001U
#define LP_WDT_SWD_DISABLE_S 30
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD
*/
#define LP_WDT_SWD_FEED (BIT(31))
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
#define LP_WDT_SWD_FEED_V 0x00000001U
#define LP_WDT_SWD_FEED_S 31
/** LP_WDT_SWD_WPROTECT_REG register
* Configure the lock function of SWD
*/
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_S 0
/** LP_WDT_INT_RAW_REG register
* Configure whether to generate timeout interrupt
*/
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes
*/
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_LP_WDT_INT_RAW_S 31
/** LP_WDT_INT_ST_REG register
* The interrupt status register of WDT
*/
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ST_S 30
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
*/
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ST_S 31
/** LP_WDT_INT_ENA_REG register
* The interrupt enable register of WDT
*/
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable
* \\1:Enable
*/
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable
* \\1:Enable
*/
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ENA_S 31
/** LP_WDT_INT_CLR_REG register
* The interrupt clear register of WDT
*/
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0:
* No\\1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0:
* No\\1: Yes
*/
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_LP_WDT_INT_CLR_S 31
/** LP_WDT_DATE_REG register
* need_des
*/
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
* Version control register
*/
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_S 0
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define LP_WDT_CLK_EN (BIT(31))
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
#define LP_WDT_CLK_EN_V 0x00000001U
#define LP_WDT_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
* Configure the RWDT operation.
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
* need_des
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t wdt_chip_reset_en:1;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable
* \\1:Disable
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable
* \\1:Enable
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2
* :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset.
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.\\0:Disable \\1:Enable
*/
uint32_t wdt_en:1;
};
uint32_t val;
} lp_wdt_config0_reg_t;
/** Type of config1 register
* Configure the RWDT timeout of stage0
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} lp_wdt_config1_reg_t;
/** Type of config2 register
* Configure the RWDT timeout of stage1
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} lp_wdt_config2_reg_t;
/** Type of config3 register
* Configure the RWDT timeout of stage2
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} lp_wdt_config3_reg_t;
/** Type of config4 register
* Configure the RWDT timeout of stage3
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} lp_wdt_config4_reg_t;
/** Type of feed register
* Configure the feed function of RWDT
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT
*/
uint32_t rtc_wdt_feed:1;
};
uint32_t val;
} lp_wdt_feed_reg_t;
/** Type of wprotect register
* Configure the lock function of SWD
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} lp_wdt_wprotect_reg_t;
/** Type of swd_config register
* Configure the SWD operation
*/
typedef union {
struct {
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes
*/
uint32_t swd_reset_flag:1;
uint32_t reserved_1:17;
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable
* \\1: Enable
*/
uint32_t swd_auto_feed_en:1;
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag
*/
uint32_t swd_rst_flag_clr:1;
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit. \\ Measurement unit:
* LP\_DYN\_FAST\_CLK
*/
uint32_t swd_signal_width:10;
/** swd_disable : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD
*/
uint32_t swd_disable:1;
/** swd_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD
*/
uint32_t swd_feed:1;
};
uint32_t val;
} lp_wdt_swd_config_reg_t;
/** Type of swd_wprotect register
* Configure the lock function of SWD
*/
typedef union {
struct {
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1:
* unlock the RWDT configuration registers.\\ Others value: Lock the RWDT
* configuration register which can`t be modified by software.
*/
uint32_t swd_wkey:32;
};
uint32_t val;
} lp_wdt_swd_wprotect_reg_t;
/** Type of int_raw register
* Configure whether to generate timeout interrupt
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes
*/
uint32_t super_wdt_int_raw:1;
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes
*/
uint32_t lp_wdt_int_raw:1;
};
uint32_t val;
} lp_wdt_int_raw_reg_t;
/** Type of int_st register
* The interrupt status register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
*/
uint32_t super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to
* CPU.\\ 0:No \\1: Yes
*/
uint32_t lp_wdt_int_st:1;
};
uint32_t val;
} lp_wdt_int_st_reg_t;
/** Type of int_ena register
* The interrupt enable register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable
* \\1:Enable
*/
uint32_t super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable
* \\1:Enable
*/
uint32_t lp_wdt_int_ena:1;
};
uint32_t val;
} lp_wdt_int_ena_reg_t;
/** Type of int_clr register
* The interrupt clear register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0:
* No\\1: Yes
*/
uint32_t super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0:
* No\\1: Yes
*/
uint32_t lp_wdt_int_clr:1;
};
uint32_t val;
} lp_wdt_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
* Version control register
*/
uint32_t lp_wdt_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_wdt_date_reg_t;
typedef struct {
volatile lp_wdt_config0_reg_t config0;
volatile lp_wdt_config1_reg_t config1;
volatile lp_wdt_config2_reg_t config2;
volatile lp_wdt_config3_reg_t config3;
volatile lp_wdt_config4_reg_t config4;
volatile lp_wdt_feed_reg_t feed;
volatile lp_wdt_wprotect_reg_t wprotect;
volatile lp_wdt_swd_config_reg_t swd_config;
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
volatile lp_wdt_int_raw_reg_t int_raw;
volatile lp_wdt_int_st_reg_t int_st;
volatile lp_wdt_int_ena_reg_t int_ena;
volatile lp_wdt_int_clr_reg_t int_clr;
uint32_t reserved_034[242];
volatile lp_wdt_date_reg_t date;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifndef __cplusplus
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* configure peri in lp system clk enable
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* lp rng clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* lp optdebug clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
* lp uart clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_UART_CK_EN (BIT(26))
#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
#define LPPERI_LP_UART_CK_EN_V 0x00000001U
#define LPPERI_LP_UART_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* lp io clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
* lp ext i2c clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_CK_EN_S 28
/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
* lp analog peri clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_CK_EN_S 29
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* efuse core clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
* force on lp cpu clk enable
* 1: enable cpu clock
* 0: cpu clock is controlled by pmu
*/
#define LPPERI_LP_CPU_CK_EN (BIT(31))
#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
#define LPPERI_LP_CPU_CK_EN_S 31
/** LPPERI_RESET_EN_REG register
* configure peri in lp system reset enable
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* lp bus reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_LP_RNG_RESET_EN : R/W; bitpos: [24]; default: 0;
* lp rng reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_RNG_RESET_EN (BIT(24))
#define LPPERI_LP_RNG_RESET_EN_M (LPPERI_LP_RNG_RESET_EN_V << LPPERI_LP_RNG_RESET_EN_S)
#define LPPERI_LP_RNG_RESET_EN_V 0x00000001U
#define LPPERI_LP_RNG_RESET_EN_S 24
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* lp optdebug reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
* lp uart reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_UART_RESET_EN (BIT(26))
#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
#define LPPERI_LP_UART_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* lp io reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
* lp ext i2c reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
* lp analog peri reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* efuse core reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
* force on lp cpu reset enable
* 1: enable cpu reset
* 0: cpu reset is controlled by pmu
*/
#define LPPERI_LP_CPU_RESET_EN (BIT(31))
#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
#define LPPERI_LP_CPU_RESET_EN_S 31
/** LPPERI_RNG_DATA_REG register
* RNG result register
*/
#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
* get rng data
*/
#define LPPERI_RND_DATA 0xFFFFFFFFU
#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
#define LPPERI_RND_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_DATA_S 0
/** LPPERI_CPU_REG register
* configure lp cpu dbg enable
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
* disable lp cpu dbg bus
* 1: disable
* 0: enable
*/
#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
/** LPPERI_BUS_TIMEOUT_REG register
* configure lp bus timeout
*/
#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
* the timeout thres which bus access time, the timeout clk is lp_aon_fast
*/
#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
* clear lp bus timeout interrupt
*/
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
* enable lp bus timeout or not,when bus timeout, the ready will been force high by fsm
* 1: enable
* 0: disable
*/
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
/** LPPERI_BUS_TIMEOUT_ADDR_REG register
* the timeout address register
*/
#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* when bus timeout, this register will record the timeout address
*/
#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
/** LPPERI_BUS_TIMEOUT_UID_REG register
* the timeout master id register
*/
#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* when bus timeout, this register will record the timeout master device
*/
#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
/** LPPERI_MEM_CTRL_REG register
* configure uart memory power mode
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* clear uart wakeup latch
* 1: clear
* 0: no operation
*/
#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* latch uart wakeup event
*/
#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_S 1
/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* enable uart wakeup not not
*/
#define LPPERI_UART_WAKEUP_EN (BIT(29))
#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_UART_WAKEUP_EN_S 29
/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* force off uart memory
*/
#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PD_S 30
/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* force on uart memory
*/
#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PU_S 31
/** LPPERI_INTERRUPT_SOURCE_REG register
* record the lp cpu interrupt
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_RNG_CFG_REG register
* configure rng register
*/
#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24)
/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
* enable rng RO
* 1: enable RO
* 0: disable RO
*/
#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0))
#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U
#define LPPERI_RNG_SAMPLE_ENABLE_S 0
/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
* configure rng timer clk div
*/
#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_S 1
/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
* enable rng xor async rng timer
*/
#define LPPERI_RNG_TIMER_EN (BIT(9))
#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
#define LPPERI_RNG_TIMER_EN_V 0x00000001U
#define LPPERI_RNG_TIMER_EN_S 9
/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3;
* enable rng xor rtc timer:
* bit(0) : enable rtc timer before crc
* Bit(1): enable rtc timer after crc
*/
#define LPPERI_RTC_TIMER_EN 0x00000003U
#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S)
#define LPPERI_RTC_TIMER_EN_V 0x00000003U
#define LPPERI_RTC_TIMER_EN_S 10
/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* get rng RO sample cnt
*/
#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_S 24
/** LPPERI_RNG_DATA_SYNC_REG register
* rng result sync register
*/
#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x28)
/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0;
* get rng sync result
*/
#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU
#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S)
#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_SYNC_DATA_S 0
/** LPPERI_DATE_REG register
* version register
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36774256;
* version register
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/lpperi_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* configure peri in lp system clk enable
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* lp rng clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* lp optdebug clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t otp_dbg_ck_en:1;
/** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
* lp uart clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_uart_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* lp io clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_io_ck_en:1;
/** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
* lp ext i2c clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_ext_i2c_ck_en:1;
/** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
* lp analog peri clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_ana_i2c_ck_en:1;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* efuse core clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t efuse_ck_en:1;
/** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
* force on lp cpu clk enable
* 1: enable cpu clock
* 0: cpu clock is controlled by pmu
*/
uint32_t lp_cpu_ck_en:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* configure peri in lp system reset enable
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* lp bus reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t bus_reset_en:1;
/** lp_rng_reset_en : R/W; bitpos: [24]; default: 0;
* lp rng reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_rng_reset_en:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* lp optdebug reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t otp_dbg_reset_en:1;
/** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
* lp uart reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_uart_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* lp io reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_io_reset_en:1;
/** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
* lp ext i2c reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_ext_i2c_reset_en:1;
/** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
* lp analog peri reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_ana_i2c_reset_en:1;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* efuse core reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t efuse_reset_en:1;
/** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
* force on lp cpu reset enable
* 1: enable cpu reset
* 0: cpu reset is controlled by pmu
*/
uint32_t lp_cpu_reset_en:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of rng_data register
* RNG result register
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* get rng data
*/
uint32_t rnd_data:32;
};
uint32_t val;
} lpperi_rng_data_reg_t;
/** Type of cpu register
* configure lp cpu dbg enable
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
* disable lp cpu dbg bus
* 1: disable
* 0: enable
*/
uint32_t lpcore_dbgm_unavaliable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of bus_timeout register
* configure lp bus timeout
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
* the timeout thres which bus access time, the timeout clk is lp_aon_fast
*/
uint32_t lp_peri_timeout_thres:16;
/** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
* clear lp bus timeout interrupt
*/
uint32_t lp_peri_timeout_int_clear:1;
/** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
* enable lp bus timeout or not,when bus timeout, the ready will been force high by fsm
* 1: enable
* 0: disable
*/
uint32_t lp_peri_timeout_protect_en:1;
};
uint32_t val;
} lpperi_bus_timeout_reg_t;
/** Type of bus_timeout_addr register
* the timeout address register
*/
typedef union {
struct {
/** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* when bus timeout, this register will record the timeout address
*/
uint32_t lp_peri_timeout_addr:32;
};
uint32_t val;
} lpperi_bus_timeout_addr_reg_t;
/** Type of bus_timeout_uid register
* the timeout master id register
*/
typedef union {
struct {
/** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* when bus timeout, this register will record the timeout master device
*/
uint32_t lp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_bus_timeout_uid_reg_t;
/** Type of mem_ctrl register
* configure uart memory power mode
*/
typedef union {
struct {
/** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* clear uart wakeup latch
* 1: clear
* 0: no operation
*/
uint32_t uart_wakeup_flag_clr:1;
/** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* latch uart wakeup event
*/
uint32_t uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* enable uart wakeup not not
*/
uint32_t uart_wakeup_en:1;
/** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* force off uart memory
*/
uint32_t uart_mem_force_pd:1;
/** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* force on uart memory
*/
uint32_t uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of interrupt_source register
* record the lp cpu interrupt
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
uint32_t lp_interrupt_source:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Type of rng_cfg register
* configure rng register
*/
typedef union {
struct {
/** rng_sample_enable : R/W; bitpos: [0]; default: 0;
* enable rng RO
* 1: enable RO
* 0: disable RO
*/
uint32_t rng_sample_enable:1;
/** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255;
* configure rng timer clk div
*/
uint32_t rng_timer_pscale:8;
/** rng_timer_en : R/W; bitpos: [9]; default: 1;
* enable rng xor async rng timer
*/
uint32_t rng_timer_en:1;
/** rtc_timer_en : R/W; bitpos: [11:10]; default: 3;
* enable rng xor rtc timer:
* bit(0) : enable rtc timer before crc
* Bit(1): enable rtc timer after crc
*/
uint32_t rtc_timer_en:2;
uint32_t reserved_12:12;
/** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
* get rng RO sample cnt
*/
uint32_t rng_sample_cnt:8;
};
uint32_t val;
} lpperi_rng_cfg_reg_t;
/** Type of rng_data_sync register
* rng result sync register
*/
typedef union {
struct {
/** rnd_sync_data : RO; bitpos: [31:0]; default: 0;
* get rng sync result
*/
uint32_t rnd_sync_data:32;
};
uint32_t val;
} lpperi_rng_data_sync_reg_t;
/** Group: Version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 36774256;
* version register
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_data_reg_t rng_data;
volatile lpperi_cpu_reg_t cpu;
volatile lpperi_bus_timeout_reg_t bus_timeout;
volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_interrupt_source_reg_t interrupt_source;
volatile lpperi_rng_cfg_reg_t rng_cfg;
volatile lpperi_rng_data_sync_reg_t rng_data_sync;
uint32_t reserved_02c[244];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* Bus access logging configuration register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[1]: Configures word monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[2]: Configures halfword monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[3]: Configures byte monitoring. \\
* 0: Disable \\
* 1: Enable\\
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 0
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode\\
* 0: Non-loop mode\\
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
/** MEM_MONITOR_LOG_SETTING1_REG register
* Bus access logging configuration register
*/
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* Configures monitored data in Bus access logging
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* Configures the data to be monitored during bus accessing.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* Configures masked data in Bus access logging
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
* 0: Not mask \\
* 1: Mask\\
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* Configures monitored address space in Bus access logging
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of the monitored address space.
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* Configures monitored address space in Bus access logging
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of the monitored address space.
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0
/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
* 0: Not update\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31))
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0
/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8
/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16
/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S)
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V 0x000000FFU
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S 24
/** MEM_MONITOR_LOG_MEM_START_REG register
* Configures the starting address of the storage memory for recorded data
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* Configures the starting address of the storage space for recorded data.
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* Configures the end address of the storage memory for recorded data
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* Configures the ending address of the storage space for recorded data.
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* Represents the address for the next write
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next write.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* Updates the address for the next write with the starting address for the recorded
* data
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
* 0: Not update (default) \\
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* Logging overflow status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow\\
* 1: Overflow\\
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
* clear\\
* 1: Clear\\
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* Register clock control
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable\\
* 1: Enable\\
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* Version control register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36733248;
* Version control register.
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* Bus access logging configuration register
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[1]: Configures word monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[2]: Configures halfword monitoring. \\
* 0: Disable \\
* 1: Enable\\
* bit[3]: Configures byte monitoring. \\
* 0: Disable \\
* 1: Enable\\
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
* Configures the writing mode for recorded data.1: Loop mode\\
* 0: Non-loop mode\\
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_5:3;
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
* enable HP CPU bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
uint32_t log_core_ena:8;
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
* to enable DMA_0 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
uint32_t log_dma_0_ena:8;
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
* to enable DMA_1 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
uint32_t log_dma_1_ena:8;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_setting1 register
* Bus access logging configuration register
*/
typedef union {
struct {
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
* to enable DMA_2 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
uint32_t log_dma_2_ena:8;
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
* to enable DMA_3 bus access logging. \\
* 0: Disable \\
* 1: Enable\\
* Bit[7:1]: Reserved
*/
uint32_t log_dma_3_ena:8;
uint32_t reserved_16:16;
};
uint32_t val;
} mem_monitor_log_setting1_reg_t;
/** Type of log_check_data register
* Configures monitored data in Bus access logging
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* Configures the data to be monitored during bus accessing.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* Configures masked data in Bus access logging
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
* Configures whether to mask the least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
* 0: Not mask \\
* 1: Mask\\
* bit[1]: Configures whether to mask the second least significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* bit[2]: Configures whether to mask the second most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
* bit[3]: Configures whether to mask the most significant byte of
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
* 0: Not mask \\
* 1: Mask\\
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* Configures monitored address space in Bus access logging
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* Configures the lower bound address of the monitored address space.
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* Configures monitored address space in Bus access logging
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* Configures the upper bound address of the monitored address space.
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mon_addr_update_0 register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
typedef union {
struct {
/** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the HP CPU bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
uint32_t log_mon_addr_core_update:8;
uint32_t reserved_8:23;
/** log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
* 0: Not update\\
*/
uint32_t log_mon_addr_all_update:1;
};
uint32_t val;
} mem_monitor_log_mon_addr_update_0_reg_t;
/** Type of log_mon_addr_update_1 register
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
*/
typedef union {
struct {
/** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_0 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
uint32_t log_mon_addr_dma_0_update:8;
/** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_1 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
uint32_t log_mon_addr_dma_1_update:8;
/** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_2 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
uint32_t log_mon_addr_dma_2_update:8;
/** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
* Configures the monitored address space of the certain master. Bit[0]: Configures
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
* monitored address space of the DMA_3 bus.1: Update\\
* 0: Not update\\
* Bit[7:1]: Reserved\\
*/
uint32_t log_mon_addr_dma_3_update:8;
};
uint32_t val;
} mem_monitor_log_mon_addr_update_1_reg_t;
/** Type of log_mem_start register
* Configures the starting address of the storage memory for recorded data
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* Configures the starting address of the storage space for recorded data.
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* Configures the end address of the storage memory for recorded data
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* Configures the ending address of the storage space for recorded data.
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* Represents the address for the next write
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next write.
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* Updates the address for the next write with the starting address for the recorded
* data
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
* 0: Not update (default) \\
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* Logging overflow status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* Represents whether data overflows the storage space.0: Not Overflow\\
* 1: Overflow\\
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
* clear\\
* 1: Clear\\
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* Register clock control
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the register clock gating.0: Disable\\
* 1: Enable\\
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36733248;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_setting1_reg_t log_setting1;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mon_addr_update_0_reg_t log_mon_addr_update_0;
volatile mem_monitor_log_mon_addr_update_1_reg_t log_mon_addr_update_1;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_038[241];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PARL_IO_RX_MODE_CFG_REG register
* Parallel RX Sampling mode configuration register.
*/
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_S 21
/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
#define PARL_IO_RX_SW_EN (BIT(25))
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
#define PARL_IO_RX_SW_EN_V 0x00000001U
#define PARL_IO_RX_SW_EN_S 25
/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
#define PARL_IO_RX_EXT_EN_INV (BIT(26))
#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U
#define PARL_IO_RX_EXT_EN_INV_S 26
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_S 30
/** PARL_IO_RX_DATA_CFG_REG register
* Parallel RX data configuration register.
*/
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
#define PARL_IO_RX_BITLEN 0x0007FFFFU
#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
#define PARL_IO_RX_BITLEN_V 0x0007FFFFU
#define PARL_IO_RX_BITLEN_S 9
/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
#define PARL_IO_RX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_RX_DATA_ORDER_INV_S 28
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_S 29
/** PARL_IO_RX_GENRL_CFG_REG register
* Parallel RX general configuration register.
*/
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
#define PARL_IO_RX_GATING_EN (BIT(12))
#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
#define PARL_IO_RX_GATING_EN_V 0x00000001U
#define PARL_IO_RX_GATING_EN_S 12
/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRES_S 13
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
#define PARL_IO_RX_TIMEOUT_EN (BIT(29))
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
#define PARL_IO_RX_TIMEOUT_EN_S 29
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
#define PARL_IO_RX_EOF_GEN_SEL (BIT(30))
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_RX_EOF_GEN_SEL_S 30
/** PARL_IO_RX_START_CFG_REG register
* Parallel RX Start configuration register.
*/
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
#define PARL_IO_RX_START (BIT(31))
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
#define PARL_IO_RX_START_V 0x00000001U
#define PARL_IO_RX_START_S 31
/** PARL_IO_TX_DATA_CFG_REG register
* Parallel TX data configuration register.
*/
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
#define PARL_IO_TX_BITLEN 0x0007FFFFU
#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
#define PARL_IO_TX_BITLEN_V 0x0007FFFFU
#define PARL_IO_TX_BITLEN_S 9
/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
#define PARL_IO_TX_DATA_ORDER_INV (BIT(28))
#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U
#define PARL_IO_TX_DATA_ORDER_INV_S 28
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_S 29
/** PARL_IO_TX_START_CFG_REG register
* Parallel TX Start configuration register.
*/
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
#define PARL_IO_TX_START (BIT(31))
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
#define PARL_IO_TX_START_V 0x00000001U
#define PARL_IO_TX_START_S 31
/** PARL_IO_TX_GENRL_CFG_REG register
* Parallel TX general configuration register.
*/
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
#define PARL_IO_TX_EOF_GEN_SEL (BIT(13))
#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_TX_EOF_GEN_SEL_S 13
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_S 14
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
#define PARL_IO_TX_GATING_EN (BIT(30))
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
#define PARL_IO_TX_GATING_EN_V 0x00000001U
#define PARL_IO_TX_GATING_EN_S 30
/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31))
#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U
#define PARL_IO_TX_VALID_OUTPUT_EN_S 31
/** PARL_IO_FIFO_CFG_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
#define PARL_IO_TX_FIFO_SRST (BIT(30))
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
#define PARL_IO_TX_FIFO_SRST_S 30
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
#define PARL_IO_RX_FIFO_SRST (BIT(31))
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
#define PARL_IO_RX_FIFO_SRST_S 31
/** PARL_IO_REG_UPDATE_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
#define PARL_IO_RX_REG_UPDATE (BIT(31))
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
#define PARL_IO_RX_REG_UPDATE_S 31
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
#define PARL_IO_TX_READY (BIT(31))
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
#define PARL_IO_TX_READY_V 0x00000001U
#define PARL_IO_TX_READY_S 31
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable singal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ENA_S 2
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw singal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1
/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
#define PARL_IO_TX_EOF_INT_RAW_S 2
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt singal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ST_S 2
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear singal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1))
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U
#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
#define PARL_IO_TX_EOF_INT_CLR_S 2
/** PARL_IO_RX_ST0_REG register
* Parallel IO RX status register0
*/
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
#define PARL_IO_RX_CNT 0x0000001FU
#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
#define PARL_IO_RX_CNT_V 0x0000001FU
#define PARL_IO_RX_CNT_S 8
/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13
/** PARL_IO_RX_ST1_REG register
* Parallel IO RX status register1
*/
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_TX_ST0_REG register
* Parallel IO TX status register0
*/
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
#define PARL_IO_TX_CNT 0x0000007FU
#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
#define PARL_IO_TX_CNT_V 0x0000007FU
#define PARL_IO_TX_CNT_S 6
/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU
#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13
/** PARL_IO_RX_CLK_CFG_REG register
* Parallel IO RX clk configuration register
*/
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
#define PARL_IO_RX_CLK_I_INV (BIT(30))
#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
#define PARL_IO_RX_CLK_I_INV_V 0x00000001U
#define PARL_IO_RX_CLK_I_INV_S 30
/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
#define PARL_IO_RX_CLK_O_INV (BIT(31))
#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
#define PARL_IO_RX_CLK_O_INV_V 0x00000001U
#define PARL_IO_RX_CLK_O_INV_S 31
/** PARL_IO_TX_CLK_CFG_REG register
* Parallel IO TX clk configuration register
*/
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
#define PARL_IO_TX_CLK_I_INV (BIT(30))
#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
#define PARL_IO_TX_CLK_I_INV_V 0x00000001U
#define PARL_IO_TX_CLK_I_INV_S 30
/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
#define PARL_IO_TX_CLK_O_INV (BIT(31))
#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
#define PARL_IO_TX_CLK_O_INV_V 0x00000001U
#define PARL_IO_TX_CLK_O_INV_S 31
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
#define PARL_IO_CLK_EN (BIT(31))
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
#define PARL_IO_CLK_EN_V 0x00000001U
#define PARL_IO_CLK_EN_S 31
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
#define PARL_IO_DATE_V 0x0FFFFFFFU
#define PARL_IO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/parl_io_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: PARL_IO RX Mode Configuration */
/** Type of rx_mode_cfg register
* Parallel RX Sampling mode configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
uint32_t rx_ext_en_sel:4;
/** rx_sw_en : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
uint32_t rx_sw_en:1;
/** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
uint32_t rx_ext_en_inv:1;
/** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
* 2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
* 3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
uint32_t rx_pulse_submode_sel:3;
/** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
uint32_t rx_smp_mode_sel:2;
};
uint32_t val;
} parl_io_rx_mode_cfg_reg_t;
/** Group: PARL_IO RX Data Configuration */
/** Type of rx_data_cfg register
* Parallel RX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
uint32_t rx_bitlen:19;
/** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
uint32_t rx_data_order_inv:1;
/** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t rx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_rx_data_cfg_reg_t;
/** Group: PARL_IO RX General Configuration */
/** Type of rx_genrl_cfg register
* Parallel RX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rx_gating_en : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
uint32_t rx_gating_en:1;
/** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
uint32_t rx_timeout_thres:16;
/** rx_timeout_en : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
uint32_t rx_timeout_en:1;
/** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
uint32_t rx_eof_gen_sel:1;
uint32_t reserved_31:1;
};
uint32_t val;
} parl_io_rx_genrl_cfg_reg_t;
/** Group: PARL_IO RX Start Configuration */
/** Type of rx_start_cfg register
* Parallel RX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
uint32_t rx_start:1;
};
uint32_t val;
} parl_io_rx_start_cfg_reg_t;
/** Group: PARL_IO TX Data Configuration */
/** Type of tx_data_cfg register
* Parallel TX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
uint32_t tx_bitlen:19;
/** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
uint32_t tx_data_order_inv:1;
/** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t tx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_tx_data_cfg_reg_t;
/** Group: PARL_IO TX Start Configuration */
/** Type of tx_start_cfg register
* Parallel TX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
uint32_t tx_start:1;
};
uint32_t val;
} parl_io_tx_start_cfg_reg_t;
/** Group: PARL_IO TX General Configuration */
/** Type of tx_genrl_cfg register
* Parallel TX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
uint32_t tx_eof_gen_sel:1;
/** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
uint32_t tx_idle_value:16;
/** tx_gating_en : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
uint32_t tx_gating_en:1;
/** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
uint32_t tx_valid_output_en:1;
};
uint32_t val;
} parl_io_tx_genrl_cfg_reg_t;
/** Group: PARL_IO FIFO Configuration */
/** Type of fifo_cfg register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
uint32_t tx_fifo_srst:1;
/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
uint32_t rx_fifo_srst:1;
};
uint32_t val;
} parl_io_fifo_cfg_reg_t;
/** Group: PARL_IO Register Update Configuration */
/** Type of reg_update register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rx_reg_update : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
uint32_t rx_reg_update:1;
};
uint32_t val;
} parl_io_reg_update_reg_t;
/** Group: PARL_IO Status */
/** Type of st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
uint32_t tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of int_ena register
* Parallel IO interrupt enable singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_ena:1;
/** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_ena:1;
/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
uint32_t tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of int_raw register
* Parallel IO interrupt raw singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_raw:1;
/** rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_raw:1;
/** tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
uint32_t tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of int_st register
* Parallel IO interrupt singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_st:1;
/** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_st:1;
/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
uint32_t tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of int_clr register
* Parallel IO interrupt clear singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
uint32_t tx_fifo_rempty_int_clr:1;
/** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
uint32_t rx_fifo_wovf_int_clr:1;
/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
uint32_t tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_clr_reg_t;
/** Group: PARL_IO Rx Status0 */
/** Type of rx_st0 register
* Parallel IO RX status register0
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** rx_cnt : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
uint32_t rx_cnt:5;
/** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
uint32_t rx_fifo_wr_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st0_reg_t;
/** Group: PARL_IO Rx Status1 */
/** Type of rx_st1 register
* Parallel IO RX status register1
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
uint32_t rx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st1_reg_t;
/** Group: PARL_IO Tx Status0 */
/** Type of tx_st0 register
* Parallel IO TX status register0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** tx_cnt : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
uint32_t tx_cnt:7;
/** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
uint32_t tx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_tx_st0_reg_t;
/** Group: PARL_IO Rx Clock Configuration */
/** Type of rx_clk_cfg register
* Parallel IO RX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
uint32_t rx_clk_i_inv:1;
/** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
uint32_t rx_clk_o_inv:1;
};
uint32_t val;
} parl_io_rx_clk_cfg_reg_t;
/** Group: PARL_IO Tx Clock Configuration */
/** Type of tx_clk_cfg register
* Parallel IO TX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
uint32_t tx_clk_i_inv:1;
/** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
uint32_t tx_clk_o_inv:1;
};
uint32_t val;
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t clk_en:1;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of version register
* Version register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725920;
* Version of this register file
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct {
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t fifo_cfg;
volatile parl_io_reg_update_reg_t reg_update;
volatile parl_io_st_reg_t st;
volatile parl_io_int_ena_reg_t int_ena;
volatile parl_io_int_raw_reg_t int_raw;
volatile parl_io_int_st_reg_t int_st;
volatile parl_io_int_clr_reg_t int_clr;
volatile parl_io_rx_st0_reg_t rx_st0;
volatile parl_io_rx_st1_reg_t rx_st1;
volatile parl_io_tx_st0_reg_t tx_st0;
volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
uint32_t reserved_04c[53];
volatile parl_io_clk_reg_t clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t version;
} parl_io_dev_t;
extern parl_io_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x0000000FU
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x0000000FU
#define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [9]; default: 0;
* mac sw backup start signal
*/
#define PAU_START_MAC (BIT(9))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 9
/** PAU_TO_MEM_MAC : R/W; bitpos: [10]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM_MAC (BIT(10))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 10
/** PAU_SEL_MAC : R/W; bitpos: [11]; default: 0;
* mac hw/sw select
*/
#define PAU_SEL_MAC (BIT(11))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
#define PAU_SEL_MAC_V 0x00000001U
#define PAU_SEL_MAC_S 11
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_ETM_LINK_SEL_0 : R/W; bitpos: [7:4]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_0 0x0000000FU
#define PAU_ETM_LINK_SEL_0_M (PAU_ETM_LINK_SEL_0_V << PAU_ETM_LINK_SEL_0_S)
#define PAU_ETM_LINK_SEL_0_V 0x0000000FU
#define PAU_ETM_LINK_SEL_0_S 4
/** PAU_ETM_LINK_SEL_1 : R/W; bitpos: [11:8]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_1 0x0000000FU
#define PAU_ETM_LINK_SEL_1_M (PAU_ETM_LINK_SEL_1_V << PAU_ETM_LINK_SEL_1_S)
#define PAU_ETM_LINK_SEL_1_V 0x0000000FU
#define PAU_ETM_LINK_SEL_1_S 8
/** PAU_ETM_LINK_SEL_2 : R/W; bitpos: [15:12]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_2 0x0000000FU
#define PAU_ETM_LINK_SEL_2_M (PAU_ETM_LINK_SEL_2_V << PAU_ETM_LINK_SEL_2_S)
#define PAU_ETM_LINK_SEL_2_V 0x0000000FU
#define PAU_ETM_LINK_SEL_2_S 12
/** PAU_ETM_LINK_SEL_3 : R/W; bitpos: [19:16]; default: 0;
* etm_link sel
*/
#define PAU_ETM_LINK_SEL_3 0x0000000FU
#define PAU_ETM_LINK_SEL_3_M (PAU_ETM_LINK_SEL_3_V << PAU_ETM_LINK_SEL_3_S)
#define PAU_ETM_LINK_SEL_3_V 0x0000000FU
#define PAU_ETM_LINK_SEL_3_S 16
/** PAU_ETM_BUSY_CAUSE : RO; bitpos: [23:20]; default: 0;
* debug
*/
#define PAU_ETM_BUSY_CAUSE 0x0000000FU
#define PAU_ETM_BUSY_CAUSE_M (PAU_ETM_BUSY_CAUSE_V << PAU_ETM_BUSY_CAUSE_S)
#define PAU_ETM_BUSY_CAUSE_V 0x0000000FU
#define PAU_ETM_BUSY_CAUSE_S 20
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_PERI_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_PERI_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_PERI_ADDR : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
#define PAU_PERI_ADDR 0xFFFFFFFFU
#define PAU_PERI_ADDR_M (PAU_PERI_ADDR_V << PAU_PERI_ADDR_S)
#define PAU_PERI_ADDR_V 0xFFFFFFFFU
#define PAU_PERI_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 36737360;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [8:5]; default: 0;
* Link select
*/
uint32_t link_sel:4;
/** start_mac : WT; bitpos: [9]; default: 0;
* mac sw backup start signal
*/
uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [10]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [11]; default: 0;
* mac hw/sw select
*/
uint32_t sel_mac:1;
uint32_t reserved_12:20;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
/** etm_link_sel_0 : R/W; bitpos: [7:4]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_0:4;
/** etm_link_sel_1 : R/W; bitpos: [11:8]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_1:4;
/** etm_link_sel_2 : R/W; bitpos: [15:12]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_2:4;
/** etm_link_sel_3 : R/W; bitpos: [19:16]; default: 0;
* etm_link sel
*/
uint32_t etm_link_sel_3:4;
/** etm_busy_cause : RO; bitpos: [23:20]; default: 0;
* debug
*/
uint32_t etm_busy_cause:4;
uint32_t reserved_24:8;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_peri_addr register
* Backup addr
*/
typedef union {
struct {
/** peri_addr : RO; bitpos: [31:0]; default: 0;
* peri addr reg
*/
uint32_t peri_addr:32;
};
uint32_t val;
} pau_regdma_peri_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36737360;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_peri_addr_reg_t regdma_peri_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
uint32_t reserved_028[245];
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit 0
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* Configures the maximum threshold for the filter. Any pulses with width less than
* this will be ignored when the filter is enabled. \\
* Measurement unit: APB_CLK cycles.\\
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a negative
* edge.\\
* 1: Increment the counter\\
* 2: Decrement the counter\\
* 0, 3: No effect \\
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* Configures the behavior when the signal input of channel 0 detects a positive edge.
* \\
* 1: Increment the counter\\
* 2: Decrement the counter\\
* 0, 3: No effect \\
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high. \\
* 0: No modification\\
* 1: Invert behavior (increase -> decrease, decrease -> increase)\\
* 2, 3: Inhibit counter modification \\
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low. \\
* 0: No modification\\
* 1: Invert behavior (increase -> decrease, decrease -> increase)\\
* 2, 3: Inhibit counter modification\\
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a negative edge.
* \\
* 1: Increment the counter\\
* 2: Decrement the counter\\
* 0, 3: No effect \\
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* Configures the behavior when the signal input of channel 1 detects a positive edge.
* \\
* 1: Increment the counter\\
* 2: Decrement the counter\\
* 0, 3: No effect \\
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is high. \\
* 0: No modification\\
* 1: Invert behavior (increase -> decrease, decrease -> increase)\\
* 2, 3: Inhibit counter modification \\
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the
* control signal is low. \\
* 0: No modification\\
* 1: Invert behavior (increase -> decrease, decrease -> increase)\\
* 2, 3: Inhibit counter modification \\
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit 0
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit 0
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* Configures the thr_h_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* Configures the thr_l_lim value for unit n. When pulse_cnt reaches this value, the
* counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Type of u3_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 3.
*/
uint32_t cnt_step_u3:16;
/** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 3.
*/
uint32_t cnt_step_lim_u3:16;
};
uint32_t val;
} pcnt_u3_change_conf_reg_t;
/** Type of u2_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 2.
*/
uint32_t cnt_step_u2:16;
/** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 2.
*/
uint32_t cnt_step_lim_u2:16;
};
uint32_t val;
} pcnt_u2_change_conf_reg_t;
/** Type of u1_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 1.
*/
uint32_t cnt_step_u1:16;
/** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 1.
*/
uint32_t cnt_step_lim_u1:16;
};
uint32_t val;
} pcnt_u1_change_conf_reg_t;
/** Type of u0_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 0.
*/
uint32_t cnt_step_u0:16;
/** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 0.
*/
uint32_t cnt_step_lim_u0:16;
};
uint32_t val;
} pcnt_u0_change_conf_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit 0
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* Represents the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNIT0 status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* Represents the pulse counter status of PCNT_Un corresponding to 0. \\
* 0: pulse counter decreases from positive to 0\\
* 1: pulse counter increases from negative to 0\\
* 2: pulse counter is negative\\
* 3: pulse counter is positive \\
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* Represents the latched value of thres1 event of PCNT_Un when threshold event
* interrupt is valid. \\
* 0: others\\
* 1: the current pulse counter equals to thres1 and thres1 event is valid \\
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* Represents the latched value of thres0 event of PCNT_Un when threshold event
* interrupt is valid. \\
* 0: others\\
* 1: the current pulse counter equals to thres0 and thres0 event is valid \\
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* Represents the latched value of low limit event of PCNT_Un when threshold event
* interrupt is valid. \\
* 0: others\\
* 1: the current pulse counter equals to thr_l_lim and low limit event is valid. \\
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* Represents the latched value of high limit event of PCNT_Un when threshold event
* interrupt is valid. \\
* 0: others\\
* 1: the current pulse counter equals to thr_h_lim and high limit event is valid. \\
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* Represents the latched value of zero threshold event of PCNT_Un when threshold
* event interrupt is valid. \\
* 0: others\\
* 1: the current pulse counter equals to 0 and zero threshold event is valid. \\
*/
uint32_t cnt_thr_zero_lat_un:1;
/** cnt_thr_step_lim_lat_un : RO; bitpos: [7]; default: 0;
* The latched value of step counter limit event of PCNT_Un when step counter event
* interrupt is valid. 1: the current pulse counter equals to reg_cnt_step_lim and
* step counter event is valid. 0: others
*/
uint32_t cnt_thr_step_lim_lat_un:1;
/** cnt_thr_step_lat_un : RO; bitpos: [8]; default: 0;
* The latched value of step counter event of PCNT_Un when step counter event
* interrupt is valid. 1: the current pulse counter increment equals to reg_cnt_step
* and step counter event is valid. 0: others
*/
uint32_t cnt_thr_step_lat_un:1;
uint32_t reserved_9:23;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36765968;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
volatile pcnt_u3_change_conf_reg_t u3_change_conf;
volatile pcnt_u2_change_conf_reg_t u2_change_conf;
volatile pcnt_u1_change_conf_reg_t u1_change_conf;
volatile pcnt_u0_change_conf_reg_t u0_change_conf;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_FUNC_ENA_CAN0 31
#define PMU_ICG_FUNC_ENA_CAN1 30
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15

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/**
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#include "soc/pmu_reg.h"
typedef union {
struct {
uint32_t reserved0 : 21;
uint32_t vdd_spi_pd_en: 1;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 4;
uint32_t wifi_pd_en : 1;
uint32_t reserved1 : 1;
uint32_t cpu_pd_en : 1;
uint32_t aon_pd_en : 1;
uint32_t top_pd_en : 1;
};
uint32_t val;
} pmu_hp_dig_power_reg_t;
typedef union {
struct {
uint32_t reserved0: 30;
uint32_t code : 2;
};
uint32_t val;
} pmu_hp_icg_modem_reg_t;
typedef union {
struct {
uint32_t reserved0 : 24;
uint32_t uart_wakeup_en : 1;
uint32_t lp_pad_hold_all: 1;
uint32_t hp_pad_hold_all: 1;
uint32_t dig_pad_slp_sel: 1;
uint32_t dig_pause_wdt : 1;
uint32_t dig_cpu_stall : 1;
uint32_t reserved1 : 2;
};
uint32_t val;
} pmu_hp_sys_cntl_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t i2c_iso_en : 1;
uint32_t i2c_retention: 1;
uint32_t xpd_bb_i2c : 1;
uint32_t xpd_bbpll_i2c: 1;
uint32_t xpd_bbpll : 1;
uint32_t reserved1 : 1;
};
uint32_t val;
} pmu_hp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 25;
uint32_t xpd_bias : 1;
uint32_t dbg_atten : 4;
uint32_t pd_cur : 1;
uint32_t bias_sleep: 1;
};
uint32_t val;
} pmu_hp_bias_reg_t;
typedef union {
struct { /* HP: Active State */
uint32_t reserved0 : 4;
uint32_t hp_sleep2active_backup_modem_clk_code: 2;
uint32_t hp_modem2active_backup_modem_clk_code: 2;
uint32_t reserved1 : 2;
uint32_t hp_active_retention_mode : 1;
uint32_t hp_sleep2active_retention_en : 1;
uint32_t hp_modem2active_retention_en : 1;
uint32_t reserved2 : 1;
uint32_t hp_sleep2active_backup_clk_sel : 2;
uint32_t hp_modem2active_backup_clk_sel : 2;
uint32_t reserved3 : 2;
uint32_t hp_sleep2active_backup_mode : 3;
uint32_t hp_modem2active_backup_mode : 3;
uint32_t reserved4 : 3;
uint32_t hp_sleep2active_backup_en : 1;
uint32_t hp_modem2active_backup_en : 1;
uint32_t reserved5 : 1;
};
struct { /* HP: Modem State */
uint32_t reserved6 : 4;
uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
uint32_t reserved7 : 4;
uint32_t hp_modem_retention_mode : 1;
uint32_t hp_sleep2modem_retention_en : 1;
uint32_t reserved8 : 2;
uint32_t hp_sleep2modem_backup_clk_sel : 2;
uint32_t reserved9 : 4;
uint32_t hp_sleep2modem_backup_mode : 3;
uint32_t reserved10 : 6;
uint32_t hp_sleep2modem_backup_en : 1;
uint32_t reserved11 : 2;
};
struct { /* HP: Sleep State */
uint32_t reserved12 : 6;
uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
uint32_t hp_active2sleep_backup_modem_clk_code: 2;
uint32_t hp_sleep_retention_mode : 1;
uint32_t reserved13 : 1;
uint32_t hp_modem2sleep_retention_en : 1;
uint32_t hp_active2sleep_retention_en : 1;
uint32_t reserved14 : 2;
uint32_t hp_modem2sleep_backup_clk_sel : 2;
uint32_t hp_active2sleep_backup_clk_sel : 2;
uint32_t reserved15 : 3;
uint32_t hp_modem2sleep_backup_mode : 3;
uint32_t hp_active2sleep_backup_mode : 3;
uint32_t reserved16 : 1;
uint32_t hp_modem2sleep_backup_en : 1;
uint32_t hp_active2sleep_backup_en : 1;
};
uint32_t val;
} pmu_hp_backup_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t dig_sysclk_nodiv: 1;
uint32_t icg_sysclk_en : 1;
uint32_t sysclk_slp_sel : 1;
uint32_t icg_slp_sel : 1;
uint32_t dig_sysclk_sel : 2;
};
uint32_t val;
} pmu_hp_sysclk_reg_t;
typedef union {
struct {
uint32_t reserved0 : 4; /* Only HP_ACTIVE modem under hp system is valid */
uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */
uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */
uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */
uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */
uint32_t slp_mem_xpd : 1;
uint32_t slp_logic_xpd : 1;
uint32_t xpd : 1;
uint32_t slp_mem_dbias : 4;
uint32_t slp_logic_dbias: 4;
uint32_t dbias : 5;
};
uint32_t val;
} pmu_hp_regulator0_reg_t;
typedef union {
struct {
uint32_t reserved0: 8;
uint32_t drv_b : 24;
};
uint32_t val;
} pmu_hp_regulator1_reg_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t xpd_xtal : 1;
};
uint32_t val;
} pmu_hp_xtal_reg_t;
typedef struct pmu_hp_hw_regmap_t{
pmu_hp_dig_power_reg_t dig_power;
uint32_t icg_func;
uint32_t icg_apb;
pmu_hp_icg_modem_reg_t icg_modem;
pmu_hp_sys_cntl_reg_t syscntl;
pmu_hp_clk_power_reg_t clk_power;
pmu_hp_bias_reg_t bias;
pmu_hp_backup_reg_t backup;
uint32_t backup_clk;
pmu_hp_sysclk_reg_t sysclk;
pmu_hp_regulator0_reg_t regulator0;
pmu_hp_regulator1_reg_t regulator1;
pmu_hp_xtal_reg_t xtal;
} pmu_hp_hw_regmap_t;
/** */
typedef union {
struct {
uint32_t reserved0: 21;
uint32_t slp_xpd : 1;
uint32_t xpd : 1;
uint32_t slp_dbias: 4;
uint32_t dbias : 5;
};
uint32_t val;
} pmu_lp_regulator0_reg_t;
typedef union {
struct {
uint32_t reserved0: 28;
uint32_t drv_b : 4;
};
uint32_t val;
} pmu_lp_regulator1_reg_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t xpd_xtal : 1;
};
uint32_t val;
} pmu_lp_xtal_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t mem_dslp : 1;
uint32_t peri_pd_en: 1;
};
uint32_t val;
} pmu_lp_dig_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 28;
uint32_t xpd_xtal32k: 1;
uint32_t xpd_rc32k : 1;
uint32_t xpd_fosc : 1;
uint32_t pd_osc : 1;
};
uint32_t val;
} pmu_lp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 25;
uint32_t xpd_bias : 1;
uint32_t dbg_atten : 4;
uint32_t pd_cur : 1;
uint32_t bias_sleep: 1;
};
uint32_t val;
} pmu_lp_bias_reg_t;
typedef struct pmu_lp_hw_regmap_t{
pmu_lp_regulator0_reg_t regulator0;
pmu_lp_regulator1_reg_t regulator1;
pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */
pmu_lp_dig_power_reg_t dig_power;
pmu_lp_clk_power_reg_t clk_power;
pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */
} pmu_lp_hw_regmap_t;
typedef union {
struct {
uint32_t tie_low_global_bbpll_icg : 1;
uint32_t tie_low_global_xtal_icg : 1;
uint32_t tie_low_i2c_retention : 1;
uint32_t tie_low_xpd_bb_i2c : 1;
uint32_t tie_low_xpd_bbpll_i2c : 1;
uint32_t tie_low_xpd_bbpll : 1;
uint32_t tie_low_xpd_xtal : 1;
uint32_t reserved0 : 18;
uint32_t tie_high_global_bbpll_icg: 1;
uint32_t tie_high_global_xtal_icg : 1;
uint32_t tie_high_i2c_retention : 1;
uint32_t tie_high_xpd_bb_i2c : 1;
uint32_t tie_high_xpd_bbpll_i2c : 1;
uint32_t tie_high_xpd_bbpll : 1;
uint32_t tie_high_xpd_xtal : 1;
};
uint32_t val;
} pmu_imm_hp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 28;
uint32_t update_dig_icg_switch: 1;
uint32_t tie_low_icg_slp_sel : 1;
uint32_t tie_high_icg_slp_sel : 1;
uint32_t update_dig_sysclk_sel: 1;
};
uint32_t val;
} pmu_imm_sleep_sysclk_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_func_en: 1;
};
uint32_t val;
} pmu_imm_hp_func_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_apb_en: 1;
};
uint32_t val;
} pmu_imm_hp_apb_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_modem_en: 1;
};
uint32_t val;
} pmu_imm_modem_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t tie_low_lp_rootclk_sel : 1;
uint32_t tie_high_lp_rootclk_sel: 1;
};
uint32_t val;
} pmu_imm_lp_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 28;
uint32_t tie_high_lp_pad_hold_all: 1;
uint32_t tie_low_lp_pad_hold_all : 1;
uint32_t tie_high_hp_pad_hold_all: 1;
uint32_t tie_low_hp_pad_hold_all : 1;
};
uint32_t val;
} pmu_imm_pad_hold_all_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t tie_high_i2c_iso_en: 1;
uint32_t tie_low_i2c_iso_en : 1;
};
uint32_t val;
} pmu_imm_i2c_isolate_reg_t;
typedef struct pmu_imm_hw_regmap_t{
pmu_imm_hp_clk_power_reg_t clk_power;
pmu_imm_sleep_sysclk_reg_t sleep_sysclk;
pmu_imm_hp_func_icg_reg_t hp_func_icg;
pmu_imm_hp_apb_icg_reg_t hp_apb_icg;
pmu_imm_modem_icg_reg_t modem_icg;
pmu_imm_lp_icg_reg_t lp_icg;
pmu_imm_pad_hold_all_reg_t pad_hold_all;
pmu_imm_i2c_isolate_reg_t i2c_iso;
} pmu_imm_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0 : 5;
uint32_t powerdown_timer: 9;
uint32_t powerup_timer : 9;
uint32_t wait_timer : 9;
};
uint32_t val;
} pmu_power_wait_timer0_reg_t;
typedef union {
struct {
uint32_t reserved0 : 9;
uint32_t powerdown_timer: 7;
uint32_t powerup_timer : 7;
uint32_t wait_timer : 9;
};
uint32_t val;
} pmu_power_wait_timer1_reg_t;
typedef union {
struct {
uint32_t force_reset : 1;
uint32_t force_iso : 1;
uint32_t force_pu : 1;
uint32_t force_no_reset: 1;
uint32_t force_no_iso : 1;
uint32_t force_pd : 1;
uint32_t mask : 5; /* Invalid of lp peripherals */
uint32_t reserved0 : 16; /* Invalid of lp peripherals */
uint32_t pd_mask : 5; /* Invalid of lp peripherals */
};
uint32_t val;
} pmu_power_domain_cntl_reg_t;
typedef union {
struct {
uint32_t force_hp_mem_iso : 4;
uint32_t force_hp_mem_pd : 4;
uint32_t reserved0 : 16;
uint32_t force_hp_mem_no_iso: 4;
uint32_t force_hp_mem_pu : 4;
};
uint32_t val;
} pmu_power_memory_cntl_reg_t;
typedef union {
struct {
uint32_t mem2_pd_mask: 5;
uint32_t mem1_pd_mask: 5;
uint32_t mem0_pd_mask: 5;
uint32_t reserved0 : 2;
uint32_t mem2_mask : 5;
uint32_t mem1_mask : 5;
uint32_t mem0_mask : 5;
};
uint32_t val;
} pmu_power_memory_mask_reg_t;
typedef union {
struct {
uint32_t force_hp_pad_no_iso_all: 1;
uint32_t force_hp_pad_iso_all : 1;
uint32_t reserved0 : 30;
};
uint32_t val;
} pmu_power_hp_pad_reg_t;
typedef union {
struct {
uint32_t reserved0 : 18;
uint32_t pwr_wait : 11;
uint32_t pwr_sw : 2;
uint32_t pwr_sel_sw: 1;
};
uint32_t val;
} pmu_power_vdd_spi_cntl_reg_t;
typedef union {
struct {
uint32_t wait_xtal_stable: 16;
uint32_t wait_pll_stable : 16;
};
uint32_t val;
} pmu_power_clk_wait_cntl_reg_t;
typedef struct pmu_power_hw_regmap_t{
pmu_power_wait_timer0_reg_t wait_timer0;
pmu_power_wait_timer1_reg_t wait_timer1;
pmu_power_domain_cntl_reg_t hp_pd[5];
pmu_power_domain_cntl_reg_t lp_peri;
pmu_power_memory_cntl_reg_t mem_cntl;
pmu_power_memory_mask_reg_t mem_mask;
pmu_power_hp_pad_reg_t hp_pad;
pmu_power_vdd_spi_cntl_reg_t vdd_spi;
pmu_power_clk_wait_cntl_reg_t clk_wait;
} pmu_power_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t sleep_req: 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl0_reg_t;
typedef union {
struct {
uint32_t sleep_reject_ena: 31;
uint32_t slp_reject_en : 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl1_reg_t;
typedef union {
struct {
uint32_t lp_min_slp_val: 8;
uint32_t hp_min_slp_val: 8;
uint32_t sleep_prt_sel : 2;
uint32_t reserved0 : 14;
};
uint32_t val;
} pmu_slp_wakeup_cntl3_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t slp_reject_cause_clr: 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl4_reg_t;
typedef union {
struct {
uint32_t modem_wait_target : 20;
uint32_t reserved0 : 4;
uint32_t lp_ana_wait_target: 8;
};
uint32_t val;
} pmu_slp_wakeup_cntl5_reg_t;
typedef union {
struct {
uint32_t soc_wakeup_wait : 20;
uint32_t reserved0 : 10;
uint32_t soc_wakeup_wait_cfg: 2;
};
uint32_t val;
} pmu_slp_wakeup_cntl6_reg_t;
typedef union {
struct {
uint32_t reserved0 : 16;
uint32_t ana_wait_target: 16;
};
uint32_t val;
} pmu_slp_wakeup_cntl7_reg_t;
typedef struct pmu_wakeup_hw_regmap_t{
pmu_slp_wakeup_cntl0_reg_t cntl0;
pmu_slp_wakeup_cntl1_reg_t cntl1;
uint32_t cntl2;
pmu_slp_wakeup_cntl3_reg_t cntl3;
pmu_slp_wakeup_cntl4_reg_t cntl4;
pmu_slp_wakeup_cntl5_reg_t cntl5;
pmu_slp_wakeup_cntl6_reg_t cntl6;
pmu_slp_wakeup_cntl7_reg_t cntl7;
uint32_t status0;
uint32_t status1;
} pmu_wakeup_hw_regmap_t;
typedef union {
struct {
uint32_t i2c_por_wait_target: 8;
uint32_t reserved0 : 24;
};
uint32_t val;
} pmu_hp_clk_poweron_reg_t;
typedef union {
struct {
uint32_t modify_icg_cntl_wait: 8;
uint32_t switch_icg_cntl_wait: 8;
uint32_t reserved0 : 16;
};
uint32_t val;
} pmu_hp_clk_cntl_reg_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t por_done : 1;
};
uint32_t val;
} pmu_por_status_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t perif_i2c_rstb: 1;
uint32_t xpd_perif_i2c : 1;
uint32_t xpd_txrf_i2c : 1;
uint32_t xpd_rfrx_pbus : 1;
uint32_t xpd_ckgen_i2c : 1;
uint32_t xpd_pll_i2c : 1;
};
uint32_t val;
} pmu_rf_pwc_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t backup_sysclk_nodiv: 1;
};
uint32_t val;
} pmu_backup_cfg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 27;
uint32_t lp_cpu_exc: 1;
uint32_t sdio_idle : 1;
uint32_t sw : 1;
uint32_t reject : 1;
uint32_t wakeup : 1;
};
uint32_t val;
} pmu_hp_intr_reg_t;
typedef struct pmu_hp_ext_hw_regmap_t{
pmu_hp_clk_poweron_reg_t clk_poweron;
pmu_hp_clk_cntl_reg_t clk_cntl;
pmu_por_status_reg_t por_status;
pmu_rf_pwc_reg_t rf_pwc;
pmu_backup_cfg_reg_t backup_cfg;
pmu_hp_intr_reg_t int_raw;
pmu_hp_intr_reg_t int_st;
pmu_hp_intr_reg_t int_ena;
pmu_hp_intr_reg_t int_clr;
} pmu_hp_ext_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0 : 20;
uint32_t lp_cpu_wakeup : 1;
uint32_t modem_switch_active_end : 1;
uint32_t sleep_switch_active_end : 1;
uint32_t sleep_switch_modem_end : 1;
uint32_t modem_switch_sleep_end : 1;
uint32_t active_swtich_sleep_end : 1;
uint32_t modem_switch_active_start: 1;
uint32_t sleep_switch_active_start: 1;
uint32_t sleep_switch_modem_start : 1;
uint32_t modem_switch_sleep_start : 1;
uint32_t active_switch_sleep_start: 1;
uint32_t sw_trigger : 1;
};
uint32_t val;
} pmu_lp_intr_reg_t;
typedef union {
struct {
uint32_t waiti_rdy : 1;
uint32_t stall_rdy : 1;
uint32_t reserved0 : 16;
uint32_t force_stall : 1;
uint32_t slp_waiti_flag_en : 1;
uint32_t slp_stall_flag_en : 1;
uint32_t slp_stall_wait : 8;
uint32_t slp_stall_en : 1;
uint32_t slp_reset_en : 1;
uint32_t slp_bypass_intr_en: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr0_reg_t;
typedef union {
struct {
uint32_t wakeup_en: 16;
uint32_t reserved0: 15;
uint32_t sleep_req: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr1_reg_t;
typedef struct pmu_lp_ext_hw_regmap_t{
pmu_lp_intr_reg_t int_raw;
pmu_lp_intr_reg_t int_st;
pmu_lp_intr_reg_t int_ena;
pmu_lp_intr_reg_t int_clr;
pmu_lp_cpu_pwr0_reg_t pwr0;
pmu_lp_cpu_pwr1_reg_t pwr1;
} pmu_lp_ext_hw_regmap_t;
typedef struct pmu_dev_t{
volatile pmu_hp_hw_regmap_t hp_sys[3];
volatile pmu_lp_hw_regmap_t lp_sys[2];
volatile pmu_imm_hw_regmap_t imm;
volatile pmu_power_hw_regmap_t power;
volatile pmu_wakeup_hw_regmap_t wakeup;
volatile pmu_hp_ext_hw_regmap_t hp_ext;
volatile pmu_lp_ext_hw_regmap_t lp_ext;
union {
struct {
uint32_t reserved0 : 30;
volatile uint32_t lp_trigger_hp: 1;
volatile uint32_t hp_trigger_lp: 1;
};
volatile uint32_t val;
} hp_lp_cpu_comm;
union {
struct {
uint32_t reserved0 : 31;
volatile uint32_t dig_regulator_en_cal: 1;
};
volatile uint32_t val;
} hp_regulator_cfg;
union {
struct {
uint32_t reserved0 : 11;
volatile uint32_t last_st : 7;
volatile uint32_t target_st : 7;
volatile uint32_t current_st: 7;
};
volatile uint32_t val;
} main_state;
union {
struct {
uint32_t reserved0: 13;
volatile uint32_t backup_st: 5;
volatile uint32_t lp_pwr_st: 5;
volatile uint32_t hp_pwr_st: 9;
};
volatile uint32_t val;
} pwr_state;
union {
struct {
volatile uint32_t stable_xpd_bbpll : 1;
volatile uint32_t stable_xpd_xtal : 1;
volatile uint32_t reserved0 : 13;
volatile uint32_t sysclk_slp_sel : 1;
volatile uint32_t sysclk_sel : 2;
volatile uint32_t sysclk_nodiv : 1;
volatile uint32_t icg_sysclk_en : 1;
volatile uint32_t icg_modem_switch : 1;
volatile uint32_t icg_modem_code : 2;
volatile uint32_t icg_slp_sel : 1;
volatile uint32_t icg_global_xtal : 1;
volatile uint32_t icg_global_pll : 1;
volatile uint32_t ana_i2c_iso_en : 1;
volatile uint32_t ana_i2c_retention: 1;
volatile uint32_t ana_xpd_bb_i2c : 1;
volatile uint32_t ana_xpd_bbpll_i2c: 1;
volatile uint32_t ana_xpd_bbpll : 1;
volatile uint32_t ana_xpd_xtal : 1;
};
volatile uint32_t val;
} clk_state0;
volatile uint32_t clk_state1;
volatile uint32_t clk_state2;
union {
struct {
uint32_t reserved0 : 31;
volatile uint32_t stable_vdd_spi_pwr_drv: 1;
};
volatile uint32_t val;
} vdd_spi_status;
uint32_t reserved[150];
union {
struct {
volatile uint32_t pmu_date: 31;
volatile uint32_t clk_en : 1;
};
volatile uint32_t val;
} date;
} pmu_dev_t;
extern pmu_dev_t PMU;
#ifndef __cplusplus
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
//_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @brief Peripheral 0 Modules
*
*/
#define DR_REG_UART0_BASE 0x60000000
#define DR_REG_UART1_BASE 0x60001000
#define DR_REG_SPIMEM0_BASE 0x60002000
#define DR_REG_SPIMEM1_BASE 0x60003000
#define DR_REG_I2C_BASE 0x60004000
#define DR_REG_UHCI_BASE 0x60005000
#define DR_REG_RMT_BASE 0x60006000
#define DR_REG_LEDC_BASE 0x60007000
#define DR_REG_TIMERG0_BASE 0x60008000
#define DR_REG_TIMERG1_BASE 0x60009000
#define DR_REG_SYSTIMER_BASE 0x6000A000
#define DR_REG_TWAI0_BASE 0x6000B000
#define DR_REG_I2S_BASE 0x6000C000
#define DR_REG_TWAI1_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM_BASE 0x60014000
#define DR_REG_PARL_IO_BASE 0x60015000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
/**
* @brief Peripheral 1 Modules
*
*/
#define DR_REG_AHB_DMA_BASE 0x60080000
#define DR_REG_GPSPI2_BASE 0x60081000
#define DR_REG_BITSCRAMBLER_BASE 0x60082000
#define DR_REG_KEYMNG_BASE 0x60087000
#define DR_REG_AES_BASE 0x60088000
#define DR_REG_SHA_BASE 0x60089000
#define DR_REG_RSA_BASE 0x6008A000
#define DR_REG_ECC_MULT_BASE 0x6008B000
#define DR_REG_DS_BASE 0x6008C000
#define DR_REG_HMAC_BASE 0x6008D000
#define DR_REG_ECDSA_BASE 0x6008E000
/**
* @brief HP Top Peripheral Modules
*
*/
#define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_MISC_BASE 0x6009F000
/**
* @brief Modem Module
*
*/
#define DR_REG_MODEM0_BASE 0x600A0000
#define DR_REG_MODEM1_BASE 0x600AC000
#define DR_REG_MODEM_PWR0_BASE 0x600AD000
#define DR_REG_MODEM_PWR1_BASE 0x600AF000
#define PWDET_CONF_REG 0x600A0810
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800
/**
* @brief LP System (RTC) Modules
*
*/
#define DR_REG_PMU_BASE 0x600B0000
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_LP_TIMER_BASE 0x600B0C00
#define DR_REG_LP_AON_BASE 0x600B1000
#define DR_REG_LP_UART_BASE 0x600B1400
#define DR_REG_LP_I2C_BASE 0x600B1800
#define DR_REG_LP_WDT_BASE 0x600B1C00
#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400
#define DR_REG_LPPERI_BASE 0x600B2800
#define DR_REG_LP_ANA_BASE 0x600B2C00
#define DR_REG_HUK_BASE 0x600B3000
#define DR_REG_LP_TEE_BASE 0x600B3400
#define DR_REG_LP_APM_BASE 0x600B3800
#define DR_REG_LP_IO_MUX_BASE 0x600B4000
#define DR_REG_LP_GPIO_BASE 0x600B4400
#define DR_REG_EFUSE_BASE 0x600B4800
#define DR_REG_OTP_DEBUG_BASE 0x600B4D00
/**
* @brief CPU Peripheral Modules
*
*/
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: FIFO R/W registers */
/** Type of chndata register
* The read and write data register for channel 0 by APB FIFO access.
*/
typedef union {
struct {
/** chndata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chndata:32;
};
uint32_t val;
} rmt_chndata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
* Configuration register 0 for channel 0
*/
typedef union {
struct {
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Configures whether to enable sending data in channel n. \\
* 0: No effect\\
* 1: Enable\\
*/
uint32_t tx_start_chn:1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Configures whether to reset RAM read address accessed by the transmitter for
* channel n. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t mem_rd_rst_chn:1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Configures whether to reset RAM W/R address accessed by APB FIFO for channel n. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t apb_mem_rst_chn:1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Configures whether to enable continuous TX mode for channel n. \\
* 0: No Effect\\
* 1: Enable\\
* In this mode, the transmitter starts transmission from the first data. If an
* end-marker is encountered, the transmitter starts transmitting data from the first
* data again. if no end-marker is encountered, the transmitter starts transmitting
* the first data again when the last data is transmitted.\\
*/
uint32_t tx_conti_mode_chn:1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* Configures whether to enable wrap TX mode for channel n. \\
* 0: No effect\\
* 1: Enable\\
* In this mode, if the TX data size is larger than the channel's RAM block size, the
* transmitter continues transmitting the first data to the last data in loops.\\
*/
uint32_t mem_tx_wrap_en_chn:1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* Configures the level of output signal for channel n when the transmitter is in idle
* state.
*/
uint32_t idle_out_lv_chn:1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* Configures whether to enable the output for channel n in idle state. \\
* 0: No effect\\
* 1: Enable\\
*/
uint32_t idle_out_en_chn:1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Configures whether to stop the transmitter of channel n sending data out. \\
* 0: No effect\\
* 1: Stop\\
*/
uint32_t tx_stop_chn:1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* Configures the divider for clock of channel n. \\
* Measurement unit: rmt_sclk\\
*/
uint32_t div_cnt_chn:8;
/** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
* Configures the maximum number of memory blocks allocated to channel n.
*/
uint32_t mem_size_chn:3;
uint32_t reserved_19:1;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* Configures whether to add carrier modulation on the output signal only at
* data-sending state for channel n. \\
* 0: Add carrier modulation on the output signal at data-sending state and idle state
* for channel n\\
* 1: Add carrier modulation on the output signal only at data-sending state for
* channel n\\
* Only valid when RMT_CARRIER_EN_CHn is 1.\\
*/
uint32_t carrier_eff_en_chn:1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* Configures whether to enable the carrier modulation on output signal for channel n.
* \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t carrier_en_chn:1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* Configures the position of carrier wave for channel n. \\
* 0: Add carrier wave on low level\\
* 1: Add carrier wave on high level\\
*/
uint32_t carrier_out_lv_chn:1;
/** afifo_rst_chn : WT; bitpos: [23]; default: 0;
* Reserved
*/
uint32_t afifo_rst_chn:1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* Synchronization bit for channel n.
*/
uint32_t conf_update_chn:1;
uint32_t reserved_25:7;
};
uint32_t val;
} rmt_chnconf0_reg_t;
/** Type of chmconf0 register
* Configuration register 0 for channel 2
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* Configures the clock divider of channel m. \\
* Measurement unit: rmt_sclk\\
*/
uint32_t div_cnt_chm:8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* Configures RX threshold. \\
* When no edge is detected on the input signal for continuous clock cycles longer
* than this field value, the receiver stops receiving data.\\
* Measurement unit: clk_div\\
*/
uint32_t idle_thres_chm:15;
/** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
* Configures the maximum number of memory blocks allocated to channel m.
*/
uint32_t mem_size_chm:3;
uint32_t reserved_26:2;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* Configures whether to enable carrier modulation on output signal for channel m. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t carrier_en_chm:1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* Configures the position of carrier wave for channel m. \\
* 0: Add carrier wave on low level\\
* 1: Add carrier wave on high level\\
*/
uint32_t carrier_out_lv_chm:1;
uint32_t reserved_30:2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Configuration register 1 for channel 2
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Configures whether to enable the receiver to start receiving data in channel m. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t rx_en_chm:1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Configures whether to reset RAM write address accessed by the receiver for channel
* m. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t mem_wr_rst_chm:1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Configures whether to reset RAM W/R address accessed by APB FIFO for channel m. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t apb_mem_rst_chm:1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* Configures the ownership of channel m's RAM block. \\
* 0: APB bus is using the RAM\\
* 1: Receiver is using the RAM\\
*/
uint32_t mem_owner_chm:1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* Configures whether to enable the receiver's filter for channel m. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t rx_filter_en_chm:1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Configures whether the receiver, when receiving data, ignores the input pulse when
* its width is shorter than this register value in units of rmt_sclk cycles. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t rx_filter_thres_chm:8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* Configures whether to enable wrap RX mode for channel m. \\
* 0: Disable\\
* 1: Enable\\
* In this mode, if the RX data size is larger than channel m's RAM block size, the
* receiver stores the RX data from the first address to the last address in loops.\\
*/
uint32_t mem_rx_wrap_en_chm:1;
/** afifo_rst_chm : WT; bitpos: [14]; default: 0;
* Reserved
*/
uint32_t afifo_rst_chm:1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* Synchronization bit for channel m.
*/
uint32_t conf_update_chm:1;
uint32_t reserved_16:16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of sys_conf register
* Configuration register for RMT APB
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* Configures the memory access mode. \\
* 0: Access memory by FIFO\\
* 1: Access memory directly\\
*/
uint32_t apb_fifo_mask:1;
/** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
* Configures whether to enable the clock for RMT memory. \\
* 0: Disable\\
* 1: Enable\\
*/
uint32_t mem_clk_force_on:1;
/** mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to power down RMT memory.
*/
uint32_t mem_force_pd:1;
/** mem_force_pu : R/W; bitpos: [3]; default: 0;
* 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
* when RMT is in light sleep mode.
*/
uint32_t mem_force_pu:1;
/** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
* the integral part of the fractional divisor
*/
uint32_t sclk_div_num:8;
/** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
* the numerator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_a:6;
/** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
* the denominator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_b:6;
/** sclk_sel : R/W; bitpos: [25:24]; default: 1;
* choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
*/
uint32_t sclk_sel:2;
/** sclk_active : R/W; bitpos: [26]; default: 1;
* rmt_sclk switch
*/
uint32_t sclk_active:1;
uint32_t reserved_27:4;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Configures whether to enable signal of RMT register clock gate. \\
* 0: Power down the drive clock of registers\\
* 1: Power up the drive clock of registers\\
*/
uint32_t clk_en:1;
};
uint32_t val;
} rmt_sys_conf_reg_t;
/** Type of ref_cnt_rst register
* RMT clock divider reset register
*/
typedef union {
struct {
/** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
* This register is used to reset the clock divider of CHANNEL0.
*/
uint32_t ref_cnt_rst_ch0:1;
/** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
* This register is used to reset the clock divider of CHANNEL1.
*/
uint32_t ref_cnt_rst_ch1:1;
/** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
* This register is used to reset the clock divider of CHANNEL2.
*/
uint32_t ref_cnt_rst_ch2:1;
/** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
* This register is used to reset the clock divider of CHANNEL3.
*/
uint32_t ref_cnt_rst_ch3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} rmt_ref_cnt_rst_reg_t;
/** Group: Status registers */
/** Type of chnstatus register
* Channel 0 status register
*/
typedef union {
struct {
/** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* Represents the memory address offset when transmitter of channel n is using the RAM.
*/
uint32_t mem_raddr_ex_chn:9;
/** state_chn : RO; bitpos: [11:9]; default: 0;
* Represents the FSM status of channel n.
*/
uint32_t state_chn:3;
/** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
* Represents the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_chn:9;
/** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
* Represents whether the offset address exceeds memory size when reading via APB bus.
* \\
* 0: Not exceed\\
* 1: Exceed\\
*/
uint32_t apb_mem_rd_err_chn:1;
/** mem_empty_chn : RO; bitpos: [22]; default: 0;
* Represents whether the TX data size exceeds the memory size and the wrap TX mode is
* disabled. \\
* 0: Not exceed\\
* 1: Exceed\\
*/
uint32_t mem_empty_chn:1;
/** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
* Represents whether the offset address exceeds memory size (overflows) when writes
* via APB bus. \\
* 0: Not exceed\\
* 1: Exceed\\
*/
uint32_t apb_mem_wr_err_chn:1;
/** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
* Represents the memory address offset when reading RAM over APB bus.
*/
uint32_t apb_mem_raddr_chn:8;
};
uint32_t val;
} rmt_chnstatus_reg_t;
/** Type of chmstatus register
* Channel 2 status register
*/
typedef union {
struct {
/** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
* Represents the memory address offset when receiver of channel m is using the RAM.
*/
uint32_t mem_waddr_ex_chm:9;
uint32_t reserved_9:3;
/** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
* Represents the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_chm:9;
uint32_t reserved_21:1;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* Represents the FSM status of channel m.
*/
uint32_t state_chm:3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* Represents whether the ownership of memory block is wrong. \\
* 0: The ownership of memory block is correct\\
* 1: The ownership of memory block is wrong\\
*/
uint32_t mem_owner_err_chm:1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* Represents whether the receiver receives more data than the memory can fit. \\
* 0: The receiver does not receive more data than the memory can fit\\
* 1: The receiver receives more data than the memory can fit\\
*/
uint32_t mem_full_chm:1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* Represents whether the offset address exceeds memory size (overflows) when reads
* RAM via APB bus. \\
* 0: Not exceed\\
* 1: Exceed\\
*/
uint32_t apb_mem_rd_err_chm:1;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_chmstatus_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmission done.
*/
uint32_t ch0_tx_end_int_raw:1;
/** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmission done.
*/
uint32_t ch1_tx_end_int_raw:1;
/** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when reception done.
*/
uint32_t ch2_rx_end_int_raw:1;
/** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when reception done.
*/
uint32_t ch3_rx_end_int_raw:1;
/** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch0_err_int_raw:1;
/** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch1_err_int_raw:1;
/** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch2_err_int_raw:1;
/** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch3_err_int_raw:1;
/** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch0_tx_thr_event_int_raw:1;
/** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch1_tx_thr_event_int_raw:1;
/** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch2_rx_thr_event_int_raw:1;
/** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch3_rx_thr_event_int_raw:1;
/** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch0_tx_loop_int_raw:1;
/** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch1_tx_loop_int_raw:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_st:1;
/** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_st:1;
/** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_st:1;
/** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_st:1;
/** ch0_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_st:1;
/** ch1_err_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_st:1;
/** ch2_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_st:1;
/** ch3_err_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_st:1;
/** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_st:1;
/** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_st:1;
/** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_st:1;
/** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_st:1;
/** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_st:1;
/** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_ena:1;
/** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_ena:1;
/** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_ena:1;
/** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_ena:1;
/** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_ena:1;
/** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_ena:1;
/** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_ena:1;
/** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_ena:1;
/** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_ena:1;
/** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_ena:1;
/** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_ena:1;
/** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_ena:1;
/** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_ena:1;
/** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_ena:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear theCH0_TX_END_INT interrupt.
*/
uint32_t ch0_tx_end_int_clr:1;
/** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear theCH1_TX_END_INT interrupt.
*/
uint32_t ch1_tx_end_int_clr:1;
/** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear theCH2_RX_END_INT interrupt.
*/
uint32_t ch2_rx_end_int_clr:1;
/** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear theCH3_RX_END_INT interrupt.
*/
uint32_t ch3_rx_end_int_clr:1;
/** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch0_err_int_clr:1;
/** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch1_err_int_clr:1;
/** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch2_err_int_clr:1;
/** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch3_err_int_clr:1;
/** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch0_tx_thr_event_int_clr:1;
/** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch1_tx_thr_event_int_clr:1;
/** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch2_rx_thr_event_int_clr:1;
/** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch3_rx_thr_event_int_clr:1;
/** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear theCH0_TX_LOOP_INT interrupt.
*/
uint32_t ch0_tx_loop_int_clr:1;
/** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear theCH1_TX_LOOP_INT interrupt.
*/
uint32_t ch1_tx_loop_int_clr:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_clr_reg_t;
/** Group: Carrier wave duty cycle registers */
/** Type of chncarrier_duty register
* Duty cycle configuration register for channel 0
*/
typedef union {
struct {
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* Configures carrier wave's low level clock period for channel n. \\
* Measurement unit: rmt_sclk\\
*/
uint32_t carrier_low_chn:16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* Configures carrier wave's high level clock period for channel n. \\
* Measurement unit: rmt_sclk\\
*/
uint32_t carrier_high_chn:16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
/** Type of chm_rx_carrier_rm register
* Carrier remove register for channel 2
*/
typedef union {
struct {
/** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
* Configures the low level period in a carrier modulation mode for channel m. \\
* The low level period in a carrier modulation mode is (RMT_CARRIER_LOW_THRES_CHm +
* 1) for channel m. \\
* Measurement unit: clk_div\\
*/
uint32_t carrier_low_thres_chm:16;
/** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
* Configures the high level period in a carrier modulation mode for channel m. \\
* The high level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.\\
* Measurement unit: clk_div\\
*/
uint32_t carrier_high_thres_chm:16;
};
uint32_t val;
} rmt_chm_rx_carrier_rm_reg_t;
/** Group: Tx event configuration registers */
/** Type of chn_tx_lim register
* Configuration register for channel 0 TX event
*/
typedef union {
struct {
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* Configures the maximum entries that channel n can send out.
*/
uint32_t tx_lim_chn:9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* Configures the maximum loop count when Continuous TX mode is valid.
*/
uint32_t tx_loop_num_chn:10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* Configures whether to enable loop count. \\
* 0: No effect\\
* 1: Enable\\
*/
uint32_t tx_loop_cnt_en_chn:1;
/** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
* Configures whether to reset the loop count when tx_conti_mode is valid. \\
* 0: No effect\\
* 1: Reset\\
*/
uint32_t loop_count_reset_chn:1;
/** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
* Configures whether to enable the loop send stop function after the loop counter
* counts to loop number for channel n. \\
* 0: No effect\\
* 1: Enable\\
*/
uint32_t loop_stop_en_chn:1;
uint32_t reserved_22:10;
};
uint32_t val;
} rmt_chn_tx_lim_reg_t;
/** Type of tx_sim register
* RMT TX synchronous register
*/
typedef union {
struct {
/** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
* Set this bit to enable CHANNEL0 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch0:1;
/** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
* Set this bit to enable CHANNEL1 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch1:1;
/** tx_sim_en : R/W; bitpos: [2]; default: 0;
* This register is used to enable multiple of channels to start sending data
* synchronously.
*/
uint32_t tx_sim_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rmt_tx_sim_reg_t;
/** Group: Rx event configuration registers */
/** Type of chm_rx_lim register
* Configuration register for channel 2 RX event
*/
typedef union {
struct {
/** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t rx_lim_chm:9;
uint32_t reserved_9:23;
};
uint32_t val;
} rmt_chm_rx_lim_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34636307;
* This is the version register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_date_reg_t;
typedef struct {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
volatile rmt_sys_conf_reg_t sys_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
uint32_t reserved_074[22];
volatile rmt_date_reg_t date;
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifndef __cplusplus
_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

212
components/soc/esp32c5/mp/include/soc/rsa_reg.h Normal file
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@@ -0,0 +1,212 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
* Represents M
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
* Represents Z
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM register
* Represents Y
*/
#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
#define RSA_Y_MEM_SIZE_BYTES 16
/** RSA_X_MEM register
* Represents X
*/
#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
#define RSA_X_MEM_SIZE_BYTES 16
/** RSA_M_PRIME_REG register
* Represents M'
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Represents M'
*/
#define RSA_M_PRIME 0xFFFFFFFFU
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFFU
#define RSA_M_PRIME_S 0
/** RSA_MODE_REG register
* Configures RSA length
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
#define RSA_MODE 0x0000007FU
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007FU
#define RSA_MODE_S 0
/** RSA_QUERY_CLEAN_REG register
* RSA initialization status
*/
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.\\
* 0: Not complete\\
* 1: Completed\\
*/
#define RSA_QUERY_CLEAN (BIT(0))
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
#define RSA_QUERY_CLEAN_V 0x00000001U
#define RSA_QUERY_CLEAN_S 0
/** RSA_SET_START_MODEXP_REG register
* Starts modular exponentiation
*/
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
* Configures whether or not to starts the modular exponentiation. \\
* 0: No effect\\
* 1: Start\\
*/
#define RSA_SET_START_MODEXP (BIT(0))
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
#define RSA_SET_START_MODEXP_V 0x00000001U
#define RSA_SET_START_MODEXP_S 0
/** RSA_SET_START_MODMULT_REG register
* Starts modular multiplication
*/
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the modular multiplication.\\
* 0: No effect\\
* 1: Start\\
*/
#define RSA_SET_START_MODMULT (BIT(0))
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
#define RSA_SET_START_MODMULT_V 0x00000001U
#define RSA_SET_START_MODMULT_S 0
/** RSA_SET_START_MULT_REG register
* Starts multiplication
*/
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the multiplication.\\
* 0: No effect\\
* 1: Start\\
*/
#define RSA_SET_START_MULT (BIT(0))
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
#define RSA_SET_START_MULT_V 0x00000001U
#define RSA_SET_START_MULT_S 0
/** RSA_QUERY_IDLE_REG register
* Represents the RSA status
*/
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
* Represents the RSA status.\\
* 0: Busy\\
* 1: Idle\\
*/
#define RSA_QUERY_IDLE (BIT(0))
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
#define RSA_QUERY_IDLE_V 0x00000001U
#define RSA_QUERY_IDLE_S 0
/** RSA_INT_CLR_REG register
* Clears RSA interrupt
*/
#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001U
#define RSA_CLEAR_INTERRUPT_S 0
/** RSA_CONSTANT_TIME_REG register
* Configures the constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option. \\
* 0: Acceleration\\
* 1: No acceleration (default)\\
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001U
#define RSA_CONSTANT_TIME_S 0
/** RSA_SEARCH_ENABLE_REG register
* Configures the search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the search option. \\
* 0: No acceleration (default)\\
* 1: Acceleration\\
* This option should be used together with RSA_SEARCH_POS_REG.
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001U
#define RSA_SEARCH_ENABLE_S 0
/** RSA_SEARCH_POS_REG register
* Configures the search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
#define RSA_SEARCH_POS 0x00000FFFU
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFFU
#define RSA_SEARCH_POS_S 0
/** RSA_INT_ENA_REG register
* Enables the RSA interrupt
*/
#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
#define RSA_INT_ENA (BIT(0))
#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S)
#define RSA_INT_ENA_V 0x00000001U
#define RSA_INT_ENA_S 0
/** RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
#define RSA_DATE 0x3FFFFFFFU
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFFU
#define RSA_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/mp/include/soc/rsa_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
* Represents M'
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
* Represents M'
*/
uint32_t m_prime:32;
};
uint32_t val;
} rsa_m_prime_reg_t;
/** Type of mode register
* Configures RSA length
*/
typedef union {
struct {
/** mode : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
uint32_t mode:7;
uint32_t reserved_7:25;
};
uint32_t val;
} rsa_mode_reg_t;
/** Type of set_start_modexp register
* Starts modular exponentiation
*/
typedef union {
struct {
/** set_start_modexp : WT; bitpos: [0]; default: 0;
* Configures whether or not to starts the modular exponentiation. \\
* 0: No effect\\
* 1: Start\\
*/
uint32_t set_start_modexp:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modexp_reg_t;
/** Type of set_start_modmult register
* Starts modular multiplication
*/
typedef union {
struct {
/** set_start_modmult : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the modular multiplication.\\
* 0: No effect\\
* 1: Start\\
*/
uint32_t set_start_modmult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modmult_reg_t;
/** Type of set_start_mult register
* Starts multiplication
*/
typedef union {
struct {
/** set_start_mult : WT; bitpos: [0]; default: 0;
* Configures whether or not to start the multiplication.\\
* 0: No effect\\
* 1: Start\\
*/
uint32_t set_start_mult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_mult_reg_t;
/** Type of query_idle register
* Represents the RSA status
*/
typedef union {
struct {
/** query_idle : RO; bitpos: [0]; default: 0;
* Represents the RSA status.\\
* 0: Busy\\
* 1: Idle\\
*/
uint32_t query_idle:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_idle_reg_t;
/** Type of constant_time register
* Configures the constant_time option
*/
typedef union {
struct {
/** constant_time : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option. \\
* 0: Acceleration\\
* 1: No acceleration (default)\\
*/
uint32_t constant_time:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_constant_time_reg_t;
/** Type of search_enable register
* Configures the search option
*/
typedef union {
struct {
/** search_enable : R/W; bitpos: [0]; default: 0;
* Configures the search option. \\
* 0: No acceleration (default)\\
* 1: Acceleration\\
* This option should be used together with RSA_SEARCH_POS_REG.
*/
uint32_t search_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_search_enable_reg_t;
/** Type of search_pos register
* Configures the search position
*/
typedef union {
struct {
/** search_pos : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
uint32_t search_pos:12;
uint32_t reserved_12:20;
};
uint32_t val;
} rsa_search_pos_reg_t;
/** Group: Status Register */
/** Type of query_clean register
* RSA initialization status
*/
typedef union {
struct {
/** query_clean : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.\\
* 0: Not complete\\
* 1: Completed\\
*/
uint32_t query_clean:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_clean_reg_t;
/** Group: Interrupt Registers */
/** Type of int_clr register
* Clears RSA interrupt
*/
typedef union {
struct {
/** clear_interrupt : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_clr_reg_t;
/** Type of int_ena register
* Enables the RSA interrupt
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_ena_reg_t;
/** Group: Version Control Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} rsa_date_reg_t;
typedef struct {
volatile uint32_t m[4];
uint32_t reserved_010[124];
volatile uint32_t z[4];
uint32_t reserved_210[124];
volatile uint32_t y[4];
uint32_t reserved_410[124];
volatile uint32_t x[4];
uint32_t reserved_610[124];
volatile rsa_m_prime_reg_t m_prime;
volatile rsa_mode_reg_t mode;
volatile rsa_query_clean_reg_t query_clean;
volatile rsa_set_start_modexp_reg_t set_start_modexp;
volatile rsa_set_start_modmult_reg_t set_start_modmult;
volatile rsa_set_start_mult_reg_t set_start_mult;
volatile rsa_query_idle_reg_t query_idle;
volatile rsa_int_clr_reg_t int_clr;
volatile rsa_constant_time_reg_t constant_time;
volatile rsa_search_enable_reg_t search_enable;
volatile rsa_search_pos_reg_t search_pos;
volatile rsa_int_ena_reg_t int_ena;
volatile rsa_date_reg_t date;
} rsa_dev_t;
extern rsa_dev_t RSA;
#ifndef __cplusplus
_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
* Configures SHA algorithm
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the SHA algorithm. \\
* 0: SHA-1\\
* 1: SHA-224\\
* 2: SHA-256\\
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x00000007U
#define SHA_MODE_S 0
/** SHA_T_STRING_REG register
* SHA 512/t configuration register 0.
*/
#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
* Sha t_string (used if and only if mode == SHA_512/t).
*/
#define SHA_T_STRING 0xFFFFFFFFU
#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S)
#define SHA_T_STRING_V 0xFFFFFFFFU
#define SHA_T_STRING_S 0
/** SHA_T_LENGTH_REG register
* SHA 512/t configuration register 1.
*/
#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
* Sha t_length (used if and only if mode == SHA_512/t).
*/
#define SHA_T_LENGTH 0x0000003FU
#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
#define SHA_T_LENGTH_V 0x0000003FU
#define SHA_T_LENGTH_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* Block number register (only effective for DMA-SHA)
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
* Configures the DMA-SHA block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000003FU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Starts the SHA accelerator for Typical SHA operation
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : RO; bitpos: [31:1]; default: 0;
* Write 1 to start Typical SHA calculation.
*/
#define SHA_START 0x7FFFFFFFU
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x7FFFFFFFU
#define SHA_START_S 1
/** SHA_CONTINUE_REG register
* Continues SHA operation (only effective in Typical SHA mode)
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
* Write 1 to continue Typical SHA calculation.
*/
#define SHA_CONTINUE 0x7FFFFFFFU
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x7FFFFFFFU
#define SHA_CONTINUE_S 1
/** SHA_BUSY_REG register
* Represents if SHA Accelerator is busy or not
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents the states of SHA accelerator. \\
* 0: idle\\
* 1: busy\\
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
#define SHA_BUSY_STATE_V 0x00000001U
#define SHA_BUSY_STATE_S 0
/** SHA_DMA_START_REG register
* Starts the SHA accelerator for DMA-SHA operation
*/
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
* Write 1 to start DMA-SHA calculation.
*/
#define SHA_DMA_START (BIT(0))
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
#define SHA_DMA_START_V 0x00000001U
#define SHA_DMA_START_S 0
/** SHA_DMA_CONTINUE_REG register
* Continues SHA operation (only effective in DMA-SHA mode)
*/
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Write 1 to continue DMA-SHA calculation.
*/
#define SHA_DMA_CONTINUE (BIT(0))
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
#define SHA_DMA_CONTINUE_V 0x00000001U
#define SHA_DMA_CONTINUE_S 0
/** SHA_CLEAR_IRQ_REG register
* DMA-SHA interrupt clear register
*/
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Write 1 to clear DMA-SHA interrupt.
*/
#define SHA_CLEAR_INTERRUPT (BIT(0))
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
#define SHA_CLEAR_INTERRUPT_S 0
/** SHA_IRQ_ENA_REG register
* DMA-SHA interrupt enable register
*/
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable DMA-SHA interrupt.
*/
#define SHA_INTERRUPT_ENA (BIT(0))
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
#define SHA_INTERRUPT_ENA_V 0x00000001U
#define SHA_INTERRUPT_ENA_S 0
/** SHA_DATE_REG register
* Version control register
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
* Version control register.
*/
#define SHA_DATE 0x3FFFFFFFU
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_H_MEM register
* Sha H memory which contains intermediate hash or finial hash.
*/
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_H_MEM_SIZE_BYTES 64
/** SHA_M_MEM register
* Sha M memory which contains message.
*/
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_M_MEM_SIZE_BYTES 64
/** SHA_3_MODE_REG register
* Initial configuration register 0.
*/
#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800)
/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0;
* Sha3 mode
*/
#define SHA_3_MODE 0x00000007U
#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S)
#define SHA_3_MODE_V 0x00000007U
#define SHA_3_MODE_S 0
/** SHA_3_CLEAN_M_REG register
* Initial configuration register 1.
*/
#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804)
/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0;
* Clean Message.
*/
#define SHA_3_CLEAN_M (BIT(0))
#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S)
#define SHA_3_CLEAN_M_V 0x00000001U
#define SHA_3_CLEAN_M_S 0
/** SHA_3_DMA_BLOCK_NUM_REG register
* DMA configuration register 0.
*/
#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c)
/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
* DMA-SHA3 block number.
*/
#define SHA_3_DMA_BLOCK_NUM 0x0000003FU
#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S)
#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_3_DMA_BLOCK_NUM_S 0
/** SHA_3_START_REG register
* Typical SHA3 configuration register 0.
*/
#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810)
/** SHA_3_START : WO; bitpos: [0]; default: 0;
* Start typical sha3.
*/
#define SHA_3_START (BIT(0))
#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S)
#define SHA_3_START_V 0x00000001U
#define SHA_3_START_S 0
/** SHA_3_CONTINUE_REG register
* Typical SHA3 configuration register 1.
*/
#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814)
/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue typical sha3.
*/
#define SHA_3_CONTINUE (BIT(0))
#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S)
#define SHA_3_CONTINUE_V 0x00000001U
#define SHA_3_CONTINUE_S 0
/** SHA_3_BUSY_REG register
* Busy register.
*/
#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818)
/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0;
* Sha3 busy state. 1'b0: idle. 1'b1: busy.
*/
#define SHA_3_BUSY_REG (BIT(0))
#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S)
#define SHA_3_BUSY_REG_V 0x00000001U
#define SHA_3_BUSY_REG_S 0
/** SHA_3_DMA_START_REG register
* DMA configuration register 1.
*/
#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c)
/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0;
* Start dma-sha3.
*/
#define SHA_3_DMA_START (BIT(0))
#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S)
#define SHA_3_DMA_START_V 0x00000001U
#define SHA_3_DMA_START_S 0
/** SHA_3_DMA_CONTINUE_REG register
* DMA configuration register 2.
*/
#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820)
/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue dma-sha3.
*/
#define SHA_3_DMA_CONTINUE (BIT(0))
#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S)
#define SHA_3_DMA_CONTINUE_V 0x00000001U
#define SHA_3_DMA_CONTINUE_S 0
/** SHA_3_CLEAR_INT_REG register
* Interrupt clear register.
*/
#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824)
/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0;
* Clear sha3 interrupt.
*/
#define SHA_3_CLEAR_INT (BIT(0))
#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S)
#define SHA_3_CLEAR_INT_V 0x00000001U
#define SHA_3_CLEAR_INT_S 0
/** SHA_3_INT_ENA_REG register
* Interrupt enable register.
*/
#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828)
/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0;
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
*/
#define SHA_3_INT_ENA (BIT(0))
#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S)
#define SHA_3_INT_ENA_V 0x00000001U
#define SHA_3_INT_ENA_S 0
/** SHA_3_SHAKE_LENGTH_REG register
* DMA configuration register 3.
*/
#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c)
/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50;
* SHAKE output hash word length
*/
#define SHA_3_SHAKE_LENGTH 0x000007FFU
#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S)
#define SHA_3_SHAKE_LENGTH_V 0x000007FFU
#define SHA_3_SHAKE_LENGTH_S 0
/** SHA_3_M_OUT_MEM register
* Sha3 hash reg which contains intermediate hash or finial hash.
*/
#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900)
#define SHA_3_M_OUT_MEM_SIZE_BYTES 200
/** SHA_3_M_MEM register
* Sha3 message reg which contains message.
*/
#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00)
#define SHA_3_M_MEM_SIZE_BYTES 200
#ifdef __cplusplus
}
#endif

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