diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h
index 574cb8d3b1..dca148feca 100644
--- a/components/soc/esp32c3/include/soc/soc.h
+++ b/components/soc/esp32c3/include/soc/soc.h
@@ -75,6 +75,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1E000)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{
diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h
index a08cb24f3c..361f58ba5c 100644
--- a/components/soc/esp32c3/include/soc/spi_reg.h
+++ b/components/soc/esp32c3/include/soc/spi_reg.h
@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SPI_REG_H_
 #define _SOC_SPI_REG_H_
 
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
 /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld
index 0ae0e5522a..f7c495fb5e 100644
--- a/components/soc/esp32c3/ld/esp32c3.peripherals.ld
+++ b/components/soc/esp32c3/ld/esp32c3.peripherals.ld
@@ -21,10 +21,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 );
 PROVIDE ( TIMERG1 = 0x60020000 );
 PROVIDE ( SYSTIMER = 0x60023000 );
 PROVIDE ( GPSPI2  = 0x60024000 );
-PROVIDE ( GPSPI3  = 0x60025000 );
 PROVIDE ( SYSCON = 0x60026000 );
 PROVIDE ( TWAI   = 0x6002B000 );
-PROVIDE ( GPSPI4 = 0x60037000 );
 PROVIDE ( APB_SARADC = 0x60040000 );
 PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
 PROVIDE ( GDMA    = 0x6003F000 );
diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h
index 2f62a827a0..5a2bad6f8f 100644
--- a/components/soc/esp32s2/include/soc/soc.h
+++ b/components/soc/esp32s2/include/soc/soc.h
@@ -83,14 +83,15 @@
 #define DR_REG_APB_SARADC_BASE                  0x3f440000
 #define DR_REG_USB_BASE                         0x60080000
 
-#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE)
-#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 )
-#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 )
-#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
-#define REG_TIMG_BASE(i)              (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_UHCI_BASE(i)        (DR_REG_UHCI0_BASE)
+#define REG_UART_BASE( i )      (DR_REG_UART_BASE + (i) * 0x10000 )
+#define REG_UART_AHB_BASE(i)    (0x60000000 + (i) * 0x10000 )
+#define UART_FIFO_AHB_REG(i)    (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE( i )       (DR_REG_I2S_BASE)
+#define REG_TIMG_BASE(i)        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+#define REG_SPI_BASE(i)         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define REG_I2C_BASE(i)         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Convenient way to replace the register ops when ulp riscv projects
 //consume this file
diff --git a/components/soc/esp32s2/include/soc/spi_mem_reg.h b/components/soc/esp32s2/include/soc/spi_mem_reg.h
index fd3bf04a41..b08abdc1fb 100644
--- a/components/soc/esp32s2/include/soc/spi_mem_reg.h
+++ b/components/soc/esp32s2/include/soc/spi_mem_reg.h
@@ -1,25 +1,16 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SPI_MEM_REG_H_
 #define _SOC_SPI_MEM_REG_H_
 
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
-#define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
 
 #define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x000)
 /* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
diff --git a/components/soc/esp32s2/include/soc/spi_reg.h b/components/soc/esp32s2/include/soc/spi_reg.h
index 0f0f732baa..1097f31a15 100644
--- a/components/soc/esp32s2/include/soc/spi_reg.h
+++ b/components/soc/esp32s2/include/soc/spi_reg.h
@@ -1,25 +1,16 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SPI_REG_H_
 #define _SOC_SPI_REG_H_
 
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
-#define REG_SPI_BASE(i)     (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
 
 #define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x000)
 /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h
index d25e852cac..4a4c62d811 100644
--- a/components/soc/esp32s3/include/soc/soc.h
+++ b/components/soc/esp32s3/include/soc/soc.h
@@ -112,14 +112,15 @@
 #define DR_REG_DPORT_END                        0x600D3FFC
 
 
-#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE - (i) * 0x8000)
-#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
-#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
-#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
-#define REG_TIMG_BASE(i)              (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_UHCI_BASE(i)        (DR_REG_UHCI0_BASE - (i) * 0x8000)
+#define REG_UART_BASE( i )      (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
+#define REG_UART_AHB_BASE(i)    (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
+#define UART_FIFO_AHB_REG(i)    (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE( i )       (DR_REG_I2S_BASE + (i) * 0x1E000)
+#define REG_TIMG_BASE(i)        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+#define REG_SPI_BASE(i)         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define REG_I2C_BASE(i)         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Convenient way to replace the register ops when ulp riscv projects
 //consume this file
diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld
index 8e59dd5354..51f98e7e92 100644
--- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld
+++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld
@@ -37,7 +37,6 @@ PROVIDE ( SYSCON = 0x60026000 );
 PROVIDE ( I2C1 = 0x60027000 );
 PROVIDE ( SDMMC = 0x60028000 );
 PROVIDE ( TWAI = 0x6002B000 );
-PROVIDE ( GPSPI4 = 0x60037000 );
 PROVIDE ( GDMA = 0x6003F000 );
 PROVIDE ( UART2  = 0x6002E000 );
 PROVIDE ( DMA = 0x6003F000 );