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Only modify headers in soc/ .

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Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
This commit is contained in:
Wangjialin
2016-09-13 23:02:03 +08:00
committed by Wu Jian Gang
parent fb64393f63
commit 41d397cf3f
30 changed files with 31346 additions and 9669 deletions
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2
components/freertos/gdbstub.c
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@@ -21,7 +21,7 @@
//ToDo: Clean up includes and sync to real rtos
#include "rom/ets_sys.h"
#include "soc/uart_register.h"
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "gdbstub.h"

18
components/freertos/panic.c
View File

@@ -21,7 +21,7 @@
#include "freertos/task.h"
#include "freertos/xtensa_api.h"
#include "soc/uart_register.h"
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc_cntl_reg.h"
@@ -105,16 +105,16 @@ void commonErrorHandler(XtExcFrame *frame);
static void haltOtherCore() {
if (xPortGetCoreID()==0) {
//Kill app cpu
CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
} else {
//Kill pro cpu
CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
}
}