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feat(h21_mp): update H21_MP soc headers

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This commit is contained in:
gaoxu
2025-08-19 17:57:53 +08:00
committed by Gao Xu
parent c91dc3f049
commit 41f954facf
23 changed files with 5999 additions and 2725 deletions
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1
Kconfig
View File

@@ -144,6 +144,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
select IDF_ENV_BRINGUP
select IDF_ENV_FPGA if ESP32H21_SELECTS_REV_MP
config IDF_TARGET_ESP32H4
bool

2
components/efuse/esp32h21/esp_efuse_utility.c
View File

@@ -21,7 +21,7 @@ extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
/*Range addresses to read blocks*/
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
{EFUSE_RD_MAC_SYS_0_REG, EFUSE_RD_MAC_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_8M
{EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_8M
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0

11
components/esp_hw_support/port/esp32h21/Kconfig.hw_support
View File

@@ -1,3 +1,14 @@
comment "NOTE! Support of ESP32-H21 MP is mutually exclusive"
comment "Read the help text of the option below for explanation"
config ESP32H21_SELECTS_REV_MP
bool "Select ESP32-H21 MP version"
default n
help
Enable this option to select ESP32-H21 MP revision.
MP revisions have some hardware differences with Beta revision.
MP revisions is not compatible with Beta revision.
choice ESP32H21_REV_MIN
prompt "Minimum Supported ESP32-H21 Revision"
default ESP32H21_REV_MIN_0

4
components/hal/esp32h21/efuse_hal.c
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@@ -91,7 +91,7 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
{
if (block == 0) {
for (unsigned i = 0; i < 5; i++) {
if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) {
return true;
}
}
@@ -99,7 +99,7 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
}
return false;

47
components/hal/esp32h21/include/hal/efuse_ll.h
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@@ -48,26 +48,6 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
return EFUSE.rd_mac_sys_1.mac_1;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void)
{
return EFUSE.rd_mac_sys_2.active_hp_dbias;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void)
{
return EFUSE.rd_mac_sys_2.active_lp_dbias;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbias(void)
{
return EFUSE.rd_mac_sys_2.dslp_dbias;
}
__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void)
{
return (EFUSE.rd_mac_sys_3.dbias_vol_gap_sign << 4)|(EFUSE.rd_mac_sys_3.dbias_vol_gap_value2 << 1)|EFUSE.rd_mac_sys_2.dbias_vol_gap_value1;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return EFUSE.rd_repeat_data2.secure_boot_en;
@@ -76,49 +56,58 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_sys_3.wafer_version_major;
//TODO: [ESP32H21] IDF-11507
return 0;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return EFUSE.rd_mac_sys_3.wafer_version_minor;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_mac_sys_3.disable_wafer_version_major;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_minor;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.disable_blk_version_major;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_sys_4.pkg_version;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
{
return EFUSE.conf.cfg_ecdsa_blk;
//TODO: [ESP32H21] IDF-11507
return 0;
}
__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
{
//TODO: [ESP32H21] IDF-11507
(void) curve;
EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
(void) efuse_blk;
}
/******************* eFuse control functions *************************/

2
components/hal/include/hal/apm_hal.h
View File

@@ -362,7 +362,7 @@ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable);
#endif //SOC_IS(ESP32P4)
#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED
#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOCKconfig_APM_SUPPORTED
#if SOC_IS(ESP32H4)
#include "soc/hp_apm_reg.h"

7
components/soc/CMakeLists.txt
View File

@@ -25,6 +25,13 @@ if(CONFIG_IDF_TARGET_ESP32P4)
else()
list(APPEND includes "${target_folder}/register/hw_ver2")
endif()
elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H4 IDF-13835
list(APPEND includes "${target_folder}/register")
if(CONFIG_ESP32H21_SELECTS_REV_MP)
list(APPEND includes "${target_folder}/register/hw_ver_mp")
else()
list(APPEND includes "${target_folder}/register/hw_ver_beta1")
endif()
else()
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
list(APPEND includes "${target_folder}/register")

0
components/soc/esp32h21/register/soc/lp_apm_reg.h → components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_reg.h
View File

0
components/soc/esp32h21/register/soc/lp_apm_struct.h → components/soc/esp32h21/register/hw_ver_beta1/soc/lp_apm_struct.h
View File

506
components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_reg.h Normal file
View File

@@ -0,0 +1,506 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_X (BIT(0))
#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_X_S 0
/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_W (BIT(1))
#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_W_S 1
/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_R (BIT(2))
#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_R_S 2
/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_X (BIT(4))
#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_X_S 4
/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_W (BIT(5))
#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_W_S 5
/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_R (BIT(6))
#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_R_S 6
/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_X (BIT(8))
#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_X_S 8
/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_W (BIT(9))
#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_W_S 9
/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_R (BIT(10))
#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_R_S 10
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_X (BIT(0))
#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_X_S 0
/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_W (BIT(1))
#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_W_S 1
/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_R (BIT(2))
#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_R_S 2
/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_X (BIT(4))
#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_X_S 4
/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_W (BIT(5))
#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_W_S 5
/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_R (BIT(6))
#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_R_S 6
/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_X (BIT(8))
#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_X_S 8
/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_W (BIT(9))
#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_W_S 9
/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_R (BIT(10))
#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_R_S 10
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_X (BIT(0))
#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_X_S 0
/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_W (BIT(1))
#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_W_S 1
/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_R (BIT(2))
#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_R_S 2
/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_X (BIT(4))
#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_X_S 4
/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_W (BIT(5))
#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_W_S 5
/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_R (BIT(6))
#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_R_S 6
/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_X (BIT(8))
#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_X_S 8
/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_W (BIT(9))
#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_W_S 9
/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_R (BIT(10))
#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_R_S 10
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_X (BIT(0))
#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_X_S 0
/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_W (BIT(1))
#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_W_S 1
/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_R (BIT(2))
#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_R_S 2
/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_X (BIT(4))
#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_X_S 4
/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_W (BIT(5))
#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_W_S 5
/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_R (BIT(6))
#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_R_S 6
/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_X (BIT(8))
#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_X_S 8
/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_W (BIT(9))
#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_W_S 9
/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_R (BIT(10))
#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_R_S 10
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M0_PMS_FUNC_EN_S 0
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_REGION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0x7fc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h21/register/hw_ver_mp/soc/lp_apm_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x800, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

1900
components/soc/esp32h21/register/soc/efuse_reg.h
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File diff suppressed because it is too large Load Diff

2321
components/soc/esp32h21/register/soc/efuse_struct.h
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File diff suppressed because it is too large Load Diff

4
components/soc/esp32h21/register/soc/io_mux_struct.h
View File

@@ -115,7 +115,7 @@ typedef union {
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 36770416;
/** reg_date : R/W; bitpos: [27:0]; default: 38806096;
* Version control register
*/
uint32_t reg_date:28;
@@ -127,7 +127,7 @@ typedef union {
typedef struct {
volatile io_mux_gpio_reg_t gpio[26];
uint32_t reserved_074[101];
uint32_t reserved_068[101];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;

11
components/soc/esp32h21/register/soc/lp_aon_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -251,6 +251,13 @@ extern "C" {
* need_des
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_PULL_LDO_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_PULL_LDO_EN (BIT(27))
#define LP_AON_IO_MUX_PULL_LDO_EN_M (LP_AON_IO_MUX_PULL_LDO_EN_V << LP_AON_IO_MUX_PULL_LDO_EN_S)
#define LP_AON_IO_MUX_PULL_LDO_EN_V 0x00000001U
#define LP_AON_IO_MUX_PULL_LDO_EN_S 27
/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
@@ -450,7 +457,7 @@ extern "C" {
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37781648;
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU

10
components/soc/esp32h21/register/soc/lp_aon_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -246,7 +246,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:28;
uint32_t reserved_0:27;
/** aon_io_mux_pull_ldo_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t aon_io_mux_pull_ldo_en:1;
/** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
@@ -431,7 +435,7 @@ typedef union {
*/
typedef union {
struct {
/** aon_date : R/W; bitpos: [30:0]; default: 37781648;
/** date : R/W; bitpos: [30:0]; default: 38814352;
* need_des
*/
uint32_t aon_date:31;

89
components/soc/esp32h21/register/soc/lp_clkrst_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -407,11 +407,96 @@ extern "C" {
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_CALI0_REG register
* need_des
*/
#define LP_CLKRST_CALI0_REG (DR_REG_LP_CLKRST_BASE + 0x38)
/** LP_CLKRST_LP_CALI_DIV_CYCLE : R/W; bitpos: [7:0]; default: 1;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_CYCLE 0x000000FFU
#define LP_CLKRST_LP_CALI_DIV_CYCLE_M (LP_CLKRST_LP_CALI_DIV_CYCLE_V << LP_CLKRST_LP_CALI_DIV_CYCLE_S)
#define LP_CLKRST_LP_CALI_DIV_CYCLE_V 0x000000FFU
#define LP_CLKRST_LP_CALI_DIV_CYCLE_S 0
/** LP_CLKRST_LP_CALI_FULL_CNT_DONE : RO; bitpos: [8]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE (BIT(8))
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_M (LP_CLKRST_LP_CALI_FULL_CNT_DONE_V << LP_CLKRST_LP_CALI_FULL_CNT_DONE_S)
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_V 0x00000001U
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_S 8
/** LP_CLKRST_LP_CALI_DIV_CALI_CNT : RO; bitpos: [24:9]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_M (LP_CLKRST_LP_CALI_DIV_CALI_CNT_V << LP_CLKRST_LP_CALI_DIV_CALI_CNT_S)
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_S 9
/** LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE (BIT(25))
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S)
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V 0x00000001U
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S 25
/** LP_CLKRST_LP_CALI_DIV_NUM : RO; bitpos: [31:26]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUM 0x0000003FU
#define LP_CLKRST_LP_CALI_DIV_NUM_M (LP_CLKRST_LP_CALI_DIV_NUM_V << LP_CLKRST_LP_CALI_DIV_NUM_S)
#define LP_CLKRST_LP_CALI_DIV_NUM_V 0x0000003FU
#define LP_CLKRST_LP_CALI_DIV_NUM_S 26
/** LP_CLKRST_CALI1_REG register
* need_des
*/
#define LP_CLKRST_CALI1_REG (DR_REG_LP_CLKRST_BASE + 0x3c)
/** LP_CLKRST_LP_CALI_DIV_NUMERATOR : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_S)
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_S 0
/** LP_CLKRST_LP_CALI_DIV_DENOMINATOR : RO; bitpos: [31:16]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_M (LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V << LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S)
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S 16
/** LP_CLKRST_CALI2_REG register
* need_des
*/
#define LP_CLKRST_CALI2_REG (DR_REG_LP_CLKRST_BASE + 0x40)
/** LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD : R/W; bitpos: [8:0]; default: 255;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD 0x000001FFU
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_M (LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V << LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S)
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V 0x000001FFU
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S 0
/** LP_CLKRST_LP_CALI_DIV_SLP_VAL : R/W; bitpos: [30:15]; default: 1;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_M (LP_CLKRST_LP_CALI_DIV_SLP_VAL_V << LP_CLKRST_LP_CALI_DIV_SLP_VAL_S)
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_S 15
/** LP_CLKRST_LP_CALI_DIV_TIMER_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN (BIT(31))
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_M (LP_CLKRST_LP_CALI_DIV_TIMER_EN_V << LP_CLKRST_LP_CALI_DIV_TIMER_EN_S)
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_V 0x00000001U
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_S 31
/** LP_CLKRST_DATE_REG register
* need_des
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37782064;
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 38806112;
* need_des
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU

86
components/soc/esp32h21/register/soc/lp_clkrst_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -323,19 +323,87 @@ typedef union {
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of clkrst_date register
/** Type of cali0 register
* need_des
*/
typedef union {
struct {
/** clkrst_clkrst_date : R/W; bitpos: [30:0]; default: 37782064;
/** lp_cali_div_cycle : R/W; bitpos: [7:0]; default: 1;
* need_des
*/
uint32_t clkrst_clkrst_date:31;
/** clkrst_clk_en : R/W; bitpos: [31]; default: 0;
uint32_t lp_cali_div_cycle:8;
/** lp_cali_full_cnt_done : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t clkrst_clk_en:1;
uint32_t lp_cali_full_cnt_done:1;
/** lp_cali_div_cali_cnt : RO; bitpos: [24:9]; default: 0;
* need_des
*/
uint32_t lp_cali_div_cali_cnt:16;
/** lp_cali_div_numerator_type : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t lp_cali_div_numerator_type:1;
/** lp_cali_div_num : RO; bitpos: [31:26]; default: 0;
* need_des
*/
uint32_t lp_cali_div_num:6;
};
uint32_t val;
} lp_clkrst_cali0_reg_t;
/** Type of cali1 register
* need_des
*/
typedef union {
struct {
/** lp_cali_div_numerator : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t lp_cali_div_numerator:16;
/** lp_cali_div_denominator : RO; bitpos: [31:16]; default: 0;
* need_des
*/
uint32_t lp_cali_div_denominator:16;
};
uint32_t val;
} lp_clkrst_cali1_reg_t;
/** Type of cali2 register
* need_des
*/
typedef union {
struct {
/** lp_cali_div_wait_pwr_good : R/W; bitpos: [8:0]; default: 255;
* need_des
*/
uint32_t lp_cali_div_wait_pwr_good:9;
uint32_t reserved_9:6;
/** lp_cali_div_slp_val : R/W; bitpos: [30:15]; default: 1;
* need_des
*/
uint32_t lp_cali_div_slp_val:16;
/** lp_cali_div_timer_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cali_div_timer_en:1;
};
uint32_t val;
} lp_clkrst_cali2_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 38806112;
* need_des
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
@@ -354,7 +422,11 @@ typedef struct {
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
uint32_t reserved_030[2];
volatile lp_clkrst_cali0_reg_t cali0;
volatile lp_clkrst_cali1_reg_t cali1;
volatile lp_clkrst_cali2_reg_t cali2;
uint32_t reserved_044[238];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;

169
components/soc/esp32h21/register/soc/pmu_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -476,7 +476,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16;
* need_des
*/
#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU
@@ -505,10 +505,13 @@ extern "C" {
/** PMU_HP_MODEM_DIG_POWER_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34)
/** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU
#define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S)
@@ -516,6 +519,7 @@ extern "C" {
#define PMU_HP_MODEM_VDD_FLASH_MODE_S 18
/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22))
#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S)
@@ -523,6 +527,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_MEM_DSLP_S 22
/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S)
@@ -530,6 +535,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23
/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27))
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S)
@@ -537,6 +543,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27
/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28))
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S)
@@ -544,6 +551,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28
/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29))
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S)
@@ -551,6 +559,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29
/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30))
#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S)
@@ -558,6 +567,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30
/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31))
#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S)
@@ -566,10 +576,13 @@ extern "C" {
/** PMU_HP_MODEM_ICG_HP_FUNC_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S)
@@ -578,10 +591,13 @@ extern "C" {
/** PMU_HP_MODEM_ICG_HP_APB_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S)
@@ -590,10 +606,13 @@ extern "C" {
/** PMU_HP_MODEM_ICG_MODEM_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40)
/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U
#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S)
@@ -602,10 +621,13 @@ extern "C" {
/** PMU_HP_MODEM_HP_SYS_CNTL_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44)
/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24))
#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S)
@@ -613,6 +635,7 @@ extern "C" {
#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24
/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25))
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S)
@@ -620,6 +643,7 @@ extern "C" {
#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25
/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26))
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S)
@@ -627,6 +651,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26
/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27))
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S)
@@ -634,6 +659,7 @@ extern "C" {
#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27
/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28))
#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S)
@@ -641,6 +667,7 @@ extern "C" {
#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28
/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29))
#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S)
@@ -649,10 +676,13 @@ extern "C" {
/** PMU_HP_MODEM_HP_CK_POWER_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48)
/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26))
#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S)
@@ -660,6 +690,7 @@ extern "C" {
#define PMU_HP_MODEM_I2C_ISO_EN_S 26
/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_I2C_RETENTION (BIT(27))
#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S)
@@ -667,6 +698,7 @@ extern "C" {
#define PMU_HP_MODEM_I2C_RETENTION_S 27
/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28))
#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S)
@@ -674,6 +706,7 @@ extern "C" {
#define PMU_HP_MODEM_XPD_BB_I2C_S 28
/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29))
#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S)
@@ -681,6 +714,7 @@ extern "C" {
#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29
/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_BBPLL (BIT(30))
#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S)
@@ -689,10 +723,13 @@ extern "C" {
/** PMU_HP_MODEM_BIAS_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
/** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9))
#define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S)
@@ -700,6 +737,7 @@ extern "C" {
#define PMU_HP_MODEM_DCDC_CCM_ENB_S 9
/** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10))
#define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S)
@@ -707,6 +745,7 @@ extern "C" {
#define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10
/** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S)
@@ -714,6 +753,7 @@ extern "C" {
#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11
/** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU
#define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S)
@@ -721,6 +761,7 @@ extern "C" {
#define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13
/** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DCM_VSET 0x0000001FU
#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S)
@@ -728,6 +769,7 @@ extern "C" {
#define PMU_HP_MODEM_DCM_VSET_S 17
/** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DCM_MODE 0x00000003U
#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S)
@@ -735,6 +777,7 @@ extern "C" {
#define PMU_HP_MODEM_DCM_MODE_S 22
/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_TRX (BIT(24))
#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S)
@@ -742,6 +785,7 @@ extern "C" {
#define PMU_HP_MODEM_XPD_TRX_S 24
/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_BIAS (BIT(25))
#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S)
@@ -749,6 +793,7 @@ extern "C" {
#define PMU_HP_MODEM_XPD_BIAS_S 25
/** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29))
#define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S)
@@ -756,6 +801,7 @@ extern "C" {
#define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29
/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_PD_CUR (BIT(30))
#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S)
@@ -763,6 +809,7 @@ extern "C" {
#define PMU_HP_MODEM_PD_CUR_S 30
/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31))
#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S)
@@ -771,10 +818,13 @@ extern "C" {
/** PMU_HP_MODEM_BACKUP_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50)
/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S)
@@ -782,6 +832,7 @@ extern "C" {
#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4
/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S)
@@ -789,6 +840,7 @@ extern "C" {
#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14
/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S)
@@ -796,6 +848,7 @@ extern "C" {
#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20
/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29))
#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S)
@@ -804,10 +857,13 @@ extern "C" {
/** PMU_HP_MODEM_BACKUP_CLK_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54)
/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU
#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S)
@@ -816,10 +872,13 @@ extern "C" {
/** PMU_HP_MODEM_SYSCLK_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58)
/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26))
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S)
@@ -827,6 +886,7 @@ extern "C" {
#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26
/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27))
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S)
@@ -834,6 +894,7 @@ extern "C" {
#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27
/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28))
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S)
@@ -841,6 +902,7 @@ extern "C" {
#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28
/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29))
#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S)
@@ -848,6 +910,7 @@ extern "C" {
#define PMU_HP_MODEM_ICG_SLP_SEL_S 29
/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U
#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S)
@@ -856,10 +919,13 @@ extern "C" {
/** PMU_HP_MODEM_HP_REGULATOR0_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0))
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S)
@@ -867,6 +933,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
@@ -874,6 +941,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
@@ -881,6 +949,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17
/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18))
#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
@@ -888,6 +957,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
@@ -895,6 +965,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
@@ -902,6 +973,7 @@ extern "C" {
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23
/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S)
@@ -910,10 +982,13 @@ extern "C" {
/** PMU_HP_MODEM_HP_REGULATOR1_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60)
/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU
#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S)
@@ -922,10 +997,13 @@ extern "C" {
/** PMU_HP_MODEM_XTAL_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
/** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_XTALX2 (BIT(30))
#define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S)
@@ -933,6 +1011,7 @@ extern "C" {
#define PMU_HP_MODEM_XPD_XTALX2_S 30
/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_MODEM_XPD_XTAL (BIT(31))
#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S)
@@ -1376,7 +1455,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16;
* need_des
*/
#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU
@@ -1450,10 +1529,13 @@ extern "C" {
/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4)
/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S)
@@ -1542,10 +1624,13 @@ extern "C" {
/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register
* need_des
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0)
/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S)
@@ -2666,12 +2751,12 @@ extern "C" {
#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S)
#define PMU_FLASH1P8_STANDBY_V 0x00000001U
#define PMU_FLASH1P8_STANDBY_S 25
/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0;
/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
* need_des
*/
#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU
#define PMU_FLASH1P8_POWER_ADJUST 0x0000000FU
#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S)
#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU
#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000000FU
#define PMU_FLASH1P8_POWER_ADJUST_S 26
/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0;
* need_des
@@ -2755,12 +2840,12 @@ extern "C" {
#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S)
#define PMU_FLASH1P2_STANDBY_V 0x00000001U
#define PMU_FLASH1P2_STANDBY_S 25
/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0;
/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
* need_des
*/
#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU
#define PMU_FLASH1P2_POWER_ADJUST 0x0000000FU
#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S)
#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU
#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000000FU
#define PMU_FLASH1P2_POWER_ADJUST_S 26
/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0;
* need_des
@@ -2898,12 +2983,12 @@ extern "C" {
#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S)
#define PMU_IO_STANDBY_V 0x00000001U
#define PMU_IO_STANDBY_S 25
/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0;
/** PMU_IO_POWER_ADJUST : R/W; bitpos: [29:26]; default: 0;
* need_des
*/
#define PMU_IO_POWER_ADJUST 0x0000001FU
#define PMU_IO_POWER_ADJUST 0x0000000FU
#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S)
#define PMU_IO_POWER_ADJUST_V 0x0000001FU
#define PMU_IO_POWER_ADJUST_V 0x0000000FU
#define PMU_IO_POWER_ADJUST_S 26
/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0;
* need_des
@@ -2936,7 +3021,7 @@ extern "C" {
* need_des
*/
#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130)
/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 384;
* need_des
*/
#define PMU_WAIT_XTL_STABLE 0x0000FFFFU
@@ -4136,10 +4221,43 @@ extern "C" {
#define PMU_DCDC_RDY_CLR_V 0x00000001U
#define PMU_DCDC_RDY_CLR_S 31
/** PMU_DCM_BOOST_CTRL_REG register
* need_des
*/
#define PMU_DCM_BOOST_CTRL_REG (DR_REG_PMU_BASE + 0x1bc)
/** PMU_DCDC_BOOST_CCM_CTRLEN : R/W; bitpos: [24]; default: 0;
* need_des
*/
#define PMU_DCDC_BOOST_CCM_CTRLEN (BIT(24))
#define PMU_DCDC_BOOST_CCM_CTRLEN_M (PMU_DCDC_BOOST_CCM_CTRLEN_V << PMU_DCDC_BOOST_CCM_CTRLEN_S)
#define PMU_DCDC_BOOST_CCM_CTRLEN_V 0x00000001U
#define PMU_DCDC_BOOST_CCM_CTRLEN_S 24
/** PMU_DCDC_BOOST_CCM_ENB : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define PMU_DCDC_BOOST_CCM_ENB (BIT(25))
#define PMU_DCDC_BOOST_CCM_ENB_M (PMU_DCDC_BOOST_CCM_ENB_V << PMU_DCDC_BOOST_CCM_ENB_S)
#define PMU_DCDC_BOOST_CCM_ENB_V 0x00000001U
#define PMU_DCDC_BOOST_CCM_ENB_S 25
/** PMU_DCDC_BOOST_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define PMU_DCDC_BOOST_EN (BIT(26))
#define PMU_DCDC_BOOST_EN_M (PMU_DCDC_BOOST_EN_V << PMU_DCDC_BOOST_EN_S)
#define PMU_DCDC_BOOST_EN_V 0x00000001U
#define PMU_DCDC_BOOST_EN_S 26
/** PMU_DCDC_BOOST_DREG : R/W; bitpos: [31:27]; default: 23;
* need_des
*/
#define PMU_DCDC_BOOST_DREG 0x0000001FU
#define PMU_DCDC_BOOST_DREG_M (PMU_DCDC_BOOST_DREG_V << PMU_DCDC_BOOST_DREG_S)
#define PMU_DCDC_BOOST_DREG_V 0x0000001FU
#define PMU_DCDC_BOOST_DREG_S 27
/** PMU_TOUCH_PWR_CTRL_REG register
* need_des
*/
#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc)
#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1c0)
/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
@@ -4169,11 +4287,30 @@ extern "C" {
#define PMU_TOUCH_FORCE_DONE_V 0x00000001U
#define PMU_TOUCH_FORCE_DONE_S 31
/** PMU_BLE_BANDGAP_CTRL_REG register
* need_des
*/
#define PMU_BLE_BANDGAP_CTRL_REG (DR_REG_PMU_BASE + 0x1c4)
/** PMU_EXT_OCODE : R/W; bitpos: [30:23]; default: 120;
* need_des
*/
#define PMU_EXT_OCODE 0x000000FFU
#define PMU_EXT_OCODE_M (PMU_EXT_OCODE_V << PMU_EXT_OCODE_S)
#define PMU_EXT_OCODE_V 0x000000FFU
#define PMU_EXT_OCODE_S 23
/** PMU_EXT_FORCE_OCODE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_EXT_FORCE_OCODE (BIT(31))
#define PMU_EXT_FORCE_OCODE_M (PMU_EXT_FORCE_OCODE_V << PMU_EXT_FORCE_OCODE_S)
#define PMU_EXT_FORCE_OCODE_V 0x00000001U
#define PMU_EXT_FORCE_OCODE_S 31
/** PMU_DATE_REG register
* need_des
*/
#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400;
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38814336;
* need_des
*/
#define PMU_PMU_DATE 0x7FFFFFFFU

52
components/soc/esp32h21/register/soc/pmu_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -960,6 +960,32 @@ typedef union
uint32_t val;
} pmu_dcm_ctrl_reg_t;
/** Type of dcm_boost_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** dcdc_boost_ccm_ctrlen : R/W; bitpos: [24]; default: 0;
* need_des
*/
uint32_t dcdc_boost_ccm_ctrlen:1;
/** dcdc_boost_ccm_enb : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t dcdc_boost_ccm_enb:1;
/** dcdc_boost_en : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t dcdc_boost_en:1;
/** dcdc_boost_dreg : R/W; bitpos: [31:27]; default: 23;
* need_des
*/
uint32_t dcdc_boost_dreg:5;
};
uint32_t val;
} pmu_dcm_boost_ctrl_reg_t;
typedef union
{
struct
@@ -973,6 +999,24 @@ typedef union
volatile uint32_t val;
} pmu_touch_pwr_ctrl_reg_t;
/** Type of ble_bandgap_ctrl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** ext_ocode : R/W; bitpos: [30:23]; default: 120;
* need_des
*/
uint32_t ext_ocode:8;
/** ext_force_ocode : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_force_ocode:1;
};
uint32_t val;
} pmu_ble_bandgap_ctrl_reg_t;
typedef struct pmu_dev_t
{
volatile pmu_hp_hw_regmap_t hp_sys[3];
@@ -993,9 +1037,11 @@ typedef struct pmu_dev_t
volatile pmu_clk_state2_reg_t clk_state2;
volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl;
volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl;
volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl;
uint32_t reserved[143];
uint32_t reserved[141];
union
{
@@ -1013,7 +1059,7 @@ extern pmu_dev_t PMU;
#ifndef __cplusplus
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_BLE_BANDGAP_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
#endif
#ifdef __cplusplus

3001
components/soc/esp32h21/register/soc/pmu_struct_mp.h Normal file
View File

File diff suppressed because it is too large Load Diff

1
components/spi_flash/esp32h21/Kconfig.flash_freq
View File

@@ -6,6 +6,7 @@ choice ESPTOOLPY_FLASHFREQ
bool "48 MHz"
config ESPTOOLPY_FLASHFREQ_32M
bool "32 MHz"
depends on IDF_ENV_FPGA
config ESPTOOLPY_FLASHFREQ_24M
bool "24 MHz"
endchoice

1
components/spi_flash/esp32h4/Kconfig.flash_freq
View File

@@ -6,6 +6,7 @@ choice ESPTOOLPY_FLASHFREQ
bool "48 MHz"
config ESPTOOLPY_FLASHFREQ_32M
bool "32 MHz"
depends on IDF_ENV_FPGA
config ESPTOOLPY_FLASHFREQ_24M
bool "24 MHz"
endchoice