From 42a6b47aa883dbcbb1fe91126d147e67829050d0 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 31 Mar 2023 19:25:46 +0800 Subject: [PATCH] hal: Adds cache hal --- components/hal/esp32/include/hal/cache_ll.h | 95 +++++++++++++++++++ components/hal/esp32s3/include/hal/cache_ll.h | 84 ++++++++++++++++ components/hal/include/hal/cache_types.h | 33 +++++++ 3 files changed, 212 insertions(+) create mode 100644 components/hal/esp32/include/hal/cache_ll.h create mode 100644 components/hal/esp32s3/include/hal/cache_ll.h create mode 100644 components/hal/include/hal/cache_types.h diff --git a/components/hal/esp32/include/hal/cache_ll.h b/components/hal/esp32/include/hal/cache_ll.h new file mode 100644 index 0000000000..7157eff9c5 --- /dev/null +++ b/components/hal/esp32/include/hal/cache_ll.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Cache register operations + +#pragma once + +#include +#include "soc/dport_reg.h" +#include "hal/cache_types.h" +#include "hal/assert.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + * @param enable 1: enable; 0: disable + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + (void) mask; + HAL_ASSERT(cache_id == 0 || cache_id == 1); + + uint32_t bus_mask = 0; + if (cache_id == 0) { + bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0; + + bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; + bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0; + + DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask); + } else { + bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0; + + bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; + bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0; + + DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask); + } +} + +/** + * Disable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + * @param enable 1: enable; 0: disable + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + (void) mask; + HAL_ASSERT(cache_id == 0 || cache_id == 1); + + uint32_t bus_mask = 0; + if (cache_id == 0) { + bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0; + + bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; + bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0; + + DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask); + } else { + bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0; + bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0; + + bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; + bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0; + + DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h new file mode 100644 index 0000000000..c4de594de1 --- /dev/null +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Cache register operations + +#pragma once + +#include "soc/extmem_reg.h" +#include "hal/cache_types.h" +#include "hal/assert.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + HAL_ASSERT(cache_id == 0 || cache_id == 1); + //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + + uint32_t ibus_mask = 0; + if (cache_id == 0) { + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; + } else { + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; + } + REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); + + uint32_t dbus_mask = 0; + if (cache_id == 1) { + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; + } else { + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; + } + REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); +} + +/** + * Disable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be disabled + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + HAL_ASSERT(cache_id == 0 || cache_id == 1); + //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + + uint32_t ibus_mask = 0; + if (cache_id == 0) { + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; + } else { + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; + } + REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); + + uint32_t dbus_mask = 0; + if (cache_id == 1) { + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; + } else { + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; + } + REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/cache_types.h b/components/hal/include/hal/cache_types.h new file mode 100644 index 0000000000..0a7cee8fe8 --- /dev/null +++ b/components/hal/include/hal/cache_types.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Ibuses and Dbuses. + * + * @note + * These enumurations are abstract concepts. Virtual address reside in one of these buses. + * Therefore, use `cache_ll_l1_get_bus(cache_id, vaddr_start, len)` to convert your vaddr into buses first + */ +typedef enum { + CACHE_BUS_IBUS0 = BIT(0), + CACHE_BUS_IBUS1 = BIT(1), + CACHE_BUS_IBUS2 = BIT(2), + CACHE_BUS_DBUS0 = BIT(3), + CACHE_BUS_DBUS1 = BIT(4), + CACHE_BUS_DBUS2 = BIT(5), +} cache_bus_mask_t; + +#ifdef __cplusplus +} +#endif