mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-09 07:34:32 +02:00
soc: remove unused MMU related macros
This commit is contained in:
@@ -21,11 +21,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END 256
|
#define SOC_MMU_IROM0_PAGES_END 256
|
||||||
#define SOC_MMU_DROM0_PAGES_START 0
|
#define SOC_MMU_DROM0_PAGES_START 0
|
||||||
#define SOC_MMU_DROM0_PAGES_END 64
|
#define SOC_MMU_DROM0_PAGES_END 64
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK
|
#define SOC_MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page)
|
#define SOC_MMU_PAGE_IN_FLASH(page) (page)
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE DPORT_PRO_FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_DPORT_APP_FLASH_MMU_TABLE DPORT_APP_FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
||||||
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
||||||
|
@@ -78,8 +78,6 @@ extern "C" {
|
|||||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||||
|
|
||||||
#define MMU_TABLE_INVALID_VAL MMU_INVALID
|
|
||||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
|
||||||
/**
|
/**
|
||||||
* MMU entry valid bit mask for mapping value. For an entry:
|
* MMU entry valid bit mask for mapping value. For an entry:
|
||||||
* valid bit + value bits
|
* valid bit + value bits
|
||||||
|
@@ -20,10 +20,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||||
|
@@ -73,8 +73,6 @@ extern "C" {
|
|||||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||||
|
|
||||||
#define MMU_TABLE_INVALID_VAL 0x100
|
|
||||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
|
||||||
/**
|
/**
|
||||||
* MMU entry valid bit mask for mapping value. For an entry:
|
* MMU entry valid bit mask for mapping value. For an entry:
|
||||||
* valid bit + value bits
|
* valid bit + value bits
|
||||||
|
@@ -20,10 +20,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||||
|
@@ -73,8 +73,6 @@ extern "C" {
|
|||||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||||
|
|
||||||
#define MMU_TABLE_INVALID_VAL 0x100
|
|
||||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
|
||||||
/**
|
/**
|
||||||
* MMU entry valid bit mask for mapping value. For an entry:
|
* MMU entry valid bit mask for mapping value. For an entry:
|
||||||
* valid bit + value bits
|
* valid bit + value bits
|
||||||
|
@@ -20,10 +20,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||||
|
@@ -102,8 +102,6 @@ extern "C" {
|
|||||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||||
|
|
||||||
#define MMU_TABLE_INVALID_VAL 0x4000
|
|
||||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
|
||||||
/**
|
/**
|
||||||
* MMU entry valid bit mask for mapping value. For an entry:
|
* MMU entry valid bit mask for mapping value. For an entry:
|
||||||
* valid bit + value bits
|
* valid bit + value bits
|
||||||
|
@@ -20,10 +20,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
||||||
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
||||||
|
@@ -73,8 +73,6 @@ extern "C" {
|
|||||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||||
|
|
||||||
#define MMU_TABLE_INVALID_VAL 0x4000
|
|
||||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
|
||||||
/**
|
/**
|
||||||
* MMU entry valid bit mask for mapping value. For an entry:
|
* MMU entry valid bit mask for mapping value. For an entry:
|
||||||
* valid bit + value bits
|
* valid bit + value bits
|
||||||
|
@@ -20,10 +20,8 @@ extern "C" {
|
|||||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
|
||||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||||
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
|
|
||||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||||
|
Reference in New Issue
Block a user