Merge branch 'master' into feature/esp32s2beta_merge

components/esp32/CMakeLists.txt

@@ -3,6 +3,8 @@ if(NOT "${target}" STREQUAL "esp32")
     return()
 endif()
 
+idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
+
 if(BOOTLOADER_BUILD)
     # For bootloader, all we need from esp32 is headers
     idf_component_register(INCLUDE_DIRS include)

components/esp32/Makefile.projbuild

@@ -10,7 +10,7 @@ ifneq ("$(filter esp32,$(TEST_COMPONENTS_LIST))","")
 CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
 endif
 ESP32_LINKER_SCRIPT_TEMPLATE := $(COMPONENT_PATH)/ld/esp32.project.ld.in
-ESP32_LINKER_SCRIPT_OUTPUT_DIR := $(abspath $(BUILD_DIR_BASE)/esp32)
+ESP32_LINKER_SCRIPT_OUTPUT_DIR := $(realpath $(BUILD_DIR_BASE)/esp32)
 
 # Target to generate linker script generator from fragments presented by each of
 # the components

components/esp32/cpu_start.c

@@ -47,7 +47,6 @@
 #include "nvs_flash.h"
 #include "esp_event.h"
 #include "esp_spi_flash.h"
-#include "esp_ipc.h"
 #include "esp_private/crosscore_int.h"
 #include "esp_log.h"
 #include "esp_vfs_dev.h"
@@ -205,18 +204,9 @@ void IRAM_ATTR call_start_cpu0(void)
     }
     ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
 
-    esp_flash_enc_mode_t mode;
-    mode = esp_get_flash_encryption_mode();
-    if (mode == ESP_FLASH_ENC_MODE_DEVELOPMENT) {
-#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
-        ESP_EARLY_LOGE(TAG, "Flash encryption settings error: mode should be RELEASE but is actually DEVELOPMENT");
-        ESP_EARLY_LOGE(TAG, "Mismatch found in security options in menuconfig and efuse settings");
-#else
-        ESP_EARLY_LOGW(TAG, "Flash encryption mode is DEVELOPMENT");
+#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
+    esp_flash_encryption_init_checks();
 #endif
-    } else if (mode == ESP_FLASH_ENC_MODE_RELEASE) {
-        ESP_EARLY_LOGI(TAG, "Flash encryption mode is RELEASE");
-    }
 
     //Flush and enable icache for APP CPU
     Cache_Flush(1);
@@ -405,9 +395,11 @@ void start_cpu0_default(void)
     /* init default OS-aware flash access critical section */
     spi_flash_guard_set(&g_flash_guard_default_ops);
 
+#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
     esp_flash_app_init();
     esp_err_t flash_ret = esp_flash_init_default_chip();
     assert(flash_ret == ESP_OK);
+#endif
 
     uint8_t revision = esp_efuse_get_chip_ver();
     ESP_LOGI(TAG, "Chip Revision: %d", revision);
@@ -444,10 +436,13 @@ void start_cpu0_default(void)
 #endif
 
     bootloader_flash_update_id();
-#if !CONFIG_SPIRAM_BOOT_INIT  // If psram is uninitialized, we need to improve some flash configuration.
-    esp_image_header_t fhdr;
-    const esp_partition_t *partition = esp_ota_get_running_partition();
-    spi_flash_read(partition->address, &fhdr, sizeof(esp_image_header_t));
+#if !CONFIG_SPIRAM_BOOT_INIT
+    // Read the application binary image header. This will also decrypt the header if the image is encrypted.
+    esp_image_header_t fhdr = {0};
+    // This assumes that DROM is the first segment in the application binary, i.e. that we can read
+    // the binary header through cache by accessing SOC_DROM_LOW address.
+    memcpy(&fhdr, (void*) SOC_DROM_LOW, sizeof(fhdr));
+    // If psram is uninitialized, we need to improve some flash configuration.
     bootloader_flash_clock_config(&fhdr);
     bootloader_flash_gpio_config(&fhdr);
     bootloader_flash_dummy_config(&fhdr);

components/esp32/intr_alloc.c

@@ -28,11 +28,15 @@
 #include "esp_log.h"
 #include "esp_intr_alloc.h"
 #include "esp_attr.h"
-#include "esp_ipc.h"
 #include <limits.h>
 #include <assert.h>
 #include "soc/soc.h"
 
+#if !CONFIG_FREERTOS_UNICORE
+#include "esp_ipc.h"
+#endif
+
+
 static const char* TAG = "intr_alloc";
 
 #define ETS_INTERNAL_TIMER0_INTR_NO 6
@@ -709,20 +713,26 @@ esp_err_t IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
     return ESP_OK;
 }
 
+#if !CONFIG_FREERTOS_UNICORE
 static void esp_intr_free_cb(void *arg)
 {
     (void)esp_intr_free((intr_handle_t)arg);
 }
+#endif /* !CONFIG_FREERTOS_UNICORE */
 
 esp_err_t esp_intr_free(intr_handle_t handle)
 {
     bool free_shared_vector=false;
     if (!handle) return ESP_ERR_INVALID_ARG;
+
+#if !CONFIG_FREERTOS_UNICORE
     //Assign this routine to the core where this interrupt is allocated on.
     if (handle->vector_desc->cpu!=xPortGetCoreID()) {
         esp_err_t ret = esp_ipc_call_blocking(handle->vector_desc->cpu, &esp_intr_free_cb, (void *)handle);
         return ret == ESP_OK ? ESP_OK : ESP_FAIL;
     }
+#endif /* !CONFIG_FREERTOS_UNICORE */
+
     portENTER_CRITICAL(&spinlock);
     esp_intr_disable(handle);
     if (handle->vector_desc->flags&VECDESC_FL_SHARED) {

components/esp32/ld/esp32.ld

@@ -21,6 +21,14 @@
 #define CONFIG_BT_RESERVE_DRAM 0
 #endif
 
+#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
+#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
+#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
+#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
+#else
+#define ESP_BOOTLOADER_RESERVE_RTC 0
+#endif
+
 #if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
 
 ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
@@ -76,7 +84,7 @@ MEMORY
   rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000
 
   /* RTC fast memory (same block as above), viewed from data bus */
-  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000
+  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
 
   /* RTC slow memory (data accessible). Persists over deep sleep.
 

components/esp32/panic.c

@@ -608,6 +608,14 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
     reconfigureAllWdts();
 #endif
 
+#if !CONFIG_ESP_PANIC_HANDLER_IRAM
+    // Re-enable CPU cache for current CPU if it was disabled
+    if (!spi_flash_cache_enabled()) {
+        spi_flash_enable_cache(core_id);
+        panicPutStr("Re-enable cpu cache.\r\n");
+    }
+#endif
+
 #if CONFIG_ESP32_PANIC_GDBSTUB
     disableAllWdts();
     rtc_wdt_disable();

components/esp32/test/test_ipc.c

@@ -3,7 +3,9 @@
 #include "freertos/task.h"
 #include "unity.h"
 #include "esp_ipc.h"
+#include "sdkconfig.h"
 
+#if !CONFIG_FREERTOS_UNICORE
 static void test_func_ipc_cb(void *arg)
 {
     vTaskDelay(50);
@@ -14,10 +16,7 @@ static void test_func_ipc_cb(void *arg)
 TEST_CASE("Test blocking IPC function call", "[ipc]")
 {
     int val = 0x5a5a;
-#ifdef CONFIG_FREERTOS_UNICORE
-    esp_ipc_call_blocking(xPortGetCoreID(), test_func_ipc_cb, &val);
-#else
     esp_ipc_call_blocking(!xPortGetCoreID(), test_func_ipc_cb, &val);
-#endif
     TEST_ASSERT_EQUAL_HEX(val, 0xa5a5);
 }
+#endif /* !CONFIG_FREERTOS_UNICORE */