Merge branch 'fix/disable_wfe_feature_for_e906_chips' into 'master'

change(esp_hw_support): disable CPU wait-for-event mode on cpu start

See merge request espressif/esp-idf!36388

components/riscv/include/esp_private/interrupt_clic.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -148,6 +148,20 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
     RV_WRITE_CSR(MTVT_CSR, mtvt_val);
 }
 
+#if SOC_CPU_SUPPORT_WFE
+/**
+ * @brief Set the MEXSTATUS_WFFEN value, used to enable/disable wait for event mode.
+ */
+FORCE_INLINE_ATTR void rv_utils_wfe_mode_enable(bool en)
+{
+    if (en) {
+        RV_SET_CSR(MEXSTATUS, MEXSTATUS_WFFEN);
+    } else {
+        RV_CLEAR_CSR(MEXSTATUS, MEXSTATUS_WFFEN);
+    }
+}
+#endif
+
 /**
  * @brief Get the current CPU raw interrupt level
  */

components/riscv/include/riscv/encoding.h

@@ -53,6 +53,14 @@
 #define MSTATUS_SXL         0x0000000C00000000
 #define MSTATUS64_SD        0x8000000000000000
 
+#define MEXSTATUS_SOFT_RST  0x00000003
+#define MEXSTATUS_LPMD      0x0000000C
+#define MEXSTATUS_WFFEN     0x00000010
+#define MEXSTATUS_EXPT_VLD  0x00000020
+#define MEXSTATUS_LOCKUP    0x00000040
+#define MEXSTATUS_NMISTS    0x00000080
+#define MEXSTATUS_BUSEER    0x00000100
+
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
 #define SSTATUS_UPIE        0x00000010