From 861e6a4ef86fb75d1520c90fa14bce699427035b Mon Sep 17 00:00:00 2001 From: wanglei Date: Mon, 19 Jun 2023 15:15:32 +0800 Subject: [PATCH] cache: patch some rom cache api, rename those apis in ld 1. Cache_Count_Flash_Pages, fix this api return enexpected + 1 2. Cache_Suspend_I/DCache, add wait cache idle after suspend cache 3. Cache_Freeze_I/DCache_Enable, add wait cache idle after freeze --- components/esp_psram/mmu_psram_flash.c | 16 +--- components/esp_rom/CMakeLists.txt | 4 + .../esp_rom/esp32s2/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32s2/esp_rom_caps.h | 1 + components/esp_rom/esp32s2/ld/esp32s2.rom.ld | 2 +- .../esp_rom/esp32s3/Kconfig.soc_caps.in | 8 ++ components/esp_rom/esp32s3/esp_rom_caps.h | 2 + components/esp_rom/esp32s3/ld/esp32s3.rom.ld | 10 +-- components/esp_rom/linker.lf | 2 + .../patches/esp_rom_cache_esp32s2_esp32s3.c | 83 +++++++++++++++++++ 10 files changed, 111 insertions(+), 21 deletions(-) create mode 100644 components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c diff --git a/components/esp_psram/mmu_psram_flash.c b/components/esp_psram/mmu_psram_flash.c index beff0fa0ac..bfa3daec3b 100644 --- a/components/esp_psram/mmu_psram_flash.c +++ b/components/esp_psram/mmu_psram_flash.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,13 +49,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size { uint32_t page_id = start_page; - /** - * TODO IDF-4387 - * `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this. - * FOR NOW, leave these logics just as it used to be. - * - * The rom API will be redesigned into a MMU driver layer function - */ uint32_t flash_pages = 0; #if CONFIG_IDF_TARGET_ESP32S2 flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped); @@ -100,13 +93,6 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si { uint32_t page_id = start_page; - /** - * TODO IDF-4387 - * `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this. - * FOR NOW, leave these logics just as it used to be. - * - * The rom API will be redesigned into a MMU driver layer function - */ uint32_t flash_pages = 0; #if CONFIG_IDF_TARGET_ESP32S2 flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped); diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index f007067ee6..fe8fe77375 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -37,6 +37,10 @@ if(CONFIG_SOC_SYSTIMER_SUPPORTED) list(APPEND sources "patches/esp_rom_systimer.c") endif() +if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG) + list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c") +endif() + idf_component_register(SRCS ${sources} INCLUDE_DIRS ${include_dirs} PRIV_REQUIRES ${private_required_comp} diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index 1c94b4d5c3..710b6c39bb 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -14,3 +14,7 @@ config ESP_ROM_HAS_MZ_CRC32 config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y + +config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG + bool + default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 35ad5c1ccc..9e68500b87 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -9,3 +9,4 @@ #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing +#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld index 20a6d3c2a9..2256bc2b32 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld @@ -17,7 +17,7 @@ PROVIDE ( Cache_Clean_All = 0x40018438 ); PROVIDE ( Cache_Clean_Items = 0x40018250 ); PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 ); PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 ); -PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 ); +PROVIDE ( rom_Cache_Count_Flash_Pages = 0x40018f70 ); PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 ); PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 ); PROVIDE ( Cache_Disable_DCache = 0x40018c68 ); diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index ebd27530c1..38f438824d 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -50,3 +50,11 @@ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND config ESP_ROM_HAS_ETS_PRINTF_BUG bool default y + +config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG + bool + default y + +config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index 89b3389ea0..fe4f5f7e17 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -18,3 +18,5 @@ #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register +#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value +#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index ce5ca8ba2c..c94150ab97 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -420,15 +420,15 @@ PROVIDE( Cache_Disable_ICache = 0x4000186c ); PROVIDE( Cache_Enable_ICache = 0x40001878 ); PROVIDE( Cache_Disable_DCache = 0x40001884 ); PROVIDE( Cache_Enable_DCache = 0x40001890 ); -PROVIDE( Cache_Suspend_ICache = 0x4000189c ); +PROVIDE( rom_Cache_Suspend_ICache = 0x4000189c ); PROVIDE( Cache_Resume_ICache = 0x400018a8 ); -PROVIDE( Cache_Suspend_DCache = 0x400018b4 ); +PROVIDE( rom_Cache_Suspend_DCache = 0x400018b4 ); PROVIDE( Cache_Resume_DCache = 0x400018c0 ); PROVIDE( Cache_Occupy_Items = 0x400018cc ); PROVIDE( Cache_Occupy_Addr = 0x400018d8 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x400018e4 ); +PROVIDE( rom_Cache_Freeze_ICache_Enable = 0x400018e4 ); PROVIDE( Cache_Freeze_ICache_Disable = 0x400018f0 ); -PROVIDE( Cache_Freeze_DCache_Enable = 0x400018fc ); +PROVIDE( rom_Cache_Freeze_DCache_Enable = 0x400018fc ); PROVIDE( Cache_Freeze_DCache_Disable = 0x40001908 ); PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001914 ); PROVIDE( flash2spiram_instruction_offset = 0x40001920 ); @@ -444,7 +444,7 @@ PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c ); PROVIDE( Cache_MMU_Init = 0x40001998 ); PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 ); PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 ); -PROVIDE( Cache_Count_Flash_Pages = 0x400019bc ); +PROVIDE( rom_Cache_Count_Flash_Pages = 0x400019bc ); PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 ); PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 ); PROVIDE( Cache_Travel_Tag_Memory2 = 0x400019e0 ); diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf index 38af2aecdc..b0e662a335 100644 --- a/components/esp_rom/linker.lf +++ b/components/esp_rom/linker.lf @@ -3,6 +3,8 @@ archive: libesp_rom.a entries: esp_rom_spiflash (noflash) esp_rom_regi2c (noflash) + if ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG = y: + esp_rom_cache_esp32s2_esp32s3 (noflash) if HEAP_TLSF_USE_ROM_IMPL = y && ESP_ROM_TLSF_CHECK_PATCH = y: esp_rom_tlsf (noflash) if SOC_SYSTIMER_SUPPORTED = y: diff --git a/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c b/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c new file mode 100644 index 0000000000..062432caad --- /dev/null +++ b/components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "soc/extmem_reg.h" +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/cache.h" +#endif + +// this api is renamed for patch +extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); +uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped) +{ + uint32_t page0_before_count = *page0_mapped; + uint32_t flash_pages = 0; + flash_pages = rom_Cache_Count_Flash_Pages(bus, page0_mapped); + +/* No page mapped to page0, in this condition, the rom api will return + * unexpected value + 1. + */ + if (page0_before_count == *page0_mapped) { + flash_pages--; + } + return flash_pages; +} +extern uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); + +#if CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG +static inline void Cache_Wait_Idle(int icache) +{ + if (icache) { + while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_ICACHE_STATE) != 1) { + ; + } + } else { + while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_DCACHE_STATE) != 1) { + ; + } + } +} +// renamed for patch +extern uint32_t rom_Cache_Suspend_ICache(void); +uint32_t Cache_Suspend_ICache(void) +{ + uint32_t ret = rom_Cache_Suspend_ICache(); + Cache_Wait_Idle(1); + return ret; +} +extern uint32_t Cache_Suspend_ICache(void); + +// renamed for patch +extern uint32_t rom_Cache_Suspend_DCache(void); +uint32_t Cache_Suspend_DCache(void) +{ + uint32_t ret = rom_Cache_Suspend_DCache(); + Cache_Wait_Idle(0); + return ret; +} +extern uint32_t Cache_Suspend_DCache(void); + +// renamed for patch +extern void rom_Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode) +{ + rom_Cache_Freeze_ICache_Enable(mode); + Cache_Wait_Idle(1); +} +extern void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +// renamed for patch +extern void rom_Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode); +void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode) +{ + rom_Cache_Freeze_DCache_Enable(mode); + Cache_Wait_Idle(0); +} +extern void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode); +#endif