Merge branch 'feat/cache_ll_invalidate_all' into 'master'

cache: cache ll to invalidate all

Closes IDF-11897

See merge request espressif/esp-idf!35743

components/hal/esp32c2/include/hal/cache_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -149,6 +149,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_ICache_All();
+}
+
 /**
  * @brief Get Cache line size, in bytes
  *

components/hal/esp32c3/include/hal/cache_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -152,6 +152,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_ICache_All();
+}
+
 /**
  * @brief Get Cache line size, in bytes
  *

components/hal/esp32c5/include/hal/cache_ll.h

@@ -129,6 +129,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_All();
+}
+
 /**
  * @brief Writeback cache supported addr
  *

components/hal/esp32c6/include/hal/cache_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_ICache_All();
+}
+
 /**
  * @brief Freeze Cache
  *

components/hal/esp32c61/include/hal/cache_ll.h

@@ -128,6 +128,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_All();
+}
+
 /**
  * @brief Writeback cache supported addr
  *

components/hal/esp32h2/include/hal/cache_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_ICache_All();
+}
+
 /**
  * @brief Freeze Cache
  *

components/hal/esp32p4/include/hal/cache_ll.h

@@ -556,6 +556,80 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     }
 }
 
+/**
+ * @brief Invalidate L1 ICache all
+ *
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_invalidate_icache_all(uint32_t cache_id)
+{
+    if (cache_id == 0) {
+        Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_0);
+    } else if (cache_id == 1) {
+        Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_1);
+    } else if (cache_id == CACHE_LL_ID_ALL) {
+        Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_MASK);
+    }
+}
+
+/**
+ * @brief Invalidate L1 DCache all
+ *
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_invalidate_dcache_all(uint32_t cache_id)
+{
+    if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
+        Cache_Invalidate_All(CACHE_MAP_L1_DCACHE);
+    }
+}
+
+/**
+ * @brief Invalidate L2 Cache all
+ *
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l2_invalidate_cache_all(uint32_t cache_id)
+{
+    if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) {
+        Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
+    }
+}
+
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    if (cache_level == 1 || cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) {
+        switch (type) {
+        case CACHE_TYPE_INSTRUCTION:
+            cache_ll_l1_invalidate_icache_all(cache_id);
+            break;
+        case CACHE_TYPE_DATA:
+            cache_ll_l1_invalidate_dcache_all(cache_id);
+            break;
+        case CACHE_TYPE_ALL:
+        default:
+            cache_ll_l1_invalidate_icache_all(cache_id);
+            cache_ll_l1_invalidate_dcache_all(cache_id);
+            break;
+        }
+    }
+
+    if (cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) {
+        cache_ll_l2_invalidate_cache_all(cache_id);
+    }
+}
+
 /*------------------------------------------------------------------------------
  * Writeback
  *----------------------------------------------------------------------------*/

components/hal/esp32s2/include/hal/cache_ll.h

@@ -350,6 +350,31 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    switch (type)
+    {
+    case CACHE_TYPE_DATA:
+        Cache_Invalidate_DCache_All();
+        break;
+    case CACHE_TYPE_INSTRUCTION:
+        Cache_Invalidate_ICache_All();
+        break;
+    default: //CACHE_TYPE_ALL
+        Cache_Invalidate_ICache_All();
+        Cache_Invalidate_DCache_All();
+        break;
+    }
+}
+
 /**
  * @brief Writeback cache supported addr
  *

components/hal/esp32s3/include/hal/cache_ll.h

@@ -360,6 +360,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    switch (type)
+    {
+    case CACHE_TYPE_DATA:
+        Cache_Invalidate_DCache_All();
+        break;
+    case CACHE_TYPE_INSTRUCTION:
+        Cache_Invalidate_ICache_All();
+        break;
+    default: //CACHE_TYPE_ALL
+        Cache_Invalidate_ICache_All();
+        Cache_Invalidate_DCache_All();
+        break;
+    }
+}
+
+
 /**
  * @brief Writeback cache supported addr
  *