From 46dae91a3976b0210ed3ed1bb747adfd16b16bc2 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 9 Nov 2023 14:00:05 +0800 Subject: [PATCH] fix(esp_pm): fix psram access faild after pd_cpu wakeup --- components/esp_pm/pm_impl.c | 7 ++++--- components/hal/esp32s3/rtc_cntl_hal.c | 10 +++++++++- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 8131f5a5f5..4fcaac746a 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -437,8 +437,11 @@ esp_err_t esp_pm_configure(const void* vconfig) min_freq_mhz, config->light_sleep_enable ? "ENABLED" : "DISABLED"); - portENTER_CRITICAL(&s_switch_lock); + // CPU & Modem power down initialization, which must be initialized before s_light_sleep_en set true, + // to avoid entering idle and sleep in this function. + esp_pm_sleep_configure(config); + portENTER_CRITICAL(&s_switch_lock); bool res __attribute__((unused)); res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]); assert(res); @@ -451,8 +454,6 @@ esp_err_t esp_pm_configure(const void* vconfig) s_config_changed = true; portEXIT_CRITICAL(&s_switch_lock); - esp_pm_sleep_configure(config); - return ESP_OK; } diff --git a/components/hal/esp32s3/rtc_cntl_hal.c b/components/hal/esp32s3/rtc_cntl_hal.c index 27d3c605be..94c74908b7 100644 --- a/components/hal/esp32s3/rtc_cntl_hal.c +++ b/components/hal/esp32s3/rtc_cntl_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,6 +68,14 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr) ); rtc_cntl_ll_enable_cpu_retention_clock(); rtc_cntl_ll_enable_cpu_retention(); +#if SOC_PM_SUPPORT_TAGMEM_PD + if (!retent->tagmem.dcache.enable) { + // Here we only need to care for the safety of the PSRAM data in the DCache. + // Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be + // modified in the sleep process code after now, so it is safe to writeback here. + Cache_WriteBack_All(); + } +#endif } } }