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reset_reasons: EFUSE_RST is treated as POWERON_RST

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ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
This commit is contained in:
KonstantinKondrashov
2021-08-11 12:20:17 +05:00
parent 83eb2c4964
commit 46f0313d6b
8 changed files with 31 additions and 30 deletions
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2
components/esp_rom/include/esp32s2/rom/rtc.h
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@@ -89,6 +89,7 @@ typedef enum {
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -106,6 +107,7 @@ _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT,
_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
typedef enum {
NO_SLEEP = 0,